From 86f89a1703abc52bbdb5c5b5494d90ba20a6ef2b Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Mon, 23 Feb 2026 06:27:09 +0000 Subject: [PATCH 01/13] Implement redesigned logger for Unified VAL - Add val_logger.c and val_logger.h as implementation - Design patchset(review comments addressed) Signed-off-by: Shruti Ghadge Change-Id: I12cc4a2338013cc80060d0c5e8795455f594c085 --- pal/baremetal/base/include/pal_pl011_uart.h | 5 +- pal/baremetal/base/src/pal_pl011_uart.c | 7 +- pal/uefi_acpi/src/pal_misc.c | 17 +- val/include/pal_common_intf.h | 34 + val/include/val_logger.h | 42 + val/src/val_logger.c | 803 ++++++++++++++++++++ 6 files changed, 903 insertions(+), 5 deletions(-) create mode 100644 val/include/pal_common_intf.h create mode 100644 val/include/val_logger.h create mode 100644 val/src/val_logger.c diff --git a/pal/baremetal/base/include/pal_pl011_uart.h b/pal/baremetal/base/include/pal_pl011_uart.h index 8da3f243..7700ff6c 100644 --- a/pal/baremetal/base/include/pal_pl011_uart.h +++ b/pal/baremetal/base/include/pal_pl011_uart.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -69,7 +69,6 @@ typedef struct { /* function prototypes */ extern void pal_driver_uart_pl011_putc(int c); - -#define pal_uart_putc(x) pal_driver_uart_pl011_putc(x) +void pal_uart_putc(char c); #endif /* _PAL_UART_PL011_H_ */ diff --git a/pal/baremetal/base/src/pal_pl011_uart.c b/pal/baremetal/base/src/pal_pl011_uart.c index 63208e32..4b574c2b 100644 --- a/pal/baremetal/base/src/pal_pl011_uart.c +++ b/pal/baremetal/base/src/pal_pl011_uart.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -91,3 +91,8 @@ void pal_driver_uart_pl011_putc(int c) /* write the data (upper 24 bits are reserved) */ ((pal_uart_t *)g_uart)->uartdr = pdata; } + +void pal_uart_putc(char c) +{ + pal_driver_uart_pl011_putc((uint8_t)c); +} diff --git a/pal/uefi_acpi/src/pal_misc.c b/pal/uefi_acpi/src/pal_misc.c index ecd642ae..3a28d735 100644 --- a/pal/uefi_acpi/src/pal_misc.c +++ b/pal/uefi_acpi/src/pal_misc.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, 2022-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, 2022-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -771,3 +771,18 @@ pal_mem_set_wb_executable ( return 0; } + +void pal_uart_putc(char c) +{ + CHAR8 ch = (CHAR8)c; + + AsciiPrint("%c", ch); + + if (g_acs_log_file_handle) { + UINTN n = 1; + EFI_STATUS Status = ShellWriteFile(g_acs_log_file_handle, &n, &ch); + if (EFI_ERROR(Status)) { + acs_print(ACS_PRINT_ERR, L" Error in writing to log file\n"); + } + } +} diff --git a/val/include/pal_common_intf.h b/val/include/pal_common_intf.h new file mode 100644 index 00000000..e60d375d --- /dev/null +++ b/val/include/pal_common_intf.h @@ -0,0 +1,34 @@ +/** @file + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef _PAL_COMMON_INTF_H_ +#define _PAL_COMMON_INTF_H_ + +#include +#include +#include + + +#define LOG_BUFFER_SIZE 8192 +#define static_assert _Static_assert + +void pal_uart_putc(char c); + +#endif /* _PAL_COMMON_INTF_H_ */ + + + diff --git a/val/include/val_logger.h b/val/include/val_logger.h new file mode 100644 index 00000000..021cdb71 --- /dev/null +++ b/val/include/val_logger.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_LOG_H +#define VAL_LOG_H + +#ifndef TARGET_UEFI +#include +#endif + +#include "pal_interface.h" +#include +#include +#include + +/* Verbosity enums, Lower the value, higher the verbosity */ +typedef enum { + TRACE = 1, + DEBUG, + INFO, + WARN, + ERROR, + FATAL +} print_verbosity_t; + +/** + * @brief - This function prints the given string and data onto the uart + * @param - verbosity : Print Verbosity level + * @param - msg : Input String + * @param - ... : ellipses for variadic args + * @return - SUCCESS((Any positive number for character written)/FAILURE(0)) +**/ +uint32_t val_printf(print_verbosity_t verbosity, const char *msg, ...); + +void val_mem_copy(char *dest, const char *src, size_t len); + +#endif /* VAL_LOG_H */ + diff --git a/val/src/val_logger.c b/val/src/val_logger.c new file mode 100644 index 00000000..92dd0b4b --- /dev/null +++ b/val/src/val_logger.c @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "include/val_logger.h" +#include "include/pal_common_intf.h" + +static void val_putc(char c) +{ + pal_uart_putc(c); +} + +enum { LOG_MAX_STRING_LENGTH = 90 }; + +/* Keep fields aligned */ +/* clang-format off */ +struct format_flags { + uint32_t minus : 1; + uint32_t plus : 1; + uint32_t space : 1; + uint32_t alt : 1; + uint32_t zero : 1; + uint32_t upper : 1; + uint32_t neg : 1; +}; +/* clang-format on */ + +enum format_base { + base2 = 2, + base8 = 8, + base10 = 10, + base16 = 16, +}; + +enum format_length { + length8 = 8, + length16 = 16, + length32 = 32, + length64 = 64, +}; + +enum length_mod { + mod_none = 0, + mod_h, + mod_hh, + mod_l, + mod_ll, + mod_bad /* j, z, t (reject these) */ +}; + +#ifndef STATIC_ASSERT_CHECKS +static_assert(sizeof(char) == sizeof(uint8_t), + "log expects char to be 8 bits wide"); +static_assert(sizeof(short) == sizeof(uint16_t), + "log expects short to be 16 bits wide"); +static_assert(sizeof(int) == sizeof(uint32_t), + "log expects int to be 32 bits wide"); +static_assert(sizeof(long) == sizeof(uint64_t), + "log expects long to be 64 bits wide"); +static_assert(sizeof(long long) == sizeof(uint64_t), + "log expects long long to be 64 bits wide"); +static_assert(sizeof(intmax_t) == sizeof(uint64_t), + "log expects intmax_t to be 64 bits wide"); +static_assert(sizeof(size_t) == sizeof(uint64_t), + "log expects size_t to be 64 bits wide"); +static_assert(sizeof(ptrdiff_t) == sizeof(uint64_t), + "log expects ptrdiff_t to be 64 bits wide"); +#endif + +/* + * These global variables for the log buffer are not static because a test needs + * to access them directly. + */ +size_t log_buffer_offset; +char log_buffer[LOG_BUFFER_SIZE]; + +/** + * @brief - Stores a character in a log buffer and outputs it via 'val_putc' + * @param - c : Input Character + * @return - Sends the character using 'val_putc' + **/ + +static void log_putchar(char c) +{ + static char prev; + + log_buffer[log_buffer_offset] = c; + log_buffer_offset = (log_buffer_offset + 1) % LOG_BUFFER_SIZE; + + /* If we are about to print '\n' and the previous char wasn't '\r', + * inject '\r' so UART terminals go back to column 0. */ + if (c == '\n' && prev != '\r') { + char cr = '\r'; + val_putc(cr); + } + + val_putc(c); + prev = c; +} + +/** + * @brief - Determines length of a string up to a maximum limit + * @param - str : Input String + * - strsz : Maximum characters to check for string's length + * @return - The length of the null-terminated byte string `str` + **/ + +static size_t log_strnlen_s(const char *str, size_t strsz) +{ + if (str == NULL) { + return 0; + } + + for (size_t i = 0; i < strsz; ++i) { + if (str[i] == '\0') { + return i; + } + } + + /* NULL character not found. */ + return strsz; +} + +/** + * @brief - Prints a literal string (i.e. '%' is not interpreted specially) to the debug log + * @param - str : Input literal String + * @return - Number of characters written + **/ + +static size_t print_raw_string(const char *str) +{ + const char *c = str; + + for (; *c != '\0'; c++) { + log_putchar(*c); + } + + return (size_t)(c - str); +} + +/** + * @brief - Prints a formatted string to the debug log + * @param - str : The full String + * - suffix : Pointer within str that indicates where suffix begins + * - min_width : Minimum width + * - flags : Whether to align to left or right + * - fill : The fill character + * @return - Number of characters written + **/ +static size_t print_string(const char *str, const char *suffix, + int min_width, struct format_flags *flags, + char fill) +{ + size_t chars_written = 0; + size_t prefix_len = (size_t)(suffix - str); + size_t suffix_len = log_strnlen_s(suffix, LOG_MAX_STRING_LENGTH); + size_t total_len = prefix_len + suffix_len; + + if (flags->minus) { + /* Left-aligned: prefix + suffix, then pad with spaces */ + while (str != suffix) { + chars_written++; + log_putchar(*str++); + } + + chars_written += print_raw_string(suffix); + + while (total_len < (size_t)min_width) { + chars_written++; + log_putchar(' '); + total_len++; + } + return chars_written; + } + + /* Right-aligned */ + if (fill == ' ') { + /* Space padding goes BEFORE prefix/sign */ + while (total_len < (size_t)min_width) { + chars_written++; + log_putchar(' '); + total_len++; + } + + /* Now print prefix and suffix */ + while (str != suffix) { + chars_written++; + log_putchar(*str++); + } + chars_written += print_raw_string(suffix); + return chars_written; + } + + /* Zero padding (or other fill) goes AFTER prefix, BEFORE digits */ + while (str != suffix) { + chars_written++; + log_putchar(*str++); + } + + while (total_len < (size_t)min_width) { + chars_written++; + log_putchar(fill); + total_len++; + } + + chars_written += print_raw_string(suffix); + return chars_written; +} + +/** + * @brief - Prints an integer to the debug log + * @param - value : Integer to be formatted and printed + * - base : Base of the integer + * - min_width : Minimum width of the integer + * - flags : Printf-style flags + * @return - Number of characters written + **/ + +static size_t print_int(size_t value, enum format_base base, int min_width, + struct format_flags *flags) +{ + static const char *digits_lower = "0123456789abcdefxb"; + static const char *digits_upper = "0123456789ABCDEFXB"; + const char *digits = flags->upper ? digits_upper : digits_lower; + char buf[LOG_MAX_STRING_LENGTH]; + char *ptr = &buf[sizeof(buf) - 1]; + char *num; + *ptr = '\0'; + do { + --ptr; + *ptr = digits[value % base]; + value /= base; + } while (value); + + /* Num stores where the actual number begins. */ + num = ptr; + + /* Add prefix if requested. */ + if (flags->alt) { + switch (base) { + case base16: + ptr -= 2; + ptr[0] = '0'; + ptr[1] = digits[16]; + break; + + case base2: + ptr -= 2; + ptr[0] = '0'; + ptr[1] = digits[17]; + break; + + case base8: + ptr--; + *ptr = '0'; + break; + + case base10: + /* do nothing */ + break; + } + } + + /* Add sign if requested. */ + if (flags->neg) { + *--ptr = '-'; + } else if (flags->plus) { + *--ptr = '+'; + } else if (flags->space) { + *--ptr = ' '; + } + return print_string(ptr, num, min_width, flags, flags->zero ? '0' : ' '); +} + +/** + * @brief - Parses the optional flags field of a printf-style format + * @param - fmt : Input format String + * - flags : Store status of formatting flags from input string + * @return - A pointer to the first non-flag character in the string + **/ + +static const char *parse_flags(const char *fmt, struct format_flags *flags) +{ + for (;; fmt++) { + switch (*fmt) { + case '-': + flags->minus = true; + break; + + case '+': + flags->plus = true; + break; + + case ' ': + flags->space = true; + break; + + case '#': + flags->alt = true; + break; + + case '0': + flags->zero = true; + break; + + default: + return fmt; + } + } +} + +/** + * @brief - Parses the optional length modifier field of a printf-style format + * @param - fmt : Input String + * - length : Indicates the size of data-type being formatted + * @return - A pointer to the first non-length modifier character in the string + **/ + +static const char *parse_length_modifier(const char *fmt, + enum format_length *length, enum length_mod *mod) +{ + switch (*fmt) { + case 'h': + fmt++; + if (*fmt == 'h') { + fmt++; + *length = length8; + *mod = mod_hh; + } else { + *length = length16; + *mod = mod_h; + } + break; + case 'l': + fmt++; + if (*fmt == 'l') { + fmt++; + *length = length64; + *mod = mod_ll; + } else { + *length = length64; + *mod = mod_l; + } + break; + + case 'j': + case 'z': + case 't': + fmt++; + *length = length64; + *mod = mod_bad; + break; + + default: + *length = length32; + *mod = mod_none; + break; + } + + return fmt; +} + +/** + * @brief - Parses the optional minimum width field of a printf-style format + * @param - fmt : Input String + * - args : List of additional arguments + * - flags : Indicates if the value is negative + * - min_width : Integer where parsed minimum width is stored + * @return - A pointer to the first non-digit character in the string + **/ + +static const char *parse_min_width(const char *fmt, va_list args, + struct format_flags *flags, int *min_width) +{ + int width = 0; + + /* Read minimum width from arguments. */ + if (*fmt == '*') { + fmt++; + width = va_arg(args, int); + if (width < 0) { + width = -width; + flags->minus = true; + } + } else { + for (; *fmt >= '0' && *fmt <= '9'; fmt++) { + width = (width * 10) + (*fmt - '0'); + } + } + + *min_width = width; + + return fmt; +} + +/** + * @brief - Reinterpret an unsigned 64-bit integer as a potentially shorter unsigned + * integer according to the length modifier. + * @param - length : Specifies target-bit width of integer + * - value : Input unsigned integer + * @return - An unsigned integer suitable for passing to `print_int` + **/ + +static uint64_t reinterpret_unsigned_int(enum format_length length, uint64_t value) +{ + switch (length) { + case length8: + return (uint8_t)value; + case length16: + return (uint16_t)value; + case length32: + return (uint32_t)value; + case length64: + return value; + } + return 0; +} + +/** + * @brief - Reinterpret an unsigned 64-bit integer as a potentially shorter signed + * integer according to the length modifier. + * @param - length : Specifies width of the integer + * - value : Input unsigned integer value + * - flags : Indicates if the value is negative + * @return - An *unsigned* integer suitable for passing to `print_int` + **/ + +static uint64_t reinterpret_signed_int(enum format_length length, uint64_t value, + struct format_flags *flags) +{ + int64_t signed_value = (int64_t)reinterpret_unsigned_int(length, value); + + switch (length) { + case length8: + if ((int8_t)signed_value < 0) { + flags->neg = true; + signed_value = (-signed_value) & 0xFF; + } + break; + case length16: + if ((int16_t)signed_value < 0) { + flags->neg = true; + signed_value = (-signed_value) & 0xFFFF; + } + break; + case length32: + if ((int32_t)signed_value < 0) { + flags->neg = true; + signed_value = (-signed_value) & 0xFFFFFFFF; + } + break; + case length64: + if ((int64_t)signed_value < 0) { + flags->neg = true; + if (signed_value == (int64_t)(1ULL << 63)) { + return (uint64_t)(1ULL << 63); + } + signed_value = -signed_value; + } + break; + } + + return (uint64_t)signed_value; +} + +/** + * @brief - This function parses and formats a string according to specified format specifiers + * @param - fmt : Input String + * - args : Arguments are passed as a va_list + * @return - Number of characters written, or `-1` if format string is invalid + **/ + +static int val_log(const char *fmt, va_list args) +{ + int chars_written = 0; + + while (*fmt != '\0') { + switch (*fmt) { + default: + chars_written++; + log_putchar(*fmt); + fmt++; + break; + + case '%': { + struct format_flags flags = {0}; + int min_width = 0; + enum format_length length = length32; + enum length_mod mod = mod_none; + uint64_t value; + + fmt++; + fmt = parse_flags(fmt, &flags); + fmt = parse_min_width(fmt, args, &flags, &min_width); + fmt = parse_length_modifier(fmt, &length, &mod); + if (mod == mod_bad) { + chars_written = -1; + goto out; + } + + /* Handle the format specifier. */ + switch (*fmt) { + case '%': + fmt++; + chars_written++; + log_putchar('%'); + break; + + case 'c': { + char str[2] = {(char)va_arg(args, int), 0}; + + fmt++; + chars_written += print_string( + str, str, min_width, &flags, ' '); + break; + } + + case 's': { + char *str = va_arg(args, char *); + if (str == NULL) + str = "(null)"; + + fmt++; + chars_written += print_string( + str, str, min_width, &flags, ' '); + break; + } + + case 'd': + case 'i': { + fmt++; + if (mod == mod_ll) { + value = (uint64_t)(int64_t)va_arg(args, long long); + } else if (length == length64) { + value = (uint64_t)(int64_t)va_arg(args, long); + } else { + value = (uint64_t)(int64_t)va_arg(args, int); + } + value = reinterpret_signed_int(length, value, + &flags); + + chars_written += print_int(value, base10, + min_width, &flags); + break; + } + + case 'b': + fmt++; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else { + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base2, + min_width, &flags); + break; + + case 'B': + fmt++; + flags.upper = true; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else { + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base2, + min_width, &flags); + break; + + case 'o': + fmt++; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else { + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base8, + min_width, &flags); + break; + + case 'x': + fmt++; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else{ + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base16, + min_width, &flags); + break; + + case 'X': + fmt++; + flags.upper = true; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else { + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base16, + min_width, &flags); + break; + + case 'u': + fmt++; + if (mod == mod_ll) { + value = (uint64_t)va_arg(args, unsigned long long); + } else if (length == length64) { + value = (uint64_t)va_arg(args, unsigned long); + } else { + value = (uint64_t)va_arg(args, unsigned int); + } + value = reinterpret_unsigned_int(length, value); + + chars_written += print_int(value, base10, + min_width, &flags); + break; + + case 'p': + fmt++; + value = (uint64_t)(uintptr_t)va_arg(args, void *); + min_width = sizeof(size_t) * 2 + 2; + flags.zero = true; + flags.alt = true; + + chars_written += print_int(value, base16, + min_width, &flags); + break; + + default: + chars_written = -1; + goto out; + } + } + } + } + +out: + return chars_written; +} + +/** + * @brief - This function prints the given string and data onto the uart + * @param - verbosity : Print Verbosity level + * - msg : Input String + * - ... : ellipses for variadic args + * @return - SUCCESS((Any positive number for character written)/FAILURE(0) + **/ + +uint32_t val_printf(print_verbosity_t verbosity, const char *msg, ...) +{ + int chars_written = 0; + static bool lastWasNewline = true; + static bool prefixPrinted; + char formatted_msg[LOG_MAX_STRING_LENGTH]; + va_list args; + + if (msg == NULL) + return 0; + + /* New line => allow prefix again */ + if (lastWasNewline) + prefixPrinted = false; + + /* Emit any leading blank lines cleanly (and don't prefix blank lines) */ + while (*msg == '\n') { + print_raw_string("\r\n"); + lastWasNewline = true; + prefixPrinted = false; + msg++; + } + + /* If msg was only newlines */ + if (*msg == '\0') + return 0; + + /* Print prefix exactly once per logical line (supports multi-call line assembly) */ + if (!prefixPrinted) { + switch (verbosity) + { + case TRACE: + print_raw_string("\t\t"); + break; + case DEBUG: + print_raw_string("\t\t"); + break; + case INFO: + print_raw_string("\t"); + break; + case WARN: + print_raw_string("\t\tWARN : "); + break; + case ERROR: + print_raw_string("\t\tERROR: "); + break; + case FATAL: + print_raw_string("\t\tFATAL: "); + break; + default: + break; + } + prefixPrinted = true; + } + + /* Bounded scan: we only safely inspect up to N-2 chars */ + const size_t max_scan = LOG_MAX_STRING_LENGTH - 2; + size_t len = log_strnlen_s(msg, max_scan); + + va_start(args, msg); + + /* + * 3 cases: + * A) msg ends with '\n' convert final LF to CRLF + * B) msg is likely longer than buffer size => truncate to N-3 and force CRLF + * C) short msg without '\n' + */ + + /* Case A: ends with '\n'*/ + if (len > 0 && msg[len - 1] == '\n') + { + val_mem_copy(formatted_msg, msg, len - 1); + formatted_msg[len - 1] = '\r'; + formatted_msg[len] = '\n'; + formatted_msg[len + 1] = '\0'; + + chars_written = val_log(formatted_msg, args); + lastWasNewline = true; + prefixPrinted = false; + } + /* Case B: likely truncated (no '\0' found within max_scan) */ + else if (len == max_scan) + { + const char trunc_msg[] = "\r\n"; + const size_t trunc_len = sizeof(trunc_msg) - 1; + + size_t perm_len = LOG_MAX_STRING_LENGTH - trunc_len - 1; + + if (perm_len > len) + perm_len = len; + + val_mem_copy(formatted_msg, msg, perm_len); + formatted_msg[perm_len] = '\0'; + + if (perm_len > 0) + chars_written += (int)print_raw_string(formatted_msg); + + chars_written += (int)print_raw_string(trunc_msg); + + lastWasNewline = true; + prefixPrinted = false; /* next line should get prefix */ + } + + /* Case C: short, no trailing '\n' */ + else + { + chars_written = val_log(msg, args); + lastWasNewline = false; + } + + va_end(args); + if (chars_written < 0) + return 0; + + return (uint32_t)chars_written; +} + +/** + @brief Copy memory from source to destination + + @param dst Destination buffer + @param src Source buffer + @param len Number of bytes to copy + + @return Pointer to destination buffer +**/ +void val_mem_copy(char *dest, const char *src, size_t len) +{ + for (size_t i = 0; i < len; ++i) + dest[i] = src[i]; +} From e7ce7e39404c88cb46d74a0259b2a01954ea2e20 Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Thu, 19 Feb 2026 12:18:10 +0000 Subject: [PATCH 02/13] Replace ASM-based System registers access with inline helper functions - Add val_sysreg*.h and val_arch.h to provide macro-based inline accessors for Timer, GIC, MPAM, PE (Reg, Test), PMU and RAS system registers, consolidating register knowledge in C - Legacy AArch64 Sysreg/PMU/RAS/timer assembly files are removed to shrink the asm surface - These framework changes have been made as a part of Unified VAL Signed-off-by: Avi Nawal Change-Id: Ibbf84bbf32dc9be03323c5c7df500174f026b1c1 --- .../base/src/AArch64/ModuleEntryPoint.S | 226 +++---- pal/baremetal/pal.cmake | 1 + pal/include/pal_sysreg.h | 58 ++ pal/uefi_acpi/PalLib.inf | 4 +- pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S | 5 +- pal/uefi_dt/PalLib.inf | 2 +- pal/uefi_dt/src/AArch64/ModuleEntryPoint.S | 5 +- val/include/acs_ete.h | 5 +- val/include/acs_gic_support.h | 15 +- val/include/acs_memory.h | 3 +- val/include/acs_mpam.h | 8 +- val/include/acs_pe.h | 104 +--- val/include/acs_pmu.h | 9 +- val/include/acs_ras.h | 20 +- val/include/acs_timer_support.h | 105 +--- val/include/val_arch.h | 52 ++ val/include/val_sysreg.h | 569 ++++++++++++++++++ val/include/val_sysreg_gic.h | 19 + val/include/val_sysreg_mpam.h | 17 + val/include/val_sysreg_pe.h | 134 +++++ val/include/val_sysreg_pmu_reg.h | 17 + val/include/val_sysreg_ras.h | 24 + val/include/val_sysreg_timer.h | 42 ++ val/src/AArch64/ArchTimerSupport.S | 296 --------- val/src/AArch64/GicSupport.S | 95 --- val/src/AArch64/MpamSupport.S | 66 -- val/src/AArch64/PeRegSysSupport.S | 531 ---------------- val/src/AArch64/PeTestSupport.S | 17 +- val/src/AArch64/PmuRegSupport.S | 83 --- val/src/AArch64/RasSupport.S | 117 ---- val/src/AArch64/generic_sysreg_support.S | 407 ------------- 31 files changed, 1072 insertions(+), 1984 deletions(-) create mode 100644 pal/include/pal_sysreg.h create mode 100644 val/include/val_arch.h create mode 100644 val/include/val_sysreg.h create mode 100644 val/include/val_sysreg_gic.h create mode 100644 val/include/val_sysreg_mpam.h create mode 100644 val/include/val_sysreg_pe.h create mode 100644 val/include/val_sysreg_pmu_reg.h create mode 100644 val/include/val_sysreg_ras.h create mode 100644 val/include/val_sysreg_timer.h delete mode 100644 val/src/AArch64/ArchTimerSupport.S delete mode 100644 val/src/AArch64/GicSupport.S delete mode 100644 val/src/AArch64/MpamSupport.S delete mode 100644 val/src/AArch64/PmuRegSupport.S delete mode 100644 val/src/AArch64/RasSupport.S delete mode 100644 val/src/AArch64/generic_sysreg_support.S diff --git a/pal/baremetal/base/src/AArch64/ModuleEntryPoint.S b/pal/baremetal/base/src/AArch64/ModuleEntryPoint.S index 51a41e9c..f14a7893 100644 --- a/pal/baremetal/base/src/AArch64/ModuleEntryPoint.S +++ b/pal/baremetal/base/src/AArch64/ModuleEntryPoint.S @@ -1,35 +1,35 @@ -#/** @file -# Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -#include "gcc_types.h" - -.text -.align 3 - -GCC_ASM_IMPORT(ArmReadMpidr) -GCC_ASM_IMPORT(PalGetSecondaryStackBase) -GCC_ASM_IMPORT(PalGetMaxMpidr) -GCC_ASM_IMPORT(PalGetMmuConfigAddr) -GCC_ASM_EXPORT(ModuleEntryPoint) - -StartupAddr: .8byte ASM_PFX(val_test_entry) -ASM_PFX(StackSize): .8byte 0x100 - +#/** @file +# Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#**/ + +#include "gcc_types.h" +#include "pal_sysreg.h" + +.text +.align 3 + +GCC_ASM_IMPORT(PalGetSecondaryStackBase) +GCC_ASM_IMPORT(PalGetMaxMpidr) +GCC_ASM_IMPORT(PalGetMmuConfigAddr) +GCC_ASM_EXPORT(ModuleEntryPoint) + +StartupAddr: .8byte ASM_PFX(val_test_entry) +ASM_PFX(StackSize): .8byte 0x100 + // PE_MMU_CONFIG structure offsets .equ MMU_CFG_TTBR0, 0 .equ MMU_CFG_TTBR1, 8 @@ -42,19 +42,19 @@ ASM_PFX(StackSize): .8byte 0x100 .equ SCTLR_M_BIT, (1 << 0) // MMU enable .equ SCTLR_C_BIT, (1 << 2) // Data cache enable .equ SCTLR_I_BIT, (1 << 12) // Instruction cache enable - -ASM_PFX(ModuleEntryPoint): -// - // Enable MMU and caches using primary PE's configuration - // -_EnableMmu: - // Get the MMU configuration address from primary PE - // Note: This is a C function call, but we haven't set up stack yet - // so we use a special calling convention (just branch and link) - adr x9, MmuConfigAddr - ldr x9, [x9] - blr x9 - + +ASM_PFX(ModuleEntryPoint): +// + // Enable MMU and caches using primary PE's configuration + // +_EnableMmu: + // Get the MMU configuration address from primary PE + // Note: This is a C function call, but we haven't set up stack yet + // so we use a special calling convention (just branch and link) + adr x9, MmuConfigAddr + ldr x9, [x9] + blr x9 + // x0 now contains the address of PE_MMU_CONFIG structure mov x11, x0 // Save config address in x11 @@ -78,9 +78,9 @@ _EnableMmu: _SetupMmuEl1: // Invalidate TLB for EL1 tlbi vmalle1 - dsb sy - isb - + dsb sy + isb + // Set MAIR, TCR, TTBR0/1 for EL1 msr mair_el1, x15 isb @@ -99,10 +99,10 @@ _SetupMmuEl1: _SetupMmuEl2: // Invalidate TLB for EL2 - tlbi alle2 - dsb sy - isb - + tlbi alle2 + dsb sy + isb + // Set MAIR, TCR, TTBR0/1 for EL2 msr mair_el2, x15 isb @@ -117,65 +117,65 @@ _SetupMmuEl2: // Use the same SCTLR value as primary PE (which has M, C, I bits set) msr sctlr_el2, x16 isb - -_MmuEnabled: - // - // MMU and caches are now enabled, proceed with original entry code - // - - // Get ID of this CPU in Multicore system - bl ASM_PFX(ArmReadMpidr) - // Keep a copy of the MpId register value - mov x10, x0 - - // With this function: CorePos = (Aff3 x maxAff2 x maxAff1 x maxAff0) + - // (Aff2 x maxAff1 x maxAff0) + (Aff1 x maxAff0) + Aff0 - and x1, x0, 0xFF - and x2, x0, 0xFF00 - lsr x2, x2, 8 - and x3, x0, 0xFF0000 - lsr x3, x3, 16 - and x4, x0, 0xFF00000000 - lsr x4, x4, 32 - - bl ASM_PFX(PalGetMaxMpidr) - and x5, x0, 0xFF - add x5, x5, 1 - and x6, x0, 0xFF00 - lsr x6, x6, 8 - add x6, x6, 1 - and x7, x0, 0xFF0000 - lsr x7, x7, 16 - add x7, x7, 1 - and x8, x0, 0xFF00000000 - lsr x8, x8, 32 - add x8, x8, 1 // x8 has maxAff3, which is reserved for future use - - madd x0, x2, x5, x1 - mul x5, x5, x6 - madd x0, x3, x5, x0 - mul x5, x5, x7 - madd x0, x4, x5, x0 - - ldr x3, StackSize - mul x3, x3, x0 -_GetStackBase: - mov x0, 0 - //ldr x4, GetStackMem - //blr x4 - //ASM_PFX(pal_allocate_stack) - bl ASM_PFX(PalGetSecondaryStackBase) - add x0, x0, x3 - mov sp, x0 -_PrepareArguments: - - ldr x4, StartupAddr - - blr x4 - -_NeverReturn: - b _NeverReturn - -// Function pointer for PalGetMmuConfigAddr -.align 3 + +_MmuEnabled: + // + // MMU and caches are now enabled, proceed with original entry code + // + + // Get ID of this CPU in Multicore system + READ_MPIDR_EL1(x0) + // Keep a copy of the MpId register value + mov x10, x0 + + // With this function: CorePos = (Aff3 x maxAff2 x maxAff1 x maxAff0) + + // (Aff2 x maxAff1 x maxAff0) + (Aff1 x maxAff0) + Aff0 + and x1, x0, 0xFF + and x2, x0, 0xFF00 + lsr x2, x2, 8 + and x3, x0, 0xFF0000 + lsr x3, x3, 16 + and x4, x0, 0xFF00000000 + lsr x4, x4, 32 + + bl ASM_PFX(PalGetMaxMpidr) + and x5, x0, 0xFF + add x5, x5, 1 + and x6, x0, 0xFF00 + lsr x6, x6, 8 + add x6, x6, 1 + and x7, x0, 0xFF0000 + lsr x7, x7, 16 + add x7, x7, 1 + and x8, x0, 0xFF00000000 + lsr x8, x8, 32 + add x8, x8, 1 // x8 has maxAff3, which is reserved for future use + + madd x0, x2, x5, x1 + mul x5, x5, x6 + madd x0, x3, x5, x0 + mul x5, x5, x7 + madd x0, x4, x5, x0 + + ldr x3, StackSize + mul x3, x3, x0 +_GetStackBase: + mov x0, 0 + //ldr x4, GetStackMem + //blr x4 + //ASM_PFX(pal_allocate_stack) + bl ASM_PFX(PalGetSecondaryStackBase) + add x0, x0, x3 + mov sp, x0 +_PrepareArguments: + + ldr x4, StartupAddr + + blr x4 + +_NeverReturn: + b _NeverReturn + +// Function pointer for PalGetMmuConfigAddr +.align 3 MmuConfigAddr: .8byte ASM_PFX(PalGetMmuConfigAddr) diff --git a/pal/baremetal/pal.cmake b/pal/baremetal/pal.cmake index 83cc12b1..d090aadf 100644 --- a/pal/baremetal/pal.cmake +++ b/pal/baremetal/pal.cmake @@ -36,6 +36,7 @@ target_include_directories(${PAL_LIB} PRIVATE ${ROOT_DIR}/pal/baremetal/base/include/ ${ROOT_DIR}/pal/baremetal/base/src/AArch64/ ${ROOT_DIR}/pal/baremetal/target/${TARGET}/include/ + ${ROOT_DIR}/pal/include/ ) unset(PAL_SRC) diff --git a/pal/include/pal_sysreg.h b/pal/include/pal_sysreg.h new file mode 100644 index 00000000..bb995860 --- /dev/null +++ b/pal/include/pal_sysreg.h @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef PAL_SYSREG_H +#define PAL_SYSREG_H + +#if defined(__ASSEMBLY__) || defined(__ASSEMBLER__) + +/* Assembly/C preprocessor macro for .S files */ +#define READ_MPIDR_EL1(reg) mrs reg, mpidr_el1 + +#else + +typedef unsigned long u_register_t; + +#ifndef _SYSREG_READ_FUNC +#define _SYSREG_READ_FUNC(_name, _reg_name) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +/* Define read function for system register */ +#define SYSREG_READ_FUNC(_name) \ + _SYSREG_READ_FUNC(_name, _name) +#endif + +SYSREG_READ_FUNC(mpidr_el1) +SYSREG_READ_FUNC(CurrentEL) +SYSREG_READ_FUNC(ttbr0_el1) +SYSREG_READ_FUNC(ttbr0_el2) +SYSREG_READ_FUNC(tcr_el1) +SYSREG_READ_FUNC(tcr_el2) +SYSREG_READ_FUNC(ttbr1_el1) +SYSREG_READ_FUNC(ttbr1_el2) +SYSREG_READ_FUNC(mair_el1) +SYSREG_READ_FUNC(mair_el2) +SYSREG_READ_FUNC(sctlr_el1) +SYSREG_READ_FUNC(sctlr_el2) +#endif + +#endif /* PAL_SYSREG_H */ diff --git a/pal/uefi_acpi/PalLib.inf b/pal/uefi_acpi/PalLib.inf index 0bcc6c11..5b2e132d 100644 --- a/pal/uefi_acpi/PalLib.inf +++ b/pal/uefi_acpi/PalLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2024-2026 Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -83,5 +83,5 @@ gEfiAcpiTableGuid [BuildOptions] - GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a -D__ASSEMBLY__ -D__ASSEMBLER__ GCC:*_*_*_CC_FLAGS = -O0 $(PAL_UEFI_ACPI_INCLUDE_FLAGS) diff --git a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S index 8490a4dd..0235d40e 100644 --- a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S @@ -16,10 +16,11 @@ # #**/ +#include "../../../include/pal_sysreg.h" + .text .align 3 -GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(PalGetSecondaryStackBase) GCC_ASM_IMPORT(PalGetMaxMpidr) GCC_ASM_IMPORT(PalGetMmuConfigAddr) @@ -131,7 +132,7 @@ _MmuEnabled: // // Get ID of this CPU in Multicore system - bl ASM_PFX(ArmReadMpidr) + READ_MPIDR_EL1(x0) // Keep a copy of the MpId register value mov x10, x0 diff --git a/pal/uefi_dt/PalLib.inf b/pal/uefi_dt/PalLib.inf index affb1808..dbaa0541 100644 --- a/pal/uefi_dt/PalLib.inf +++ b/pal/uefi_dt/PalLib.inf @@ -82,5 +82,5 @@ gFdtTableGuid [BuildOptions] - GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a -D__ASSEMBLY__ -D__ASSEMBLER__ GCC:*_*_*_CC_FLAGS = -O0 $(PAL_UEFI_DT_INCLUDE_FLAGS) $(BASE_FDT_LIB_INCLUDE_FLAGS) diff --git a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S index 8490a4dd..0235d40e 100644 --- a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S @@ -16,10 +16,11 @@ # #**/ +#include "../../../include/pal_sysreg.h" + .text .align 3 -GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(PalGetSecondaryStackBase) GCC_ASM_IMPORT(PalGetMaxMpidr) GCC_ASM_IMPORT(PalGetMmuConfigAddr) @@ -131,7 +132,7 @@ _MmuEnabled: // // Get ID of this CPU in Multicore system - bl ASM_PFX(ArmReadMpidr) + READ_MPIDR_EL1(x0) // Keep a copy of the MpId register value mov x10, x0 diff --git a/val/include/acs_ete.h b/val/include/acs_ete.h index 2fe151e6..faec920b 100644 --- a/val/include/acs_ete.h +++ b/val/include/acs_ete.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -169,10 +169,7 @@ uint64_t AA64DisableETETrace(void); uint64_t AA64SetupTraceAccess(void); uint64_t AA64EnableTRBUTrace(uint32_t index, uint64_t buffer_addr, uint32_t trbu_mode); uint64_t AA64DisableTRBUTrace(void); -uint64_t AA64ReadTrbPtrEl1(void); -uint64_t AA64ReadTrblimitr1(void); -void AA64WriteTrblimitr1(uint64_t data); void AA64EnableTFO(void); void AA64DisableTFO(void); diff --git a/val/include/acs_gic_support.h b/val/include/acs_gic_support.h index 646c3911..323a20eb 100644 --- a/val/include/acs_gic_support.h +++ b/val/include/acs_gic_support.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020, 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020, 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,6 +18,8 @@ #ifndef __GIC_SYS_REGS_H__ #define __GIC_SYS_REGS_H__ +#include "val_sysreg_gic.h" + #define LPI_MIN_ID 8192 typedef enum { @@ -31,15 +33,4 @@ typedef enum { uint64_t val_gic_reg_read(uint32_t reg_id); void val_gic_reg_write(uint32_t reg_id, uint64_t write_data); -uint64_t GicReadIchHcr(void); -uint64_t GicReadIchMisr(void); - -void GicWriteIchHcr(uint64_t write_data); -void GicWriteIccIgrpen1(uint64_t write_data); -void GicWriteIccBpr1(uint64_t write_data); -void GicWriteIccPmr(uint64_t write_data); -void GicClearDaif(void); -void TestExecuteBarrier(void); -void GicWriteHcr(uint64_t write_data); - #endif // __GIC_SYS_REGS_H__ diff --git a/val/include/acs_memory.h b/val/include/acs_memory.h index 9c1f160b..a1be072a 100644 --- a/val/include/acs_memory.h +++ b/val/include/acs_memory.h @@ -18,6 +18,8 @@ #ifndef __ACS_MEMORY_H__ #define __ACS_MEMORY_H__ +#include "val_sysreg.h" + #define MEM_MAP_SUCCESS 0x0 #define MEM_MAP_NO_MEM 0x1 #define MEM_MAP_FAILURE 0x2 @@ -43,7 +45,6 @@ void *val_aligned_alloc(uint32_t alignment, uint32_t size); void val_memory_free_aligned(void *addr); void *val_memory_alloc_cacheable(uint32_t bdf, uint32_t size, void **pa); void val_memory_free_cacheable(uint32_t bdf, uint32_t size, void *va, void *pa); -void AA64IssueDSB(void); void val_mem_issue_dsb(void); uint32_t val_memory_region_has_52bit_addr(void); diff --git a/val/include/acs_mpam.h b/val/include/acs_mpam.h index 37bd447b..8e91f4e2 100644 --- a/val/include/acs_mpam.h +++ b/val/include/acs_mpam.h @@ -18,6 +18,8 @@ #ifndef __ACS_MPAM_H__ #define __ACS_MPAM_H__ +#include "val_sysreg_mpam.h" + /* The return value is always 64-bit, type casting is needed by the caller and (m > n) */ #define CLEAR_BITS_M_TO_N(num, m, n) (num & ((~0UL << (m+1)) | ((1UL << n) - 1))) @@ -78,12 +80,6 @@ typedef enum { void val_mpam_reg_write(MPAM_SYS_REGS reg_id, uint64_t write_data); uint64_t val_mpam_reg_read(MPAM_SYS_REGS reg_id); -uint64_t AA64ReadMpamidr(void); -uint64_t AA64ReadMpam1(void); -uint64_t AA64ReadMpam2(void); -void AA64IssueDSB(void); -void AA64WriteMpam1(uint64_t write_data); -void AA64WriteMpam2(uint64_t write_data); uint64_t val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index); uint32_t val_mpam_msc_supports_mbwpart(uint32_t msc_index); diff --git a/val/include/acs_pe.h b/val/include/acs_pe.h index 599f90a2..e30a310e 100644 --- a/val/include/acs_pe.h +++ b/val/include/acs_pe.h @@ -18,6 +18,8 @@ #ifndef __ACS_PE_H__ #define __ACS_PE_H__ +#include "val_sysreg_pe.h" + /* Processor Family Type 4 */ #define PROCESSOR_FAMILY_ARMV9 0x102 @@ -196,113 +198,12 @@ typedef enum { VTCR_EL2 } BSA_ACS_PE_REGS; -uint64_t ArmReadMpidr(void); -uint64_t ArmReadIdPfr0(void); -uint64_t ArmReadIdPfr1(void); -uint64_t AA64ReadMmfr0(void); -uint64_t AA64ReadMmfr1(void); -uint64_t AA64ReadMmfr2(void); -uint64_t AA64ReadMmfr3(void); -uint64_t AA64ReadCtr(void); -uint64_t AA64ReadIsar0(void); -uint64_t AA64ReadIsar1(void); -uint64_t AA64ReadIsar2(void); -uint64_t AA64ReadSctlr3(void); -uint64_t AA64ReadSctlr2(void); -uint64_t AA64ReadSctlr1(void); -uint64_t AA64ReadPmcr(void); -uint64_t AA64ReadIdDfr0(void); -uint64_t AA64ReadIdDfr1(void); -uint64_t AA64ReadCurrentEL(void); -uint64_t AA64ReadMdcr2(void); -uint64_t AA64ReadVbar2(void); -uint64_t AA64ReadCcsidr(void); -uint64_t AA64ReadCsselr(void); -uint64_t AA64ReadClidr(void); -uint64_t ArmReadDfr0(void); -uint64_t ArmReadIsar0(void); -uint64_t ArmReadIsar1(void); -uint64_t ArmReadIsar2(void); -uint64_t ArmReadIsar3(void); -uint64_t ArmReadIsar4(void); -uint64_t ArmReadIsar5(void); -uint64_t ArmReadMmfr0(void); -uint64_t ArmReadMmfr1(void); -uint64_t ArmReadMmfr2(void); -uint64_t ArmReadMmfr3(void); -uint64_t ArmReadMmfr4(void); -uint64_t ArmReadPfr0(void); -uint64_t ArmReadPfr1(void); -uint64_t ArmReadMidr(void); -uint64_t ArmReadMvfr0(void); -uint64_t ArmReadMvfr1(void); -uint64_t ArmReadMvfr2(void); -uint64_t AA64ReadPmceid0(void); -uint64_t AA64ReadPmceid1(void); -uint64_t AA64ReadVmpidr(void); -uint64_t AA64ReadVpidr(void); -uint64_t AA64ReadPmbidr(void); -uint64_t AA64ReadPmsidr(void); -uint64_t AA64ReadLorid(void); -uint64_t AA64ReadErridr(void); -uint64_t AA64ReadErr0fr(void); -uint64_t AA64ReadErr1fr(void); -uint64_t AA64ReadErr2fr(void); -uint64_t AA64ReadErr3fr(void); -uint64_t AA64ReadMair1(void); -uint64_t AA64ReadMair2(void); -uint64_t AA64ReadTcr1(void); -uint64_t AA64ReadTcr2(void); -uint64_t AA64ReadTtbr0El1(void); -uint64_t AA64ReadTtbr0El2(void); -uint64_t AA64ReadTtbr1El1(void); -uint64_t AA64ReadTtbr1El2(void); uint64_t AA64WriteSp(uint64_t write_data); -uint64_t AA64ReadEsr2(void); uint64_t AA64ReadSp(void); -uint64_t AA64ReadFar2(void); uint64_t ArmRdvl(void); -uint64_t AA64ReadDbgbcr0El1(void); -uint64_t AA64ReadDbgbcr1El1(void); -uint64_t AA64ReadDbgbcr2El1(void); -uint64_t AA64ReadDbgbcr3El1(void); -uint64_t AA64ReadDbgbcr4El1(void); -uint64_t AA64ReadDbgbcr5El1(void); -uint64_t AA64ReadDbgbcr6El1(void); -uint64_t AA64ReadDbgbcr7El1(void); -uint64_t AA64ReadDbgbcr8El1(void); -uint64_t AA64ReadDbgbcr9El1(void); -uint64_t AA64ReadDbgbcr10El1(void); -uint64_t AA64ReadDbgbcr11El1(void); -uint64_t AA64ReadDbgbcr12El1(void); -uint64_t AA64ReadDbgbcr13El1(void); -uint64_t AA64ReadDbgbcr14El1(void); -uint64_t AA64ReadDbgbcr15El1(void); -uint64_t AA64ReadZfr0(void); -uint64_t AA64ReadBrbidr0(void); -uint64_t AA64ReadTrbidr(void); -uint64_t AA64ReadVtcr(void); -uint64_t AA64ReadTrcidr0(void); -uint64_t AA64ReadTrcidr4(void); -uint64_t AA64ReadTrcidr5(void); void AA64IssueISB(void); void DisableSpe(void); -void ArmCallWFI(void); -void ArmExecuteMemoryBarrier(void); -void AA64WritePmsirr(uint64_t write_data); -void AA64WritePmscr2(uint64_t write_data); -void AA64WritePmsfcr(uint64_t write_data); -void AA64WritePmblimitr(uint64_t write_data); -void AA64WritePmbptr(uint64_t write_data); -void AA64WriteMdcr2(uint64_t write_data); -void AA64WritePmcr(uint64_t write_data); -void AA64WritePmovsset(uint64_t write_data); -void AA64WritePmovsclr(uint64_t write_data); -void AA64WritePmintenset(uint64_t write_data); -void AA64WritePmintenclr(uint64_t write_data); -void AA64WriteCsselr(uint64_t write_data); -void AA64WriteVbar2(uint64_t write_data); void val_pe_update_elr(void *context, uint64_t offset); void val_pe_context_save(uint64_t sp, uint64_t elr); @@ -381,4 +282,3 @@ uint32_t pe067_entry(uint32_t num_pe); uint32_t pe068_entry(uint32_t num_pe); #endif - diff --git a/val/include/acs_pmu.h b/val/include/acs_pmu.h index bfb77ff0..bb17de70 100644 --- a/val/include/acs_pmu.h +++ b/val/include/acs_pmu.h @@ -18,6 +18,8 @@ #ifndef __ACS_PMU_H__ #define __ACS_PMU_H__ +#include "val_sysreg_pmu_reg.h" + /* EL2 Cycle Count Filter Enable */ #define NSH_EN 27 /* Cycle Counter Enable */ @@ -37,13 +39,6 @@ #define PMCR_NUM_COUNTERS_MASK 0xF800 -uint64_t AA64ReadPmccntr(void); -uint64_t AA64ReadPmccfiltr(void); -uint64_t AA64ReadPmcntenset(void); -void AA64WritePmccntr(uint64_t WriteData); -void AA64WritePmccfiltr(uint64_t WriteData); -void AA64WritePmcntenset(uint64_t WriteData); - uint64_t val_pmu_get_info(PMU_INFO_e type, uint32_t node_index); uint8_t val_pmu_supports_dedicated_cycle_counter(uint32_t node_index); uint32_t val_pmu_get_monitor_count(uint32_t node_index); diff --git a/val/include/acs_ras.h b/val/include/acs_ras.h index 423410df..49dc3acd 100644 --- a/val/include/acs_ras.h +++ b/val/include/acs_ras.h @@ -18,6 +18,7 @@ #ifndef __ACS_RAS_H #define __ACS_RAS_H +#include "val_sysreg_ras.h" #define ERR_FR_CE_MASK (0x3ull << 53) #define ERR_FR_DE_MASK (0x1ull << 52) @@ -131,23 +132,4 @@ uint32_t ras016_entry(uint32_t num_pe); uint32_t ras017_entry(uint32_t num_pe); uint32_t ras018_entry(uint32_t num_pe); -uint64_t AA64ReadErrIdr1(void); -uint64_t AA64ReadErrAddr1(void); -uint64_t AA64ReadErrCtlr1(void); -uint64_t AA64ReadErrFr1(void); -uint64_t AA64ReadErrStatus1(void); -uint64_t AA64ReadErrSelr1(void); -uint64_t AA64ReadErrPfgf1(void); -uint64_t AA64ReadErrPfgctl1(void); -uint64_t AA64ReadErrPfgcdn1(void); - -void AA64WriteErrIdr1(uint64_t write_data); -void AA64WriteErrAddr1(uint64_t write_data); -void AA64WriteErrCtlr1(uint64_t write_data); -void AA64WriteErrStatus1(uint64_t write_data); -void AA64WriteErrSelr1(uint64_t write_data); -void AA64WriteErrPfgf1(uint64_t write_data); -void AA64WriteErrPfgctl1(uint64_t write_data); -void AA64WriteErrPfgcdn1(uint64_t write_data); - #endif // __ACS_RAS_H diff --git a/val/include/acs_timer_support.h b/val/include/acs_timer_support.h index f158d1e0..1b4661c7 100644 --- a/val/include/acs_timer_support.h +++ b/val/include/acs_timer_support.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022, 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022, 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,6 +18,8 @@ #ifndef __ARM_ARCH_TIMER_H__ #define __ARM_ARCH_TIMER_H__ +#include "val_sysreg_timer.h" + #define ARM_ARCH_TIMER_ENABLE (1 << 0) #define ARM_ARCH_TIMER_IMASK (1 << 1) #define ARM_ARCH_TIMER_ISTATUS (1 << 2) @@ -59,113 +61,12 @@ ArmArchTimerWriteReg ( uint64_t *data_buf ); -uint64_t -ArmReadCntFrq ( - void - ); - void ArmWriteCntFrq ( uint64_t FreqInHz ); -uint64_t -ArmReadCntPct ( - void - ); - -uint64_t -ArmReadCntPctSS ( - void -); - -uint64_t -ArmReadCntkCtl ( - void - ); - -void -ArmWriteCntkCtl ( - uint64_t Val - ); - -uint64_t -ArmReadCntpTval ( - void - ); - -void -ArmWriteCntpTval ( - uint64_t Val - ); - -uint64_t -ArmReadCntpCtl ( - void - ); - -void -ArmWriteCntpCtl ( - uint64_t Val - ); - -uint64_t -ArmReadCntvTval ( - void - ); - -void -ArmWriteCntvTval ( - uint64_t Val - ); - -uint64_t -ArmReadCntvCtl ( - void - ); - -void ArmWriteCntvCtl (uint64_t Val); -uint64_t ArmReadCntvCt (void); -uint64_t ArmReadCntVctSS (void); -uint64_t ArmReadCntpCval (void); -void ArmWriteCntpCval (uint64_t Val); - -uint64_t ArmReadCntvCval (void); -void ArmWriteCntvCval (uint64_t Val); -uint64_t ArmReadCntvOff (void); -void ArmWriteCntvOff (uint64_t Val); - -uint64_t ArmReadCnthpCtl (void); -void ArmWriteCnthpCtl (uint64_t Val); -uint64_t ArmReadCnthpTval (void); -void ArmWriteCnthpTval (uint64_t Val); - -uint64_t ArmReadCnthvCtl (void); -void ArmWriteCnthvCtl (uint64_t Val); -uint64_t ArmReadCnthvTval (void); -void ArmWriteCnthvTval (uint64_t Val); void ArmGenericTimerEnableTimer (ARM_ARCH_TIMER_REGS reg); void ArmGenericTimerDisableTimer (ARM_ARCH_TIMER_REGS reg); -uint64_t ArmReadHcrEl2(void); -uint64_t ArmReadAA64MMFR1EL1(void); -uint64_t ArmReadAA64MMFR4EL1(void); - -uint64_t ArmReadCntpCtl02(void); -uint64_t ArmReadCntpTval02(void); -uint64_t ArmReadCntpCval02(void); -void ArmWriteCntpCtl02(uint64_t val); -void ArmWriteCntpTval02(uint64_t val); -void ArmWriteCntpCval02(uint64_t val); - -uint64_t ArmReadCntvTval02(void); -uint64_t ArmReadCntvCtl02(void); -uint64_t ArmReadCntvCval02(void); -void ArmWriteCntvTval02(uint64_t val); -void ArmWriteCntvCtl02(uint64_t val); -void ArmWriteCntvCval02(uint64_t val); - -uint64_t ArmReadCntkCtl12(void); -void ArmWriteCntkCtl12(uint64_t val); - #endif // __ARM_ARCH_TIMER_H__ diff --git a/val/include/val_arch.h b/val/include/val_arch.h new file mode 100644 index 00000000..1bb58a29 --- /dev/null +++ b/val/include/val_arch.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_ARCH_H +#define VAL_ARCH_H + +/* + * For those constants to be shared between C and other sources, apply a 'U', + * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid + * undefined or unintended behaviour. + * + * The GNU assembler and linker do not support these suffixes (it causes the + * build process to fail) therefore the suffix is omitted when used in linker + * scripts and assembler files. +*/ +#if defined(__LINKER__) || defined(__ASSEMBLY__) +# define U(_x) (_x) +# define UL(_x) (_x) +# define ULL(_x) (_x) +# define L(_x) (_x) +# define LL(_x) (_x) +#else +# define U(_x) (_x##U) +# define UL(_x) (_x##UL) +# define ULL(_x) (_x##ULL) +# define L(_x) (_x##L) +# define LL(_x) (_x##LL) +#endif + + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (U(1) << 0) +#define DAIF_IRQ_BIT (U(1) << 1) +#define DAIF_ABT_BIT (U(1) << 2) +#define DAIF_DBG_BIT (U(1) << 3) +#define DAIF_CONFIG (U(0x7)) + +#define PMSELR_EL0_SEL_MASK U(0x1f) + +#define EL_IMPL_NONE ULL(0) +#define MODE_EL_SHIFT U(0x2) +#define MODE_EL_MASK U(0x3) +#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) + +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_ELX_MASK ULL(0xf) + +#endif /* VAL_ARCH_H */ diff --git a/val/include/val_sysreg.h b/val/include/val_sysreg.h new file mode 100644 index 00000000..fe12d746 --- /dev/null +++ b/val/include/val_sysreg.h @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_H +#define VAL_SYSREG_H + +#include +#ifndef TARGET_UEFI +#include +#include +#endif + +#include "val_arch.h" +#include "pal_interface.h" + +typedef unsigned long u_register_t; + +#define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory") + +#ifndef __dead2 +#define __dead2 __attribute__((noreturn)) +#endif + +/********************************************************************** + * Macros to create inline functions for system instructions + *********************************************************************/ + +/* Define function for simple system instruction */ +#define SYSOP_FUNC(_op) \ +static inline void _op(void) \ +{ \ + __asm__ volatile (#_op ::: "memory"); \ +} + +/* Define function for system instruction with type specifier */ +#define SYSOP_TYPE_FUNC(_op, _type) \ +static inline void _op ## _type(void) \ +{ \ + __asm__ volatile (#_op " " #_type ::: "memory"); \ +} + +/* Define function for system instruction with register parameter */ +#define SYSOP_TYPE_PARAM_FUNC(_op, _type) \ +static inline void _op ## _type(uint64_t v) \ +{ \ + __asm__ volatile (#_op " " #_type ", %0" :: "r"(v) : "memory"); \ +} + +SYSOP_FUNC(isb) + +/********************************************************************** + * Macros which create inline functions to read or write CPU system + * registers + *********************************************************************/ + +#define _SYSREG_READ_FUNC(_name, _reg_name) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +#define _SYSREG_WRITE_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(u_register_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ + isb(); \ +} + +#define SYSREG_WRITE_CONST(reg_name, v) \ + do { \ + __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)); \ + isb(); \ + } while (0) + +/* Define read function for system register */ +#define SYSREG_READ_FUNC(_name) \ + _SYSREG_READ_FUNC(_name, _name) + +/* Define read & write function for system register */ +#define SYSREG_RW_FUNCS(_name) \ + _SYSREG_READ_FUNC(_name, _name) \ + _SYSREG_WRITE_FUNC(_name, _name) + +/* Define read & write function for renamed system register */ +#define RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ + _SYSREG_READ_FUNC(_name, _reg_name) \ + _SYSREG_WRITE_FUNC(_name, _reg_name) + +/* Define read function for renamed system register */ +#define RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ + _SYSREG_READ_FUNC(_name, _reg_name) + +/* Define write function for renamed system register */ +#define RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ + _SYSREG_WRITE_FUNC(_name, _reg_name) + +/******************************************************************************* + * TLB maintenance accessor prototypes + ******************************************************************************/ + +#if ERRATA_A57_813419 +/* + * Define function for TLBI instruction with type specifier that implements + * the workaround for errata 813419 of Cortex-A57. + */ +#define TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ +static inline void tlbi ## _type(void) \ +{ \ + __asm__("tlbi " #_type "\n" \ + "dsb ish\n" \ + "tlbi " #_type); \ +} + +/* + * Define function for TLBI instruction with register parameter that implements + * the workaround for errata 813419 of Cortex-A57. + */ +#define TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ +static inline void tlbi ## _type(uint64_t v) \ +{ \ + __asm__("tlbi " #_type ", %0\n" \ + "dsb ish\n" \ + "tlbi " #_type ", %0" : : "r" (v)); \ +} +#endif /* ERRATA_A57_813419 */ + +SYSOP_TYPE_FUNC(tlbi, alle1) +SYSOP_TYPE_FUNC(tlbi, alle1is) +SYSOP_TYPE_FUNC(tlbi, alle2) +SYSOP_TYPE_FUNC(tlbi, alle2is) +#if ERRATA_A57_813419 +TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) +TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) +#else +SYSOP_TYPE_FUNC(tlbi, alle3) +SYSOP_TYPE_FUNC(tlbi, alle3is) +#endif +SYSOP_TYPE_FUNC(tlbi, vmalle1) + +SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) +SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) +SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) +SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) +#if ERRATA_A57_813419 +TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) +TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) +#else +SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) +SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) +#endif + +/******************************************************************************* + * Cache maintenance accessor prototypes + ******************************************************************************/ +SYSOP_TYPE_PARAM_FUNC(dc, isw) +SYSOP_TYPE_PARAM_FUNC(dc, cisw) +SYSOP_TYPE_PARAM_FUNC(dc, csw) +SYSOP_TYPE_PARAM_FUNC(dc, cvac) +SYSOP_TYPE_PARAM_FUNC(dc, ivac) +SYSOP_TYPE_PARAM_FUNC(dc, civac) +SYSOP_TYPE_PARAM_FUNC(dc, cvau) +SYSOP_TYPE_PARAM_FUNC(dc, zva) + +/******************************************************************************* + * Address translation accessor prototypes + ******************************************************************************/ +SYSOP_TYPE_PARAM_FUNC(at, s12e1r) +SYSOP_TYPE_PARAM_FUNC(at, s12e1w) +SYSOP_TYPE_PARAM_FUNC(at, s12e0r) +SYSOP_TYPE_PARAM_FUNC(at, s12e0w) +SYSOP_TYPE_PARAM_FUNC(at, s1e1r) +SYSOP_TYPE_PARAM_FUNC(at, s1e2r) +SYSOP_TYPE_PARAM_FUNC(at, s1e3r) + +void flush_dcache_range(uintptr_t addr, size_t size); +void clean_dcache_range(uintptr_t addr, size_t size); +void inv_dcache_range(uintptr_t addr, size_t size); + +void dcsw_op_louis(u_register_t op_type); +void dcsw_op_all(u_register_t op_type); + +void disable_mmu(void); +void disable_mmu_icache(void); + +/******************************************************************************* + * Misc. accessor prototypes + ******************************************************************************/ + +#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) +#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) + +SYSREG_RW_FUNCS(par_el1) +SYSREG_READ_FUNC(id_aa64pfr0_el1) +SYSREG_READ_FUNC(id_afr0_el1) +SYSREG_READ_FUNC(CurrentEL) +SYSREG_RW_FUNCS(daif) +SYSREG_RW_FUNCS(nzcv) +SYSREG_READ_FUNC(spsel) +SYSREG_RW_FUNCS(spsr_el1) +SYSREG_RW_FUNCS(spsr_el2) +SYSREG_RW_FUNCS(spsr_el3) +SYSREG_RW_FUNCS(elr_el1) +SYSREG_RW_FUNCS(elr_el2) +SYSREG_RW_FUNCS(elr_el3) + +SYSOP_FUNC(wfi) +SYSOP_FUNC(wfe) +SYSOP_FUNC(sev) +SYSOP_TYPE_FUNC(dsb, sy) +SYSOP_TYPE_FUNC(dmb, sy) +SYSOP_TYPE_FUNC(dmb, st) +SYSOP_TYPE_FUNC(dmb, ld) +SYSOP_TYPE_FUNC(dsb, ish) +SYSOP_TYPE_FUNC(dsb, nsh) +SYSOP_TYPE_FUNC(dsb, ishst) +SYSOP_TYPE_FUNC(dmb, oshld) +SYSOP_TYPE_FUNC(dmb, oshst) +SYSOP_TYPE_FUNC(dmb, osh) +SYSOP_TYPE_FUNC(dmb, nshld) +SYSOP_TYPE_FUNC(dmb, nshst) +SYSOP_TYPE_FUNC(dmb, nsh) +SYSOP_TYPE_FUNC(dmb, ishld) +SYSOP_TYPE_FUNC(dmb, ishst) +SYSOP_TYPE_FUNC(dmb, ish) + +static inline void enable_irq(void) +{ + /* + * The compiler memory barrier will prevent the compiler from + * scheduling non-volatile memory access after the write to the + * register. + * + * This could happen if some initialization code issues non-volatile + * accesses to an area used by an interrupt handler, in the assumption + * that it is safe as the interrupts are disabled at the time it does + * that (according to program order). However, non-volatile accesses + * are not necessarily in program order relatively with volatile inline + * assembly statements (and volatile accesses). + */ + COMPILER_BARRIER(); + write_daifclr(DAIF_IRQ_BIT); +} + +static inline void enable_fiq(void) +{ + COMPILER_BARRIER(); + write_daifclr(DAIF_FIQ_BIT); +} + +static inline void enable_serror(void) +{ + COMPILER_BARRIER(); + write_daifclr(DAIF_ABT_BIT); +} + +static inline void enable_debug_exceptions(void) +{ + COMPILER_BARRIER(); + write_daifclr(DAIF_DBG_BIT); +} + +static inline void disable_irq(void) +{ + COMPILER_BARRIER(); + write_daifset(DAIF_IRQ_BIT); +} + +static inline void disable_fiq(void) +{ + COMPILER_BARRIER(); + write_daifset(DAIF_FIQ_BIT); +} + +static inline void disable_serror(void) +{ + COMPILER_BARRIER(); + write_daifset(DAIF_ABT_BIT); +} + +static inline void disable_debug_exceptions(void) +{ + COMPILER_BARRIER(); + write_daifset(DAIF_DBG_BIT); +} + +void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +SYSREG_READ_FUNC(id_aa64mmfr1_el1) + +SYSREG_RW_FUNCS(scr_el3) +SYSREG_RW_FUNCS(hcr_el2) + +SYSREG_RW_FUNCS(vbar_el1) +SYSREG_RW_FUNCS(vbar_el3) + +SYSREG_RW_FUNCS(actlr_el1) +SYSREG_RW_FUNCS(actlr_el2) +SYSREG_RW_FUNCS(actlr_el3) + +SYSREG_RW_FUNCS(esr_el1) +SYSREG_RW_FUNCS(esr_el3) + +SYSREG_RW_FUNCS(afsr0_el1) +SYSREG_RW_FUNCS(afsr0_el2) +SYSREG_RW_FUNCS(afsr0_el3) + +SYSREG_RW_FUNCS(afsr1_el1) +SYSREG_RW_FUNCS(afsr1_el2) +SYSREG_RW_FUNCS(afsr1_el3) + +SYSREG_RW_FUNCS(far_el1) +SYSREG_RW_FUNCS(far_el3) + +SYSREG_RW_FUNCS(mair_el3) + +SYSREG_RW_FUNCS(amair_el1) +SYSREG_RW_FUNCS(amair_el2) +SYSREG_RW_FUNCS(amair_el3) + +SYSREG_READ_FUNC(rvbar_el1) +SYSREG_READ_FUNC(rvbar_el2) +SYSREG_READ_FUNC(rvbar_el3) + +SYSREG_RW_FUNCS(rmr_el1) +SYSREG_RW_FUNCS(rmr_el2) +SYSREG_RW_FUNCS(rmr_el3) + +SYSREG_RW_FUNCS(tcr_el3) + +SYSREG_RW_FUNCS(ttbr0_el3) + +SYSREG_RW_FUNCS(vttbr_el2) + +SYSREG_RW_FUNCS(cptr_el2) +SYSREG_RW_FUNCS(cptr_el3) + +SYSREG_RW_FUNCS(cpacr_el1) +SYSREG_READ_FUNC(cntpct_el0) +SYSREG_READ_FUNC(cntvct_el0) + +#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ + CNTP_CTL_ENABLE_MASK) +#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ + CNTP_CTL_IMASK_MASK) +#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ + CNTP_CTL_ISTATUS_MASK) + +#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) + +#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) + +SYSREG_RW_FUNCS(tpidr_el3) + +SYSREG_READ_FUNC(isr_el1) + +SYSREG_RW_FUNCS(mdcr_el3) +SYSREG_RW_FUNCS(hstr_el2) + +SYSREG_RW_FUNCS(pmcntenclr_el0) +SYSREG_RW_FUNCS(pmevtyper0_el0) +SYSREG_RW_FUNCS(pmevcntr0_el0) +SYSREG_RW_FUNCS(pmselr_el0) +SYSREG_RW_FUNCS(pmuserenr_el0); +SYSREG_RW_FUNCS(pmxevtyper_el0) +SYSREG_RW_FUNCS(pmxevcntr_el0) + +/* parameterised event counter accessors */ +static inline u_register_t read_pmevcntrn_el0(uint32_t ctr_num) +{ + write_pmselr_el0(ctr_num & PMSELR_EL0_SEL_MASK); + return read_pmxevcntr_el0(); +} + +static inline void write_pmevcntrn_el0(uint32_t ctr_num, u_register_t val) +{ + write_pmselr_el0(ctr_num & PMSELR_EL0_SEL_MASK); + write_pmxevcntr_el0(val); +} + +static inline u_register_t read_pmevtypern_el0(uint32_t ctr_num) +{ + write_pmselr_el0(ctr_num & PMSELR_EL0_SEL_MASK); + return read_pmxevtyper_el0(); +} + +static inline void write_pmevtypern_el0(uint32_t ctr_num, u_register_t val) +{ + write_pmselr_el0(ctr_num & PMSELR_EL0_SEL_MASK); + write_pmxevtyper_el0(val); +} + +/* GICv3 System Registers */ + +RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) +RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) +RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) +RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) +RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) +RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) +RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) +RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) +RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) +RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) +RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) +RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) +RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) +RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) + +RENAME_SYSREG_RW_FUNCS(icv_ctrl_el1, ICV_CTRL_EL1) +RENAME_SYSREG_READ_FUNC(icv_iar1_el1, ICV_IAR1_EL1) +RENAME_SYSREG_RW_FUNCS(icv_igrpen1_el1, ICV_IGRPEN1_EL1) +RENAME_SYSREG_WRITE_FUNC(icv_eoir1_el1, ICV_EOIR1_EL1) +RENAME_SYSREG_RW_FUNCS(icv_pmr_el1, ICV_PMR_EL1) +RENAME_SYSREG_RW_FUNCS(icv_bpr0_el1, ICV_BPR0_EL1) + +RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) +RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) +RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) +RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) +RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) +RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) +RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) +RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) + +RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) +RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) + +RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) +RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) + +RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) +RENAME_SYSREG_RW_FUNCS(svcr, SVCR) +RENAME_SYSREG_RW_FUNCS(tpidr2_el0, TPIDR2_EL0) +RENAME_SYSREG_RW_FUNCS(smcr_el2, SMCR_EL2) + +RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) + +RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) +RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) + +/* Armv8.1 Registers */ +RENAME_SYSREG_RW_FUNCS(pan, PAN) + +/* Armv8.3 Pointer Authentication Registers */ +/* Instruction keys A and B */ +RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) +RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) + +RENAME_SYSREG_RW_FUNCS(apibkeyhi_el1, APIBKeyHi_EL1) +RENAME_SYSREG_RW_FUNCS(apibkeylo_el1, APIBKeyLo_EL1) + +/* Data keys A and B */ +RENAME_SYSREG_RW_FUNCS(apdakeyhi_el1, APDAKeyHi_EL1) +RENAME_SYSREG_RW_FUNCS(apdakeylo_el1, APDAKeyLo_EL1) + +RENAME_SYSREG_RW_FUNCS(apdbkeyhi_el1, APDBKeyHi_EL1) +RENAME_SYSREG_RW_FUNCS(apdbkeylo_el1, APDBKeyLo_EL1) + +/* Generic key */ +RENAME_SYSREG_RW_FUNCS(apgakeyhi_el1, APGAKeyHi_EL1) +RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) + +/* MTE registers */ +RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) +RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) +RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) +RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) + +/* Armv8.4 Data Independent Timing */ +RENAME_SYSREG_RW_FUNCS(dit, DIT) + +/* Armv8.6 Fine Grained Virtualization Traps Registers */ +RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) +RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) +RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) +RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) +RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) + +/* Armv8.6 Enhanced Counter Virtualization Register */ +RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) + +/* Armv9.0 Trace buffer extension System Registers */ +RENAME_SYSREG_RW_FUNCS(trbbaser_el1, TRBBASER_EL1) +RENAME_SYSREG_RW_FUNCS(trbsr_el1, TRBSR_EL1) +RENAME_SYSREG_RW_FUNCS(trbmar_el1, TRBMAR_EL1) +RENAME_SYSREG_RW_FUNCS(trbtrg_el1, TRBTRG_EL1) + +/* Armv8.4 Trace filter control System Registers */ +RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1) +RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) + +/* Trace System Registers */ +RENAME_SYSREG_RW_FUNCS(trcauxctlr, TRCAUXCTLR) +RENAME_SYSREG_RW_FUNCS(trcrsr, TRCRSR) +RENAME_SYSREG_RW_FUNCS(trcbbctlr, TRCBBCTLR) +RENAME_SYSREG_RW_FUNCS(trcccctlr, TRCCCCTLR) +RENAME_SYSREG_RW_FUNCS(trcextinselr0, TRCEXTINSELR0) +RENAME_SYSREG_RW_FUNCS(trcextinselr1, TRCEXTINSELR1) +RENAME_SYSREG_RW_FUNCS(trcextinselr2, TRCEXTINSELR2) +RENAME_SYSREG_RW_FUNCS(trcextinselr3, TRCEXTINSELR3) +RENAME_SYSREG_RW_FUNCS(trcclaimset, TRCCLAIMSET) +RENAME_SYSREG_RW_FUNCS(trcclaimclr, TRCCLAIMCLR) +RENAME_SYSREG_READ_FUNC(trcdevarch, TRCDEVARCH) + +/* FEAT_HCX HCRX_EL2 */ +RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) + +#define IS_IN_EL(x) \ + (GET_EL(read_CurrentEL()) == MODE_EL##x) + +#define IS_IN_EL1() IS_IN_EL(1) +#define IS_IN_EL2() IS_IN_EL(2) +#define IS_IN_EL3() IS_IN_EL(3) + +static inline unsigned int get_current_el(void) +{ + return GET_EL(read_CurrentEL()); +} + +/* + * Check if an EL is implemented from AA64PFR0 register fields. + */ +static inline uint64_t el_implemented(unsigned int el) +{ + if (el > 3U) { + return EL_IMPL_NONE; + } else { + unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; + + return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; + } +} + +/* Read the count value of the system counter. */ +static inline uint64_t syscounter_read(void) +{ + /* + * The instruction barrier is needed to guarantee that we read an + * accurate value. Otherwise, the CPU might speculatively read it and + * return a stale value. + */ + isb(); + return read_cntpct_el0(); +} + +/* Read the value of the Counter-timer virtual count. */ +static inline uint64_t virtualcounter_read(void) +{ + /* + * The instruction barrier is needed to guarantee that we read an + * accurate value. Otherwise, the CPU might speculatively read it and + * return a stale value. + */ + isb(); + return read_cntvct_el0(); +} +#endif /* VAL_SYSREG_H */ diff --git a/val/include/val_sysreg_gic.h b/val/include/val_sysreg_gic.h new file mode 100644 index 00000000..9609f83f --- /dev/null +++ b/val/include/val_sysreg_gic.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_GIC_H +#define VAL_SYSREG_GIC_H + +#include "val_sysreg.h" + +SYSREG_RW_FUNCS(ich_hcr_el2) +SYSREG_READ_FUNC(ich_misr_el2) +RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) +SYSREG_RW_FUNCS(icc_bpr1_el1) +RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) + +#endif /* VAL_SYSREG_GIC_H */ diff --git a/val/include/val_sysreg_mpam.h b/val/include/val_sysreg_mpam.h new file mode 100644 index 00000000..e8c01f7b --- /dev/null +++ b/val/include/val_sysreg_mpam.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_MPAM_H +#define VAL_SYSREG_MPAM_H + +#include "val_sysreg.h" + +SYSREG_RW_FUNCS(mpam1_el1) +RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) +RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) + +#endif /* VAL_SYSREG_MPAM_H */ diff --git a/val/include/val_sysreg_pe.h b/val/include/val_sysreg_pe.h new file mode 100644 index 00000000..7d18e45d --- /dev/null +++ b/val/include/val_sysreg_pe.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_PE_H +#define VAL_SYSREG_PE_H + +#include "val_sysreg.h" + +SYSREG_READ_FUNC(id_pfr0_el1) +SYSREG_READ_FUNC(id_pfr1_el1) +SYSREG_READ_FUNC(id_aa64isar0_el1) +SYSREG_READ_FUNC(id_aa64isar1_el1) +SYSREG_READ_FUNC(id_aa64isar2_el1) +SYSREG_READ_FUNC(id_aa64pfr1_el1) +SYSREG_READ_FUNC(id_aa64dfr0_el1) +SYSREG_READ_FUNC(id_aa64dfr1_el1) + +SYSREG_READ_FUNC(ctr_el0) + +SYSREG_READ_FUNC(midr_el1) +SYSREG_READ_FUNC(mpidr_el1) +SYSREG_READ_FUNC(id_aa64mmfr0_el1) + +SYSREG_RW_FUNCS(vbar_el2) + +SYSREG_RW_FUNCS(sctlr_el1) +SYSREG_RW_FUNCS(sctlr_el2) +SYSREG_RW_FUNCS(sctlr_el3) + +SYSREG_RW_FUNCS(esr_el2) + +SYSREG_RW_FUNCS(far_el2) + +SYSREG_RW_FUNCS(mair_el1) +SYSREG_RW_FUNCS(mair_el2) + +SYSREG_RW_FUNCS(tcr_el1) +SYSREG_RW_FUNCS(tcr_el2) + +SYSREG_RW_FUNCS(ttbr0_el1) +SYSREG_RW_FUNCS(ttbr0_el2) + +SYSREG_RW_FUNCS(ttbr1_el1) +SYSREG_READ_FUNC(ttbr1_el2) + +SYSREG_READ_FUNC(vtcr_el2) +SYSREG_RW_FUNCS(vpidr_el2) +SYSREG_RW_FUNCS(vmpidr_el2) + +SYSREG_READ_FUNC(pmbidr_el1) +SYSREG_READ_FUNC(pmsidr_el1) +SYSREG_READ_FUNC(lorid_el1) + +SYSREG_RW_FUNCS(mdcr_el2) + +SYSREG_RW_FUNCS(pmcr_el0) +SYSREG_RW_FUNCS(pmovsclr_el0) +SYSREG_RW_FUNCS(pmovsset_el0) +SYSREG_RW_FUNCS(pmintenclr_el1) +SYSREG_RW_FUNCS(pmintenset_el1) + +SYSREG_READ_FUNC(ccsidr_el1) +SYSREG_RW_FUNCS(csselr_el1) +SYSREG_READ_FUNC(clidr_el1) + +SYSREG_READ_FUNC(id_dfr0_el1) +SYSREG_READ_FUNC(id_isar0_el1) +SYSREG_READ_FUNC(id_isar1_el1) +SYSREG_READ_FUNC(id_isar2_el1) +SYSREG_READ_FUNC(id_isar3_el1) +SYSREG_READ_FUNC(id_isar4_el1) +SYSREG_READ_FUNC(id_isar5_el1) + +SYSREG_READ_FUNC(id_mmfr0_el1) +SYSREG_READ_FUNC(id_mmfr1_el1) +SYSREG_READ_FUNC(id_mmfr2_el1) +SYSREG_READ_FUNC(id_mmfr3_el1) +SYSREG_READ_FUNC(id_mmfr4_el1) + +SYSREG_READ_FUNC(mvfr0_el1) +SYSREG_READ_FUNC(mvfr1_el1) +SYSREG_READ_FUNC(mvfr2_el1) + +SYSREG_READ_FUNC(pmceid0_el0) +SYSREG_READ_FUNC(pmceid1_el0) + +SYSREG_READ_FUNC(id_aa64zfr0_el1) +SYSREG_READ_FUNC(brbidr0_el1) + +RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) +SYSREG_READ_FUNC(id_aa64mmfr3_el1) + +SYSREG_READ_FUNC(dbgbcr0_el1) +SYSREG_READ_FUNC(dbgbcr1_el1) +SYSREG_READ_FUNC(dbgbcr2_el1) +SYSREG_READ_FUNC(dbgbcr3_el1) +SYSREG_READ_FUNC(dbgbcr4_el1) +SYSREG_READ_FUNC(dbgbcr5_el1) +SYSREG_READ_FUNC(dbgbcr6_el1) +SYSREG_READ_FUNC(dbgbcr7_el1) +SYSREG_READ_FUNC(dbgbcr8_el1) +SYSREG_READ_FUNC(dbgbcr9_el1) +SYSREG_READ_FUNC(dbgbcr10_el1) +SYSREG_READ_FUNC(dbgbcr11_el1) +SYSREG_READ_FUNC(DBGBCR12_EL1) +SYSREG_READ_FUNC(dbgbcr13_el1) +SYSREG_READ_FUNC(dbgbcr14_el1) +SYSREG_READ_FUNC(dbgbcr15_el1) + +RENAME_SYSREG_RW_FUNCS(trblimitr_el1, TRBLIMITR_EL1) +RENAME_SYSREG_RW_FUNCS(trbptr_el1, TRBPTR_EL1) +RENAME_SYSREG_READ_FUNC(trbidr_el1, TRBIDR_EL1) + +SYSREG_READ_FUNC(trcidr0) +SYSREG_READ_FUNC(trcidr4) +SYSREG_READ_FUNC(trcidr5) + +SYSREG_READ_FUNC(err0fr_el1) +SYSREG_READ_FUNC(err1fr_el1) +SYSREG_READ_FUNC(err2fr_el1) +SYSREG_READ_FUNC(err3fr_el1) + +SYSREG_RW_FUNCS(pmsirr_el1) +SYSREG_RW_FUNCS(pmscr_el2) +SYSREG_RW_FUNCS(pmsfcr_el1) +SYSREG_RW_FUNCS(pmbptr_el1) + +RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) + +#endif /* VAL_SYSREG_PE_H */ diff --git a/val/include/val_sysreg_pmu_reg.h b/val/include/val_sysreg_pmu_reg.h new file mode 100644 index 00000000..aef456fa --- /dev/null +++ b/val/include/val_sysreg_pmu_reg.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_PMU_REG_H +#define VAL_SYSREG_PMU_REG_H + +#include "val_sysreg.h" + +SYSREG_RW_FUNCS(pmcntenset_el0) +SYSREG_RW_FUNCS(pmccntr_el0) +SYSREG_RW_FUNCS(pmccfiltr_el0) + +#endif /* VAL_SYSREG_PMU_REG_H */ diff --git a/val/include/val_sysreg_ras.h b/val/include/val_sysreg_ras.h new file mode 100644 index 00000000..7298b786 --- /dev/null +++ b/val/include/val_sysreg_ras.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_RAS_H +#define VAL_SYSREG_RAS_H + +#include "val_sysreg.h" + +RENAME_SYSREG_RW_FUNCS(errselr_el1, ERRSELR_EL1) + +RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) +RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) +RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) +RENAME_SYSREG_RW_FUNCS(erxaddr_el1, ERXADDR_EL1) + +SYSREG_READ_FUNC(erxpfgf_el1) +SYSREG_RW_FUNCS(erxpfgctl_el1) +SYSREG_RW_FUNCS(erxpfgcdn_el1) + +#endif /* VAL_SYSREG_RAS_H */ diff --git a/val/include/val_sysreg_timer.h b/val/include/val_sysreg_timer.h new file mode 100644 index 00000000..d9538712 --- /dev/null +++ b/val/include/val_sysreg_timer.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef VAL_SYSREG_TIMER_H +#define VAL_SYSREG_TIMER_H + +#include "val_sysreg.h" + +SYSREG_READ_FUNC(s3_0_c0_c7_4) +SYSREG_RW_FUNCS(cntfrq_el0) +SYSREG_RW_FUNCS(cnthp_ctl_el2) +SYSREG_RW_FUNCS(cnthp_tval_el2) +SYSREG_RW_FUNCS(cnthv_ctl_el2) +SYSREG_RW_FUNCS(cnthv_tval_el2) +SYSREG_RW_FUNCS(cnthp_cval_el2) +SYSREG_RW_FUNCS(cntps_ctl_el1) +SYSREG_RW_FUNCS(cntps_tval_el1) +SYSREG_RW_FUNCS(cntps_cval_el1) +SYSREG_RW_FUNCS(cntp_ctl_el0) +SYSREG_RW_FUNCS(cntp_ctl_el02) +SYSREG_RW_FUNCS(cntp_tval_el0) +SYSREG_RW_FUNCS(cntp_tval_el02) +SYSREG_RW_FUNCS(cntp_cval_el0) +SYSREG_RW_FUNCS(cntp_cval_el02) +SYSREG_READ_FUNC(cntpctss_el0) +SYSREG_RW_FUNCS(cntv_ctl_el0) +SYSREG_RW_FUNCS(cntv_ctl_el02) +SYSREG_RW_FUNCS(cntv_tval_el0) +SYSREG_RW_FUNCS(cntv_tval_el02) +SYSREG_RW_FUNCS(cntv_cval_el0) +SYSREG_RW_FUNCS(cntv_cval_el02) +SYSREG_READ_FUNC(cntvctss_el0) +SYSREG_RW_FUNCS(cnthctl_el2) +SYSREG_RW_FUNCS(cntkctl_el1) +SYSREG_RW_FUNCS(cntkctl_el12) +SYSREG_RW_FUNCS(cntvoff_el2) + +#endif /* VAL_SYSREG_TIMER_H */ diff --git a/val/src/AArch64/ArchTimerSupport.S b/val/src/AArch64/ArchTimerSupport.S deleted file mode 100644 index ed1964bc..00000000 --- a/val/src/AArch64/ArchTimerSupport.S +++ /dev/null @@ -1,296 +0,0 @@ -#/** @file -# Copyright (c) 2016-2018,2023-2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -/* Private worker functions for ASM_PFX() */ -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -/* The __USER_LABEL_PREFIX__ macro predefined by GNUC represents - the prefix on symbols in assembly language.*/ -#define __USER_LABEL_PREFIX__ - -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 2 - -GCC_ASM_EXPORT(ArmReadHcrEl2) -GCC_ASM_EXPORT(ArmReadAA64MMFR1EL1) -GCC_ASM_EXPORT(ArmReadAA64MMFR4EL1) -GCC_ASM_EXPORT(ArmReadCntFrq) -GCC_ASM_EXPORT(ArmReadCntPct) -GCC_ASM_EXPORT(ArmReadCntPctSS) -GCC_ASM_EXPORT(ArmReadCntkCtl) -GCC_ASM_EXPORT(ArmWriteCntkCtl) -GCC_ASM_EXPORT(ArmReadCntkCtl12) -GCC_ASM_EXPORT(ArmWriteCntkCtl12) -GCC_ASM_EXPORT(ArmReadCntpTval) -GCC_ASM_EXPORT(ArmWriteCntpTval) -GCC_ASM_EXPORT(ArmReadCntpTval02) -GCC_ASM_EXPORT(ArmWriteCntpTval02) -GCC_ASM_EXPORT(ArmReadCntpCtl) -GCC_ASM_EXPORT(ArmReadCntpCtl02) -GCC_ASM_EXPORT(ArmReadCntvTval) -GCC_ASM_EXPORT(ArmWriteCntvTval) -GCC_ASM_EXPORT(ArmReadCntvTval02) -GCC_ASM_EXPORT(ArmWriteCntvTval02) -GCC_ASM_EXPORT(ArmReadCntvCtl) -GCC_ASM_EXPORT(ArmWriteCntvCtl) -GCC_ASM_EXPORT(ArmReadCntvCtl02) -GCC_ASM_EXPORT(ArmWriteCntvCtl02) -GCC_ASM_EXPORT(ArmReadCntvCt) -GCC_ASM_EXPORT(ArmReadCntVctSS) -GCC_ASM_EXPORT(ArmReadCntpCval) -GCC_ASM_EXPORT(ArmWriteCntpCval) -GCC_ASM_EXPORT(ArmReadCntpCval02) -GCC_ASM_EXPORT(ArmWriteCntpCval02) -GCC_ASM_EXPORT(ArmReadCntvCval) -GCC_ASM_EXPORT(ArmWriteCntvCval) -GCC_ASM_EXPORT(ArmReadCntvCval02) -GCC_ASM_EXPORT(ArmWriteCntvCval02) -GCC_ASM_EXPORT(ArmReadCntvOff) -GCC_ASM_EXPORT(ArmWriteCntvOff) -GCC_ASM_EXPORT(ArmReadCnthpCtl) -GCC_ASM_EXPORT(ArmWriteCnthpCtl) -GCC_ASM_EXPORT(ArmReadCnthpTval) -GCC_ASM_EXPORT(ArmWriteCnthpTval) -GCC_ASM_EXPORT(ArmReadCnthvCtl) -GCC_ASM_EXPORT(ArmWriteCnthvCtl) -GCC_ASM_EXPORT(ArmReadCnthvTval) -GCC_ASM_EXPORT(ArmWriteCnthvTval) -GCC_ASM_EXPORT(ArmWriteCntpCtl) -GCC_ASM_EXPORT(ArmWriteCntpCtl02) - -ASM_PFX(ArmReadHcrEl2): - mrs x0, hcr_el2 // Read HCR_EL2 - ret - -ASM_PFX(ArmReadAA64MMFR1EL1): - mrs x0, id_aa64mmfr1_el1 // Read ID_AA64MMFR1_EL1 - ret - -ASM_PFX(ArmReadAA64MMFR4EL1): - //mrs x0, id_aa64mmfr4_el1 // Read ID_AA64MMFR4_EL1 - mrs x0, s3_0_c0_c7_4 - ret - -ASM_PFX(ArmReadCntFrq): - mrs x0, cntfrq_el0 // Read CNTFRQ - ret - - -ASM_PFX(ArmReadCntPct): - mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register) - ret - -ASM_PFX(ArmReadCntPctSS): - mrs x0, cntpctss_el0 // Read CNTPCTSS_EL0 (Physical Count register, self-synchronized) - ret - -ASM_PFX(ArmReadCntkCtl): - mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register) - ret - -ASM_PFX(ArmReadCntkCtl12): - mrs x0, cntkctl_el12 // Read CNTK_CTL (Timer PL1 Control Register) when EL2 Host - ret - -ASM_PFX(ArmWriteCntkCtl): - msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register) - isb - ret - -ASM_PFX(ArmWriteCntkCtl12): - msr cntkctl_el12, x0 // Write to CNTK_CTL (Timer PL1 Control Register) when EL2 Host - isb - ret - -ASM_PFX(ArmReadCntpTval): - mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register) - ret - -ASM_PFX(ArmReadCntpTval02): - mrs x0, cntp_tval_el02 // Read CNTP_TVAL (PL1 physical timer value register) when EL2 Host - ret - -ASM_PFX(ArmWriteCntpTval): - msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register) - isb - ret - -ASM_PFX(ArmWriteCntpTval02): - msr cntp_tval_el02, x0 // Write to CNTP_TVAL (PL1 physical timer value register) EL2 Host - isb - ret - -ASM_PFX(ArmReadCntpCtl): - mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register) - ret - -ASM_PFX(ArmReadCntpCtl02): - mrs x0, cntp_ctl_el02 // Read CNTP_CTL (PL1 Physical Timer Control Register) when EL2 Host - ret - - -ASM_PFX(ArmWriteCntpCtl): - msr cntp_ctl_el0, x0 // Write CNTP_CTL (PL1 Physical Timer Control Register) - isb - ret - -ASM_PFX(ArmWriteCntpCtl02): - msr cntp_ctl_el02, x0 // Write CNTP_CTL (PL1 Physical Timer Control Register) when EL2 Host - isb - ret - -ASM_PFX(ArmReadCntvTval): - mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register) - ret - -ASM_PFX(ArmReadCntvTval02): - mrs x0, cntv_tval_el02 // Read CNTV_TVAL_EL02 (Virtual Timer Value register) - ret - -ASM_PFX(ArmWriteCntvTval): - msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register) - isb - ret - -ASM_PFX(ArmWriteCntvTval02): - msr cntv_tval_el02, x0 // Write to CNTV_TVAL_EL02 (Virtual Timer Value register) - isb - ret - -ASM_PFX(ArmReadCntvCtl): - mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register) - ret - -ASM_PFX(ArmReadCntvCtl02): - mrs x0, cntv_ctl_el02 // Read CNTV_CTL_EL02 (Virtual Timer Control Register) - ret - -ASM_PFX(ArmWriteCntvCtl): - msr cntv_ctl_el0, x0 // Write to CNTV_CTL (Virtual Timer Control Register) - isb - ret - -ASM_PFX(ArmWriteCntvCtl02): - msr cntv_ctl_el02, x0 // Write to CNTV_CTL_EL02 (Virtual Timer Control Register) - isb - ret - -ASM_PFX(ArmReadCntvCt): - mrs x0, cntvct_el0 // Read CNTVCT (Virtual Count Register) - ret - - -ASM_PFX(ArmReadCntVctSS): - mrs x0, cntvctss_el0 // Read CNTVCTSS_EL0 (Virtual Count register, self-synchronized) - ret - -ASM_PFX(ArmReadCntpCval): - mrs x0, cntp_cval_el0 // Read CNTP_CTVAL (Physical Timer Compare Value Register) - ret - -ASM_PFX(ArmReadCntpCval02): - mrs x0, cntp_cval_el02 // Read CNTP_CTVAL_EL02 (Physical Timer Compare Value Register) - ret - -ASM_PFX(ArmWriteCntpCval): - msr cntp_cval_el0, x0 // Write to CNTP_CTVAL (Physical Timer Compare Value Register) - isb - ret - -ASM_PFX(ArmWriteCntpCval02): - msr cntp_cval_el02, x0 // Write to CNTP_CTVAL_EL02 (Physical Timer Compare Value Register) - isb - ret - -ASM_PFX(ArmReadCntvCval): - mrs x0, cntv_cval_el0 // Read CNTV_CTVAL (Virtual Timer Compare Value Register) - ret - -ASM_PFX(ArmReadCntvCval02): - mrs x0, cntv_cval_el02 // Read CNTV_CTVAL_EL02 (Virtual Timer Compare Value Register) - ret - -ASM_PFX(ArmWriteCntvCval): - msr cntv_cval_el0, x0 // write to CNTV_CTVAL (Virtual Timer Compare Value Register) - isb - ret - -ASM_PFX(ArmWriteCntvCval02): - msr cntv_cval_el02, x0 // write to CNTV_CTVAL_EL02 (Virtual Timer Compare Value Register) - isb - ret - -ASM_PFX(ArmReadCntvOff): - mrs x0, cntvoff_el2 // Read CNTVOFF (virtual Offset register) - ret - - -ASM_PFX(ArmWriteCntvOff): - msr cntvoff_el2, x0 // Write to CNTVOFF (Virtual Offset register) - isb - ret - -ASM_PFX(ArmReadCnthpCtl): - mrs x0, cnthp_ctl_el2 - ret - - -ASM_PFX(ArmWriteCnthpCtl): - msr cnthp_ctl_el2, x0 - isb - ret - -ASM_PFX(ArmReadCnthpTval): - mrs x0, cnthp_tval_el2 - ret - - -ASM_PFX(ArmWriteCnthpTval): - msr cnthp_tval_el2, x0 - isb - ret - -ASM_PFX(ArmReadCnthvCtl): - mrs x0, cnthv_ctl_el2 - ret - - -ASM_PFX(ArmWriteCnthvCtl): - msr cnthv_ctl_el2, x0 - isb - ret - -ASM_PFX(ArmReadCnthvTval): - mrs x0, cnthv_tval_el2 - ret - - -ASM_PFX(ArmWriteCnthvTval): - msr cnthv_tval_el2, x0 - isb - ret \ No newline at end of file diff --git a/val/src/AArch64/GicSupport.S b/val/src/AArch64/GicSupport.S deleted file mode 100644 index e3087228..00000000 --- a/val/src/AArch64/GicSupport.S +++ /dev/null @@ -1,95 +0,0 @@ -#/** @file -# Copyright (c) 2016-2018,2023-2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -/* Private worker functions for ASM_PFX() */ -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -/* The __USER_LABEL_PREFIX__ macro predefined by GNUC represents - the prefix on symbols in assembly language.*/ -#define __USER_LABEL_PREFIX__ - -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 2 - -GCC_ASM_EXPORT(GicReadIchHcr) -GCC_ASM_EXPORT(GicWriteIchHcr) -GCC_ASM_EXPORT(GicReadIchMisr) -GCC_ASM_EXPORT(GicWriteIccIgrpen1) -GCC_ASM_EXPORT(GicWriteIccBpr1) -GCC_ASM_EXPORT(GicWriteIccPmr) -GCC_ASM_EXPORT(GicClearDaif) -GCC_ASM_EXPORT(GicWriteHcr) -GCC_ASM_EXPORT(TestExecuteBarrier) - -ASM_PFX(GicReadIchHcr): - //mrs_s x0, ich_hcr_el2 - .inst 0xd53ccb00 - ret - -ASM_PFX(GicWriteIchHcr): - //msr ich_hcr_el2, x0 - .inst 0xd51ccb00 - isb - ret - -ASM_PFX(GicReadIchMisr): - //mrs x0, ich_misr_el2 - .inst 0xd53ccb40 - ret - -ASM_PFX(GicWriteIccIgrpen1): - //msr icc_igrpen1_el1, x0 - .inst 0xd518cce0 - isb - ret - -ASM_PFX(GicWriteIccBpr1): - //msr icc_brp1_el1, x0 - .inst 0xd518cc60 - isb - ret - -ASM_PFX(GicWriteIccPmr): - //msr icc_pmr_el1, x0 - .inst 0xd5184600 - isb - ret - -ASM_PFX(GicClearDaif): - msr daifclr, 0x7 - isb - ret - -ASM_PFX(GicWriteHcr): - msr hcr_el2, x0 - ret - -ASM_PFX(TestExecuteBarrier): - dsb sy - isb - ret diff --git a/val/src/AArch64/MpamSupport.S b/val/src/AArch64/MpamSupport.S deleted file mode 100644 index 7a4a0d1a..00000000 --- a/val/src/AArch64/MpamSupport.S +++ /dev/null @@ -1,66 +0,0 @@ -#/** @file -# Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -// -// Private worker functions for ASM_PFX() -// -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -#define __USER_LABEL_PREFIX__ -// -// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix -// on symbols in assembly language. -// -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 2 - -GCC_ASM_EXPORT(AA64ReadMpam1) -GCC_ASM_EXPORT(AA64WriteMpam1) -GCC_ASM_EXPORT(AA64ReadMpam2) -GCC_ASM_EXPORT(AA64WriteMpam2) -GCC_ASM_EXPORT(AA64ReadMpamidr) - -ASM_PFX(AA64ReadMpam1): - mrs x0, mpam1_el1 - ret - -ASM_PFX(AA64WriteMpam1): - msr mpam1_el1, x0 - ret - -ASM_PFX(AA64ReadMpam2): - mrs x0, mpam2_el2 - ret - -ASM_PFX(AA64WriteMpam2): - msr mpam2_el2, x0 - ret - -ASM_PFX(AA64ReadMpamidr): - mrs x0, mpamidr_el1 - ret diff --git a/val/src/AArch64/PeRegSysSupport.S b/val/src/AArch64/PeRegSysSupport.S index a59fec95..a5d9f397 100644 --- a/val/src/AArch64/PeRegSysSupport.S +++ b/val/src/AArch64/PeRegSysSupport.S @@ -38,403 +38,17 @@ .align 3 -GCC_ASM_EXPORT (ArmReadMpidr) -GCC_ASM_EXPORT (ArmReadIdPfr0) -GCC_ASM_EXPORT (ArmReadIdPfr1) -GCC_ASM_EXPORT (AA64ReadMmfr0) -GCC_ASM_EXPORT (AA64ReadMmfr1) -GCC_ASM_EXPORT (AA64ReadMmfr2) -GCC_ASM_EXPORT (AA64ReadMmfr3) -GCC_ASM_EXPORT (AA64ReadCtr) -GCC_ASM_EXPORT (ArmReadMmfr0) -GCC_ASM_EXPORT (AA64ReadIsar0) -GCC_ASM_EXPORT (AA64ReadIsar1) -GCC_ASM_EXPORT (AA64ReadIsar2) -GCC_ASM_EXPORT (AA64ReadSctlr3) -GCC_ASM_EXPORT (AA64ReadSctlr2) -GCC_ASM_EXPORT (AA64ReadSctlr1) -GCC_ASM_EXPORT (AA64ReadPmcr) -GCC_ASM_EXPORT (AA64ReadIdDfr0) -GCC_ASM_EXPORT (AA64ReadIdDfr1) -GCC_ASM_EXPORT (AA64ReadCurrentEL) -GCC_ASM_EXPORT (AA64ReadIdMdrar) -GCC_ASM_EXPORT (AA64ReadMdcr2) -GCC_ASM_EXPORT (AA64WriteMdcr2) -GCC_ASM_EXPORT (AA64ReadVbar2) -GCC_ASM_EXPORT (AA64WriteVbar2) -GCC_ASM_EXPORT (AA64WritePmcr) -GCC_ASM_EXPORT (AA64WritePmovsset) -GCC_ASM_EXPORT (AA64WritePmintenset) -GCC_ASM_EXPORT (AA64WritePmovsclr) -GCC_ASM_EXPORT (AA64WritePmintenclr) -GCC_ASM_EXPORT (AA64ReadCcsidr) -GCC_ASM_EXPORT (AA64ReadCsselr) -GCC_ASM_EXPORT (AA64WriteCsselr) -GCC_ASM_EXPORT (AA64ReadClidr) -GCC_ASM_EXPORT (ArmReadDfr0) -GCC_ASM_EXPORT (ArmReadIsar0) -GCC_ASM_EXPORT (ArmReadIsar1) -GCC_ASM_EXPORT (ArmReadIsar2) -GCC_ASM_EXPORT (ArmReadIsar3) -GCC_ASM_EXPORT (ArmReadIsar4) -GCC_ASM_EXPORT (ArmReadIsar5) -GCC_ASM_EXPORT (ArmReadMmfr0) -GCC_ASM_EXPORT (ArmReadMmfr1) -GCC_ASM_EXPORT (ArmReadMmfr2) -GCC_ASM_EXPORT (ArmReadMmfr3) -GCC_ASM_EXPORT (ArmReadMmfr4) -GCC_ASM_EXPORT (ArmReadPfr0) -GCC_ASM_EXPORT (ArmReadPfr1) -GCC_ASM_EXPORT (ArmReadMidr) -GCC_ASM_EXPORT (ArmReadMvfr0) -GCC_ASM_EXPORT (ArmReadMvfr1) -GCC_ASM_EXPORT (ArmReadMvfr2) -GCC_ASM_EXPORT (AA64ReadPmceid0) -GCC_ASM_EXPORT (AA64ReadPmceid1) -GCC_ASM_EXPORT (AA64ReadVmpidr) -GCC_ASM_EXPORT (AA64ReadVpidr) -GCC_ASM_EXPORT (AA64ReadPmbidr) -GCC_ASM_EXPORT (AA64ReadPmsidr) -GCC_ASM_EXPORT (AA64ReadLorid) -GCC_ASM_EXPORT (AA64ReadErridr) -GCC_ASM_EXPORT (AA64ReadErr0fr) -GCC_ASM_EXPORT (AA64ReadErr1fr) -GCC_ASM_EXPORT (AA64ReadErr2fr) -GCC_ASM_EXPORT (AA64ReadErr3fr) -GCC_ASM_EXPORT (AA64WritePmsirr) -GCC_ASM_EXPORT (AA64WritePmscr2) -GCC_ASM_EXPORT (AA64WritePmsfcr) -GCC_ASM_EXPORT (AA64WritePmbptr) -GCC_ASM_EXPORT (AA64WritePmblimitr) -GCC_ASM_EXPORT (AA64ReadEsr2) GCC_ASM_EXPORT (AA64ReadSp) GCC_ASM_EXPORT (AA64WriteSp) -GCC_ASM_EXPORT (AA64ReadFar2) GCC_ASM_EXPORT (ArmRdvl) -GCC_ASM_EXPORT (AA64ReadMair1) -GCC_ASM_EXPORT (AA64ReadMair2) -GCC_ASM_EXPORT (AA64ReadTcr1) -GCC_ASM_EXPORT (AA64ReadTcr2) -GCC_ASM_EXPORT (AA64ReadTtbr0El1) -GCC_ASM_EXPORT (AA64ReadTtbr0El2) -GCC_ASM_EXPORT (AA64ReadTtbr1El1) -GCC_ASM_EXPORT (AA64ReadTtbr1El2) -GCC_ASM_EXPORT (AA64ReadDbgbcr0El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr1El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr2El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr3El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr4El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr5El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr6El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr7El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr8El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr9El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr10El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr11El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr12El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr13El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr14El1) -GCC_ASM_EXPORT (AA64ReadDbgbcr15El1) -GCC_ASM_EXPORT (AA64ReadZfr0) -GCC_ASM_EXPORT (AA64ReadBrbidr0) -GCC_ASM_EXPORT (AA64ReadTrbidr) -GCC_ASM_EXPORT (AA64ReadTrcidr0) -GCC_ASM_EXPORT (AA64ReadTrcidr4) -GCC_ASM_EXPORT (AA64ReadTrcidr5) -GCC_ASM_EXPORT (AA64ReadVtcr) GCC_ASM_EXPORT (AA64SetupTraceAccess) GCC_ASM_EXPORT (AA64EnableETETrace) GCC_ASM_EXPORT (AA64EnableTRBUTrace) GCC_ASM_EXPORT (AA64GenerateETETrace) GCC_ASM_EXPORT (AA64DisableTRBUTrace) GCC_ASM_EXPORT (AA64DisableETETrace) -GCC_ASM_EXPORT (AA64ReadTrbPtrEl1) GCC_ASM_EXPORT (AA64EnableTFO) GCC_ASM_EXPORT (AA64DisableTFO) -GCC_ASM_EXPORT (AA64ReadTrblimitr1) -GCC_ASM_EXPORT (AA64WriteTrblimitr1) -GCC_ASM_EXPORT (AA64IssueISB) - -ASM_PFX(ArmReadMpidr): - mrs x0, mpidr_el1 // read EL1 MPIDR - ret - -ASM_PFX(ArmReadIdPfr0): - mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register - ret - -ASM_PFX(ArmReadIdPfr1): - mrs x0, id_aa64pfr1_el1 // Read ID_AA64PFR0 Register - ret - -ASM_PFX(AA64ReadMmfr0): - mrs x0, id_aa64mmfr0_el1 - ret - -ASM_PFX(AA64ReadMmfr1): - mrs x0, id_aa64mmfr1_el1 - ret - -ASM_PFX(AA64ReadMmfr2): - mrs x0, id_aa64mmfr2_el1 - ret - -ASM_PFX(AA64ReadMmfr3): - mrs x0, id_aa64mmfr3_el1 - ret - -ASM_PFX(AA64ReadCtr): - mrs x0, ctr_el0 - ret - -ASM_PFX(AA64ReadIsar0): - mrs x0, id_aa64isar0_el1 - ret - -ASM_PFX(AA64ReadIsar1): - mrs x0, id_aa64isar1_el1 - ret - -ASM_PFX(AA64ReadIsar2): - mrs x0, id_aa64isar2_el1 - ret - -ASM_PFX(AA64ReadSctlr3): - mrs x0, sctlr_el3 - ret - -ASM_PFX(AA64ReadSctlr2): - mrs x0, sctlr_el2 - ret - -ASM_PFX(AA64ReadSctlr1): - mrs x0, sctlr_el1 - ret - -ASM_PFX(AA64ReadPmcr): - mrs x0, pmcr_el0 - ret - -ASM_PFX(AA64ReadIdDfr0): - mrs x0, id_aa64dfr0_el1 - ret - -ASM_PFX(AA64ReadIdDfr1): - mrs x0, id_aa64dfr1_el1 - ret - -ASM_PFX(AA64ReadCurrentEL): - mrs x0, CurrentEL - ret - -ASM_PFX(AA64ReadMdcr2): - mrs x0, mdcr_el2 - ret - -ASM_PFX(AA64WriteMdcr2): - msr mdcr_el2, x0 - isb - ret - -ASM_PFX(AA64ReadVbar2): - mrs x0, vbar_el2 - ret - -ASM_PFX(AA64WriteVbar2): - msr vbar_el2, x0 - isb - ret - -ASM_PFX(AA64WritePmcr): - msr pmcr_el0, x0 - isb - ret - -ASM_PFX(AA64WritePmovsset): - msr pmovsset_el0, x0 - isb - ret - -ASM_PFX(AA64WritePmovsclr): - msr pmovsclr_el0, x0 - isb - ret - -ASM_PFX(AA64WritePmintenset): - msr pmintenset_el1, x0 - isb - ret - -ASM_PFX(AA64WritePmintenclr): - msr pmintenclr_el1, x0 - isb - ret - -ASM_PFX(AA64ReadCcsidr): - mrs x0, ccsidr_el1 - ret - -ASM_PFX(AA64ReadCsselr): - mrs x0, csselr_el1 - ret - -ASM_PFX(AA64WriteCsselr): - msr csselr_el1, x0 - isb - ret - -ASM_PFX(AA64ReadClidr): - mrs x0, clidr_el1 - ret - -ASM_PFX(ArmReadDfr0): - mrs x0, id_dfr0_el1 - ret - -ASM_PFX(ArmReadIsar0): - mrs x0, id_isar0_el1 - ret - -ASM_PFX(ArmReadIsar1): - mrs x0, id_isar1_el1 - ret - -ASM_PFX(ArmReadIsar2): - mrs x0, id_isar2_el1 - ret - -ASM_PFX(ArmReadIsar3): - mrs x0, id_isar3_el1 - ret - -ASM_PFX(ArmReadIsar4): - mrs x0, id_isar4_el1 - ret - -ASM_PFX(ArmReadIsar5): - mrs x0, id_isar5_el1 - ret - -ASM_PFX(ArmReadMmfr0): - mrs x0, id_mmfr0_el1 - ret - -ASM_PFX(ArmReadMmfr1): - mrs x0, id_mmfr1_el1 - ret - -ASM_PFX(ArmReadMmfr2): - mrs x0, id_mmfr2_el1 - ret - -ASM_PFX(ArmReadMmfr3): - mrs x0, id_mmfr3_el1 - ret - -ASM_PFX(ArmReadMmfr4): - mrs x0, id_mmfr4_el1 - ret - -ASM_PFX(ArmReadPfr0): - mrs x0, id_pfr0_el1 - ret - -ASM_PFX(ArmReadPfr1): - mrs x0, id_pfr1_el1 - ret - -ASM_PFX(ArmReadMidr): - mrs x0, midr_el1 - ret - -ASM_PFX(ArmReadMvfr0): - mrs x0, mvfr0_el1 - ret - -ASM_PFX(ArmReadMvfr1): - mrs x0, mvfr1_el1 - ret - -ASM_PFX(ArmReadMvfr2): - mrs x0, mvfr2_el1 - ret - -ASM_PFX(AA64ReadPmceid0): - mrs x0, pmceid0_el0 - ret - -ASM_PFX(AA64ReadPmceid1): - mrs x0, pmceid1_el0 - ret - -ASM_PFX(AA64ReadVmpidr): - mrs x0, vmpidr_el2 - ret - -ASM_PFX(AA64ReadVpidr): - mrs x0, vpidr_el2 - ret - -ASM_PFX(AA64ReadPmbidr): - mrs x0, pmbidr_el1 - ret - -ASM_PFX(AA64ReadPmsidr): - mrs x0, pmsidr_el1 - ret - -ASM_PFX(AA64ReadLorid): - mrs x0, lorid_el1 - ret - -ASM_PFX(AA64ReadErridr): - mrs x0, erridr_el1 - ret - -ASM_PFX(AA64ReadErr0fr): - // mrs x0, err0fr_el1 - ret - -ASM_PFX(AA64ReadErr1fr): - //mrs x0, err1fr_el1 - ret - -ASM_PFX(AA64ReadErr2fr): - //mrs x0, err2fr_el1 - ret - -ASM_PFX(AA64ReadErr3fr): - //mrs x0, err3fr_el1 - ret - -ASM_PFX(AA64WritePmsirr): - //mrs pmsirr_el1,x0 - isb - ret - -ASM_PFX(AA64WritePmscr2): - //mrs pmscr_el2,x0 - isb - ret - -ASM_PFX(AA64WritePmsfcr): - //mrs pmsfcr_el1,x0 - isb - ret - -ASM_PFX(AA64WritePmbptr): - //mrs pmbptr_el1,x0 - isb - ret - -ASM_PFX(AA64WritePmblimitr): - //mrs pmblimitr_el1,x0 - isb - ret - -ASM_PFX(AA64ReadEsr2): - mrs x0, esr_el2 - ret ASM_PFX(AA64ReadSp): mov x0, sp @@ -444,148 +58,11 @@ ASM_PFX(AA64WriteSp): mov sp, x0 ret -ASM_PFX(AA64ReadFar2): - mrs x0, far_el2 - ret - -ASM_PFX(AA64ReadMair1): - mrs x0, mair_el1 // read EL1 MAIR - ret - -ASM_PFX(AA64ReadMair2): - mrs x0, mair_el2 // read EL2 MAIR - ret - -ASM_PFX(AA64ReadTcr1): - mrs x0, tcr_el1 // read EL1 TCR - ret - -ASM_PFX(AA64ReadTcr2): - mrs x0, tcr_el2 // read EL2 TCR - ret - -ASM_PFX(AA64ReadTtbr0El2): - mrs x0, ttbr0_el2 // read EL2 TTBR0 - ret - -ASM_PFX(AA64ReadTtbr1El2): - mrs x0, ttbr1_el2 // read EL2 TTBR1 - ret - -ASM_PFX(AA64ReadTtbr0El1): - mrs x0, ttbr0_el1 // read EL1 TTBR0 - ret - -ASM_PFX(AA64ReadTtbr1El1): - mrs x0, ttbr1_el1 // read EL1 TTBR1 - ret - ASM_PFX(ArmRdvl): //RDVL x0, #8 // TODO once instruction supports Read Vector Length .inst 0x04BF5100 ret - ASM_PFX(AA64ReadDbgbcr0El1): - mrs x0, dbgbcr0_el1 // read EL1 DBGBCR0 - ret - -ASM_PFX(AA64ReadDbgbcr1El1): - mrs x0, dbgbcr1_el1 // read EL1 DBGBCR1 - ret - -ASM_PFX(AA64ReadDbgbcr2El1): - mrs x0, dbgbcr2_el1 // read EL1 DBGBCR2 - ret - -ASM_PFX(AA64ReadDbgbcr3El1): - mrs x0, dbgbcr3_el1 // read EL1 DBGBCR3 - ret - -ASM_PFX(AA64ReadDbgbcr4El1): - mrs x0, dbgbcr4_el1 // read EL1 DBGBCR4 - ret - -ASM_PFX(AA64ReadDbgbcr5El1): - mrs x0, dbgbcr5_el1 // read EL1 DBGBCR5 - ret - -ASM_PFX(AA64ReadDbgbcr6El1): - mrs x0, dbgbcr6_el1 // read EL1 DBGBCR6 - ret - -ASM_PFX(AA64ReadDbgbcr7El1): - mrs x0, dbgbcr7_el1 // read EL1 DBGBCR7 - ret - -ASM_PFX(AA64ReadDbgbcr8El1): - mrs x0, dbgbcr8_el1 // read EL1 DBGBCR8 - ret - -ASM_PFX(AA64ReadDbgbcr9El1): - mrs x0, dbgbcr9_el1 // read EL1 DBGBCR9 - ret - -ASM_PFX(AA64ReadDbgbcr10El1): - mrs x0, dbgbcr10_el1 // read EL1 DBGBCR10 - ret - -ASM_PFX(AA64ReadDbgbcr11El1): - mrs x0, dbgbcr11_el1 // read EL1 DBGBCR11 - ret - -ASM_PFX(AA64ReadDbgbcr12El1): - mrs x0, DBGBCR12_EL1 // read EL1 DBGBCR12 - ret - -ASM_PFX(AA64ReadDbgbcr13El1): - mrs x0, dbgbcr13_el1 // read EL1 DBGBCR13 - ret - -ASM_PFX(AA64ReadDbgbcr14El1): - mrs x0, dbgbcr14_el1 // read EL1 DBGBCR14 - ret - -ASM_PFX(AA64ReadDbgbcr15El1): - mrs x0, dbgbcr15_el1 // read EL1 DBGBCR15 - ret - -ASM_PFX(AA64ReadZfr0): - mrs x0, id_aa64zfr0_el1 - ret - -ASM_PFX(AA64ReadBrbidr0): - mrs x0, brbidr0_el1 - ret - -ASM_PFX(AA64ReadTrbidr): - mrs x0, trbidr_el1 - ret - -ASM_PFX(AA64ReadTrcidr0): - mrs x0, trcidr0 - ret - -ASM_PFX(AA64ReadTrcidr4): - mrs x0, trcidr4 - ret - -ASM_PFX(AA64ReadTrcidr5): - mrs x0, trcidr5 - ret - -ASM_PFX(AA64ReadVtcr): - mrs x0, vtcr_el2 - ret - -ASM_PFX(AA64ReadTrblimitr1): - mrs x0, TRBLIMITR_EL1 - ret - -ASM_PFX(AA64WriteTrblimitr1): - msr TRBLIMITR_EL1, x0 - isb - ret - ASM_PFX(AA64SetupTraceAccess): // Allows TRBU reg writes from EL1 and EL2 // Programming of MDCR_EL3.NSTB = 0b11 is done in arm-tf @@ -728,14 +205,6 @@ ASM_PFX(AA64DisableETETrace): CMP x2, xzr B return1 -ASM_PFX(AA64ReadTrbPtrEl1): - mrs x0, TRBPTR_EL1 - ret - -ASM_PFX(AA64IssueISB): - isb - ret - // MMU register write functions for secondary PE initialization GCC_ASM_EXPORT (AA64WriteMair1) diff --git a/val/src/AArch64/PeTestSupport.S b/val/src/AArch64/PeTestSupport.S index bea84544..0d75d46e 100644 --- a/val/src/AArch64/PeTestSupport.S +++ b/val/src/AArch64/PeTestSupport.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2019, 2022-2025, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2019, 2022-2026, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,15 +36,8 @@ .text .align 3 -GCC_ASM_EXPORT (ArmCallWFI) GCC_ASM_EXPORT (SpeProgramUnderProfiling) GCC_ASM_EXPORT (DisableSpe) -GCC_ASM_EXPORT (ArmExecuteMemoryBarrier) -GCC_ASM_EXPORT (AA64IssueDSB) - -ASM_PFX(ArmCallWFI): - wfi - ret ASM_PFX(SpeProgramUnderProfiling): mov x2,#12 // No of instructions in the loop @@ -82,11 +75,3 @@ ASM_PFX(DisableSpe): isb ret - -ASM_PFX(ArmExecuteMemoryBarrier): - dmb sy - ret - -ASM_PFX(AA64IssueDSB): - dsb sy - ret diff --git a/val/src/AArch64/PmuRegSupport.S b/val/src/AArch64/PmuRegSupport.S deleted file mode 100644 index 3782bc61..00000000 --- a/val/src/AArch64/PmuRegSupport.S +++ /dev/null @@ -1,83 +0,0 @@ -#/** @file -# Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -// -// Private worker functions for ASM_PFX() -// -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -#define __USER_LABEL_PREFIX__ -// -// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix -// on symbols in assembly language. -// -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -.text -.align 3 - -//GCC_ASM_EXPORT (AA64ReadPmcr) -GCC_ASM_EXPORT (AA64ReadPmccntr) -GCC_ASM_EXPORT (AA64ReadPmccfiltr) -GCC_ASM_EXPORT (AA64ReadPmcntenset) -//GCC_ASM_EXPORT (AA64WritePmcr) -GCC_ASM_EXPORT (AA64WritePmccntr) -GCC_ASM_EXPORT (AA64WritePmccfiltr) -GCC_ASM_EXPORT (AA64WritePmcntenset) - - -//ASM_PFX(AA64ReadPmcr): -// mrs x0, pmcr_el0 -// ret - -ASM_PFX(AA64ReadPmccntr): - mrs x0, pmccntr_el0 - ret - -ASM_PFX(AA64ReadPmccfiltr): - mrs x0, pmccfiltr_el0 - ret - -ASM_PFX(AA64ReadPmcntenset): - mrs x0, pmcntenset_el0 - ret - -//ASM_PFX(AA64WritePmcr): -// msr pmcr_el0, x0 -// isb -// ret - -ASM_PFX(AA64WritePmccntr): - msr pmccntr_el0, x0 - isb - ret - -ASM_PFX(AA64WritePmccfiltr): - msr pmccfiltr_el0, x0 - isb - ret - -ASM_PFX(AA64WritePmcntenset): - msr pmcntenset_el0, x0 - isb - ret diff --git a/val/src/AArch64/RasSupport.S b/val/src/AArch64/RasSupport.S deleted file mode 100644 index 26fe00fa..00000000 --- a/val/src/AArch64/RasSupport.S +++ /dev/null @@ -1,117 +0,0 @@ -#/** @file -# Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -// -// Private worker functions for ASM_PFX() -// -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -#define __USER_LABEL_PREFIX__ -// -// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix -// on symbols in assembly language. -// -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 2 - -GCC_ASM_EXPORT(AA64ReadErrIdr1) -GCC_ASM_EXPORT(AA64ReadErrAddr1) -GCC_ASM_EXPORT(AA64WriteErrAddr1) -GCC_ASM_EXPORT(AA64ReadErrCtlr1) -GCC_ASM_EXPORT(AA64WriteErrCtlr1) -GCC_ASM_EXPORT(AA64ReadErrFr1) -GCC_ASM_EXPORT(AA64ReadErrStatus1) -GCC_ASM_EXPORT(AA64WriteErrStatus1) -GCC_ASM_EXPORT(AA64ReadErrSelr1) -GCC_ASM_EXPORT(AA64WriteErrSelr1) -GCC_ASM_EXPORT(AA64ReadErrPfgf1) -GCC_ASM_EXPORT(AA64ReadErrPfgctl1) -GCC_ASM_EXPORT(AA64ReadErrPfgcdn1) -GCC_ASM_EXPORT(AA64WriteErrPfgctl1) -GCC_ASM_EXPORT(AA64WriteErrPfgcdn1) - - -ASM_PFX(AA64ReadErrIdr1): - mrs x0, erridr_el1 - ret - -ASM_PFX(AA64ReadErrAddr1): - mrs x0, erxaddr_el1 - ret - -ASM_PFX(AA64WriteErrAddr1): - msr erxaddr_el1, x0 - ret - -ASM_PFX(AA64ReadErrCtlr1): - mrs x0, erxctlr_el1 - ret - -ASM_PFX(AA64WriteErrCtlr1): - msr erxctlr_el1, x0 - ret - -ASM_PFX(AA64ReadErrFr1): - mrs x0, erxfr_el1 - ret - -ASM_PFX(AA64ReadErrStatus1): - mrs x0, erxstatus_el1 - ret - -ASM_PFX(AA64WriteErrStatus1): - msr erxstatus_el1, x0 - ret - -ASM_PFX(AA64ReadErrSelr1): - mrs x0, errselr_el1 - ret - -ASM_PFX(AA64WriteErrSelr1): - msr errselr_el1, x0 - ret - -ASM_PFX(AA64ReadErrPfgf1): - mrs x0, erxpfgf_el1 - ret - -ASM_PFX(AA64ReadErrPfgctl1): - mrs x0, erxpfgctl_el1 - ret - -ASM_PFX(AA64WriteErrPfgctl1): - msr erxpfgctl_el1, x0 - ret - -ASM_PFX(AA64ReadErrPfgcdn1): - mrs x0, erxpfgcdn_el1 - ret - -ASM_PFX(AA64WriteErrPfgcdn1): - msr erxpfgcdn_el1, x0 - ret diff --git a/val/src/AArch64/generic_sysreg_support.S b/val/src/AArch64/generic_sysreg_support.S deleted file mode 100644 index c4a15b61..00000000 --- a/val/src/AArch64/generic_sysreg_support.S +++ /dev/null @@ -1,407 +0,0 @@ -#/** @file -# Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -// -// Private worker functions for ASM_PFX() -// -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -#define __USER_LABEL_PREFIX__ -// -// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix -// on symbols in assembly language. -// -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - - -.text -.align 3 - - -GCC_ASM_EXPORT (arm64_read_mpidr) -GCC_ASM_EXPORT (arm64_read_idpfr0) -GCC_ASM_EXPORT (arm64_read_idpfr1) -GCC_ASM_EXPORT (arm64_read_mmfr0) -GCC_ASM_EXPORT (arm64_read_mmfr1) -GCC_ASM_EXPORT (arm64_read_mmfr2) -GCC_ASM_EXPORT (arm64_read_ctr) -GCC_ASM_EXPORT (arm64_read_isar0) -GCC_ASM_EXPORT (arm64_read_isar1) -GCC_ASM_EXPORT (arm64_read_sctlr3) -GCC_ASM_EXPORT (arm64_read_sctlr2) -GCC_ASM_EXPORT (arm64_read_pmcr) -GCC_ASM_EXPORT (arm64_read_iddfr0) -GCC_ASM_EXPORT (arm64_read_iddfr1) -GCC_ASM_EXPORT (arm_read_hcr) -GCC_ASM_EXPORT (arm64_read_cur_el) -GCC_ASM_EXPORT (AA64ReadIdMdrar) -GCC_ASM_EXPORT (arm64_read_mdcr2) -GCC_ASM_EXPORT (arm64_write_mdcr2) -GCC_ASM_EXPORT (arm64_read_vbar2) -GCC_ASM_EXPORT (arm64_write_vbar2) -GCC_ASM_EXPORT (arm64_write_pmcr) -GCC_ASM_EXPORT (arm64_write_pmovsset) -GCC_ASM_EXPORT (arm64_write_pmintenset) -GCC_ASM_EXPORT (arm64_write_pmovsclr) -GCC_ASM_EXPORT (arm64_write_pmintenclr) -GCC_ASM_EXPORT (arm64_read_ccsidr) -GCC_ASM_EXPORT (arm64_read_csselr) -GCC_ASM_EXPORT (arm64_write_csselr) -GCC_ASM_EXPORT (arm64_read_clidr) -GCC_ASM_EXPORT (arm_read_dfr0) -GCC_ASM_EXPORT (arm_read_isar0) -GCC_ASM_EXPORT (arm_read_isar1) -GCC_ASM_EXPORT (arm_read_isar2) -GCC_ASM_EXPORT (arm_read_isar3) -GCC_ASM_EXPORT (arm_read_isar4) -GCC_ASM_EXPORT (arm_read_isar5) -GCC_ASM_EXPORT (arm_read_midr) -GCC_ASM_EXPORT (arm_read_mvfr0) -GCC_ASM_EXPORT (arm_read_mvfr1) -GCC_ASM_EXPORT (arm_read_mvfr2) -GCC_ASM_EXPORT (arm64_read_pmceid0) -GCC_ASM_EXPORT (arm64_read_pmceid1) -GCC_ASM_EXPORT (arm64_read_vmpidr) -GCC_ASM_EXPORT (arm64_read_vpidr) -GCC_ASM_EXPORT (arm64_read_pmbidr) -GCC_ASM_EXPORT (arm64_read_pmsidr) -GCC_ASM_EXPORT (arm64_read_lorid) -GCC_ASM_EXPORT (arm64_read_erridr) -GCC_ASM_EXPORT (arm64_read_err0fr) -GCC_ASM_EXPORT (arm64_read_err1fr) -GCC_ASM_EXPORT (arm64_read_err2fr) -GCC_ASM_EXPORT (arm64_read_err3fr) -GCC_ASM_EXPORT (arm64_write_pmsirr) -GCC_ASM_EXPORT (arm64_write_pmscr2) -GCC_ASM_EXPORT (arm64_write_pmsfcr) -GCC_ASM_EXPORT (arm64_write_pmbptr) -GCC_ASM_EXPORT (arm64_write_pmblimitr) -GCC_ASM_EXPORT (arm64_read_esr2) -GCC_ASM_EXPORT (arm64_read_sp) -GCC_ASM_EXPORT (arm64_write_sp) -GCC_ASM_EXPORT (arm64_read_far2) -GCC_ASM_EXPORT (arm64_read_pmccntr) -GCC_ASM_EXPORT (arm64_read_pmccfiltr) -GCC_ASM_EXPORT (arm64_read_pmcntenset) -GCC_ASM_EXPORT (arm64_write_pmccntr) -GCC_ASM_EXPORT (arm64_write_pmccfiltr) -GCC_ASM_EXPORT (arm64_write_pmcntenset) -GCC_ASM_EXPORT (arm64_issue_dmb) -GCC_ASM_EXPORT (arm64_issue_dsb) -GCC_ASM_EXPORT (arm64_issue_isb) - -ASM_PFX(arm64_read_mpidr): - mrs x0, mpidr_el1 // read EL1 MPIDR - ret - -ASM_PFX(arm64_read_idpfr0): - mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register - ret - -ASM_PFX(arm64_read_idpfr1): - mrs x0, id_aa64pfr1_el1 // Read ID_AA64PFR0 Register - ret - -ASM_PFX(arm64_read_mmfr0): - mrs x0, id_aa64mmfr0_el1 - ret - -ASM_PFX(arm64_read_mmfr1): - mrs x0, id_aa64mmfr1_el1 - ret - -ASM_PFX(arm64_read_mmfr2): - mrs x0, id_aa64mmfr2_el1 - ret - -ASM_PFX(arm64_read_ctr): - mrs x0, ctr_el0 - ret - -ASM_PFX(arm64_read_isar0): - mrs x0, id_aa64isar0_el1 - ret - -ASM_PFX(arm64_read_isar1): - mrs x0, id_aa64isar1_el1 - ret - -ASM_PFX(arm64_read_sctlr3): - mrs x0, sctlr_el3 - ret - -ASM_PFX(arm64_read_sctlr2): - mrs x0, sctlr_el2 - ret - -ASM_PFX(arm64_read_pmcr): - mrs x0, pmcr_el0 - ret - -ASM_PFX(arm64_read_iddfr0): - mrs x0, id_aa64dfr0_el1 - ret - -ASM_PFX(arm64_read_iddfr1): - mrs x0, id_aa64dfr1_el1 - ret - -ASM_PFX(arm_read_hcr): - mrs x0, hcr_el2 - ret - -ASM_PFX(arm64_read_cur_el): - mrs x0, CurrentEL - ret - -ASM_PFX(arm64_read_mdcr2): - mrs x0, mdcr_el2 - ret - -ASM_PFX(arm64_write_mdcr2): - msr mdcr_el2, x0 - isb - ret - -ASM_PFX(arm64_read_vbar2): - mrs x0, vbar_el2 - ret - -ASM_PFX(arm64_write_vbar2): - msr vbar_el2, x0 - isb - ret - -ASM_PFX(arm64_write_pmcr): - msr pmcr_el0, x0 - isb - ret - -ASM_PFX(arm64_write_pmovsset): - msr pmovsset_el0, x0 - isb - ret - -ASM_PFX(arm64_write_pmovsclr): - msr pmovsclr_el0, x0 - isb - ret - -ASM_PFX(arm64_write_pmintenset): - msr pmintenset_el1, x0 - isb - ret - -ASM_PFX(arm64_write_pmintenclr): - msr pmintenclr_el1, x0 - isb - ret - -ASM_PFX(arm64_read_ccsidr): - mrs x0, ccsidr_el1 - ret - -ASM_PFX(arm64_read_csselr): - mrs x0, csselr_el1 - ret - -ASM_PFX(arm64_write_csselr): - msr csselr_el1, x0 - isb - ret - -ASM_PFX(arm64_read_clidr): - mrs x0, clidr_el1 - ret - -ASM_PFX(arm_read_dfr0): - mrs x0, id_dfr0_el1 - ret - -ASM_PFX(arm_read_isar0): - mrs x0, id_isar0_el1 - ret - -ASM_PFX(arm_read_isar1): - mrs x0, id_isar1_el1 - ret - -ASM_PFX(arm_read_isar2): - mrs x0, id_isar2_el1 - ret - -ASM_PFX(arm_read_isar3): - mrs x0, id_isar3_el1 - ret - -ASM_PFX(arm_read_isar4): - mrs x0, id_isar4_el1 - ret - -ASM_PFX(arm_read_isar5): - mrs x0, id_isar5_el1 - ret - -ASM_PFX(arm_read_midr): - mrs x0, midr_el1 - ret - -ASM_PFX(arm_read_mvfr0): - mrs x0, mvfr0_el1 - ret - -ASM_PFX(arm_read_mvfr1): - mrs x0, mvfr1_el1 - ret - -ASM_PFX(arm_read_mvfr2): - mrs x0, mvfr2_el1 - ret - -ASM_PFX(arm64_read_pmceid0): - mrs x0, pmceid0_el0 - ret - -ASM_PFX(arm64_read_pmceid1): - mrs x0, pmceid1_el0 - ret - -ASM_PFX(arm64_read_vmpidr): - mrs x0, vmpidr_el2 - ret - -ASM_PFX(arm64_read_vpidr): - mrs x0, vpidr_el2 - ret - -ASM_PFX(arm64_read_pmbidr): - //mrs x0, pmbidr_el1 - ret - -ASM_PFX(arm64_read_pmsidr): - //mrs x0, pmsidr_el1 - ret - -ASM_PFX(arm64_read_lorid): - //mrs x0, lorid_el1 - ret - -ASM_PFX(arm64_read_erridr): - //mrs x0, erridr_el1 - ret - -ASM_PFX(arm64_read_err0fr): - // mrs x0, err0fr_el1 - ret - -ASM_PFX(arm64_read_err1fr): - //mrs x0, err1fr_el1 - ret - -ASM_PFX(arm64_read_err2fr): - //mrs x0, err2fr_el1 - ret - -ASM_PFX(arm64_read_err3fr): - //mrs x0, err3fr_el1 - ret - -ASM_PFX(arm64_write_pmsirr): - //mrs pmsirr_el1,x0 - isb - ret - -ASM_PFX(arm64_write_pmscr2): - //mrs pmscr_el2,x0 - isb - ret - -ASM_PFX(arm64_write_pmsfcr): - //mrs pmsfcr_el1,x0 - isb - ret - -ASM_PFX(arm64_write_pmbptr): - //mrs pmbptr_el1,x0 - isb - ret - -ASM_PFX(arm64_write_pmblimitr): - //mrs pmblimitr_el1,x0 - isb - ret - -ASM_PFX(arm64_read_esr2): - mrs x0, esr_el2 - ret - -ASM_PFX(arm64_read_sp): - mov x0, sp - ret - -ASM_PFX(arm64_write_sp): - mov sp, x0 - ret - -ASM_PFX(arm64_read_far2): - mrs x0, far_el2 - ret - -ASM_PFX(arm64_read_pmccntr): - mrs x0, pmccntr_el0 - ret - -ASM_PFX(arm64_read_pmccfiltr): - mrs x0, pmccfiltr_el0 - ret - -ASM_PFX(arm64_read_pmcntenset): - mrs x0, pmcntenset_el0 - ret - -ASM_PFX(arm64_write_pmccntr): - msr pmccntr_el0, x0 - isb - ret - -ASM_PFX(arm64_write_pmccfiltr): - msr pmccfiltr_el0, x0 - isb - ret - -ASM_PFX(arm64_write_pmcntenset): - msr pmcntenset_el0, x0 - isb - ret - -ASM_PFX(arm64_issue_dmb): - dmb sy - ret - -ASM_PFX(arm64_issue_dsb): - dsb sy - ret - -ASM_PFX(arm64_issue_isb): - isb - ret From dbc7d0406be92bfb17b62dd631578a64990d9080 Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Thu, 19 Feb 2026 12:19:06 +0000 Subject: [PATCH 03/13] Update ACS to comply with inline Sysreg helper refactoring - Point existing headers at the new Sysreg helpers and remove numerous old prototypes - Modified all function callers to the new inline accessors - These changes have been made as a part of Unified VAL Signed-off-by: Avi Nawal Change-Id: Id308002dcc1eb4d3f447d2c7e4e8b9df62fbb53d --- apps/uefi/Bsa.inf | 2 +- apps/uefi/Drtm.inf | 2 +- apps/uefi/Mem.inf | 2 +- apps/uefi/Mpam.inf | 2 +- apps/uefi/Pfdi.inf | 2 +- apps/uefi/Sbsa.inf | 2 +- apps/uefi/SbsaNist.inf | 2 +- apps/uefi/Vbsa.inf | 2 +- apps/uefi/pc_bsa.inf | 2 +- apps/uefi/xbsa_acpi.inf | 2 +- pal/baremetal/base/src/pal_pe.c | 37 ++--- pal/uefi_acpi/PalLib.inf | 2 +- pal/uefi_acpi/SbsaPalNistLib.inf | 2 +- pal/uefi_acpi/src/pal_pe.c | 36 ++--- pal/uefi_dt/PalLib.inf | 2 +- pal/uefi_dt/src/pal_pe.c | 36 ++--- test_pool/ete/ete003.c | 8 +- test_pool/ete/ete004.c | 4 +- test_pool/mpam/error002.c | 2 +- test_pool/mpam/error004.c | 2 +- test_pool/timer/t008.c | 12 +- val/ValLib.inf | 8 +- val/ValLibRB.inf | 8 +- val/driver/gic/its/acs_gic_its.c | 13 +- val/driver/gic/v2/gic_v2.c | 4 +- val/driver/gic/v3/gic_v3.c | 8 +- val/driver/gic/v3/gic_v3_extended.c | 2 +- val/driver/smmu_v3/smmu_v3.c | 2 +- val/include/pal_interface.h | 6 + val/src/acs_ete.c | 4 +- val/src/acs_gic_support.c | 12 +- val/src/acs_memory.c | 2 +- val/src/acs_mpam.c | 10 +- val/src/acs_msc_error.c | 2 +- val/src/acs_pcie.c | 2 +- val/src/acs_pe.c | 216 ++++++++++++++-------------- val/src/acs_pmu.c | 16 +-- val/src/acs_ras.c | 26 ++-- val/src/acs_timer_support.c | 74 +++++----- val/src/acs_wakeup.c | 2 +- val/src/rule_based_orchestrator.c | 4 +- 41 files changed, 272 insertions(+), 312 deletions(-) diff --git a/apps/uefi/Bsa.inf b/apps/uefi/Bsa.inf index 61d1a4a9..d9a4d5b5 100644 --- a/apps/uefi/Bsa.inf +++ b/apps/uefi/Bsa.inf @@ -358,4 +358,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.1-a+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/Drtm.inf b/apps/uefi/Drtm.inf index f8968e0f..65de40a0 100644 --- a/apps/uefi/Drtm.inf +++ b/apps/uefi/Drtm.inf @@ -95,4 +95,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -DTARGET_UEFI $(ACS_DRTM_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse -DTARGET_UEFI $(ACS_DRTM_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) diff --git a/apps/uefi/Mem.inf b/apps/uefi/Mem.inf index 9585c649..8c82d7d2 100644 --- a/apps/uefi/Mem.inf +++ b/apps/uefi/Mem.inf @@ -215,4 +215,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a - GCC:*_*_*_CC_FLAGS = -g -gdwarf-4 $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -mstrict-align -march=armv8.2-a -O0 $(MEM_TEST_KVM_INCLUDE_FLAGS) $(MEM_TEST_DEFINE_FLAGS) + GCC:*_*_*_CC_FLAGS = -g -gdwarf-4 $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -mstrict-align -march=armv8.6-a+sve+profile+lse -O0 $(MEM_TEST_KVM_INCLUDE_FLAGS) $(MEM_TEST_DEFINE_FLAGS) diff --git a/apps/uefi/Mpam.inf b/apps/uefi/Mpam.inf index 2a6e1933..eebb35c7 100644 --- a/apps/uefi/Mpam.inf +++ b/apps/uefi/Mpam.inf @@ -111,4 +111,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/Pfdi.inf b/apps/uefi/Pfdi.inf index 17205e24..b9ad87a8 100644 --- a/apps/uefi/Pfdi.inf +++ b/apps/uefi/Pfdi.inf @@ -100,4 +100,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/Sbsa.inf b/apps/uefi/Sbsa.inf index 8a3919ff..7a90174e 100644 --- a/apps/uefi/Sbsa.inf +++ b/apps/uefi/Sbsa.inf @@ -363,4 +363,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.1-a+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/SbsaNist.inf b/apps/uefi/SbsaNist.inf index 15ff9547..a2156207 100644 --- a/apps/uefi/SbsaNist.inf +++ b/apps/uefi/SbsaNist.inf @@ -251,4 +251,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.1-a+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/Vbsa.inf b/apps/uefi/Vbsa.inf index 2e19a355..96cb286a 100644 --- a/apps/uefi/Vbsa.inf +++ b/apps/uefi/Vbsa.inf @@ -361,4 +361,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.1-a+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/pc_bsa.inf b/apps/uefi/pc_bsa.inf index 65ce3864..3dab32e6 100644 --- a/apps/uefi/pc_bsa.inf +++ b/apps/uefi/pc_bsa.inf @@ -361,4 +361,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.1-a+lse -DPC_BSA $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse -DPC_BSA $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/apps/uefi/xbsa_acpi.inf b/apps/uefi/xbsa_acpi.inf index e30dd2b1..a68840ec 100644 --- a/apps/uefi/xbsa_acpi.inf +++ b/apps/uefi/xbsa_acpi.inf @@ -359,4 +359,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS+ = -march=armv8.5-a+lse+ls2 - GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.5-a+lse -DPC_BSA $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse -DPC_BSA $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/pal/baremetal/base/src/pal_pe.c b/pal/baremetal/base/src/pal_pe.c index 0b4888b6..463d450e 100644 --- a/pal/baremetal/base/src/pal_pe.c +++ b/pal/baremetal/base/src/pal_pe.c @@ -18,7 +18,7 @@ #include "pal_common_support.h" #include "pal_pcie_enum.h" #include "platform_override_struct.h" - +#include "pal_sysreg.h" extern const PE_INFO_TABLE platform_pe_cfg; extern const PE_SMBIOS_PROCESSOR_INFO_TABLE platform_smbios_cfg; @@ -35,19 +35,6 @@ uint64_t gMpidrMax; **/ static PE_MMU_CONFIG gMmuConfig __attribute__((aligned(64))); -/* External assembly functions for reading MMU registers */ -uint64_t AA64ReadCurrentEL(void); -uint64_t AA64ReadTtbr0El1(void); -uint64_t AA64ReadTtbr0El2(void); -uint64_t AA64ReadTtbr1El1(void); -uint64_t AA64ReadTtbr1El2(void); -uint64_t AA64ReadTcr1(void); -uint64_t AA64ReadTcr2(void); -uint64_t AA64ReadMair1(void); -uint64_t AA64ReadMair2(void); -uint64_t AA64ReadSctlr1(void); -uint64_t AA64ReadSctlr2(void); - #define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core #define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) @@ -171,23 +158,23 @@ PalCaptureMmuConfig(void) uint64_t CurrentEl; /* Read current exception level */ - CurrentEl = (AA64ReadCurrentEL() >> 2) & 0x3; + CurrentEl = (read_CurrentEL() >> 2) & 0x3; gMmuConfig.current_el = (uint32_t)CurrentEl; /* Read MMU configuration registers based on current EL */ if (CurrentEl == 2) { - gMmuConfig.ttbr0 = AA64ReadTtbr0El2(); - gMmuConfig.ttbr1 = AA64ReadTtbr1El2(); - gMmuConfig.tcr = AA64ReadTcr2(); - gMmuConfig.mair = AA64ReadMair2(); - gMmuConfig.sctlr = AA64ReadSctlr2(); + gMmuConfig.ttbr0 = read_ttbr0_el2(); + gMmuConfig.ttbr1 = read_ttbr1_el2(); + gMmuConfig.tcr = read_tcr_el2(); + gMmuConfig.mair = read_mair_el2(); + gMmuConfig.sctlr = read_sctlr_el2(); } else { /* Assume EL1 */ - gMmuConfig.ttbr0 = AA64ReadTtbr0El1(); - gMmuConfig.ttbr1 = AA64ReadTtbr1El1(); - gMmuConfig.tcr = AA64ReadTcr1(); - gMmuConfig.mair = AA64ReadMair1(); - gMmuConfig.sctlr = AA64ReadSctlr1(); + gMmuConfig.ttbr0 = read_ttbr0_el1(); + gMmuConfig.ttbr1 = read_ttbr1_el1(); + gMmuConfig.tcr = read_tcr_el1(); + gMmuConfig.mair = read_mair_el1(); + gMmuConfig.sctlr = read_sctlr_el1(); } print(ACS_PRINT_INFO, " MMU Config captured at EL%d\n", gMmuConfig.current_el); diff --git a/pal/uefi_acpi/PalLib.inf b/pal/uefi_acpi/PalLib.inf index 5b2e132d..263cd8ce 100644 --- a/pal/uefi_acpi/PalLib.inf +++ b/pal/uefi_acpi/PalLib.inf @@ -84,4 +84,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a -D__ASSEMBLY__ -D__ASSEMBLER__ - GCC:*_*_*_CC_FLAGS = -O0 $(PAL_UEFI_ACPI_INCLUDE_FLAGS) + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(PAL_UEFI_ACPI_INCLUDE_FLAGS) diff --git a/pal/uefi_acpi/SbsaPalNistLib.inf b/pal/uefi_acpi/SbsaPalNistLib.inf index da1931c8..e229d775 100644 --- a/pal/uefi_acpi/SbsaPalNistLib.inf +++ b/pal/uefi_acpi/SbsaPalNistLib.inf @@ -85,5 +85,5 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a - GCC:*_*_*_CC_FLAGS = -O0 $(PAL_NIST_INCLUDE_FLAGS) + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(PAL_NIST_INCLUDE_FLAGS) diff --git a/pal/uefi_acpi/src/pal_pe.c b/pal/uefi_acpi/src/pal_pe.c index 82b0094f..0101ad5e 100644 --- a/pal/uefi_acpi/src/pal_pe.c +++ b/pal/uefi_acpi/src/pal_pe.c @@ -26,6 +26,7 @@ #include #include "pal_uefi.h" +#include "pal_sysreg.h" static EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *gMadtHdr; UINT8 *gSecondaryPeStack; @@ -40,19 +41,6 @@ extern INT32 gPsciConduit; **/ static PE_MMU_CONFIG gMmuConfig __attribute__((aligned(64))); -/* External assembly functions for reading MMU registers */ -UINT64 AA64ReadCurrentEL(VOID); -UINT64 AA64ReadTtbr0El1(VOID); -UINT64 AA64ReadTtbr0El2(VOID); -UINT64 AA64ReadTtbr1El1(VOID); -UINT64 AA64ReadTtbr1El2(VOID); -UINT64 AA64ReadTcr1(VOID); -UINT64 AA64ReadTcr2(VOID); -UINT64 AA64ReadMair1(VOID); -UINT64 AA64ReadMair2(VOID); -UINT64 AA64ReadSctlr1(VOID); -UINT64 AA64ReadSctlr2(VOID); - #define MAX_NUM_OF_SMBIOS_SLOTS_SUPPORTED 1024 #define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core #define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) @@ -241,29 +229,29 @@ PalCaptureMmuConfig(VOID) UINT32 SkipTtbr1; /* Read current exception level */ - CurrentEl = (AA64ReadCurrentEL() >> 2) & 0x3; + CurrentEl = (read_CurrentEL() >> 2) & 0x3; gMmuConfig.current_el = (UINT32)CurrentEl; /* Read MMU configuration registers based on current EL */ if (CurrentEl == 2) { - gMmuConfig.ttbr0 = AA64ReadTtbr0El2(); - gMmuConfig.tcr = AA64ReadTcr2(); - gMmuConfig.mair = AA64ReadMair2(); - gMmuConfig.sctlr = AA64ReadSctlr2(); + gMmuConfig.ttbr0 = read_ttbr0_el2(); + gMmuConfig.tcr = read_tcr_el2(); + gMmuConfig.mair = read_mair_el2(); + gMmuConfig.sctlr = read_sctlr_el2(); /* Read TTBR1_EL2 only if TCR_EL2 allows translation via TTBR1 (EPD1 bit[23]) */ SkipTtbr1 = (gMmuConfig.tcr >> TCR_EPD1_BIT) & 0x1; if (!SkipTtbr1) - gMmuConfig.ttbr1 = AA64ReadTtbr1El2(); + gMmuConfig.ttbr1 = read_ttbr1_el2(); } else { /* Assume EL1 */ - gMmuConfig.ttbr0 = AA64ReadTtbr0El1(); - gMmuConfig.tcr = AA64ReadTcr1(); - gMmuConfig.mair = AA64ReadMair1(); - gMmuConfig.sctlr = AA64ReadSctlr1(); + gMmuConfig.ttbr0 = read_ttbr0_el1(); + gMmuConfig.tcr = read_tcr_el1(); + gMmuConfig.mair = read_mair_el1(); + gMmuConfig.sctlr = read_sctlr_el1(); /* Read TTBR1_EL1 only if TCR_EL1 allows translation via TTBR1 (EPD1 bit[23]) */ SkipTtbr1 = (gMmuConfig.tcr >> TCR_EPD1_BIT) & 0x1; if (!SkipTtbr1) - gMmuConfig.ttbr1 = AA64ReadTtbr1El1(); + gMmuConfig.ttbr1 = read_ttbr1_el1(); } acs_print(ACS_PRINT_DEBUG, L" MMU Config captured at EL%d\n", gMmuConfig.current_el); diff --git a/pal/uefi_dt/PalLib.inf b/pal/uefi_dt/PalLib.inf index dbaa0541..86f8a771 100644 --- a/pal/uefi_dt/PalLib.inf +++ b/pal/uefi_dt/PalLib.inf @@ -83,4 +83,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a -D__ASSEMBLY__ -D__ASSEMBLER__ - GCC:*_*_*_CC_FLAGS = -O0 $(PAL_UEFI_DT_INCLUDE_FLAGS) $(BASE_FDT_LIB_INCLUDE_FLAGS) + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(PAL_UEFI_DT_INCLUDE_FLAGS) $(BASE_FDT_LIB_INCLUDE_FLAGS) diff --git a/pal/uefi_dt/src/pal_pe.c b/pal/uefi_dt/src/pal_pe.c index 392d2c7d..e3661695 100644 --- a/pal/uefi_dt/src/pal_pe.c +++ b/pal/uefi_dt/src/pal_pe.c @@ -29,6 +29,7 @@ #include "pal_uefi.h" #include "pal_dt.h" #include "pal_dt_spec.h" +#include "pal_sysreg.h" UINT8 *gSecondaryPeStack; UINT64 gMpidrMax; @@ -44,19 +45,6 @@ pal_strncmp(CHAR8 *str1, CHAR8 *str2, UINT32 len); **/ static PE_MMU_CONFIG gMmuConfig __attribute__((aligned(64))); -/* External assembly functions for reading MMU registers */ -UINT64 AA64ReadCurrentEL(VOID); -UINT64 AA64ReadTtbr0El1(VOID); -UINT64 AA64ReadTtbr0El2(VOID); -UINT64 AA64ReadTtbr1El1(VOID); -UINT64 AA64ReadTtbr1El2(VOID); -UINT64 AA64ReadTcr1(VOID); -UINT64 AA64ReadTcr2(VOID); -UINT64 AA64ReadMair1(VOID); -UINT64 AA64ReadMair2(VOID); -UINT64 AA64ReadSctlr1(VOID); -UINT64 AA64ReadSctlr2(VOID); - static char pmu_dt_arr[][PMU_COMPATIBLE_STR_LEN] = { "arm,armv8-pmuv3", "arm,cortex-a78-pmu", @@ -284,29 +272,29 @@ PalCaptureMmuConfig(VOID) UINT32 SkipTtbr1; /* Read current exception level */ - CurrentEl = (AA64ReadCurrentEL() >> 2) & 0x3; + CurrentEl = (read_CurrentEL() >> 2) & 0x3; gMmuConfig.current_el = (UINT32)CurrentEl; /* Read MMU configuration registers based on current EL */ if (CurrentEl == 2) { - gMmuConfig.ttbr0 = AA64ReadTtbr0El2(); - gMmuConfig.tcr = AA64ReadTcr2(); - gMmuConfig.mair = AA64ReadMair2(); - gMmuConfig.sctlr = AA64ReadSctlr2(); + gMmuConfig.ttbr0 = read_ttbr0_el2(); + gMmuConfig.tcr = read_tcr_el2(); + gMmuConfig.mair = read_mair_el2(); + gMmuConfig.sctlr = read_sctlr_el2(); /* Read TTBR1_EL2 only if TCR_EL2 allows translation via TTBR1 (EPD1 bit[23]) */ SkipTtbr1 = (gMmuConfig.tcr >> TCR_EPD1_BIT) & 0x1; if (!SkipTtbr1) - gMmuConfig.ttbr1 = AA64ReadTtbr1El2(); + gMmuConfig.ttbr1 = read_ttbr1_el2(); } else { /* Assume EL1 */ - gMmuConfig.ttbr0 = AA64ReadTtbr0El1(); - gMmuConfig.tcr = AA64ReadTcr1(); - gMmuConfig.mair = AA64ReadMair1(); - gMmuConfig.sctlr = AA64ReadSctlr1(); + gMmuConfig.ttbr0 = read_ttbr0_el1(); + gMmuConfig.tcr = read_tcr_el1(); + gMmuConfig.mair = read_mair_el1(); + gMmuConfig.sctlr = read_sctlr_el1(); /* Read TTBR1_EL1 only if TCR_EL1 allows translation via TTBR1 (EPD1 bit[23]) */ SkipTtbr1 = (gMmuConfig.tcr >> TCR_EPD1_BIT) & 0x1; if (!SkipTtbr1) - gMmuConfig.ttbr1 = AA64ReadTtbr1El1(); + gMmuConfig.ttbr1 = read_ttbr1_el1(); } acs_print(ACS_PRINT_DEBUG, L" MMU Config captured at EL%d\n", gMmuConfig.current_el); diff --git a/test_pool/ete/ete003.c b/test_pool/ete/ete003.c index 437ba936..2f5f7253 100644 --- a/test_pool/ete/ete003.c +++ b/test_pool/ete/ete003.c @@ -119,10 +119,10 @@ static void payload(void) * for accessing TRFCR_* Registers */ /* Enable Timer */ - ArmWriteCntpCtl((ArmReadCntpCtl() | ARM_ARCH_TIMER_ENABLE) & (~ARM_ARCH_TIMER_IMASK)); + write_cntp_ctl_el0((read_cntp_ctl_el0() | ARM_ARCH_TIMER_ENABLE) & (~ARM_ARCH_TIMER_IMASK)); /* Store Start Timestamp values which will be used later */ - start_timestamp[index] = ArmReadCntPct(); + start_timestamp[index] = read_cntpct_el0(); val_data_cache_ops_by_va((addr_t)(start_timestamp + index), CLEAN_AND_INVALIDATE); val_print_primary_pe(ACS_PRINT_INFO, "\n Start Timestamp : 0x%llx", start_timestamp[index], index); @@ -134,10 +134,10 @@ static void payload(void) /* Disable Timer */ - ArmWriteCntpCtl((ArmReadCntpCtl() | ARM_ARCH_TIMER_IMASK) & (~ARM_ARCH_TIMER_ENABLE)); + write_cntp_ctl_el0((read_cntp_ctl_el0() | ARM_ARCH_TIMER_IMASK) & (~ARM_ARCH_TIMER_ENABLE)); /* Read Current Counter Value */ - end_timestamp[index] = ArmReadCntPct(); + end_timestamp[index] = read_cntpct_el0(); val_data_cache_ops_by_va((addr_t)(end_timestamp + index), CLEAN_AND_INVALIDATE); val_print_primary_pe(ACS_PRINT_INFO, "\n End Timestamp : 0x%llx", end_timestamp[index], index); diff --git a/test_pool/ete/ete004.c b/test_pool/ete/ete004.c index 39e8b4a2..71263512 100644 --- a/test_pool/ete/ete004.c +++ b/test_pool/ete/ete004.c @@ -68,7 +68,7 @@ static void payload(void) * for accessing TRFCR_* Registers */ /* Enable Timer */ - ArmWriteCntpCtl((ArmReadCntpCtl() | ARM_ARCH_TIMER_ENABLE) & (~ARM_ARCH_TIMER_IMASK)); + write_cntp_ctl_el0((read_cntp_ctl_el0() | ARM_ARCH_TIMER_ENABLE) & (~ARM_ARCH_TIMER_IMASK)); /* Generate Trace when SelfHostedTraceEnabled = TRUE */ traced_timestamp_1 = val_ete_generate_trace(trace_buffer_addr, SH_TRACE_ENABLE_TRUE); @@ -89,7 +89,7 @@ static void payload(void) "\n traced_timestamp_3 : 0x%llx", traced_timestamp_3, index); /* Disable Timer */ - ArmWriteCntpCtl((ArmReadCntpCtl() | ARM_ARCH_TIMER_IMASK) & (~ARM_ARCH_TIMER_ENABLE)); + write_cntp_ctl_el0((read_cntp_ctl_el0() | ARM_ARCH_TIMER_IMASK) & (~ARM_ARCH_TIMER_ENABLE)); if ((traced_timestamp_1 == ACS_STATUS_FAIL) || (traced_timestamp_2 == ACS_STATUS_FAIL) || diff --git a/test_pool/mpam/error002.c b/test_pool/mpam/error002.c index b971f5ea..69587afe 100644 --- a/test_pool/mpam/error002.c +++ b/test_pool/mpam/error002.c @@ -43,7 +43,7 @@ void payload(void) total_nodes = val_mpam_get_msc_count(); /* Save MPAM2_EL2 to a temp storage */ - mpam2_el2_temp = AA64ReadMpam2(); + mpam2_el2_temp = read_mpam2_el2(); for (index = 0; index < total_nodes; index++) { diff --git a/test_pool/mpam/error004.c b/test_pool/mpam/error004.c index 1ea8f92f..51fdfc5d 100644 --- a/test_pool/mpam/error004.c +++ b/test_pool/mpam/error004.c @@ -43,7 +43,7 @@ void payload(void) total_nodes = val_mpam_get_msc_count(); /* Save MPAM2_EL2 to a temp storage */ - mpam2_el2_temp = AA64ReadMpam2(); + mpam2_el2_temp = read_mpam2_el2(); for (index = 0; index < total_nodes; index++) { diff --git a/test_pool/timer/t008.c b/test_pool/timer/t008.c index a31ccf6d..6564eda6 100644 --- a/test_pool/timer/t008.c +++ b/test_pool/timer/t008.c @@ -49,7 +49,7 @@ void payload(void) goto read_virt_ss_timer; while (iter) { - curr_value = ArmReadCntPctSS(); + curr_value = read_cntpctss_el0(); if (curr_value < prev_value) { val_print_primary_pe(ACS_PRINT_ERR, "\n CNTPCTSS_EL0 did not increment", 0, index); @@ -71,7 +71,7 @@ void payload(void) iter = NUM_ITERATIONS; while (iter) { - curr_value = ArmReadCntVctSS(); + curr_value = read_cntvctss_el0(); if (curr_value < prev_value) { val_print_primary_pe(ACS_PRINT_ERR, "\n CNTVCTSS_EL0 did not increment", 0, index); @@ -95,8 +95,8 @@ void payload(void) val_print_primary_pe(ACS_PRINT_DEBUG, "\n FEAT_ECV isn't Implemented, Reading CntPct", 0, index); while (iter) { - AA64IssueISB(); - curr_value = ArmReadCntPct(); + isb(); + curr_value = read_cntpct_el0(); if (curr_value < prev_value) { val_print_primary_pe(ACS_PRINT_ERR, "\n CNTPCT_EL0 did not increment", 0, index); @@ -118,8 +118,8 @@ void payload(void) iter = NUM_ITERATIONS; while (iter) { - AA64IssueISB(); - curr_value = ArmReadCntvCt(); + isb(); + curr_value = read_cntvct_el0(); if (curr_value < prev_value) { val_print_primary_pe(ACS_PRINT_ERR, "\n CNTVCT_EL0 did not increment", 0, index); diff --git a/val/ValLib.inf b/val/ValLib.inf index 76f353f3..bdd09090 100644 --- a/val/ValLib.inf +++ b/val/ValLib.inf @@ -29,14 +29,8 @@ [Sources.common] src/AArch64/PeRegSysSupport.S src/AArch64/PeTestSupport.S - src/AArch64/ArchTimerSupport.S - src/AArch64/GicSupport.S - src/AArch64/MpamSupport.S - src/AArch64/RasSupport.S - src/AArch64/PmuRegSupport.S src/AArch64/Drtm.S src/AArch64/SystemReg.S - src/AArch64/generic_sysreg_support.S src/acs_status.c src/acs_pe.c src/acs_pe_infra.c @@ -89,4 +83,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.6-a+sve+profile - GCC:*_*_*_CC_FLAGS = $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/val/ValLibRB.inf b/val/ValLibRB.inf index 1bf3c7ec..99b53148 100644 --- a/val/ValLibRB.inf +++ b/val/ValLibRB.inf @@ -31,14 +31,8 @@ [Sources.common] src/AArch64/PeRegSysSupport.S src/AArch64/PeTestSupport.S - src/AArch64/ArchTimerSupport.S - src/AArch64/GicSupport.S - src/AArch64/MpamSupport.S - src/AArch64/RasSupport.S - src/AArch64/PmuRegSupport.S src/AArch64/Drtm.S src/AArch64/SystemReg.S - src/AArch64/generic_sysreg_support.S src/acs_status.c src/acs_pe.c src/acs_pe_infra.c @@ -94,4 +88,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.6-a+sve+profile - GCC:*_*_*_CC_FLAGS = $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI -DCOMPILE_RB_EXE + GCC:*_*_*_CC_FLAGS = -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI -DCOMPILE_RB_EXE diff --git a/val/driver/gic/its/acs_gic_its.c b/val/driver/gic/its/acs_gic_its.c index 9d70e93c..811efc41 100644 --- a/val/driver/gic/its/acs_gic_its.c +++ b/val/driver/gic/its/acs_gic_its.c @@ -18,8 +18,7 @@ #include "acs_gic_its.h" #include "acs_gic_support.h" - -uint64_t ArmReadMpidr(void); +#include "val_sysreg_pe.h" extern GIC_ITS_INFO *g_gic_its_info; static uint32_t *g_cwriter_ptr; @@ -44,7 +43,7 @@ uint64_t val_its_get_curr_rdbase(uint64_t rd_base, uint32_t length) uint64_t curr_rd_base; /* RD Base for Current CPU */ uint32_t typer; - Mpidr = ArmReadMpidr(); + Mpidr = read_mpidr_el1(); CpuAffinity = (Mpidr & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | ((Mpidr & ARM_CORE_AFF3) >> 8); @@ -500,14 +499,14 @@ void val_its_clear_lpi_map(uint32_t its_index, uint32_t device_id, uint32_t int_ /* ITS SYNC Command */ WriteCmdQSYNC(its_index, (uint64_t *)(ItsCommandBase), RDBase); - TestExecuteBarrier(); + dsbsy(); /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/ value = ((g_cwriter_ptr[its_index] * NUM_BYTES_IN_DW)); val_mmio_write64((ItsBase + ARM_GITS_CWRITER), value); /* Check CREADR value which ensures Command Queue is processed */ PollTillCommandQueueDone(its_index); - TestExecuteBarrier(); + dsbsy(); } @@ -551,7 +550,7 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id, /* ITS SYNC Command */ WriteCmdQSYNC(its_index, (uint64_t *)(ItsCommandBase), RDBase); - TestExecuteBarrier(); + dsbsy(); /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/ value = ((g_cwriter_ptr[its_index] * NUM_BYTES_IN_DW)); @@ -559,7 +558,7 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id, /* Check CREADR value which ensures Command Queue is processed */ PollTillCommandQueueDone(its_index); - TestExecuteBarrier(); + dsbsy(); } diff --git a/val/driver/gic/v2/gic_v2.c b/val/driver/gic/v2/gic_v2.c index 6cc48222..5ef96a64 100644 --- a/val/driver/gic/v2/gic_v2.c +++ b/val/driver/gic/v2/gic_v2.c @@ -121,10 +121,10 @@ v2_Init(void) if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { /* Route exception to EL2 */ - GicWriteHcr(1 << 27); + write_hcr_el2(1 << 27); } - GicClearDaif(); + write_daifclr(DAIF_CONFIG); /* Set default priority */ for (index = 0; index < max_num_interrupts; index++) { diff --git a/val/driver/gic/v3/gic_v3.c b/val/driver/gic/v3/gic_v3.c index b1e0b50e..25f5cd7e 100644 --- a/val/driver/gic/v3/gic_v3.c +++ b/val/driver/gic/v3/gic_v3.c @@ -74,7 +74,7 @@ CurrentCpuRDBase(uint64_t mGicRedistributorBase, uint32_t length) uint64_t GicCpuRedistributorBase; uint64_t Mpidr; - Mpidr = ArmReadMpidr(); + Mpidr = read_mpidr_el1(); CpuAffinity = (Mpidr & (PE_AFF0 | PE_AFF1 | PE_AFF2)) | ((Mpidr & PE_AFF3) >> 8); @@ -395,10 +395,10 @@ v3_Init(void) if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { /* Route exception to EL2 */ - GicWriteHcr(1 << 27); + write_hcr_el2(1 << 27); } - GicClearDaif(); + write_daifclr(DAIF_CONFIG); /* Wake up redistributor before programming SGI/PPI state */ WakeUpRD(); @@ -419,7 +419,7 @@ v3_Init(void) } #endif - Mpidr = ArmReadMpidr(); + Mpidr = read_mpidr_el1(); cpuTarget = Mpidr & (PE_AFF0 | PE_AFF1 | PE_AFF2 | PE_AFF3); #if defined(TARGET_SIMULATION) diff --git a/val/driver/gic/v3/gic_v3_extended.c b/val/driver/gic/v3/gic_v3_extended.c index 4d0de42d..8226db10 100644 --- a/val/driver/gic/v3/gic_v3_extended.c +++ b/val/driver/gic/v3/gic_v3_extended.c @@ -265,7 +265,7 @@ v3_route_extended_interrupt(uint32_t int_id) /* Get the distributor base */ gicd_base = val_get_gicd_base(); - Mpidr = ArmReadMpidr(); + Mpidr = read_mpidr_el1(); cpuTarget = Mpidr & (PE_AFF0 | PE_AFF1 | PE_AFF2 | PE_AFF3); val_mmio_write64(gicd_base + GICD_IROUTERn + (int_id * 8), cpuTarget); diff --git a/val/driver/smmu_v3/smmu_v3.c b/val/driver/smmu_v3/smmu_v3.c index 7d34e87d..f388c80e 100644 --- a/val/driver/smmu_v3/smmu_v3.c +++ b/val/driver/smmu_v3/smmu_v3.c @@ -105,7 +105,7 @@ static int smmu_cmdq_write_cmd(smmu_dev_t *smmu, uint64_t *cmd) queue.prod = smmu_inc_prod(&queue); #ifndef TARGET_LINUX - ArmExecuteMemoryBarrier(); + dmbsy(); #endif val_mmio_write((uint64_t)cmdq->prod_reg, queue.prod); diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 07050d68..7cd8b08d 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -90,6 +90,7 @@ #endif //TARGET_LINUX #ifdef TARGET_UEFI + #include #include "platform_override.h" typedef INT8 int8_t; typedef INT32 int32_t; @@ -102,6 +103,11 @@ typedef UINT64 uint64_t; typedef UINT64 addr_t; typedef UINT64 dma_addr_t; + typedef UINTN uintptr_t; + typedef INTN intptr_t; + typedef INT64 intmax_t; + typedef UINT64 uintmax_t; + #if defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L /* bool is a keyword */ diff --git a/val/src/acs_ete.c b/val/src/acs_ete.c index a5d5eb0d..3d5f4650 100644 --- a/val/src/acs_ete.c +++ b/val/src/acs_ete.c @@ -377,7 +377,7 @@ uint64_t val_ete_generate_trace(uint64_t buffer_addr, uint32_t self_hosted_trace AA64EnableETETrace(); /* Read TRBPTR_EL1 before generating the trace */ - trbptr_before = AA64ReadTrbPtrEl1(); + trbptr_before = read_trbptr_el1(); /* Generate Trace */ AA64GenerateETETrace(); @@ -391,7 +391,7 @@ uint64_t val_ete_generate_trace(uint64_t buffer_addr, uint32_t self_hosted_trace AA64DisableTFO(); /* Read TRBPTR_EL1 after generating the trace */ - trbptr_after = AA64ReadTrbPtrEl1(); + trbptr_after = read_trbptr_el1(); /* If Trace is not generated or timestamp for current PE not updated */ if (trbptr_before == trbptr_after) diff --git a/val/src/acs_gic_support.c b/val/src/acs_gic_support.c index dd81f8d7..984a1b74 100644 --- a/val/src/acs_gic_support.c +++ b/val/src/acs_gic_support.c @@ -46,11 +46,11 @@ val_gic_reg_read(uint32_t reg_id) switch(reg_id) { case ICH_HCR_EL2: if (val_gic_get_info(GIC_INFO_VERSION) >= 3) - return GicReadIchHcr(); + return read_ich_hcr_el2(); else return val_mmio_read(val_get_gich_base() + 0); /* 0 is GICH_HCR offset */ case ICH_MISR_EL2: - return GicReadIchMisr(); + return read_ich_misr_el2(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(0, 0xFF), NULL); @@ -75,18 +75,18 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data) switch(reg_id) { case ICH_HCR_EL2: if (val_gic_get_info(GIC_INFO_VERSION) >= 3) - GicWriteIchHcr(write_data); + write_ich_hcr_el2(write_data); else val_mmio_write64(val_get_gich_base() + 0, write_data); /* 0 is GICH_HCR offset */ break; case ICC_IGRPEN1_EL1: - GicWriteIccIgrpen1(write_data); + write_icc_igrpen1_el1(write_data); break; case ICC_BPR1_EL1: - GicWriteIccBpr1(write_data); + write_icc_bpr1_el1(write_data); break; case ICC_PMR_EL1: - GicWriteIccPmr(write_data); + write_icc_pmr_el1(write_data); break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), diff --git a/val/src/acs_memory.c b/val/src/acs_memory.c index ced8ac39..a2226628 100644 --- a/val/src/acs_memory.c +++ b/val/src/acs_memory.c @@ -614,7 +614,7 @@ void val_mem_issue_dsb(void) { #ifndef TARGET_LINUX - AA64IssueDSB(); + dsbsy(); #endif return; } diff --git a/val/src/acs_mpam.c b/val/src/acs_mpam.c index f8ec0406..3385ef3a 100644 --- a/val/src/acs_mpam.c +++ b/val/src/acs_mpam.c @@ -116,11 +116,11 @@ val_mpam_reg_read(MPAM_SYS_REGS reg_id) { switch (reg_id) { case MPAMIDR_EL1: - return AA64ReadMpamidr(); + return read_mpamidr_el1(); case MPAM2_EL2: - return AA64ReadMpam2(); + return read_mpam2_el2(); case MPAM1_EL1: - return AA64ReadMpam1(); + return read_mpam1_el1(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(0, STATUS_SYS_REG_ACCESS_FAIL), NULL); @@ -142,10 +142,10 @@ val_mpam_reg_write(MPAM_SYS_REGS reg_id, uint64_t write_data) { switch (reg_id) { case MPAM2_EL2: - AA64WriteMpam2(write_data); + write_mpam2_el2(write_data); break; case MPAM1_EL1: - AA64WriteMpam1(write_data); + write_mpam1_el1(write_data); break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), diff --git a/val/src/acs_msc_error.c b/val/src/acs_msc_error.c index 04f55ebd..c70c8d01 100644 --- a/val/src/acs_msc_error.c +++ b/val/src/acs_msc_error.c @@ -176,7 +176,7 @@ uint32_t val_mpam_msc_generate_por_error(uint32_t msc_index) val_print(ACS_PRINT_DEBUG, "\n MSC Max PARTID is %d", msc_max_partid); /* Extract max PARTID supported by MPAMIDR_EL1 */ - mpamidr = AA64ReadMpamidr(); + mpamidr = read_mpamidr_el1(); pe_max_partid = (mpamidr >> MPAMIDR_PARTID_MAX_SHIFT) & MPAMIDR_PARTID_MAX_MASK; val_print(ACS_PRINT_DEBUG, "\n PE Max PARTID is %d", pe_max_partid); diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c index fdfc79ed..a5fd1835 100644 --- a/val/src/acs_pcie.c +++ b/val/src/acs_pcie.c @@ -1451,7 +1451,7 @@ val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t num_bitfield { uint32_t bdf; - uint32_t dp_type; + uint32_t dp_type = 0; uint32_t tbl_index; uint32_t num_fails; uint32_t num_pass; diff --git a/val/src/acs_pe.c b/val/src/acs_pe.c index 6dc0097c..119725be 100644 --- a/val/src/acs_pe.c +++ b/val/src/acs_pe.c @@ -53,177 +53,181 @@ val_pe_reg_read(uint32_t reg_id) switch(reg_id) { case MPIDR_EL1: - return ArmReadMpidr(); + return read_mpidr_el1(); case ID_AA64PFR0_EL1: - return ArmReadIdPfr0(); + return read_id_aa64pfr0_el1(); case ID_AA64PFR1_EL1: - return ArmReadIdPfr1(); + return read_id_aa64pfr1_el1(); case ID_AA64MMFR0_EL1: - return AA64ReadMmfr0(); + return read_id_aa64mmfr0_el1(); case ID_AA64MMFR1_EL1: - return AA64ReadMmfr1(); + return read_id_aa64mmfr1_el1(); case ID_AA64MMFR2_EL1: - return AA64ReadMmfr2(); + return read_id_aa64mmfr2_el1(); case ID_AA64MMFR3_EL1: - return AA64ReadMmfr3(); + return read_id_aa64mmfr3_el1(); case CTR_EL0: - return AA64ReadCtr(); + return read_ctr_el0(); case ID_AA64ISAR0_EL1: - return AA64ReadIsar0(); + return read_id_aa64isar0_el1(); case ID_AA64ISAR1_EL1: - return AA64ReadIsar1(); + return read_id_aa64isar1_el1(); case ID_AA64ISAR2_EL1: - return AA64ReadIsar2(); + return read_id_aa64isar2_el1(); case SCTLR_EL3: - return AA64ReadSctlr3(); + return read_sctlr_el3(); case SCTLR_EL2: - return AA64ReadSctlr2(); + return read_sctlr_el2(); case SCTLR_EL1: - return AA64ReadSctlr1(); + return read_sctlr_el1(); case PMCR_EL0: - return AA64ReadPmcr(); + return read_pmcr_el0(); case ID_AA64DFR0_EL1: - return AA64ReadIdDfr0(); + return read_id_aa64dfr0_el1(); case ID_AA64DFR1_EL1: - return AA64ReadIdDfr1(); + return read_id_aa64dfr1_el1(); case CurrentEL: - return AA64ReadCurrentEL(); + return read_CurrentEL(); case MDCR_EL2: - return AA64ReadMdcr2(); + return read_mdcr_el2(); case VBAR_EL2: - return AA64ReadVbar2(); + return read_vbar_el2(); case CCSIDR_EL1: - return AA64ReadCcsidr(); + return read_ccsidr_el1(); case CSSELR_EL1: - return AA64ReadCsselr(); + return read_csselr_el1(); case CLIDR_EL1: - return AA64ReadClidr(); + return read_clidr_el1(); case ID_DFR0_EL1: - return ArmReadDfr0(); + return read_id_dfr0_el1(); case ID_ISAR0_EL1: - return ArmReadIsar0(); + return read_id_isar0_el1(); case ID_ISAR1_EL1: - return ArmReadIsar1(); + return read_id_isar1_el1(); case ID_ISAR2_EL1: - return ArmReadIsar2(); + return read_id_isar2_el1(); case ID_ISAR3_EL1: - return ArmReadIsar3(); + return read_id_isar3_el1(); case ID_ISAR4_EL1: - return ArmReadIsar4(); + return read_id_isar4_el1(); case ID_ISAR5_EL1: - return ArmReadIsar5(); + return read_id_isar5_el1(); case ID_MMFR0_EL1: - return ArmReadMmfr0(); + return read_id_mmfr0_el1(); case ID_MMFR1_EL1: - return ArmReadMmfr1(); + return read_id_mmfr1_el1(); case ID_MMFR2_EL1: - return ArmReadMmfr2(); + return read_id_mmfr2_el1(); case ID_MMFR3_EL1: - return ArmReadMmfr3(); + return read_id_mmfr3_el1(); case ID_MMFR4_EL1: - return ArmReadMmfr4(); + return read_id_mmfr4_el1(); case ID_PFR0_EL1: - return ArmReadPfr0(); + return read_id_pfr0_el1(); case ID_PFR1_EL1: - return ArmReadPfr1(); + return read_id_pfr1_el1(); case MIDR_EL1: - return ArmReadMidr(); + return read_midr_el1(); case MVFR0_EL1: - return ArmReadMvfr0(); + return read_mvfr0_el1(); case MVFR1_EL1: - return ArmReadMvfr1(); + return read_mvfr1_el1(); case MVFR2_EL1: - return ArmReadMvfr2(); + return read_mvfr2_el1(); case PMCEID0_EL0: - return AA64ReadPmceid0(); + return read_pmceid0_el0(); case PMCEID1_EL0: - return AA64ReadPmceid1(); + return read_pmceid1_el0(); case VMPIDR_EL2: - return AA64ReadVmpidr(); + return read_vmpidr_el2(); case VPIDR_EL2: - return AA64ReadVpidr(); + return read_vpidr_el2(); case PMBIDR_EL1: - return AA64ReadPmbidr(); + return read_pmbidr_el1(); case PMSIDR_EL1: - return AA64ReadPmsidr(); + return read_pmsidr_el1(); case LORID_EL1: - return AA64ReadLorid(); + return read_lorid_el1(); case ERRIDR_EL1: - return AA64ReadErridr(); + return read_erridr_el1(); case ERR0FR_EL1: - return AA64ReadErr0fr(); + return 0x0; + // return read_err0fr_el1(); case ERR1FR_EL1: - return AA64ReadErr1fr(); + return 0x0; + // return read_err1fr_el1(); case ERR2FR_EL1: - return AA64ReadErr2fr(); + return 0x0; + // return read_err2fr_el1(); case ERR3FR_EL1: - return AA64ReadErr3fr(); + return 0x0; + // return read_err3fr_el1(); case ESR_EL2: - return AA64ReadEsr2(); + return read_esr_el2(); case FAR_EL2: - return AA64ReadFar2(); + return read_far_el2(); case RDVL: return ArmRdvl(); case MAIR_ELx: - if (AA64ReadCurrentEL() == AARCH64_EL1) - return AA64ReadMair1(); - if (AA64ReadCurrentEL() == AARCH64_EL2) - return AA64ReadMair2(); + if (read_CurrentEL() == AARCH64_EL1) + return read_mair_el1(); + if (read_CurrentEL() == AARCH64_EL2) + return read_mair_el2(); break; case TCR_ELx: - if (AA64ReadCurrentEL() == AARCH64_EL1) - return AA64ReadTcr1(); - if (AA64ReadCurrentEL() == AARCH64_EL2) - return AA64ReadTcr2(); + if (read_CurrentEL() == AARCH64_EL1) + return read_tcr_el1(); + if (read_CurrentEL() == AARCH64_EL2) + return read_tcr_el2(); break; case DBGBCR0_EL1: - return AA64ReadDbgbcr0El1(); + return read_dbgbcr0_el1(); case DBGBCR1_EL1: - return AA64ReadDbgbcr1El1(); + return read_dbgbcr1_el1(); case DBGBCR2_EL1: - return AA64ReadDbgbcr2El1(); + return read_dbgbcr2_el1(); case DBGBCR3_EL1: - return AA64ReadDbgbcr3El1(); + return read_dbgbcr3_el1(); case DBGBCR4_EL1: - return AA64ReadDbgbcr4El1(); + return read_dbgbcr4_el1(); case DBGBCR5_EL1: - return AA64ReadDbgbcr5El1(); + return read_dbgbcr5_el1(); case DBGBCR6_EL1: - return AA64ReadDbgbcr6El1(); + return read_dbgbcr6_el1(); case DBGBCR7_EL1: - return AA64ReadDbgbcr7El1(); + return read_dbgbcr7_el1(); case DBGBCR8_EL1: - return AA64ReadDbgbcr8El1(); + return read_dbgbcr8_el1(); case DBGBCR9_EL1: - return AA64ReadDbgbcr9El1(); + return read_dbgbcr9_el1(); case DBGBCR10_EL1: - return AA64ReadDbgbcr10El1(); + return read_dbgbcr10_el1(); case DBGBCR11_EL1: - return AA64ReadDbgbcr11El1(); + return read_dbgbcr11_el1(); case DBGBCR12_EL1: - return AA64ReadDbgbcr12El1(); + return read_DBGBCR12_EL1(); case DBGBCR13_EL1: - return AA64ReadDbgbcr13El1(); + return read_dbgbcr13_el1(); case DBGBCR14_EL1: - return AA64ReadDbgbcr14El1(); + return read_dbgbcr14_el1(); case DBGBCR15_EL1: - return AA64ReadDbgbcr15El1(); + return read_dbgbcr15_el1(); case ID_AA64ZFR0_EL1: - return AA64ReadZfr0(); + return read_id_aa64zfr0_el1(); case BRBIDR0_EL1: - return AA64ReadBrbidr0(); + return read_brbidr0_el1(); case TRBIDR_EL1: - return AA64ReadTrbidr(); + return read_trbidr_el1(); case TRCIDR0: - return AA64ReadTrcidr0(); + return read_trcidr0(); case TRCIDR4: - return AA64ReadTrcidr4(); + return read_trcidr4(); case TRCIDR5: - return AA64ReadTrcidr5(); + return read_trcidr5(); case HCR_EL2: - return ArmReadHcrEl2(); + return read_hcr_el2(); case VTCR_EL2: - return AA64ReadVtcr(); + return read_vtcr_el2(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(0, 0xFF), NULL); @@ -247,43 +251,43 @@ val_pe_reg_write(uint32_t reg_id, uint64_t write_data) switch(reg_id) { case CSSELR_EL1: - AA64WriteCsselr(write_data); + write_csselr_el1(write_data); break; case PMCR_EL0: - AA64WritePmcr(write_data); + write_pmcr_el0(write_data); break; case PMOVSSET_EL0: - AA64WritePmovsset(write_data); + write_pmovsset_el0(write_data); break; case PMOVSCLR_EL0: - AA64WritePmovsclr(write_data); + write_pmovsclr_el0(write_data); break; case PMINTENSET_EL1: - AA64WritePmintenset(write_data); + write_pmintenset_el1(write_data); break; case PMINTENCLR_EL1: - AA64WritePmintenclr(write_data); + write_pmintenclr_el1(write_data); break; case MDCR_EL2: - AA64WriteMdcr2(write_data); + write_mdcr_el2(write_data); break; case VBAR_EL2: - AA64WriteVbar2(write_data); + write_vbar_el2(write_data); break; case PMSIRR_EL1: - AA64WritePmsirr(write_data); + // write_pmsirr_el1(write_data); break; case PMSCR_EL2: - AA64WritePmscr2(write_data); + // write_pmscr_el2(write_data); break; case PMSFCR_EL1: - AA64WritePmsfcr(write_data); + // write_pmsfcr_el1(write_data); break; case PMBPTR_EL1: - AA64WritePmbptr(write_data); + // write_pmbptr_el1(write_data); break; case PMBLIMITR_EL1: - AA64WritePmblimitr(write_data); + // write_pmblimitr_el1(write_data); break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), @@ -414,7 +418,7 @@ val_pe_spe_disable(void) uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr) { uint64_t val = val_pe_reg_read(TCR_ELx); - uint32_t el = AA64ReadCurrentEL() & AARCH64_EL_MASK; + uint32_t el = read_CurrentEL() & AARCH64_EL_MASK; uint8_t tg_ttbr0[3] = {12 /*4KB*/, 16 /*64KB*/, 14 /*16KB*/}; uint8_t tg_ttbr1[4] = {0 /* N/A */, 14 /*16KB*/, 12 /*4KB*/, 16 /* 64KB*/}; uint64_t e2h = 0; @@ -424,7 +428,7 @@ uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr) return ACS_STATUS_ERR; if (el == AARCH64_EL2) - e2h = ArmReadHcrEl2() & AARCH64_HCR_E2H_MASK; + e2h = read_hcr_el2() & AARCH64_HCR_E2H_MASK; if (el == AARCH64_EL1 || (el == AARCH64_EL2 && e2h)) { @@ -467,10 +471,10 @@ uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr) **/ uint32_t val_pe_reg_read_ttbr(uint32_t ttbr1, uint64_t *ttbr_ptr) { - uint32_t el = AA64ReadCurrentEL() & AARCH64_EL_MASK; - typedef uint64_t (*ReadTtbr_t)(void); - ReadTtbr_t ReadTtbr[2][2] = {{AA64ReadTtbr0El1, AA64ReadTtbr0El2}, - {AA64ReadTtbr1El1, AA64ReadTtbr1El2}}; + uint32_t el = read_CurrentEL() & AARCH64_EL_MASK; + typedef u_register_t (*ReadTtbr_t)(void); + ReadTtbr_t ReadTtbr[2][2] = {{read_ttbr0_el1, read_ttbr0_el2}, + {read_ttbr1_el1, read_ttbr1_el2} }; if ((ttbr_ptr == NULL) || (el != AARCH64_EL1 && el != AARCH64_EL2) || diff --git a/val/src/acs_pmu.c b/val/src/acs_pmu.c index 05a2891b..eb0635ec 100644 --- a/val/src/acs_pmu.c +++ b/val/src/acs_pmu.c @@ -42,13 +42,13 @@ val_pmu_reg_read ( switch (RegId) { case PMCR_EL0: - return AA64ReadPmcr(); + return read_pmcr_el0(); case PMCCNTR_EL0: - return AA64ReadPmccntr(); + return read_pmccntr_el0(); case PMCCFILTR_EL0: - return AA64ReadPmccfiltr(); + return read_pmccfiltr_el0(); case PMCNTENSET_EL0: - return AA64ReadPmcntenset(); + return read_pmcntenset_el0(); default: val_print(ACS_PRINT_ERR, "\n FATAL - Unsupported PMU register read \n", 0); } @@ -72,16 +72,16 @@ val_pmu_reg_write ( switch (RegId) { case PMCR_EL0: - AA64WritePmcr(WriteData); + write_pmcr_el0(WriteData); break; case PMCCNTR_EL0: - AA64WritePmccntr(WriteData); + write_pmccntr_el0(WriteData); break; case PMCCFILTR_EL0: - AA64WritePmccfiltr(WriteData); + write_pmccfiltr_el0(WriteData); break; case PMCNTENSET_EL0: - AA64WritePmcntenset(WriteData); + write_pmcntenset_el0(WriteData); break; default: val_print(ACS_PRINT_ERR, "\n FATAL - Unsupported PMU register read \n", 0); diff --git a/val/src/acs_ras.c b/val/src/acs_ras.c index d9b00bbd..8b874e50 100644 --- a/val/src/acs_ras.c +++ b/val/src/acs_ras.c @@ -451,19 +451,19 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) /* System register based read */ /* RAS registers reads with ERRSELR_EL1.SEL set to start error record index */ - AA64WriteErrSelr1(start_rec_index); + write_errselr_el1(start_rec_index); switch (reg) { case RAS_ERR_FR: - value = AA64ReadErrFr1(); + value = read_erxfr_el1(); break; case RAS_ERR_CTLR: - value = AA64ReadErrCtlr1(); + value = read_erxctlr_el1(); break; case RAS_ERR_PFGCDN: /* ERRPFGCDN RAS register is valid only for first error record */ if (err_rec_idx == start_rec_index) - value = AA64ReadErrPfgcdn1(); + value = read_erxpfgcdn_el1(); else { val_print(ACS_PRINT_ERR, "\n RAS_REG_READ : ERR<%d>PFGCDN is RES0 for the node index :", err_rec_idx); @@ -474,7 +474,7 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) case RAS_ERR_PFGCTL: /* ERRPFGCTL RAS register is valid only for first error record */ if (err_rec_idx == start_rec_index) - value = AA64ReadErrPfgctl1(); + value = read_erxpfgctl_el1(); else { val_print(ACS_PRINT_ERR, "\n RAS_REG_READ : ERR<%d>PFGCTL is RES0 for the node index :", err_rec_idx); @@ -488,14 +488,14 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) /* RAS registers reads with ERRSELR_EL1.SEL set to current error record index These registers are unique to given error record */ - AA64WriteErrSelr1(err_rec_idx); + write_errselr_el1(err_rec_idx); switch (reg) { case RAS_ERR_STATUS: - value = AA64ReadErrStatus1(); + value = read_erxstatus_el1(); break; case RAS_ERR_ADDR: - value = AA64ReadErrAddr1(); + value = read_erxaddr_el1(); break; default: break; @@ -553,20 +553,20 @@ val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data) /* System register based Write */ /* Update ERRSELR_EL1.SEL to choose which record index to use */ - AA64WriteErrSelr1(rec_index); + write_errselr_el1(rec_index); switch (reg) { case RAS_ERR_CTLR: - AA64WriteErrCtlr1(write_data); + write_erxctlr_el1(write_data); break; case RAS_ERR_STATUS: - AA64WriteErrStatus1(write_data); + write_erxstatus_el1(write_data); break; case RAS_ERR_PFGCDN: - AA64WriteErrPfgcdn1(write_data); + write_erxpfgcdn_el1(write_data); break; case RAS_ERR_PFGCTL: - AA64WriteErrPfgctl1(write_data); + write_erxpfgctl_el1(write_data); break; default: break; diff --git a/val/src/acs_timer_support.c b/val/src/acs_timer_support.c index 2ee007c4..95e60c04 100644 --- a/val/src/acs_timer_support.c +++ b/val/src/acs_timer_support.c @@ -33,9 +33,9 @@ uint8_t get_effective_e2h(void) return 0; } - uint32_t hcr_e2h = VAL_EXTRACT_BITS(ArmReadHcrEl2(), 34, 34); - uint32_t feat_vhe = VAL_EXTRACT_BITS(ArmReadAA64MMFR1EL1(), 8, 11); - uint32_t e2h0 = VAL_EXTRACT_BITS(ArmReadAA64MMFR4EL1(), 24, 27); + uint32_t hcr_e2h = VAL_EXTRACT_BITS(read_hcr_el2(), 34, 34); + uint32_t feat_vhe = VAL_EXTRACT_BITS(read_id_aa64mmfr1_el1(), 8, 11); + uint32_t e2h0 = VAL_EXTRACT_BITS(read_s3_0_c0_c7_4(), 24, 27); val_print(ACS_PRINT_DEBUG, "\n hcr_e2h : 0x%x", hcr_e2h); val_print(ACS_PRINT_DEBUG, "\n feat_vhe : 0x%x", feat_vhe); @@ -71,53 +71,53 @@ ArmArchTimerReadReg ( switch (Reg) { case CntFrq: - return ArmReadCntFrq(); + return read_cntfrq_el0(); case CntPct: - return ArmReadCntPct(); + return read_cntpct_el0(); case CntPctSS: - return ArmReadCntPctSS(); + return read_cntpctss_el0(); case CntkCtl: - return effective_e2h ? ArmReadCntkCtl12() : ArmReadCntkCtl(); + return effective_e2h ? read_cntkctl_el12() : read_cntkctl_el1(); case CntpTval: /* Check For E2H, If EL2 Host then access to cntp_tval_el02 */ - return effective_e2h ? ArmReadCntpTval02() : ArmReadCntpTval(); + return effective_e2h ? read_cntp_tval_el02() : read_cntp_tval_el0(); case CntpCtl: /* Check For E2H, If EL2 Host then access to cntp_ctl_el02 */ - return effective_e2h ? ArmReadCntpCtl02() : ArmReadCntpCtl(); + return effective_e2h ? read_cntp_ctl_el02() : read_cntp_ctl_el0(); case CntvTval: - return effective_e2h ? ArmReadCntvTval02() : ArmReadCntvTval(); + return effective_e2h ? read_cntv_tval_el02() : read_cntv_tval_el0(); case CntvCtl: - return effective_e2h ? ArmReadCntvCtl02() : ArmReadCntvCtl(); + return effective_e2h ? read_cntv_ctl_el02() : read_cntv_ctl_el0(); case CntvCt: - return ArmReadCntvCt(); + return read_cntvct_el0(); case CntVctSS: - return ArmReadCntVctSS(); + return read_cntvctss_el0(); case CntpCval: - return effective_e2h ? ArmReadCntpCval02() : ArmReadCntpCval(); + return effective_e2h ? read_cntp_cval_el02() : read_cntp_cval_el0(); case CntvCval: - return effective_e2h ? ArmReadCntvCval02() : ArmReadCntvCval(); + return effective_e2h ? read_cntv_cval_el02() : read_cntv_cval_el0(); case CntvOff: - return ArmReadCntvOff(); + return read_cntvoff_el2(); case CnthpCtl: - return ArmReadCnthpCtl(); + return read_cnthp_ctl_el2(); case CnthpTval: - return ArmReadCnthpTval(); + return read_cnthp_tval_el2(); case CnthvCtl: - return ArmReadCnthvCtl(); + return read_cnthv_ctl_el2(); case CnthvTval: - return ArmReadCnthvTval(); + return read_cnthv_tval_el2(); case CnthCtl: case CnthpCval: @@ -159,37 +159,37 @@ ArmArchTimerWriteReg ( case CntkCtl: if (effective_e2h) - ArmWriteCntkCtl12(*data_buf); + write_cntkctl_el12(*data_buf); else - ArmWriteCntkCtl(*data_buf); + write_cntkctl_el1(*data_buf); break; case CntpTval: if (effective_e2h) - ArmWriteCntpTval02(*data_buf); + write_cntp_tval_el02(*data_buf); else - ArmWriteCntpTval(*data_buf); + write_cntp_tval_el0(*data_buf); break; case CntpCtl: if (effective_e2h) - ArmWriteCntpCtl02(*data_buf); + write_cntp_ctl_el02(*data_buf); else - ArmWriteCntpCtl(*data_buf); + write_cntp_ctl_el0(*data_buf); break; case CntvTval: if (effective_e2h) - ArmWriteCntvTval02(*data_buf); + write_cntv_tval_el02(*data_buf); else - ArmWriteCntvTval(*data_buf); + write_cntv_tval_el0(*data_buf); break; case CntvCtl: if (effective_e2h) - ArmWriteCntvCtl02(*data_buf); + write_cntv_ctl_el02(*data_buf); else - ArmWriteCntvCtl(*data_buf); + write_cntv_ctl_el0(*data_buf); break; case CntvCt: @@ -197,28 +197,28 @@ ArmArchTimerWriteReg ( break; case CntpCval: - ArmWriteCntpCval(*data_buf); + write_cntp_cval_el0(*data_buf); break; case CntvCval: - ArmWriteCntvCval(*data_buf); + write_cntv_cval_el0(*data_buf); break; case CntvOff: - ArmWriteCntvOff(*data_buf); + write_cntvoff_el2(*data_buf); break; case CnthpTval: - ArmWriteCnthpTval(*data_buf); + write_cnthp_tval_el2(*data_buf); break; case CnthpCtl: - ArmWriteCnthpCtl(*data_buf); + write_cnthp_ctl_el2(*data_buf); break; case CnthvTval: - ArmWriteCnthvTval(*data_buf); + write_cnthv_tval_el2(*data_buf); break; case CnthvCtl: - ArmWriteCnthvCtl(*data_buf); + write_cnthv_ctl_el2(*data_buf); break; case CnthCtl: case CnthpCval: diff --git a/val/src/acs_wakeup.c b/val/src/acs_wakeup.c index 5ded14a3..a30678af 100644 --- a/val/src/acs_wakeup.c +++ b/val/src/acs_wakeup.c @@ -116,7 +116,7 @@ val_power_enter_semantic(BSA_POWER_SEM_e semantic) switch (semantic) { case BSA_POWER_SEM_B: - ArmCallWFI(); + wfi(); break; default: break; diff --git a/val/src/rule_based_orchestrator.c b/val/src/rule_based_orchestrator.c index 71290945..a8a41612 100644 --- a/val/src/rule_based_orchestrator.c +++ b/val/src/rule_based_orchestrator.c @@ -413,8 +413,8 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) bool test_warn_flag; uint32_t i, j; uint32_t alias_rule_map_index; - uint32_t rule_test_status; - uint32_t base_rule_status; + uint32_t rule_test_status = 0; + uint32_t base_rule_status = 0; uint32_t precheck_status; uint32_t rule_support_status; uint32_t num_pe; From ede6df2f49279be84fe2dd0e9722c2cb3c5faa03 Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Mon, 23 Feb 2026 06:42:55 +0000 Subject: [PATCH 04/13] Align tests and val infra with new logger implementation - Update acs to align with new verbosity levels - Align val infra to call new logger API Signed-off-by: Shruti Ghadge Change-Id: Ia693e814efd239ed46e01dc70cadd38ad9d7be5b --- apps/baremetal/acs_common.c | 22 +-- apps/baremetal/acs_helpers.c | 6 +- apps/baremetal/bsa_main.c | 42 ++--- apps/baremetal/pc_bsa_main.c | 42 ++--- apps/baremetal/sbsa_main.c | 40 ++--- apps/uefi/acs.h | 2 +- apps/uefi/acs_helpers.c | 40 ++--- apps/uefi/bsa_main.c | 20 +-- apps/uefi/drtm_main.c | 24 +-- apps/uefi/mem_test_main.c | 32 ++-- apps/uefi/mpam_main.c | 16 +- apps/uefi/pc_bsa_main.c | 20 +-- apps/uefi/pfdi_main.c | 22 +-- apps/uefi/sbsa_main.c | 20 +-- apps/uefi/sbsa_nist_main.c | 26 +-- apps/uefi/vbsa_main.c | 20 +-- apps/uefi/xbsa_main.c | 14 +- pal/uefi_dt/src/pal_misc.c | 15 ++ test_pool/cxl/cxl001.c | 6 +- test_pool/cxl/cxl002.c | 10 +- test_pool/cxl/cxl003.c | 4 +- test_pool/cxl/cxl004.c | 14 +- test_pool/cxl/cxl010.c | 6 +- test_pool/cxl/cxl011.c | 20 +-- test_pool/cxl/cxl013.c | 28 ++-- test_pool/drtm/dl001.c | 24 +-- test_pool/drtm/dl002.c | 18 +- test_pool/drtm/dl003.c | 24 +-- test_pool/drtm/dl004.c | 20 +-- test_pool/drtm/dl005.c | 114 ++++++------- test_pool/drtm/dl006.c | 116 ++++++------- test_pool/drtm/dl007.c | 12 +- test_pool/drtm/dl008.c | 28 ++-- test_pool/drtm/dl009.c | 8 +- test_pool/drtm/dl010.c | 16 +- test_pool/drtm/dl011.c | 22 +-- test_pool/drtm/dl012.c | 26 +-- test_pool/drtm/interface001.c | 6 +- test_pool/drtm/interface002.c | 6 +- test_pool/drtm/interface003.c | 8 +- test_pool/drtm/interface004.c | 4 +- test_pool/drtm/interface005.c | 8 +- test_pool/drtm/interface006.c | 6 +- test_pool/drtm/interface007.c | 10 +- test_pool/drtm/interface008.c | 2 +- test_pool/drtm/interface009.c | 2 +- test_pool/drtm/interface010.c | 12 +- test_pool/drtm/interface011.c | 8 +- test_pool/drtm/interface012.c | 4 +- test_pool/drtm/interface013.c | 10 +- test_pool/drtm/interface014.c | 14 +- test_pool/drtm/interface015.c | 6 +- test_pool/ete/ete001.c | 2 +- test_pool/ete/ete002.c | 26 +-- test_pool/ete/ete003.c | 28 ++-- test_pool/ete/ete004.c | 16 +- test_pool/ete/ete005.c | 2 +- test_pool/ete/ete006.c | 4 +- test_pool/ete/ete007.c | 4 +- test_pool/ete/ete008.c | 4 +- test_pool/exerciser/e001.c | 24 +-- test_pool/exerciser/e002.c | 32 ++-- test_pool/exerciser/e003.c | 24 +-- test_pool/exerciser/e004.c | 18 +- test_pool/exerciser/e006.c | 18 +- test_pool/exerciser/e007.c | 12 +- test_pool/exerciser/e008.c | 16 +- test_pool/exerciser/e010.c | 10 +- test_pool/exerciser/e011.c | 10 +- test_pool/exerciser/e012.c | 22 +-- test_pool/exerciser/e013.c | 20 +-- test_pool/exerciser/e014.c | 10 +- test_pool/exerciser/e015.c | 16 +- test_pool/exerciser/e016.c | 16 +- test_pool/exerciser/e017.c | 14 +- test_pool/exerciser/e019.c | 36 ++-- test_pool/exerciser/e020.c | 42 ++--- test_pool/exerciser/e021.c | 34 ++-- test_pool/exerciser/e022.c | 14 +- test_pool/exerciser/e023.c | 56 +++---- test_pool/exerciser/e024.c | 50 +++--- test_pool/exerciser/e025.c | 20 +-- test_pool/exerciser/e026.c | 26 +-- test_pool/exerciser/e027.c | 50 +++--- test_pool/exerciser/e028.c | 28 ++-- test_pool/exerciser/e029.c | 34 ++-- test_pool/exerciser/e030.c | 24 +-- test_pool/exerciser/e033.c | 20 +-- test_pool/exerciser/e035.c | 28 ++-- test_pool/exerciser/e036.c | 52 +++--- test_pool/exerciser/e039.c | 20 +-- test_pool/exerciser/e040.c | 24 +-- test_pool/exerciser/e041.c | 26 +-- test_pool/exerciser/e043.c | 12 +- test_pool/exerciser/e044.c | 10 +- test_pool/exerciser/e045.c | 12 +- test_pool/gic/g001.c | 4 +- test_pool/gic/g002.c | 4 +- test_pool/gic/g003.c | 4 +- test_pool/gic/g005.c | 20 +-- test_pool/gic/g006.c | 8 +- test_pool/gic/g007.c | 8 +- test_pool/gic/g008.c | 10 +- test_pool/gic/g009.c | 14 +- test_pool/gic/g010.c | 12 +- test_pool/gic/g011.c | 12 +- test_pool/gic/g012.c | 4 +- test_pool/gic/g013.c | 12 +- test_pool/gic/g014.c | 16 +- test_pool/gic/g015.c | 12 +- test_pool/gic/g016.c | 4 +- test_pool/gic/its001.c | 12 +- test_pool/gic/its002.c | 20 +-- test_pool/gic/its003.c | 22 +-- test_pool/gic/its004.c | 14 +- test_pool/gic/its005.c | 8 +- test_pool/gic/v2m001.c | 8 +- test_pool/gic/v2m002.c | 10 +- test_pool/gic/v2m003.c | 10 +- test_pool/gic/v2m004.c | 10 +- test_pool/memory_map/m001.c | 11 +- test_pool/memory_map/m002.c | 14 +- test_pool/memory_map/m004.c | 12 +- test_pool/memory_map/m005.c | 12 +- test_pool/mpam/error001.c | 8 +- test_pool/mpam/error002.c | 10 +- test_pool/mpam/error003.c | 12 +- test_pool/mpam/error004.c | 10 +- test_pool/mpam/error005.c | 14 +- test_pool/mpam/error006.c | 14 +- test_pool/mpam/error007.c | 14 +- test_pool/mpam/error008.c | 16 +- test_pool/mpam/error009.c | 10 +- test_pool/mpam/error010.c | 18 +- test_pool/mpam/error011.c | 10 +- test_pool/mpam/error012.c | 20 +-- test_pool/mpam/error013.c | 24 +-- test_pool/mpam/error014.c | 24 +-- test_pool/mpam/feat001.c | 36 ++-- test_pool/mpam/intr001.c | 16 +- test_pool/mpam/intr002.c | 14 +- test_pool/mpam/intr003.c | 24 +-- test_pool/mpam/intr004.c | 26 +-- test_pool/mpam/intr005.c | 34 ++-- test_pool/mpam/intr006.c | 28 ++-- test_pool/mpam/mem001.c | 54 +++--- test_pool/mpam/mem002.c | 36 ++-- test_pool/mpam/mem003.c | 54 +++--- test_pool/mpam/monitor001.c | 26 +-- test_pool/mpam/monitor002.c | 26 +-- test_pool/mpam/monitor003.c | 22 +-- test_pool/mpam/monitor004.c | 22 +-- test_pool/mpam/monitor005.c | 32 ++-- test_pool/mpam/monitor006.c | 10 +- test_pool/mpam/monitor007.c | 24 +-- test_pool/mpam/monitor008.c | 24 +-- test_pool/mpam/mpam002.c | 28 ++-- test_pool/mpam/mpam003.c | 22 +-- test_pool/mpam/mpam004.c | 16 +- test_pool/mpam/mpam005.c | 24 +-- test_pool/mpam/mpam006.c | 38 ++--- test_pool/mpam/mpam007.c | 54 +++--- test_pool/mpam/partition001.c | 32 ++-- test_pool/mpam/partition002.c | 32 ++-- test_pool/mpam/partition003.c | 32 ++-- test_pool/mpam/partition004.c | 50 +++--- test_pool/mpam/partition005.c | 30 ++-- test_pool/mpam/partition006.c | 54 +++--- test_pool/mpam/reg001.c | 10 +- test_pool/mpam/reg002.c | 2 +- test_pool/mpam/reg003.c | 56 +++---- test_pool/mpam/reg004.c | 10 +- test_pool/mpam/reg005.c | 4 +- test_pool/mpam/reg006.c | 4 +- test_pool/nist_sts/test_n001.c | 24 +-- test_pool/pcie/p001.c | 2 +- test_pool/pcie/p002.c | 44 ++--- test_pool/pcie/p003.c | 12 +- test_pool/pcie/p004.c | 44 ++--- test_pool/pcie/p005.c | 48 +++--- test_pool/pcie/p006.c | 10 +- test_pool/pcie/p007.c | 6 +- test_pool/pcie/p008.c | 12 +- test_pool/pcie/p009.c | 8 +- test_pool/pcie/p010.c | 6 +- test_pool/pcie/p011.c | 10 +- test_pool/pcie/p017.c | 14 +- test_pool/pcie/p018.c | 8 +- test_pool/pcie/p019.c | 18 +- test_pool/pcie/p021.c | 2 +- test_pool/pcie/p023.c | 14 +- test_pool/pcie/p030.c | 22 +-- test_pool/pcie/p031.c | 6 +- test_pool/pcie/p032.c | 6 +- test_pool/pcie/p033.c | 8 +- test_pool/pcie/p035.c | 24 +-- test_pool/pcie/p036.c | 16 +- test_pool/pcie/p037.c | 8 +- test_pool/pcie/p038.c | 12 +- test_pool/pcie/p039.c | 10 +- test_pool/pcie/p042.c | 16 +- test_pool/pcie/p045.c | 38 ++--- test_pool/pcie/p046.c | 8 +- test_pool/pcie/p047.c | 12 +- test_pool/pcie/p051.c | 2 +- test_pool/pcie/p058.c | 34 ++-- test_pool/pcie/p061.c | 8 +- test_pool/pcie/p062.c | 12 +- test_pool/pcie/p063.c | 22 +-- test_pool/pcie/p064.c | 8 +- test_pool/pcie/p065.c | 14 +- test_pool/pcie/p066.c | 10 +- test_pool/pcie/p067.c | 8 +- test_pool/pcie/p068.c | 4 +- test_pool/pcie/p069.c | 12 +- test_pool/pcie/p070.c | 6 +- test_pool/pcie/p071.c | 18 +- test_pool/pcie/p072.c | 6 +- test_pool/pcie/p078.c | 18 +- test_pool/pcie/p079.c | 20 +-- test_pool/pcie/p080.c | 8 +- test_pool/pcie/p081.c | 24 +-- test_pool/pcie/p082.c | 18 +- test_pool/pcie/p083.c | 26 +-- test_pool/pcie/p084.c | 12 +- test_pool/pcie/p085.c | 8 +- test_pool/pcie/p086.c | 30 ++-- test_pool/pcie/p087.c | 12 +- test_pool/pcie/p089.c | 4 +- test_pool/pcie/p090.c | 10 +- test_pool/pcie/p091.c | 4 +- test_pool/pcie/p092.c | 22 +-- test_pool/pcie/p093.c | 20 +-- test_pool/pcie/p094.c | 40 ++--- test_pool/pcie/p095.c | 8 +- test_pool/pcie/p096.c | 30 ++-- test_pool/pcie/p097.c | 22 +-- test_pool/pcie/p100.c | 8 +- test_pool/pcie/p105.c | 6 +- test_pool/pe/pe001.c | 74 ++++----- test_pool/pe/pe002.c | 4 +- test_pool/pe/pe006.c | 2 +- test_pool/pe/pe009.c | 4 +- test_pool/pe/pe010.c | 8 +- test_pool/pe/pe011.c | 4 +- test_pool/pe/pe012.c | 2 +- test_pool/pe/pe014.c | 4 +- test_pool/pe/pe016.c | 16 +- test_pool/pe/pe020.c | 2 +- test_pool/pe/pe026.c | 2 +- test_pool/pe/pe032.c | 4 +- test_pool/pe/pe033.c | 2 +- test_pool/pe/pe034.c | 2 +- test_pool/pe/pe036.c | 2 +- test_pool/pe/pe037.c | 4 +- test_pool/pe/pe040.c | 4 +- test_pool/pe/pe043.c | 4 +- test_pool/pe/pe047.c | 2 +- test_pool/pe/pe053.c | 4 +- test_pool/pe/pe056.c | 6 +- test_pool/pe/pe060.c | 2 +- test_pool/pe/pe061.c | 4 +- test_pool/pe/pe062.c | 22 +-- test_pool/pe/pe065.c | 2 +- test_pool/pe/pe066.c | 14 +- test_pool/peripherals/d001.c | 31 ++-- test_pool/peripherals/d002.c | 12 +- test_pool/peripherals/d003.c | 36 ++-- test_pool/peripherals/d004.c | 16 +- test_pool/pfdi/pfdi001.c | 18 +- test_pool/pfdi/pfdi002.c | 30 ++-- test_pool/pfdi/pfdi003.c | 10 +- test_pool/pfdi/pfdi004.c | 22 +-- test_pool/pfdi/pfdi005.c | 36 ++-- test_pool/pfdi/pfdi006.c | 24 +-- test_pool/pfdi/pfdi007.c | 68 ++++---- test_pool/pfdi/pfdi008.c | 42 ++--- test_pool/pfdi/pfdi009.c | 26 +-- test_pool/pfdi/pfdi010.c | 22 +-- test_pool/pfdi/pfdi011.c | 18 +- test_pool/pfdi/pfdi012.c | 72 ++++---- test_pool/pfdi/pfdi013.c | 20 +-- test_pool/pfdi/pfdi014.c | 22 +-- test_pool/pfdi/pfdi016.c | 22 +-- test_pool/pfdi/pfdi017.c | 22 +-- test_pool/pfdi/pfdi018.c | 22 +-- test_pool/pfdi/pfdi019.c | 24 +-- test_pool/pfdi/pfdi020.c | 26 +-- test_pool/pfdi/pfdi021.c | 22 +-- test_pool/pfdi/pfdi022.c | 22 +-- test_pool/pfdi/pfdi023.c | 22 +-- test_pool/pfdi/pfdi024.c | 22 +-- test_pool/pfdi/pfdi025.c | 22 +-- test_pool/pfdi/pfdi026.c | 22 +-- test_pool/pfdi/pfdi027.c | 34 ++-- test_pool/pfdi/pfdi028.c | 28 ++-- test_pool/pfdi/pfdi029.c | 22 +-- test_pool/pfdi/pfdi030.c | 22 +-- test_pool/pfdi/pfdi031.c | 22 +-- test_pool/pmu/pmu001.c | 4 +- test_pool/pmu/pmu004.c | 32 ++-- test_pool/pmu/pmu005.c | 20 +-- test_pool/pmu/pmu008.c | 38 ++--- test_pool/pmu/pmu009.c | 28 ++-- test_pool/power_wakeup/u001.c | 8 +- test_pool/power_wakeup/u002.c | 14 +- test_pool/power_wakeup/u003.c | 14 +- test_pool/power_wakeup/u004.c | 20 +-- test_pool/power_wakeup/u005.c | 20 +-- test_pool/power_wakeup/u006.c | 32 ++-- test_pool/ras/ras001.c | 18 +- test_pool/ras/ras002.c | 22 +-- test_pool/ras/ras003.c | 20 +-- test_pool/ras/ras004.c | 22 +-- test_pool/ras/ras005.c | 24 +-- test_pool/ras/ras006.c | 46 +++--- test_pool/ras/ras007.c | 16 +- test_pool/ras/ras008.c | 6 +- test_pool/ras/ras009.c | 39 +++-- test_pool/ras/ras010.c | 4 +- test_pool/ras/ras011.c | 70 ++++---- test_pool/ras/ras012.c | 12 +- test_pool/ras/ras013.c | 14 +- test_pool/ras/ras014.c | 10 +- test_pool/ras/ras016.c | 16 +- test_pool/ras/ras017.c | 18 +- test_pool/ras/ras018.c | 44 +++-- test_pool/smmu/i001.c | 4 +- test_pool/smmu/i002.c | 12 +- test_pool/smmu/i003.c | 14 +- test_pool/smmu/i004.c | 14 +- test_pool/smmu/i005.c | 10 +- test_pool/smmu/i006.c | 8 +- test_pool/smmu/i007.c | 8 +- test_pool/smmu/i008.c | 20 +-- test_pool/smmu/i009.c | 28 ++-- test_pool/smmu/i010.c | 12 +- test_pool/smmu/i011.c | 12 +- test_pool/smmu/i012.c | 14 +- test_pool/smmu/i013.c | 4 +- test_pool/smmu/i014.c | 4 +- test_pool/smmu/i015.c | 6 +- test_pool/smmu/i016.c | 8 +- test_pool/smmu/i017.c | 14 +- test_pool/smmu/i018.c | 6 +- test_pool/smmu/i019.c | 8 +- test_pool/smmu/i020.c | 4 +- test_pool/smmu/i021.c | 16 +- test_pool/smmu/i022.c | 30 ++-- test_pool/smmu/i023.c | 22 +-- test_pool/smmu/i024.c | 6 +- test_pool/smmu/i025.c | 18 +- test_pool/timer/t001.c | 12 +- test_pool/timer/t002.c | 10 +- test_pool/timer/t003.c | 34 ++-- test_pool/timer/t004.c | 18 +- test_pool/timer/t005.c | 14 +- test_pool/timer/t006.c | 4 +- test_pool/timer/t008.c | 32 ++-- test_pool/tpm/tpm001.c | 4 +- test_pool/tpm/tpm002.c | 26 +-- test_pool/watchdog/w001.c | 10 +- test_pool/watchdog/w002.c | 24 +-- test_pool/watchdog/w003.c | 10 +- val/ValLib.inf | 1 + val/ValLibRB.inf | 1 + val/driver/gic/acs_exception.c | 10 +- val/driver/gic/gic.c | 4 +- val/driver/gic/its/acs_gic_its.c | 30 ++-- val/driver/gic/its/acs_gic_redistributor.c | 6 +- val/driver/gic/v2/gic_v2.c | 6 +- val/driver/gic/v3/gic_v3.c | 6 +- val/driver/gic/v3/gic_v3_extended.c | 4 +- val/driver/pcie/pcie.c | 6 +- val/driver/smmu_v3/smmu_v3.c | 170 +++++++++---------- val/include/acs_common.h | 1 + val/include/acs_drtm.h | 8 +- val/include/pal_interface.h | 2 +- val/include/val_interface.h | 17 +- val/include/val_logger.h | 1 - val/src/AArch64/Drtm.S | 2 +- val/src/AArch64/SystemReg.S | 2 +- val/src/AArch64/VecTable.S | 2 +- val/src/acs_cxl.c | 182 ++++++++++----------- val/src/acs_dma.c | 17 +- val/src/acs_ete.c | 14 +- val/src/acs_exerciser.c | 47 +++--- val/src/acs_gic.c | 60 +++---- val/src/acs_gic_support.c | 28 ++-- val/src/acs_gic_v2m.c | 8 +- val/src/acs_interface.c | 36 ++-- val/src/acs_iovirt.c | 92 +++++------ val/src/acs_memory.c | 19 +-- val/src/acs_mmu.c | 62 +++---- val/src/acs_mpam.c | 118 ++++++------- val/src/acs_msc_error.c | 36 ++-- val/src/acs_pcc.c | 9 +- val/src/acs_pcie.c | 180 ++++++++++---------- val/src/acs_pe.c | 25 ++- val/src/acs_pe_infra.c | 62 +++---- val/src/acs_peripherals.c | 28 ++-- val/src/acs_pfdi.c | 4 +- val/src/acs_pgt.c | 24 ++- val/src/acs_pmu.c | 53 +++--- val/src/acs_ras.c | 67 ++++---- val/src/acs_smmu.c | 8 +- val/src/acs_status.c | 36 ++-- val/src/acs_test_infra.c | 94 +++++------ val/src/acs_timer.c | 20 +-- val/src/acs_timer_support.c | 26 +-- val/src/acs_tpm.c | 11 +- val/src/acs_wakeup.c | 8 +- val/src/acs_wd.c | 10 +- val/src/bsa_execute_test.c | 88 +++++----- val/src/drtm_execute_test.c | 18 +- val/src/mpam_execute_test.c | 24 +-- val/src/pc_bsa_execute_test.c | 40 ++--- val/src/rule_based_execution_helpers.c | 66 ++++---- val/src/rule_based_orchestrator.c | 33 ++-- val/src/sbsa_execute_test.c | 104 ++++++------ val/src/test_wrappers.c | 2 +- val/src/val_logger.c | 12 +- 422 files changed, 4384 insertions(+), 4408 deletions(-) diff --git a/apps/baremetal/acs_common.c b/apps/baremetal/acs_common.c index 458eb078..e917009f 100644 --- a/apps/baremetal/acs_common.c +++ b/apps/baremetal/acs_common.c @@ -77,8 +77,8 @@ acs_apply_el3_params(void) return; if (!g_el3_param_addr) { - val_print(ACS_PRINT_WARN, - "EL3 param magic set but param address is 0, ignoring\n", 0); + val_print(WARN, + "EL3 param magic set but param address is 0, ignoring\n"); return; } @@ -86,15 +86,15 @@ acs_apply_el3_params(void) /* Optional: version check (kept minimal, versioned for future proofing) */ if (params->version != ACS_EL3_PARAM_VERSION) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "Unsupported EL3 param version %ld, ignoring\n", params->version); return; } - val_print(ACS_PRINT_DEBUG, "EL3 params: tests=0x%lx", params->rule_array_addr); - val_print(ACS_PRINT_DEBUG, " (%ld),", params->rule_array_count); - val_print(ACS_PRINT_DEBUG, " modules=0x%lx", params->module_array_addr); - val_print(ACS_PRINT_DEBUG, " (%ld)\n", params->module_array_count); + val_print(DEBUG, "EL3 params: tests=0x%lx", params->rule_array_addr); + val_print(DEBUG, " (%ld),", params->rule_array_count); + val_print(DEBUG, " modules=0x%lx", params->module_array_addr); + val_print(DEBUG, " (%ld)\n", params->module_array_count); /* Override tests if provided */ if (params->rule_array_addr && params->rule_array_count) { @@ -130,10 +130,10 @@ acs_apply_compile_params(void) */ g_print_level = ACS_VERBOSE_LEVEL; - if (g_print_level < ACS_PRINT_INFO) - g_print_level = ACS_PRINT_INFO; - else if (g_print_level > ACS_PRINT_ERR) - g_print_level = ACS_PRINT_ERR; + if (g_print_level < TRACE) + g_print_level = TRACE; + else if (g_print_level > ERROR) + g_print_level = ERROR; #endif return; diff --git a/apps/baremetal/acs_helpers.c b/apps/baremetal/acs_helpers.c index a8d13ce9..53af1cf3 100644 --- a/apps/baremetal/acs_helpers.c +++ b/apps/baremetal/acs_helpers.c @@ -268,9 +268,9 @@ createInfoTable( { uint64_t *InfoTable; - val_print(ACS_PRINT_DEBUG, "\n Allocating memory for ", 0); - val_print(ACS_PRINT_DEBUG, table_name, 0); - val_print(ACS_PRINT_DEBUG, " info table", 0); + val_print(DEBUG, "\n Allocating memory for "); + val_print(DEBUG, table_name); + val_print(DEBUG, " info table"); InfoTable = val_aligned_alloc(SIZE_4K, info_table_size); diff --git a/apps/baremetal/bsa_main.c b/apps/baremetal/bsa_main.c index 99864d65..d1bb2b1a 100644 --- a/apps/baremetal/bsa_main.c +++ b/apps/baremetal/bsa_main.c @@ -106,14 +106,14 @@ uint32_t apply_user_config_and_defaults(void) } /* Check sanity of print level, default accordingly */ - if (g_print_level < ACS_PRINT_INFO) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_INFO); - g_print_level = ACS_PRINT_INFO; - } else if (g_print_level > ACS_PRINT_ERR) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_ERR); - g_print_level = ACS_PRINT_ERR; + if (g_print_level < TRACE) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", TRACE); + g_print_level = TRACE; + } else if (g_print_level > ERROR) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", ERROR); + g_print_level = ERROR; } return ACS_STATUS_PASS; @@ -137,7 +137,7 @@ ShellAppMainbsa() Status = apply_user_config_and_defaults(); if (Status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\napply_user_config_and_defaults() failed, Exiting...\n", 0); + val_print(ERROR, "\napply_user_config_and_defaults() failed, Exiting...\n"); goto exit_acs; } @@ -150,18 +150,18 @@ ShellAppMainbsa() */ acs_apply_el3_params(); - val_print(ACS_PRINT_TEST, "\n\n BSA Architecture Compliance Suite\n", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", BSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", BSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", BSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n BSA Architecture Compliance Suite\n"); + val_print(INFO, "\n Version %d.", BSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", BSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", BSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, BSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); #if ACS_ENABLE_MMU - val_print(ACS_PRINT_TEST, " Enabling MMU\n", 0); + val_print(INFO, " Enabling MMU\n"); /* Create MMU page tables before enabling the MMU at EL2 */ if (val_setup_mmu()) @@ -171,10 +171,10 @@ ShellAppMainbsa() if (val_enable_mmu()) return ACS_STATUS_FAIL; #else - val_print(ACS_PRINT_TEST, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n", 0); + val_print(INFO, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n"); #endif - val_print(ACS_PRINT_TEST, " Creating Platform Information Tables\n", 0); + val_print(INFO, " Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) @@ -244,20 +244,20 @@ ShellAppMainbsa() /* Merge arch rules if any, then apply CLI filters (-skip, -m, -skipmodule) */ g_rule_count = filter_rule_list_by_cli(&g_rule_list, g_rule_count); if (g_rule_count == 0 || g_rule_list == NULL) { - val_print(ACS_PRINT_ERR, "\nRule list empty, nothing to execute, Exiting...\n", 0); + val_print(ERROR, "\nRule list empty, nothing to execute, Exiting...\n"); return -1; } /* Run rule based test orchestrator */ run_tests(g_rule_list, g_rule_count); } else { - val_print(ACS_PRINT_ERR, "\nInvalid rule list or arch selected, Exiting...\n", 0); + val_print(ERROR, "\nInvalid rule list or arch selected, Exiting...\n"); return -1; } print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** BSA tests complete. Reset the system. ***\n\n", 0); + val_print(INFO, "\n *** BSA tests complete. Reset the system. ***\n\n"); exit_acs: freeAcsMeM(); diff --git a/apps/baremetal/pc_bsa_main.c b/apps/baremetal/pc_bsa_main.c index 5c0bb829..c6c8220c 100644 --- a/apps/baremetal/pc_bsa_main.c +++ b/apps/baremetal/pc_bsa_main.c @@ -120,14 +120,14 @@ apply_user_config_and_defaults(void) } /* Check sanity of print level, default accordingly */ - if (g_print_level < ACS_PRINT_INFO) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_INFO); - g_print_level = ACS_PRINT_INFO; - } else if (g_print_level > ACS_PRINT_ERR) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_ERR); - g_print_level = ACS_PRINT_ERR; + if (g_print_level < TRACE) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", TRACE); + g_print_level = TRACE; + } else if (g_print_level > ERROR) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", ERROR); + g_print_level = ERROR; } return ACS_STATUS_PASS; @@ -149,7 +149,7 @@ ShellAppMainpcbsa(void) Status = apply_user_config_and_defaults(); if (Status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\napply_user_config_and_defaults() failed, Exiting...\n", 0); + val_print(ERROR, "\napply_user_config_and_defaults() failed, Exiting...\n"); goto exit_acs; } @@ -163,7 +163,7 @@ ShellAppMainpcbsa(void) acs_apply_el3_params(); #if ACS_ENABLE_MMU - val_print(ACS_PRINT_TEST, " Enabling MMU\n", 0); + val_print(INFO, " Enabling MMU\n"); /* Create MMU page tables before enabling the MMU at EL2 */ if (val_setup_mmu()) @@ -173,20 +173,20 @@ ShellAppMainpcbsa(void) if (val_enable_mmu()) return ACS_STATUS_FAIL; #else - val_print(ACS_PRINT_TEST, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n", 0); + val_print(INFO, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n"); #endif - val_print(ACS_PRINT_TEST, "\n\n PC BSA Architecture Compliance Suite\n", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", PC_BSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", PC_BSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", PC_BSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n PC BSA Architecture Compliance Suite\n"); + val_print(INFO, "\n Version %d.", PC_BSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", PC_BSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", PC_BSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, PCBSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, " Creating Platform Information Tables\n", 0); + val_print(INFO, " Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) @@ -261,20 +261,20 @@ ShellAppMainpcbsa(void) /* Merge arch rules if any, then apply CLI filters (-skip, -m, -skipmodule) */ g_rule_count = filter_rule_list_by_cli(&g_rule_list, g_rule_count); if (g_rule_count == 0 || g_rule_list == NULL) { - val_print(ACS_PRINT_ERR, "\nRule list empty, nothing to execute, Exiting...\n", 0); + val_print(ERROR, "\nRule list empty, nothing to execute, Exiting...\n"); return -1; } /* Run rule based test orchestrator */ run_tests(g_rule_list, g_rule_count); } else { - val_print(ACS_PRINT_ERR, "\nInvalid rule list or arch selected, Exiting...\n", 0); + val_print(ERROR, "\nInvalid rule list or arch selected, Exiting...\n"); return -1; } print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** PC BSA tests complete. Reset the system. ***\n\n", 0); + val_print(INFO, "\n *** PC BSA tests complete. Reset the system. ***\n\n"); exit_acs: freeAcsMem(); diff --git a/apps/baremetal/sbsa_main.c b/apps/baremetal/sbsa_main.c index 91f9ed26..eac7f438 100644 --- a/apps/baremetal/sbsa_main.c +++ b/apps/baremetal/sbsa_main.c @@ -125,14 +125,14 @@ uint32_t apply_user_config_and_defaults(void) } /* Check sanity of print level, default accordingly */ - if (g_print_level < ACS_PRINT_INFO) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_INFO); - g_print_level = ACS_PRINT_INFO; - } else if (g_print_level > ACS_PRINT_ERR) { - val_print(ACS_PRINT_ERR, "\nPrint Level %d is not supported.\n", g_print_level); - val_print(ACS_PRINT_ERR, "\nSetting Print level to %d\n", ACS_PRINT_ERR); - g_print_level = ACS_PRINT_ERR; + if (g_print_level < TRACE) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", TRACE); + g_print_level = TRACE; + } else if (g_print_level > ERROR) { + val_print(ERROR, "\nPrint Level %d is not supported.\n", g_print_level); + val_print(ERROR, "\nSetting Print level to %d\n", ERROR); + g_print_level = ERROR; } /* Set g_build_sbsa hint for test */ @@ -217,7 +217,7 @@ ShellAppMainsbsa() Status = apply_user_config_and_defaults(); if (Status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\napply_user_config_and_defaults() failed, Exiting...\n", 0); + val_print(ERROR, "\napply_user_config_and_defaults() failed, Exiting...\n"); goto exit_acs; } @@ -231,7 +231,7 @@ ShellAppMainsbsa() if (val_enable_mmu()) return ACS_STATUS_FAIL; #else - val_print(ACS_PRINT_TEST, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n", 0); + val_print(INFO, "Skipping MMU setup/enable (ACS_ENABLE_MMU=0)\n"); #endif /* apply any compile-time test/module overrides before * we look at g_num_modules and build masks. @@ -242,18 +242,18 @@ ShellAppMainsbsa() */ acs_apply_el3_params(); - val_print(ACS_PRINT_TEST, "\n\n SBSA Architecture Compliance Suite\n", 0); - val_print(ACS_PRINT_TEST, " Version %d.", SBSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", SBSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", SBSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n SBSA Architecture Compliance Suite\n"); + val_print(INFO, " Version %d.", SBSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", SBSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", SBSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, SBSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, " Creating Platform Information Tables\n", 0); + val_print(INFO, " Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) @@ -335,20 +335,20 @@ ShellAppMainsbsa() /* Merge arch rules if any, then apply CLI filters (-skip, -m, -skipmodule) */ g_rule_count = filter_rule_list_by_cli(&g_rule_list, g_rule_count); if (g_rule_count == 0 || g_rule_list == NULL) { - val_print(ACS_PRINT_ERR, "\nRule list empty, nothing to execute, Exiting...\n", 0); + val_print(ERROR, "\nRule list empty, nothing to execute, Exiting...\n"); return -1; } /* Run rule based test orchestrator */ run_tests(g_rule_list, g_rule_count); } else { - val_print(ACS_PRINT_ERR, "\nInvalid rule list or arch selected, Exiting...\n", 0); + val_print(ERROR, "\nInvalid rule list or arch selected, Exiting...\n"); return -1; } print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** SBSA tests complete. Reset the system. ***\n\n", 0); + val_print(INFO, "\n *** SBSA tests complete. Reset the system. ***\n\n"); exit_acs: freeAcsMeM(); diff --git a/apps/uefi/acs.h b/apps/uefi/acs.h index 09a14938..178cdb59 100644 --- a/apps/uefi/acs.h +++ b/apps/uefi/acs.h @@ -61,7 +61,7 @@ #define PFDI_ACS_MINOR_VER 8 #define PFDI_ACS_SUBMINOR_VER 0 -#define G_PRINT_LEVEL ACS_PRINT_TEST +#define G_PRINT_LEVEL INFO #define G_SW_OS 0 #define G_SW_HYP 1 diff --git a/apps/uefi/acs_helpers.c b/apps/uefi/acs_helpers.c index a53039dd..71909ff7 100644 --- a/apps/uefi/acs_helpers.c +++ b/apps/uefi/acs_helpers.c @@ -1044,62 +1044,62 @@ print_selection_summary(void) UINT32 i; RULE_ID_e rid; UINT32 mid; - val_print(ACS_PRINT_TEST, "\nSelected rules: ", 0); + val_print(INFO, "\nSelected rules: "); for (i = 0; i < g_rule_count; i++) { rid = g_rule_list[i]; if (rid < RULE_ID_SENTINEL && rule_id_string[rid] != NULL) { - val_print(ACS_PRINT_TEST, (char8_t *)rule_id_string[rid], 0); + val_print(INFO, (char8_t *)rule_id_string[rid]); } else { - val_print(ACS_PRINT_TEST, "", 0); + val_print(INFO, ""); } if (i + 1 < g_rule_count) - val_print(ACS_PRINT_TEST, ",", 0); + val_print(INFO, ","); } - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); if (g_skip_rule_count > 0 && g_skip_rule_list != NULL) { - val_print(ACS_PRINT_TEST, "Skipped rules (-skip): ", 0); + val_print(INFO, "Skipped rules (-skip): "); for (i = 0; i < g_skip_rule_count; i++) { rid = g_skip_rule_list[i]; if (rid < RULE_ID_SENTINEL && rule_id_string[rid] != NULL) { - val_print(ACS_PRINT_TEST, (char8_t *)rule_id_string[rid], 0); + val_print(INFO, (char8_t *)rule_id_string[rid]); } else { - val_print(ACS_PRINT_TEST, "", 0); + val_print(INFO, ""); } if (i + 1 < g_skip_rule_count) - val_print(ACS_PRINT_TEST, ",", 0); + val_print(INFO, ","); } - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); } if (g_num_modules > 0 && g_execute_modules != NULL) { - val_print(ACS_PRINT_TEST, "Selected modules (-m): ", 0); + val_print(INFO, "Selected modules (-m): "); for (i = 0; i < g_num_modules; i++) { mid = g_execute_modules[i]; if (mid < MODULE_ID_SENTINEL && module_name_string[mid] != NULL) { - val_print(ACS_PRINT_TEST, (char8_t *)module_name_string[mid], 0); + val_print(INFO, (char8_t *)module_name_string[mid]); } else { - val_print(ACS_PRINT_TEST, "", 0); + val_print(INFO, ""); } if (i + 1 < g_num_modules) - val_print(ACS_PRINT_TEST, ",", 0); + val_print(INFO, ","); } - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); } if (g_num_skip_modules > 0 && g_skip_modules != NULL) { - val_print(ACS_PRINT_TEST, "Skipped modules (-skipmodule): ", 0); + val_print(INFO, "Skipped modules (-skipmodule): "); for (i = 0; i < g_num_skip_modules; i++) { mid = g_skip_modules[i]; if (mid < MODULE_ID_SENTINEL && module_name_string[mid] != NULL) { - val_print(ACS_PRINT_TEST, (char8_t *)module_name_string[mid], 0); + val_print(INFO, (char8_t *)module_name_string[mid]); } else { - val_print(ACS_PRINT_TEST, "", 0); + val_print(INFO, ""); } if (i + 1 < g_num_skip_modules) - val_print(ACS_PRINT_TEST, ",", 0); + val_print(INFO, ","); } - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); } } diff --git a/apps/uefi/bsa_main.c b/apps/uefi/bsa_main.c index 575daccc..fff98439 100644 --- a/apps/uefi/bsa_main.c +++ b/apps/uefi/bsa_main.c @@ -137,8 +137,8 @@ apply_cli_defaults(VOID) /* Check sanity of value of level */ if (g_level_value >= BSA_LEVEL_SENTINEL) { - val_print(ACS_PRINT_ERR, "\nInvalid level value passed (%d), ", g_level_value); - val_print(ACS_PRINT_ERR, "value should be less than %d.", BSA_LEVEL_SENTINEL); + val_print(ERROR, "\nInvalid level value passed (%d), ", g_level_value); + val_print(ERROR, "value should be less than %d.", BSA_LEVEL_SENTINEL); return ACS_STATUS_FAIL; } @@ -156,16 +156,16 @@ execute_tests() goto exit_acs; } - val_print(ACS_PRINT_TEST, "\n\n BSA Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", BSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", BSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", BSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n BSA Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", BSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", BSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", BSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, BSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); /* Modifying default memory attributes of UEFI*/ val_setup_mair_register(); @@ -210,7 +210,7 @@ execute_tests() print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** BSA tests complete. Reset the system. ***\n\n", 0); + val_print(INFO, "\n *** BSA tests complete. Reset the system. ***\n\n"); exit_acs: diff --git a/apps/uefi/drtm_main.c b/apps/uefi/drtm_main.c index 30f27cef..bf9f7692 100644 --- a/apps/uefi/drtm_main.c +++ b/apps/uefi/drtm_main.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -301,12 +301,12 @@ execute_tests() { UINT32 Status; - val_print(ACS_PRINT_TEST, "\n\n DRTM Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", DRTM_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", DRTM_ACS_MINOR_VER); + val_print(INFO, "\n\n DRTM Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", DRTM_ACS_MAJOR_VER); + val_print(INFO, "%d\n", DRTM_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "\n Starting tests with print level : %2d\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "\n Starting tests with print level : %2d\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) @@ -329,15 +329,15 @@ execute_tests() Status |= val_drtm_execute_dl_tests(val_pe_get_num()); /* Print Summary */ - val_print(ACS_PRINT_ERR, "\n -------------------------------------------------------\n", 0); - val_print(ACS_PRINT_ERR, " Total Tests run = %4d", g_acs_tests_total); - val_print(ACS_PRINT_ERR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ACS_PRINT_ERR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ACS_PRINT_ERR, " -------------------------------------------------------\n", 0); + val_print(INFO, "\n -------------------------------------------------------\n"); + val_print(INFO, " Total Tests run = %4d", g_acs_tests_total); + val_print(INFO, " Tests Passed = %4d", g_acs_tests_pass); + val_print(INFO, " Tests Failed = %4d\n", g_acs_tests_fail); + val_print(INFO, " -------------------------------------------------------\n"); freeBsaAcsMem(); - val_print(ACS_PRINT_ERR, "\n *** DRTM tests complete. *** \n\n", 0); + val_print(INFO, "\n *** DRTM tests complete. *** \n\n"); if (g_acs_log_file_handle) { ShellCloseFile(&g_acs_log_file_handle); diff --git a/apps/uefi/mem_test_main.c b/apps/uefi/mem_test_main.c index bd492cd3..8aa6b6d3 100644 --- a/apps/uefi/mem_test_main.c +++ b/apps/uefi/mem_test_main.c @@ -708,20 +708,20 @@ execute_tests() VOID *branch_label; UINT32 Status; - val_print(ACS_PRINT_TEST, "\n\n BSA Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", BSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", BSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", BSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n BSA Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", BSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", BSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", BSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, BSA_LEVEL_PRINT_FORMAT(g_bsa_level, g_bsa_only_level), + val_print(INFO, BSA_LEVEL_PRINT_FORMAT(g_bsa_level, g_bsa_only_level), (g_bsa_level > BSA_MAX_LEVEL_SUPPORTED) ? 0 : g_bsa_level); if (g_bsa_only_level) g_bsa_level = 0; - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); Status = createPeInfoTable(); @@ -756,11 +756,11 @@ execute_tests() val_pe_initialize_default_exception_handler(val_pe_default_esr); print_test_status: - val_print(ACS_PRINT_ERR, "\n -------------------------------------------------------\n", 0); - val_print(ACS_PRINT_ERR, " Total Tests run = %4d", g_acs_tests_total); - val_print(ACS_PRINT_ERR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ACS_PRINT_ERR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ACS_PRINT_ERR, " -------------------------------------------------------\n", 0); + val_print(ERROR, "\n -------------------------------------------------------\n"); + val_print(ERROR, " Total Tests run = %4d", g_acs_tests_total); + val_print(ERROR, " Tests Passed = %4d", g_acs_tests_pass); + val_print(ERROR, " Tests Failed = %4d\n", g_acs_tests_fail); + val_print(ERROR, " -------------------------------------------------------\n"); freeBsaAcsMem(); @@ -768,12 +768,12 @@ execute_tests() ShellCloseFile(&g_dtb_log_file_handle); } - val_print(ACS_PRINT_ERR, "\n *** BSA tests complete. Reset the system. ***\n\n", 0); + val_print(ERROR, "\n *** BSA tests complete. Reset the system. ***\n\n"); /*** Starting memory model consistency tests ***/ - val_print(ACS_PRINT_ERR, "\n\n *** Starting memory model consistency tests *** \n", 0); - val_print(ACS_PRINT_ERR, "\nInitializing kvm-unit-tests framework ...", 0); - val_print(ACS_PRINT_ERR, "\nLoad address of the image is: 0x%lx\n", (unsigned long)&_textbsa); + val_print(ERROR, "\n\n *** Starting memory model consistency tests *** \n"); + val_print(ERROR, "\nInitializing kvm-unit-tests framework ..."); + val_print(ERROR, "\nLoad address of the image is: 0x%lx\n", (unsigned long)&_textbsa); mem_model_execute_tests(myImageHandle, mySystemTable); if (g_acs_log_file_handle) { diff --git a/apps/uefi/mpam_main.c b/apps/uefi/mpam_main.c index e7d91dfa..f1e1fc86 100644 --- a/apps/uefi/mpam_main.c +++ b/apps/uefi/mpam_main.c @@ -404,8 +404,8 @@ execute_tests() /* check if PE supports MPAM extension, else skip all MPAM tests */ if (val_pe_feat_check(PE_FEAT_MPAM)) { - val_print(ACS_PRINT_TEST, - "\n PE MPAM extension unimplemented. Skipping all MPAM tests\n", 0); + val_print(INFO, + "\n PE MPAM extension unimplemented. Skipping all MPAM tests\n"); goto print_test_status; } @@ -430,7 +430,7 @@ execute_tests() /* Get total number of MSCs reported by MPAM ACPI table */ msc_node_cnt = val_mpam_get_msc_count(); if (msc_node_cnt == 0) { - val_print(ACS_PRINT_TEST, "\n *** Exiting suite - No MPAM nodes *** \n", 0); + val_print(INFO, "\n *** Exiting suite - No MPAM nodes *** \n"); goto print_test_status; } @@ -454,11 +454,11 @@ execute_tests() FreeMpamAcsMem(); print_test_status: - val_print(ACS_PRINT_ERR, "\n ------------------------------------------------------- \n", 0); - val_print(ACS_PRINT_ERR, " Total Tests run = %4d;", g_acs_tests_total); - val_print(ACS_PRINT_ERR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ACS_PRINT_ERR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ACS_PRINT_ERR, " --------------------------------------------------------- \n", 0); + val_print(ERROR, "\n ------------------------------------------------------- \n"); + val_print(ERROR, " Total Tests run = %4d;", g_acs_tests_total); + val_print(ERROR, " Tests Passed = %4d", g_acs_tests_pass); + val_print(ERROR, " Tests Failed = %4d\n", g_acs_tests_fail); + val_print(ERROR, " --------------------------------------------------------- \n"); if (g_acs_log_file_handle) { ShellCloseFile(&g_acs_log_file_handle); diff --git a/apps/uefi/pc_bsa_main.c b/apps/uefi/pc_bsa_main.c index d5e8502a..f1f4a93d 100644 --- a/apps/uefi/pc_bsa_main.c +++ b/apps/uefi/pc_bsa_main.c @@ -118,8 +118,8 @@ apply_cli_defaults(VOID) /* Check sanity of value of level */ if (g_level_value >= PCBSA_LEVEL_SENTINEL) { - val_print(ACS_PRINT_ERR, "\nInvalid level value passed (%d), ", g_level_value); - val_print(ACS_PRINT_ERR, "value should be less than %d.", PCBSA_LEVEL_SENTINEL); + val_print(ERROR, "\nInvalid level value passed (%d), ", g_level_value); + val_print(ERROR, "value should be less than %d.", PCBSA_LEVEL_SENTINEL); return ACS_STATUS_FAIL; } @@ -137,17 +137,17 @@ execute_tests() goto exit_acs; } - val_print(ACS_PRINT_TEST, "\n\n PC BSA Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", PC_BSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", PC_BSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", PC_BSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n PC BSA Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", PC_BSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", PC_BSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", PC_BSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, BSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); /* Modifying default memory attributes of UEFI*/ val_setup_mair_register(); @@ -194,7 +194,7 @@ execute_tests() print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** PC BSA tests complete. Reset the system. ***\n\n", 0); + val_print(ERROR, "\n *** PC BSA tests complete. Reset the system. ***\n\n"); freeAcsMem(); diff --git a/apps/uefi/pfdi_main.c b/apps/uefi/pfdi_main.c index f8842b75..04b4f71e 100644 --- a/apps/uefi/pfdi_main.c +++ b/apps/uefi/pfdi_main.c @@ -79,8 +79,8 @@ apply_cli_defaults(void) } if (g_level_value >= PFDI_LEVEL_SENTINEL) { - val_print(ACS_PRINT_ERR, "\nInvalid level value passed (%d), ", g_level_value); - val_print(ACS_PRINT_ERR, "value should be less than %d.", PFDI_LEVEL_SENTINEL); + val_print(ERROR, "\nInvalid level value passed (%d), ", g_level_value); + val_print(ERROR, "value should be less than %d.", PFDI_LEVEL_SENTINEL); return ACS_STATUS_FAIL; } @@ -97,13 +97,13 @@ execute_tests() goto exit_close; } - val_print(ACS_PRINT_TEST, "\n\n PFDI Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", PFDI_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", PFDI_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", PFDI_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n PFDI Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", PFDI_ACS_MAJOR_VER); + val_print(INFO, "%d.", PFDI_ACS_MINOR_VER); + val_print(INFO, "%d\n", PFDI_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, "\n Starting tests with print level : %2d\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "\n Starting tests with print level : %2d\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) @@ -117,7 +117,7 @@ execute_tests() Status = val_pfdi_check_implementation(); if (Status == PFDI_ACS_NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n PFDI not implemented - Skipping all PFDI tests\n", 0); + val_print(ERROR, "\n PFDI not implemented - Skipping all PFDI tests\n"); goto exit_summary; } else if (Status != ACS_STATUS_PASS) { goto exit_summary; @@ -131,12 +131,12 @@ execute_tests() print_selection_summary(); run_tests(g_rule_list, g_rule_count); } else { - val_print(ACS_PRINT_TEST, "\nNo rules selected for execution.\n", 0); + val_print(INFO, "\nNo rules selected for execution.\n"); } exit_summary: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** PFDI tests complete. *** \n\n", 0); + val_print(ERROR, "\n *** PFDI tests complete. *** \n\n"); exit_close: freePfdiAcsMem(); diff --git a/apps/uefi/sbsa_main.c b/apps/uefi/sbsa_main.c index 281b97ca..af5f17e9 100644 --- a/apps/uefi/sbsa_main.c +++ b/apps/uefi/sbsa_main.c @@ -139,8 +139,8 @@ apply_cli_defaults(VOID) /* Check sanity of value of level */ if (g_level_value >= SBSA_LEVEL_SENTINEL) { - val_print(ACS_PRINT_ERR, "\nInvalid level value passed (%d), ", g_level_value); - val_print(ACS_PRINT_ERR, "value should be less than %d.", SBSA_LEVEL_SENTINEL); + val_print(ERROR, "\nInvalid level value passed (%d), ", g_level_value); + val_print(ERROR, "value should be less than %d.", SBSA_LEVEL_SENTINEL); return ACS_STATUS_FAIL; } @@ -162,16 +162,16 @@ execute_tests() goto exit_acs; } - val_print(ACS_PRINT_ERR, "\n\n SBSA Architecture Compliance Suite\n", 0); - val_print(ACS_PRINT_ERR, " Version %d.", SBSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_ERR, "%d.", SBSA_ACS_MINOR_VER); - val_print(ACS_PRINT_ERR, "%d\n", SBSA_ACS_SUBMINOR_VER); + val_print(ERROR, "\n\n SBSA Architecture Compliance Suite\n"); + val_print(ERROR, " Version %d.", SBSA_ACS_MAJOR_VER); + val_print(ERROR, "%d.", SBSA_ACS_MINOR_VER); + val_print(ERROR, "%d\n", SBSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, SBSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); /* Modifying default memory attributes of UEFI*/ val_setup_mair_register(); @@ -225,7 +225,7 @@ execute_tests() print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** SBSA tests complete. Reset the system. ***\n\n", 0); + val_print(INFO, "\n *** SBSA tests complete. Reset the system. ***\n\n"); freeAcsMem(); diff --git a/apps/uefi/sbsa_nist_main.c b/apps/uefi/sbsa_nist_main.c index ec6fd1b0..09e20d16 100644 --- a/apps/uefi/sbsa_nist_main.c +++ b/apps/uefi/sbsa_nist_main.c @@ -688,20 +688,20 @@ execute_tests() VOID *branch_label; UINT32 Status; - val_print(ACS_PRINT_ERR, "\n\n SBSA Architecture Compliance Suite\n", 0); - val_print(ACS_PRINT_ERR, " Version %d.", SBSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_ERR, "%d.", SBSA_ACS_MINOR_VER); - val_print(ACS_PRINT_ERR, "%d\n", SBSA_ACS_SUBMINOR_VER); + val_print(ERROR, "\n\n SBSA Architecture Compliance Suite\n"); + val_print(ERROR, " Version %d.", SBSA_ACS_MAJOR_VER); + val_print(ERROR, "%d.", SBSA_ACS_MINOR_VER); + val_print(ERROR, "%d\n", SBSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, SBSA_LEVEL_PRINT_FORMAT(g_sbsa_level, g_sbsa_only_level), + val_print(INFO, SBSA_LEVEL_PRINT_FORMAT(g_sbsa_level, g_sbsa_only_level), (g_sbsa_level > SBSA_MAX_LEVEL_SUPPORTED) ? 0 : g_sbsa_level); if (g_sbsa_only_level) g_sbsa_level = 0; - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); Status = createPeInfoTable(); @@ -750,15 +750,15 @@ execute_tests() val_pe_initialize_default_exception_handler(val_pe_default_esr); print_test_status: - val_print(ACS_PRINT_ERR, "\n -------------------------------------------------------\n", 0); - val_print(ACS_PRINT_ERR, " Total Tests run = %4d", g_acs_tests_total); - val_print(ACS_PRINT_ERR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ACS_PRINT_ERR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ACS_PRINT_ERR, " -------------------------------------------------------\n", 0); + val_print(ERROR, "\n -------------------------------------------------------\n"); + val_print(ERROR, " Total Tests run = %4d", g_acs_tests_total); + val_print(ERROR, " Tests Passed = %4d", g_acs_tests_pass); + val_print(ERROR, " Tests Failed = %4d\n", g_acs_tests_fail); + val_print(ERROR, " -------------------------------------------------------\n"); freeBsaAcsMem(); - val_print(ACS_PRINT_ERR, "\n *** SBSA tests complete. Reset the system. ***\n\n", 0); + val_print(ERROR, "\n *** SBSA tests complete. Reset the system. ***\n\n"); if (g_acs_log_file_handle) { ShellCloseFile(&g_acs_log_file_handle); diff --git a/apps/uefi/vbsa_main.c b/apps/uefi/vbsa_main.c index 9aea20c3..d676730b 100644 --- a/apps/uefi/vbsa_main.c +++ b/apps/uefi/vbsa_main.c @@ -124,8 +124,8 @@ apply_cli_defaults(VOID) /* Check sanity of value of level */ if (g_level_value >= VBSA_LEVEL_SENTINEL) { - val_print(ACS_PRINT_ERR, "\nInvalid level value passed (%d), ", g_level_value); - val_print(ACS_PRINT_ERR, "value should be less than %d.", VBSA_LEVEL_SENTINEL); + val_print(ERROR, "\nInvalid level value passed (%d), ", g_level_value); + val_print(ERROR, "value should be less than %d.", VBSA_LEVEL_SENTINEL); return ACS_STATUS_FAIL; } @@ -143,17 +143,17 @@ execute_tests() goto exit_acs; } - val_print(ACS_PRINT_TEST, "\n\n VBSA Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", VBSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", VBSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", VBSA_ACS_SUBMINOR_VER); + val_print(INFO, "\n\n VBSA Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", VBSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", VBSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", VBSA_ACS_SUBMINOR_VER); /* "Starting tests for level" banner */ - val_print(ACS_PRINT_TEST, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, + val_print(INFO, LEVEL_PRINT_FORMAT(g_level_value, g_level_filter_mode, VBSA_LEVEL_FR), g_level_value); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); Status = createPeInfoTable(); if (Status) { @@ -195,7 +195,7 @@ execute_tests() print_test_status: val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** VBSA tests complete. Reset the system. ***\n\n", 0); + val_print(ERROR, "\n *** VBSA tests complete. Reset the system. ***\n\n"); freeAcsMem(); diff --git a/apps/uefi/xbsa_main.c b/apps/uefi/xbsa_main.c index 62c71745..c580e146 100644 --- a/apps/uefi/xbsa_main.c +++ b/apps/uefi/xbsa_main.c @@ -193,12 +193,12 @@ execute_tests() } /* Print ACS header */ - val_print(ACS_PRINT_TEST, "\n\nxBSA Architecture Compliance Suite", 0); - val_print(ACS_PRINT_TEST, "\n Version %d.", XBSA_ACS_MAJOR_VER); - val_print(ACS_PRINT_TEST, "%d.", XBSA_ACS_MINOR_VER); - val_print(ACS_PRINT_TEST, "%d\n", XBSA_ACS_SUBMINOR_VER); - val_print(ACS_PRINT_TEST, "(Print level is %2d)\n\n", g_print_level); - val_print(ACS_PRINT_TEST, "\n Creating Platform Information Tables\n", 0); + val_print(INFO, "\n\nxBSA Architecture Compliance Suite"); + val_print(INFO, "\n Version %d.", XBSA_ACS_MAJOR_VER); + val_print(INFO, "%d.", XBSA_ACS_MINOR_VER); + val_print(INFO, "%d\n", XBSA_ACS_SUBMINOR_VER); + val_print(INFO, "(Print level is %2d)\n\n", g_print_level); + val_print(INFO, "\n Creating Platform Information Tables\n"); /* Create info tables */ @@ -253,7 +253,7 @@ execute_tests() } val_print_acs_test_status_summary(); - val_print(ACS_PRINT_ERR, "\n *** ACS tests complete. Reset the system. ***\n\n", 0); + val_print(ERROR, "\n *** ACS tests complete. Reset the system. ***\n\n"); freeAcsMem(); diff --git a/pal/uefi_dt/src/pal_misc.c b/pal/uefi_dt/src/pal_misc.c index e9f20501..1bfeafed 100644 --- a/pal/uefi_dt/src/pal_misc.c +++ b/pal/uefi_dt/src/pal_misc.c @@ -688,3 +688,18 @@ pal_mem_free_pages( { gBS->FreePages((EFI_PHYSICAL_ADDRESS)(UINTN)PageBase, NumPages); } + +void pal_uart_putc(char c) +{ + CHAR8 ch = (CHAR8)c; + + AsciiPrint("%c", ch); + + if (g_acs_log_file_handle) { + UINTN n = 1; + EFI_STATUS Status = ShellWriteFile(g_acs_log_file_handle, &n, &ch); + if (EFI_ERROR(Status)) { + acs_print(ACS_PRINT_ERR, L" Error in writing to log file\n"); + } + } +} diff --git a/test_pool/cxl/cxl001.c b/test_pool/cxl/cxl001.c index c1d0ba71..05c29cb7 100644 --- a/test_pool/cxl/cxl001.c +++ b/test_pool/cxl/cxl001.c @@ -39,7 +39,7 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { - val_print(ACS_PRINT_DEBUG, "\n No CXL devices discovered", 0); + val_print(DEBUG, "\n No CXL devices discovered"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -55,14 +55,14 @@ payload(void) vh_capable = 0; bdf = val_cxl_get_component_info(CXL_COMPONENT_INFO_BDF_INDEX, index); if (val_cxl_find_capability(bdf, CXL_DVSEC_ID_PCIE_FLEXBUS_PORT, &pciecs_base)) { - val_print(ACS_PRINT_ERR, "\n CXL Flexbus port capability absent for bdf 0x%0x", bdf); + val_print(ERROR, "\n CXL Flexbus port capability absent for bdf 0x%0x", bdf); test_fails++; continue; } val_pcie_read_cfg(bdf, pciecs_base + CXL_DVSEC_HDR2_OFFSET, ®_value); if ((reg_value & CXL_DVSEC_HDR2_ID_MASK) != CXL_DVSEC_ID_PCIE_FLEXBUS_PORT) { - val_print(ACS_PRINT_ERR, "\n CXL Flexbus port ID mismatch for bdf 0x%0x", bdf); + val_print(ERROR, "\n CXL Flexbus port ID mismatch for bdf 0x%0x", bdf); test_fails++; continue; } diff --git a/test_pool/cxl/cxl002.c b/test_pool/cxl/cxl002.c index cf6d43f2..c0d7f607 100644 --- a/test_pool/cxl/cxl002.c +++ b/test_pool/cxl/cxl002.c @@ -48,7 +48,7 @@ payload(void) comp_count = val_cxl_get_component_info(CXL_COMPONENT_INFO_COUNT, 0); if (comp_count == 0) { - val_print(ACS_PRINT_INFO, "\n No CXL components discovered", 0); + val_print(TRACE, "\n No CXL components discovered"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -66,7 +66,7 @@ payload(void) smmu_idx = val_iovirt_get_rc_smmu_index(seg_num, rid); if (smmu_idx == ACS_INVALID_INDEX) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n CXL Type1/Type2 component not behind SMMU, BDF: 0x%x", bdf); test_fail++; @@ -75,7 +75,7 @@ payload(void) smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, smmu_idx); if (smmu_rev < 3u) { - val_print(ACS_PRINT_ERR, "\n CXL path SMMU is not SMMUv3, index: %u", smmu_idx); + val_print(ERROR, "\n CXL path SMMU is not SMMUv3, index: %u", smmu_idx); test_fail++; continue; } @@ -83,13 +83,13 @@ payload(void) idr0 = val_smmu_read_cfg(SMMUv3_IDR0, smmu_idx); ats_supported = VAL_EXTRACT_BITS(idr0, SMMUV3_ATS_BIT, SMMUV3_ATS_BIT); if (ats_supported == 0) { - val_print(ACS_PRINT_ERR, "\n SMMUv3 ATS unsupported, index: %u", smmu_idx); + val_print(ERROR, "\n SMMUv3 ATS unsupported, index: %u", smmu_idx); test_fail++; } } if (test_skip == 0) { - val_print(ACS_PRINT_INFO, "\n No CXL Type1/Type2 components discovered", 0); + val_print(TRACE, "\n No CXL Type1/Type2 components discovered"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); } else if (test_fail) { val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); diff --git a/test_pool/cxl/cxl003.c b/test_pool/cxl/cxl003.c index 458c9b7b..3682e95b 100644 --- a/test_pool/cxl/cxl003.c +++ b/test_pool/cxl/cxl003.c @@ -33,7 +33,7 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { - val_print(ACS_PRINT_DEBUG, "\n No CXL devices discovered", 0); + val_print(DEBUG, "\n No CXL devices discovered"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -42,7 +42,7 @@ payload(void) cxl_hb_base = val_cxl_get_info(CXL_INFO_COMPONENT_BASE, index); cxl_hb_len = val_cxl_get_info(CXL_INFO_COMPONENT_LENGTH, index); if ((cxl_hb_base == 0) || (cxl_hb_len == 0)) { - val_print(ACS_PRINT_ERR, "\n CHBCR address map failed for CXL HB %x", index); + val_print(ERROR, "\n CHBCR address map failed for CXL HB %x", index); test_fails++; } } diff --git a/test_pool/cxl/cxl004.c b/test_pool/cxl/cxl004.c index e0ed0052..e224faf6 100644 --- a/test_pool/cxl/cxl004.c +++ b/test_pool/cxl/cxl004.c @@ -55,12 +55,12 @@ log_capability_issue(uint32_t index, uint32_t cap_id, uint8_t requirement) return; if (requirement == CAP_REQ_MANDATORY) { - val_print(ACS_PRINT_ERR, "\n %a is not supported", (uint64_t)cap_name); + val_print(ERROR, "\n %a is not supported", (uint64_t)cap_name); } else if (requirement == CAP_REQ_NOT_PERMITTED) { - val_print(ACS_PRINT_ERR, "\n %a is supported", (uint64_t)cap_name); + val_print(ERROR, "\n %a is supported", (uint64_t)cap_name); } - val_print(ACS_PRINT_ERR, " for host index 0x%x", index); + val_print(ERROR, " for host index 0x%x", index); } static void @@ -80,7 +80,7 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { - val_print(ACS_PRINT_INFO, "\n No CXL Host Bridges discovered via CEDT", 0); + val_print(TRACE, "\n No CXL Host Bridges discovered via CEDT"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -89,9 +89,9 @@ payload(void) cxl_hb_base = val_cxl_get_info(CXL_INFO_COMPONENT_BASE, index); cxl_hb_len = val_cxl_get_info(CXL_INFO_COMPONENT_LENGTH, index); - val_print(ACS_PRINT_INFO, "\n HB[%x] CHBCR cxl_hb_base", index); - val_print(ACS_PRINT_INFO, " = 0x%llx", cxl_hb_base); - val_print(ACS_PRINT_INFO, " cxl_hb_len = 0x%llx", cxl_hb_len); + val_print(TRACE, "\n HB[%x] CHBCR cxl_hb_base", index); + val_print(TRACE, " = 0x%llx", cxl_hb_base); + val_print(TRACE, " cxl_hb_len = 0x%llx", cxl_hb_len); cap_id_size = (uint32_t)(sizeof(g_capability_checks) / sizeof(g_capability_checks[0])); for (cap_check = 0; cap_check < cap_id_size; cap_check++) { diff --git a/test_pool/cxl/cxl010.c b/test_pool/cxl/cxl010.c index 87f9976c..126db377 100644 --- a/test_pool/cxl/cxl010.c +++ b/test_pool/cxl/cxl010.c @@ -38,14 +38,14 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { - val_print(ACS_PRINT_DEBUG, "\n No CXL devices discovered", 0); + val_print(DEBUG, "\n No CXL devices discovered"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } for (index = 0; index < num_cxl_hb; index++) { if (val_cxl_check_persistent_memory(index)) { - val_print(ACS_PRINT_DEBUG, "\n No Persistent memory supported", 0); + val_print(DEBUG, "\n No Persistent memory supported"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -56,7 +56,7 @@ payload(void) if ((dpb_field == 0x1) || (dpb_field == 0x2)) { val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); } else { - val_print(ACS_PRINT_ERR, "\n ID_AA64ISAR1_EL1.DPB does not indicate PCMO support", 0); + val_print(ERROR, "\n ID_AA64ISAR1_EL1.DPB does not indicate PCMO support"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); } } diff --git a/test_pool/cxl/cxl011.c b/test_pool/cxl/cxl011.c index 43f8d85a..67416dc6 100644 --- a/test_pool/cxl/cxl011.c +++ b/test_pool/cxl/cxl011.c @@ -53,7 +53,7 @@ esr(uint64_t interrupt_type, void *context) uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception type: %d", interrupt_type); + val_print(ERROR, "\n Received exception type: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); } @@ -171,7 +171,7 @@ payload(void) status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to install exception handler", 0); + val_print(ERROR, "\n Failed to install exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -179,15 +179,15 @@ payload(void) branch_to_test = &&exception_return; dpb_field = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 0, 3); - val_print(ACS_PRINT_INFO, "\n DPB %x", dpb_field); + val_print(TRACE, "\n DPB %x", dpb_field); if ((dpb_field != 0x1) && (dpb_field != 0x2)) { - val_print(ACS_PRINT_INFO, "\n DC CVAP/CVADP not supported by this PE", 0); + val_print(TRACE, "\n DC CVAP/CVADP not supported by this PE"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } if (find_cxl_mem_target(&target)) { - val_print(ACS_PRINT_INFO, "\n No CXL Type 3 mem-capable target found", 0); + val_print(TRACE, "\n No CXL Type 3 mem-capable target found"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -209,7 +209,7 @@ payload(void) val_pcie_enable_msa(target.rp_bdf); if (get_aer_status(target.rp_bdf, &aer_ori)) { - val_print(ACS_PRINT_ERR, "\n AER capability not found on root port 0x%x", target.rp_bdf); + val_print(ERROR, "\n AER capability not found on root port 0x%x", target.rp_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -226,13 +226,13 @@ payload(void) val_data_cache_ops_by_va((addr_t)test_addr, CLEAN_POC); if (get_aer_status(target.rp_bdf, &aer_updated)) { - val_print(ACS_PRINT_ERR, "\n Failed to read AER status after PCMO sequence", 0); + val_print(ERROR, "\n Failed to read AER status after PCMO sequence"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); return; } if (compare_aer_status(&aer_ori, &aer_updated)) { - val_print(ACS_PRINT_ERR, "\n AER errors detected after PCMO sequence", 0); + val_print(ERROR, "\n AER errors detected after PCMO sequence"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); return; } @@ -244,8 +244,8 @@ payload(void) } if (read_back != CXL_TEST_PATTERN) { - val_print(ACS_PRINT_ERR, "\n Readback mismatch: expected 0x%llx", CXL_TEST_PATTERN); - val_print(ACS_PRINT_ERR, " observed 0x%llx", read_back); + val_print(ERROR, "\n Readback mismatch: expected 0x%llx", CXL_TEST_PATTERN); + val_print(ERROR, " observed 0x%llx", read_back); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 6)); return; } diff --git a/test_pool/cxl/cxl013.c b/test_pool/cxl/cxl013.c index 54b47dde..6117ab94 100644 --- a/test_pool/cxl/cxl013.c +++ b/test_pool/cxl/cxl013.c @@ -44,7 +44,7 @@ esr(uint64_t interrupt_type, void *context) uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception type: %d", interrupt_type); + val_print(ERROR, "\n Received exception type: %d", interrupt_type); exception = 1; val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); } @@ -206,7 +206,7 @@ payload(void) atomic_feat = VAL_EXTRACT_BITS(data, 20, 23); if (atomic_feat < 0x2) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n FEAT_LSE not supported (ID_AA64ISAR0_EL1.Atomic = 0x%x)", atomic_feat); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -215,7 +215,7 @@ payload(void) data = val_pe_reg_read(ID_AA64MMFR2_EL1); lse2_feat = VAL_EXTRACT_BITS(data, 32, 35); if (lse2_feat == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n FEAT_LSE2 not supported (ID_AA64MMFR2_EL1.AT = 0x%x)", lse2_feat); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -224,7 +224,7 @@ payload(void) status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to install exception handler", 0); + val_print(ERROR, "\n Failed to install exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -232,21 +232,21 @@ payload(void) exception = 0; if (find_cxl_type3_target(&target) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_INFO, "\n No CXL Type-3 memory target found", 0); + val_print(TRACE, "\n No CXL Type-3 memory target found"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } status = val_cxl_get_cfmws_window(target.host_index, &cfmws_base, &cfmws_size); if ((status != ACS_STATUS_PASS) || (cfmws_base == 0) || (cfmws_size < SIZE_4KB)) { - val_print(ACS_PRINT_ERR, "\n Failed to locate usable CFMWS window", 0); + val_print(ERROR, "\n Failed to locate usable CFMWS window"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); return; } status = val_cxl_map_hdm_address(cfmws_base, SIZE_4KB, &mapped); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed to map CXL Type-3 memory region", 0); + val_print(ERROR, "\n Failed to map CXL Type-3 memory region"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); return; } @@ -258,7 +258,7 @@ payload(void) return; if ((status != ACS_STATUS_PASS) || exception) { - val_print(ACS_PRINT_ERR, "\n Atomic sequence failed on CXL memory", 0); + val_print(ERROR, "\n Atomic sequence failed on CXL memory"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); return; } @@ -267,32 +267,32 @@ payload(void) data = val_pe_reg_read(ID_AA64ISAR1_EL1); ls64_feat = VAL_EXTRACT_BITS(data, 60, 63); if (ls64_feat == 0) - val_print(ACS_PRINT_WARN, "\n FEAT_LS64/LS4_V/LS64_ACCDATA is not supported", 0); + val_print(WARN, "\n FEAT_LS64/LS4_V/LS64_ACCDATA is not supported"); data = val_pe_reg_read(ID_AA64PFR0_EL1); ras_feat = VAL_EXTRACT_BITS(data, 28, 31); if (ras_feat == 0) - val_print(ACS_PRINT_WARN, "\n FEAT_RAS is not supported", 0); + val_print(WARN, "\n FEAT_RAS is not supported"); rme_feat = VAL_EXTRACT_BITS(data, 52, 55); if (rme_feat == 0) - val_print(ACS_PRINT_WARN, "\n FEAT_RME is not supported", 0); + val_print(WARN, "\n FEAT_RME is not supported"); data = val_pe_reg_read(ID_AA64PFR1_EL1); mte_feat = VAL_EXTRACT_BITS(data, 8, 11); if (mte_feat == 0) - val_print(ACS_PRINT_WARN, "\n FEAT_MTE/MTE2 is not supported", 0); + val_print(WARN, "\n FEAT_MTE/MTE2 is not supported"); mte_frac_feat = VAL_EXTRACT_BITS(data, 40, 43); if (!((mte_feat >= 3) || ((mte_feat == 2) && (mte_frac_feat == 0)))) - val_print(ACS_PRINT_WARN, "\n FEAT_MTE_ASYNC is not supported", 0); + val_print(WARN, "\n FEAT_MTE_ASYNC is not supported"); data = val_pe_reg_read(ID_AA64MMFR3_EL1); mec_feat = VAL_EXTRACT_BITS(data, 28, 31); if (mec_feat == 0) - val_print(ACS_PRINT_WARN, "\n Optional feature FEAT_MEC is not supported", 0); + val_print(WARN, "\n Optional feature FEAT_MEC is not supported"); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); } diff --git a/test_pool/drtm/dl001.c b/test_pool/drtm/dl001.c index 62f8fb13..4a1d5b23 100644 --- a/test_pool/drtm/dl001.c +++ b/test_pool/drtm/dl001.c @@ -41,14 +41,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -59,12 +59,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params + 4); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } } @@ -76,13 +76,13 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); drtm_params->dlme_region_address = drtm_params->dlme_region_address - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); } } @@ -95,13 +95,13 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); drtm_params->dlme_image_start = drtm_params->dlme_image_start - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); } } @@ -114,13 +114,13 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); drtm_params->dlme_data_offset = drtm_params->dlme_data_offset - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); } } @@ -137,7 +137,7 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); temp = drtm_params->dlme_image_start; drtm_params->dlme_image_start = drtm_params->dlme_data_offset; @@ -145,7 +145,7 @@ payload(uint32_t num_pe) if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 12)); } } diff --git a/test_pool/drtm/dl002.c b/test_pool/drtm/dl002.c index 555f03ca..6367e310 100644 --- a/test_pool/drtm/dl002.c +++ b/test_pool/drtm/dl002.c @@ -41,14 +41,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -57,14 +57,14 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed", 0); + val_print(ERROR, "\n DRTM Dynamic Launch failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -73,7 +73,7 @@ payload(uint32_t num_pe) status = val_drtm_check_dl_result(drtm_params->dlme_region_address, drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM check DL result failed", 0); + val_print(ERROR, "\n DRTM check DL result failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_dlme_region; } @@ -81,17 +81,17 @@ payload(uint32_t num_pe) /* Part 2 : DRTM_GET_ERROR Success Case in case of no errors in previous Dynamic Launch */ status = val_drtm_get_error(&feat1); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Get Error failed err=%d", status); + val_print(ERROR, "\n DRTM Get Error failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); goto free_dlme_region; } - val_print(ACS_PRINT_INFO, "\n Get Error code 0x%x\n", feat1); + val_print(TRACE, "\n Get Error code 0x%x\n", feat1); /* Part 3 : Call unprotect memory again, it should return DENIED as no memory protected */ status = val_drtm_unprotect_memory(); if (status != DRTM_ACS_DENIED) { - val_print(ACS_PRINT_ERR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); - val_print(ACS_PRINT_ERR, ", Found = %d", status); + val_print(ERROR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); + val_print(ERROR, ", Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); goto free_dlme_region; } diff --git a/test_pool/drtm/dl003.c b/test_pool/drtm/dl003.c index 3c5830d2..0be36922 100644 --- a/test_pool/drtm/dl003.c +++ b/test_pool/drtm/dl003.c @@ -41,14 +41,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -58,7 +58,7 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Dynamic Launch failed err=%d", status); + val_print(ERROR, "\n Dynamic Launch failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } @@ -67,7 +67,7 @@ payload(uint32_t num_pe) status = val_drtm_check_dl_result(drtm_params->dlme_region_address, drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM check DL result failed", 0); + val_print(ERROR, "\n DRTM check DL result failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -75,7 +75,7 @@ payload(uint32_t num_pe) /* Call DRTM Error, it should return 0 as DL did not enter remediation */ status = val_drtm_get_error(&feat1); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Get Error failed err=%d", status); + val_print(ERROR, "\n Get Error failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_dlme_region; } @@ -84,13 +84,13 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This Should Return Fail*/ if (status != DRTM_ACS_DENIED) { - val_print(ACS_PRINT_ERR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); - val_print(ACS_PRINT_ERR, ", Found = %d", status); + val_print(ERROR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); + val_print(ERROR, ", Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); } } @@ -100,7 +100,7 @@ payload(uint32_t num_pe) /* Call DRTM Unprotect Memory */ status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); goto free_dlme_region; } @@ -109,7 +109,7 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Dynamic Launch failed err=%d", status); + val_print(ERROR, "\n Dynamic Launch failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); goto free_dlme_region; } @@ -117,7 +117,7 @@ payload(uint32_t num_pe) /* Call DRTM Unprotect Memory */ status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); goto free_dlme_region; } @@ -126,7 +126,7 @@ payload(uint32_t num_pe) status = val_drtm_check_dl_result(drtm_params->dlme_region_address, drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM check DL result failed", 0); + val_print(ERROR, "\n DRTM check DL result failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); goto free_dlme_region; } diff --git a/test_pool/drtm/dl004.c b/test_pool/drtm/dl004.c index b6c9717b..b6b60820 100644 --- a/test_pool/drtm/dl004.c +++ b/test_pool/drtm/dl004.c @@ -38,14 +38,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -54,14 +54,14 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed err=%d", status); + val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -69,8 +69,8 @@ payload(uint32_t num_pe) /* Part 1 : Check Close Locality for Locality 1, Should Result INVALID Parameters */ status = val_drtm_close_locality(DRTM_LOC_1); if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Unexpected Status for close locality %d", status); - val_print(ACS_PRINT_ERR, " Expected %d,", DRTM_ACS_INVALID_PARAMETERS); + val_print(ERROR, "\n Unexpected Status for close locality %d", status); + val_print(ERROR, " Expected %d,", DRTM_ACS_INVALID_PARAMETERS); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_dlme_region; } @@ -80,8 +80,8 @@ payload(uint32_t num_pe) * After the DLME has completed its measurements. */ status = val_drtm_close_locality(DRTM_LOC_2); if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Close Locality 2 failed err=%d", status); - val_print(ACS_PRINT_ERR, " Expected %d,", DRTM_ACS_SUCCESS); + val_print(ERROR, "\n DRTM Close Locality 2 failed err=%d", status); + val_print(ERROR, " Expected %d,", DRTM_ACS_SUCCESS); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); goto free_dlme_region; } @@ -90,8 +90,8 @@ payload(uint32_t num_pe) * Already closed, as it is already closed. */ status = val_drtm_close_locality(DRTM_LOC_2); if (status != DRTM_ACS_ALREADY_CLOSED) { - val_print(ACS_PRINT_ERR, "\n DRTM Close Locality 2 failed err=%d", status); - val_print(ACS_PRINT_ERR, " Expected %d,", DRTM_ACS_ALREADY_CLOSED); + val_print(ERROR, "\n DRTM Close Locality 2 failed err=%d", status); + val_print(ERROR, " Expected %d,", DRTM_ACS_ALREADY_CLOSED); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); goto free_dlme_region; } diff --git a/test_pool/drtm/dl005.c b/test_pool/drtm/dl005.c index 61f0fd51..1c86087d 100644 --- a/test_pool/drtm/dl005.c +++ b/test_pool/drtm/dl005.c @@ -31,55 +31,55 @@ static DRTM_DLME_DATA_HDR *dlme_data_header; static void print_dlme_data_header(DRTM_DLME_DATA_HDR *dlme_data_header) { - val_print(ACS_PRINT_DEBUG, "\n DLME Data Header", 0); - val_print(ACS_PRINT_DEBUG, "\n Revision = 0x%08lx", + val_print(DEBUG, "\n DLME Data Header"); + val_print(DEBUG, "\n Revision = 0x%08lx", dlme_data_header->revision); - val_print(ACS_PRINT_DEBUG, "\n Size = %d Bytes", + val_print(DEBUG, "\n Size = %d Bytes", dlme_data_header->size); - val_print(ACS_PRINT_DEBUG, "\n DLME_data_size = %d Bytes", + val_print(DEBUG, "\n DLME_data_size = %d Bytes", dlme_data_header->dlme_data_size); - val_print(ACS_PRINT_DEBUG, "\n Protected Regions Size = %d Bytes", + val_print(DEBUG, "\n Protected Regions Size = %d Bytes", dlme_data_header->protected_regions_size); - val_print(ACS_PRINT_DEBUG, "\n Address Map Size = %d Bytes", + val_print(DEBUG, "\n Address Map Size = %d Bytes", dlme_data_header->address_map_size); - val_print(ACS_PRINT_DEBUG, "\n DRTM Event Log Size = %d Bytes", + val_print(DEBUG, "\n DRTM Event Log Size = %d Bytes", dlme_data_header->drtm_event_log_size); - val_print(ACS_PRINT_DEBUG, "\n TCB Hash Table Size = %d Bytes", + val_print(DEBUG, "\n TCB Hash Table Size = %d Bytes", dlme_data_header->tcb_hash_table_size); - val_print(ACS_PRINT_DEBUG, "\n ACPI Table Region Size = %d Bytes", + val_print(DEBUG, "\n ACPI Table Region Size = %d Bytes", dlme_data_header->acpi_table_region_size); - val_print(ACS_PRINT_DEBUG, "\n Implementation Region Size= %d Bytes", + val_print(DEBUG, "\n Implementation Region Size= %d Bytes", dlme_data_header->implementation_region_size); } static void print_protected_region_info(void) { - val_print(ACS_PRINT_DEBUG, "\n\n Protected Region", 0); - val_print(ACS_PRINT_DEBUG, "\n Revision : 0x%08lx", + val_print(DEBUG, "\n\n Protected Region"); + val_print(DEBUG, "\n Revision : 0x%08lx", prot_region->header.revision); - val_print(ACS_PRINT_DEBUG, "\n Number of Regions : 0x%08lx", + val_print(DEBUG, "\n Number of Regions : 0x%08lx", prot_region->header.num_regions); for (uint32_t i = 0; i < prot_region->header.num_regions; i++) { - val_print(ACS_PRINT_DEBUG, "\n Region : 0x%lx", i); - val_print(ACS_PRINT_DEBUG, "\n Start Address : 0x%08lx", + val_print(DEBUG, "\n Region : 0x%lx", i); + val_print(DEBUG, "\n Start Address : 0x%08lx", prot_region->regions[i].start_addr); - val_print(ACS_PRINT_DEBUG, "\n Region Size/Type : 0x%08lx", + val_print(DEBUG, "\n Region Size/Type : 0x%08lx", prot_region->regions[i].size_type); } } static void print_address_map_info(void) { - val_print(ACS_PRINT_DEBUG, "\n\n Address Map", 0); - val_print(ACS_PRINT_DEBUG, "\n Revision : 0x%08lx", + val_print(DEBUG, "\n\n Address Map"); + val_print(DEBUG, "\n Revision : 0x%08lx", addr_map->header.revision); - val_print(ACS_PRINT_DEBUG, "\n Number of Regions : 0x%08lx", + val_print(DEBUG, "\n Number of Regions : 0x%08lx", addr_map->header.num_regions); for (uint32_t i = 0; i < addr_map->header.num_regions; i++) { - val_print(ACS_PRINT_DEBUG, "\n Region : 0x%lx", i); - val_print(ACS_PRINT_DEBUG, "\n Start Address : 0x%08lx", + val_print(DEBUG, "\n Region : 0x%lx", i); + val_print(DEBUG, "\n Start Address : 0x%08lx", addr_map->regions[i].start_addr); - val_print(ACS_PRINT_DEBUG, "\n Region Size/Type : 0x%08lx", + val_print(DEBUG, "\n Region Size/Type : 0x%08lx", addr_map->regions[i].size_type); } } @@ -111,32 +111,32 @@ static void print_dlme_data_info(uint64_t dlme_data_address) print_address_map_info(); if (dlme_data_header->tcb_hash_table_size != 0) { - val_print(ACS_PRINT_DEBUG, "\n\n TCB Hash Table", 0); + val_print(DEBUG, "\n\n TCB Hash Table"); tcb_hash_table = (DRTM_TCB_HASH_TABLE *)(tcb_hash_address); - val_print(ACS_PRINT_DEBUG, "\n Revision : 0x%08lx", + val_print(DEBUG, "\n Revision : 0x%08lx", tcb_hash_table->header.revision); - val_print(ACS_PRINT_DEBUG, "\n Number of Hashes : 0x%08lx", + val_print(DEBUG, "\n Number of Hashes : 0x%08lx", tcb_hash_table->header.num_hashes); - val_print(ACS_PRINT_DEBUG, "\n Hash Algorithm : 0x%08lx", + val_print(DEBUG, "\n Hash Algorithm : 0x%08lx", tcb_hash_table->header.hash_algo); for (uint32_t i = 0; i < tcb_hash_table->header.num_hashes; i++) { - val_print(ACS_PRINT_DEBUG, "\n HASH Index : 0x%lx", i); - val_print(ACS_PRINT_DEBUG, "\n HASH ID : 0x%08lx", + val_print(DEBUG, "\n HASH Index : 0x%lx", i); + val_print(DEBUG, "\n HASH ID : 0x%08lx", tcb_hash_table->hashes[i].hash_id); for (uint32_t j = 0; j < 32; j = j+4) { - val_print(ACS_PRINT_DEBUG, "\n HASH Val : ", 0); - val_print(ACS_PRINT_DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j]); - val_print(ACS_PRINT_DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+1]); - val_print(ACS_PRINT_DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+2]); - val_print(ACS_PRINT_DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+3]); + val_print(DEBUG, "\n HASH Val : "); + val_print(DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j]); + val_print(DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+1]); + val_print(DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+2]); + val_print(DEBUG, "%02x ", (tcb_hash_table->hashes[i]).hash_val[j+3]); } } } if (dlme_data_header->acpi_table_region_size != 0) { /* Print the XSDT Address and Present Tables */ - val_print(ACS_PRINT_DEBUG, "\n\n ACPI Tables", 0); - val_print(ACS_PRINT_DEBUG, "\n Signature : %llx", + val_print(DEBUG, "\n\n ACPI Tables"); + val_print(DEBUG, "\n Signature : %llx", (uint32_t)(*((uint64_t *)acpi_region_address))); if ((uint32_t)(*((uint64_t *)acpi_region_address)) == ACS_ACPI_SIGNATURE('X', 'S', 'D', 'T')) { /* Print all Present ACPI Tables */ @@ -149,7 +149,7 @@ static void print_dlme_data_info(uint64_t dlme_data_address) } } } - val_print(ACS_PRINT_DEBUG, "\n\n", 0); + val_print(DEBUG, "\n\n"); } @@ -172,14 +172,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -188,14 +188,14 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed", 0); + val_print(ERROR, "\n DRTM Dynamic Launch failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -204,7 +204,7 @@ payload(uint32_t num_pe) status = val_drtm_check_dl_result(drtm_params->dlme_region_address, drtm_params->dlme_data_offset); if (status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_ERR, "\n DRTM check DL result failed", 0); + val_print(ERROR, "\n DRTM check DL result failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_dlme_region; } @@ -217,26 +217,26 @@ payload(uint32_t num_pe) /* R314050 : All the sub-regions referenced by DLME_DATA_HEADER must be within DLME region.*/ if ((dlme_data_address + dlme_data_header->dlme_data_size) > (drtm_params->dlme_region_address + drtm_params->dlme_region_size)) { - val_print(ACS_PRINT_ERR, "\n DLME Data Header outside DLME Region", 0); + val_print(ERROR, "\n DLME Data Header outside DLME Region"); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); goto free_dlme_region; } /* R314060 : Check if Protected Region size is not zero */ if (dlme_data_header->protected_regions_size == 0) { - val_print(ACS_PRINT_ERR, "\n DLME Data Protected Region Size is 0", 0); + val_print(ERROR, "\n DLME Data Protected Region Size is 0"); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); goto free_dlme_region; } /* R314060 : Check if Address Map size is not zero */ if (dlme_data_header->address_map_size == 0) { - val_print(ACS_PRINT_ERR, "\n DLME Data Address Map Size is 0", 0); + val_print(ERROR, "\n DLME Data Address Map Size is 0"); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); goto free_dlme_region; } /* R314060 : Check if Event Log size is not zero */ if (dlme_data_header->drtm_event_log_size <= 0) { - val_print(ACS_PRINT_ERR, "\n DLME Data Event Log Size is incorrect", 0); + val_print(ERROR, "\n DLME Data Event Log Size is incorrect"); val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); goto free_dlme_region; } @@ -244,7 +244,7 @@ payload(uint32_t num_pe) /* R314090 : Size of fields in the DATA_HEADER must not extend beyond bounds of DLME data.*/ if ((dlme_data_header->dlme_data_size) > (drtm_params->dlme_region_address + drtm_params->dlme_region_size - dlme_data_address)) { - val_print(ACS_PRINT_ERR, "\n DLME Data Header exceeds DLME Data", 0); + val_print(ERROR, "\n DLME Data Header exceeds DLME Data"); val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); goto free_dlme_region; } @@ -252,7 +252,7 @@ payload(uint32_t num_pe) /* R314110 Part 2 : Check Protected Regions is populated */ /* Do revision check and num of regions check */ if ((prot_region->header.revision != 1) || (prot_region->header.num_regions == 0)) { - val_print(ACS_PRINT_ERR, "\n Protected region not populated", 0); + val_print(ERROR, "\n Protected region not populated"); val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); goto free_dlme_region; } @@ -261,7 +261,7 @@ payload(uint32_t num_pe) if (VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7) == 1) { if ((prot_region->header.num_regions != 1) || (prot_region->regions[0].start_addr != 0)) { - val_print(ACS_PRINT_ERR, "\n Protected region wrongly populated", 0); + val_print(ERROR, "\n Protected region wrongly populated"); val_set_status(index, RESULT_FAIL(TEST_NUM, 12)); goto free_dlme_region; } @@ -270,7 +270,7 @@ payload(uint32_t num_pe) /* R314100 Part 3 : Check Address Map is populated */ /* Do revision check and num of regions check */ if ((addr_map->header.revision != 1) || (addr_map->header.num_regions == 0)) { - val_print(ACS_PRINT_ERR, "\n Address Map not populated", 0); + val_print(ERROR, "\n Address Map not populated"); val_set_status(index, RESULT_FAIL(TEST_NUM, 13)); goto free_dlme_region; } @@ -280,7 +280,7 @@ payload(uint32_t num_pe) /* R313020 : All region addresses must not overlap */ for (uint32_t i = 0; i < prot_region->header.num_regions; i++) { if (!(DRTM_IS_4KB_ALIGNED(prot_region->regions[i].start_addr))) { - val_print(ACS_PRINT_ERR, "\n Protected Memory Regions Not 4KB Aligned", 0); + val_print(ERROR, "\n Protected Memory Regions Not 4KB Aligned"); val_set_status(index, RESULT_FAIL(TEST_NUM, 14)); test_fails++; } @@ -289,7 +289,7 @@ payload(uint32_t num_pe) continue; if (prot_region->regions[i].start_addr < prot_region->regions[i-1].start_addr) { - val_print(ACS_PRINT_ERR, "\n Protected Regions Memory Regions Not Sorted", 0); + val_print(ERROR, "\n Protected Regions Memory Regions Not Sorted"); val_set_status(index, RESULT_FAIL(TEST_NUM, 15)); test_fails++; } @@ -297,7 +297,7 @@ payload(uint32_t num_pe) for (uint32_t i = 0; i < addr_map->header.num_regions; i++) { if (!(DRTM_IS_4KB_ALIGNED(addr_map->regions[i].start_addr))) { - val_print(ACS_PRINT_ERR, "\n Address Map Memory Regions Not 4KB Aligned", 0); + val_print(ERROR, "\n Address Map Memory Regions Not 4KB Aligned"); val_set_status(index, RESULT_FAIL(TEST_NUM, 16)); test_fails++; } @@ -306,7 +306,7 @@ payload(uint32_t num_pe) continue; if (addr_map->regions[i].start_addr < addr_map->regions[i-1].start_addr) { - val_print(ACS_PRINT_ERR, "\n Address Map Memory Regions Not Sorted", 0); + val_print(ERROR, "\n Address Map Memory Regions Not Sorted"); val_set_status(index, RESULT_FAIL(TEST_NUM, 17)); test_fails++; } @@ -317,14 +317,14 @@ payload(uint32_t num_pe) /* Check num of hashes is not zero & revision = 1 */ if ((tcb_hash_table->header.revision != 1) || (tcb_hash_table->header.num_hashes == 0)) { /* Fail The test */ - val_print(ACS_PRINT_ERR, "\n TCB_HASH_TABLE Not Correctly Formatted", 0); + val_print(ERROR, "\n TCB_HASH_TABLE Not Correctly Formatted"); val_set_status(index, RESULT_FAIL(TEST_NUM, 18)); goto free_dlme_region; } /* R315040 In Success Case. Check if Maximum number of entries is greator than num_hashes */ if (tcb_hash_table->header.num_hashes > VAL_EXTRACT_BITS(g_drtm_features.tcb_hash_features.value, 0, 7)) { - val_print(ACS_PRINT_ERR, "\n Number of hashes exceeds maximum allowed value", 0); + val_print(ERROR, "\n Number of hashes exceeds maximum allowed value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 19)); test_fails++; } @@ -336,7 +336,7 @@ payload(uint32_t num_pe) if (dlme_data_header->acpi_table_region_size != 0) { if ((uint32_t)(*((uint64_t *)acpi_region_address)) != ACS_ACPI_SIGNATURE('X', 'S', 'D', 'T')) { - val_print(ACS_PRINT_ERR, "\n ACPI XSDT Table Check Failed", 0); + val_print(ERROR, "\n ACPI XSDT Table Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 20)); test_fails++; } @@ -345,7 +345,7 @@ payload(uint32_t num_pe) /* R314150 Part 7 : Check one of tcb_hash_table or acpi_table_region is present */ if ((dlme_data_header->tcb_hash_table_size != 0) && (dlme_data_header->acpi_table_region_size != 0)) { - val_print(ACS_PRINT_ERR, "\n TCB Hash Table & ACPI Table Region Check Failed", 0); + val_print(ERROR, "\n TCB Hash Table & ACPI Table Region Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 21)); test_fails++; } diff --git a/test_pool/drtm/dl006.c b/test_pool/drtm/dl006.c index 20b7104c..9cecc63a 100644 --- a/test_pool/drtm/dl006.c +++ b/test_pool/drtm/dl006.c @@ -27,16 +27,16 @@ static void print_dlme_region(DRTM_PARAMETERS *drtm_params) { - val_print(ACS_PRINT_DEBUG, "\n DLME Region : ", 0); - val_print(ACS_PRINT_DEBUG, "\n Alloc address : 0x%lx", + val_print(DEBUG, "\n DLME Region : "); + val_print(DEBUG, "\n Alloc address : 0x%lx", drtm_params->dlme_region_address); - val_print(ACS_PRINT_DEBUG, "\n Region size : 0x%lx", + val_print(DEBUG, "\n Region size : 0x%lx", drtm_params->dlme_region_size); - val_print(ACS_PRINT_DEBUG, "\n Free space 1 size : 0x%lx", + val_print(DEBUG, "\n Free space 1 size : 0x%lx", drtm_params->dlme_image_start); - val_print(ACS_PRINT_DEBUG, "\n Image size : 0x%lx", + val_print(DEBUG, "\n Image size : 0x%lx", drtm_params->dlme_image_size); - val_print(ACS_PRINT_DEBUG, "\n Data size : 0x%lx\n", + val_print(DEBUG, "\n Data size : 0x%lx\n", (drtm_params->dlme_region_size - drtm_params->dlme_data_offset)); } @@ -44,24 +44,24 @@ static void print_dlme_data_header(DRTM_DLME_DATA_HDR *dlme_data_header) { - val_print(ACS_PRINT_DEBUG, "\n DLME Data Header :", 0); - val_print(ACS_PRINT_DEBUG, "\n Revision : 0x%08lx", + val_print(DEBUG, "\n DLME Data Header :"); + val_print(DEBUG, "\n Revision : 0x%08lx", dlme_data_header->revision); - val_print(ACS_PRINT_DEBUG, "\n Size : %d Bytes", + val_print(DEBUG, "\n Size : %d Bytes", dlme_data_header->size); - val_print(ACS_PRINT_DEBUG, "\n DLME_data_size : %d Bytes", + val_print(DEBUG, "\n DLME_data_size : %d Bytes", dlme_data_header->dlme_data_size); - val_print(ACS_PRINT_DEBUG, "\n Protected Regions Size : %d Bytes", + val_print(DEBUG, "\n Protected Regions Size : %d Bytes", dlme_data_header->protected_regions_size); - val_print(ACS_PRINT_DEBUG, "\n Address Map Size : %d Bytes", + val_print(DEBUG, "\n Address Map Size : %d Bytes", dlme_data_header->address_map_size); - val_print(ACS_PRINT_DEBUG, "\n DRTM Event Log Size : %d Bytes", + val_print(DEBUG, "\n DRTM Event Log Size : %d Bytes", dlme_data_header->drtm_event_log_size); - val_print(ACS_PRINT_DEBUG, "\n TCB Hash Table Size : %d Bytes", + val_print(DEBUG, "\n TCB Hash Table Size : %d Bytes", dlme_data_header->tcb_hash_table_size); - val_print(ACS_PRINT_DEBUG, "\n ACPI Table Region Size : %d Bytes", + val_print(DEBUG, "\n ACPI Table Region Size : %d Bytes", dlme_data_header->acpi_table_region_size); - val_print(ACS_PRINT_DEBUG, "\n Implementation Region Size : %d Bytes\n", + val_print(DEBUG, "\n Implementation Region Size : %d Bytes\n", dlme_data_header->implementation_region_size); } @@ -74,45 +74,45 @@ print_event_spec(TCG_EFI_SPECID_EVENT *event_spec) VENDOR_INFO *vendor_info; uint8_t *vendor_data; - val_print(ACS_PRINT_DEBUG, "\n TCG Spec ID :", 0); - val_print(ACS_PRINT_DEBUG, "\n Signature : %a", + val_print(DEBUG, "\n TCG Spec ID :"); + val_print(DEBUG, "\n Signature : %a", (uint64_t)event_spec->signature); - val_print(ACS_PRINT_DEBUG, "\n Platform Class : 0x%x", event_spec->platform_class); - val_print(ACS_PRINT_DEBUG, "\n Spec Version Minor : %d", + val_print(DEBUG, "\n Platform Class : 0x%x", event_spec->platform_class); + val_print(DEBUG, "\n Spec Version Minor : %d", event_spec->spec_version_minor); - val_print(ACS_PRINT_DEBUG, "\n Spec Version Major : %d", + val_print(DEBUG, "\n Spec Version Major : %d", event_spec->spec_version_major); - val_print(ACS_PRINT_DEBUG, "\n Spec Errata : %d", event_spec->spec_errata); - val_print(ACS_PRINT_DEBUG, "\n Uintn Size : %d", event_spec->uintn_size); - val_print(ACS_PRINT_DEBUG, "\n Number Of Algorithms : %d\n", + val_print(DEBUG, "\n Spec Errata : %d", event_spec->spec_errata); + val_print(DEBUG, "\n Uintn Size : %d", event_spec->uintn_size); + val_print(DEBUG, "\n Number Of Algorithms : %d\n", event_spec->number_of_algorithms); /* Check Event Signature */ if (val_strncmp((char8_t *)event_spec->signature, "Spec ID Event03", EVENT_SPEC_ID_STR_LEN)) { - val_print(ACS_PRINT_ERR, " Event Specification mismatch", 0); + val_print(ERROR, " Event Specification mismatch"); return ACS_STATUS_FAIL; } digest_algo = (TCG_EFI_SPECID_EVENT_ALGO_SIZE *)event_spec->digest_sizes; for (index = 0; index < event_spec->number_of_algorithms; index++) { - val_print(ACS_PRINT_DEBUG, "\n Digest(%d)", index); - val_print(ACS_PRINT_DEBUG, "\n Algorithm Id : %d", + val_print(DEBUG, "\n Digest(%d)", index); + val_print(DEBUG, "\n Algorithm Id : %d", digest_algo[index].algorithm_id); - val_print(ACS_PRINT_DEBUG, "\n Digest Size : %d\n", + val_print(DEBUG, "\n Digest Size : %d\n", digest_algo[index].digest_size); } vendor_info = (VENDOR_INFO *)(&digest_algo[event_spec->number_of_algorithms]); - val_print(ACS_PRINT_DEBUG, "\n Vendor Info Size : %d", + val_print(DEBUG, "\n Vendor Info Size : %d", vendor_info->vendor_info_size); vendor_data = (uint8_t *)&vendor_info->vendor_info[0]; - val_print(ACS_PRINT_DEBUG, "\n Vendor Info : ", 0); + val_print(DEBUG, "\n Vendor Info : "); for (index = 0; index < vendor_info->vendor_info_size; index++) { - val_print(ACS_PRINT_DEBUG, "%c", vendor_data[index]); + val_print(DEBUG, "%c", vendor_data[index]); } - val_print(ACS_PRINT_DEBUG, "\n", 0); + val_print(DEBUG, "\n"); return ACS_STATUS_PASS; } @@ -123,26 +123,26 @@ print_tcg_event_header(TCG_PCR_EVENT *event_head) { uint32_t index; - val_print(ACS_PRINT_DEBUG, "\n EVENT LOG HEADER:", 0); - val_print(ACS_PRINT_DEBUG, "\n PCR Index : %d", event_head->pcr_index); + val_print(DEBUG, "\n EVENT LOG HEADER:"); + val_print(DEBUG, "\n PCR Index : %d", event_head->pcr_index); /* Check Event Log Header PCRIndex should be zero */ if (event_head->pcr_index != 0) { - val_print(ACS_PRINT_ERR, "\n Event Log Header should have PCRIndex as zero", 0); + val_print(ERROR, "\n Event Log Header should have PCRIndex as zero"); return ACS_STATUS_FAIL; } - val_print(ACS_PRINT_DEBUG, "\n Event Type : 0x%x", event_head->event_type); + val_print(DEBUG, "\n Event Type : 0x%x", event_head->event_type); /* Check Event Log Header EventType should be EV_NO_ACTION */ if (event_head->event_type != EV_NO_ACTION) { - val_print(ACS_PRINT_ERR, "\n Event Log Header should have EventType as EV_NO_ACTION", 0); + val_print(ERROR, "\n Event Log Header should have EventType as EV_NO_ACTION"); return ACS_STATUS_FAIL; } - val_print(ACS_PRINT_DEBUG, "\n Digest - ", 0); + val_print(DEBUG, "\n Digest - "); for (index = 0; index < sizeof(TCG_DIGEST); index++) { - val_print(ACS_PRINT_DEBUG, "%02x ", event_head->digest.digest[index]); + val_print(DEBUG, "%02x ", event_head->digest.digest[index]); } - val_print(ACS_PRINT_DEBUG, "\n Event Size : 0x%x\n", event_head->event_size); + val_print(DEBUG, "\n Event Size : 0x%x\n", event_head->event_size); return ACS_STATUS_PASS; } @@ -175,14 +175,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -191,7 +191,7 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed err=%d", status); + val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } @@ -199,7 +199,7 @@ payload(uint32_t num_pe) /* Call DRTM Unprotect Memory */ status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -218,7 +218,7 @@ payload(uint32_t num_pe) status = print_tcg_event_header(event_log_head); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Event Log Header Checks failed", 0); + val_print(ERROR, "\n Event Log Header Checks failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_dlme_region; } @@ -227,7 +227,7 @@ payload(uint32_t num_pe) status = print_event_spec(event_spec); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Event Log signature check failed", 0); + val_print(ERROR, "\n Event Log signature check failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); goto free_dlme_region; } @@ -246,22 +246,22 @@ payload(uint32_t num_pe) if ((event->pcr_index == 0) && (event->event_type == 0) && (event->digests.count == 0)) { break; } - val_print(ACS_PRINT_DEBUG, "\n EVENT2 : ", 0); - val_print(ACS_PRINT_DEBUG, "\n PCR Index : %d", event->pcr_index); - val_print(ACS_PRINT_DEBUG, "\n Event Type : 0x%x", event->event_type); - val_print(ACS_PRINT_DEBUG, "\n Digest Count : 0x%x", event->digests.count); + val_print(DEBUG, "\n EVENT2 : "); + val_print(DEBUG, "\n PCR Index : %d", event->pcr_index); + val_print(DEBUG, "\n Event Type : 0x%x", event->event_type); + val_print(DEBUG, "\n Digest Count : 0x%x", event->digests.count); /* Print Digest values for all hash algorithms */ digest = (TPMT_HA *)&event->digests.digests[0]; for (digest_index = 0; digest_index < event->digests.count; digest_index++) { - val_print(ACS_PRINT_DEBUG, "\n Hash Alg : 0x%x", + val_print(DEBUG, "\n Hash Alg : 0x%x", digest[digest_index].hashalg); - val_print(ACS_PRINT_DEBUG, "\n Digest(%02d) :", digest_index); + val_print(DEBUG, "\n Digest(%02d) :", digest_index); digest_buffer = (uint8_t *)(digest[digest_index].digest); for (i = 0; i < SHA256_DIGEST_SIZE; i++) { if ((!(i % 8)) && (i != 0)) - val_print(ACS_PRINT_DEBUG, "\n ", 0); - val_print(ACS_PRINT_DEBUG, " %02x", digest_buffer[i]); + val_print(DEBUG, "\n "); + val_print(DEBUG, " %02x", digest_buffer[i]); } } @@ -271,13 +271,13 @@ payload(uint32_t num_pe) } event_data = (EVENT_DATA *)((uint8_t *)&digest[--digest_index].digest[SHA256_DIGEST_SIZE]); - val_print(ACS_PRINT_DEBUG, "\n Event Size : 0x%x", event_data->event_size); - val_print(ACS_PRINT_DEBUG, "\n Event Data : ", 0); + val_print(DEBUG, "\n Event Size : 0x%x", event_data->event_size); + val_print(DEBUG, "\n Event Data : "); data = (uint8_t *)((uint8_t *)event_data + sizeof(uint32_t)); for (i = 0; i < event_data->event_size; i++) { - val_print(ACS_PRINT_DEBUG, " %x", data[i]); + val_print(DEBUG, " %x", data[i]); } - val_print(ACS_PRINT_DEBUG, "\n", 0); + val_print(DEBUG, "\n"); /* Gent next event address and continue the loop */ event2 = (TCG_PCR_EVENT2 *)((uint8_t *)event_data + sizeof(event_data->event_size) + diff --git a/test_pool/drtm/dl007.c b/test_pool/drtm/dl007.c index af280757..16548b05 100644 --- a/test_pool/drtm/dl007.c +++ b/test_pool/drtm/dl007.c @@ -54,7 +54,7 @@ payload(uint32_t num_pe) num_of_pe = val_pe_get_num(); if (num_of_pe < 2) { /* Skip the test as there is no secondary PE */ - val_print(ACS_PRINT_ERR, "\n No secondary PE Present. Skipping", 0); + val_print(ERROR, "\n No secondary PE Present. Skipping"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -70,14 +70,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -91,14 +91,14 @@ payload(uint32_t num_pe) dl_done = 1; /* This should return Fail as secondary pe is on */ if (status != DRTM_ACS_SECONDARY_PE_NOT_OFF) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed, Expected = %d", + val_print(ERROR, "\n DRTM Dynamic Launch failed, Expected = %d", DRTM_ACS_SECONDARY_PE_NOT_OFF); - val_print(ACS_PRINT_ERR, " Found = %d", status); + val_print(ERROR, " Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } } diff --git a/test_pool/drtm/dl008.c b/test_pool/drtm/dl008.c index 4d068f41..c784056c 100644 --- a/test_pool/drtm/dl008.c +++ b/test_pool/drtm/dl008.c @@ -42,14 +42,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -78,12 +78,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } } @@ -112,12 +112,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); } } @@ -137,12 +137,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); } } @@ -152,8 +152,8 @@ payload(uint32_t num_pe) /* Restore */ drtm_params->launch_features = original_launch_features; } else { - val_print(ACS_PRINT_DEBUG, - "\n DRTM implementation supports DLME Image Authentication, skip check", 0); + val_print(DEBUG, + "\n DRTM implementation supports DLME Image Authentication, skip check"); } /* Part 4: R44065 : DRTM_PARAMETER should not request features that are @@ -169,12 +169,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); } } @@ -183,8 +183,8 @@ payload(uint32_t num_pe) drtm_params->launch_features = 0; } else { - val_print(ACS_PRINT_DEBUG, - "\n DRTM implementation supports TPM based hashing, skip check", 0); + val_print(DEBUG, + "\n DRTM implementation supports TPM based hashing, skip check"); } val_set_status(index, RESULT_PASS(TEST_NUM, 1)); diff --git a/test_pool/drtm/dl009.c b/test_pool/drtm/dl009.c index 4692f687..800cde17 100644 --- a/test_pool/drtm/dl009.c +++ b/test_pool/drtm/dl009.c @@ -40,14 +40,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -63,12 +63,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -2 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } } diff --git a/test_pool/drtm/dl010.c b/test_pool/drtm/dl010.c index 21e69cf3..6f88f557 100644 --- a/test_pool/drtm/dl010.c +++ b/test_pool/drtm/dl010.c @@ -59,7 +59,7 @@ payload(uint32_t num_pe) num_of_pe = val_pe_get_num(); if (num_of_pe < 2) { /* Skip the test as there is no secondary PE */ - val_print(ACS_PRINT_ERR, "\n No secondary PE Present. Skipping", 0); + val_print(ERROR, "\n No secondary PE Present. Skipping"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -75,14 +75,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -99,22 +99,22 @@ payload(uint32_t num_pe) val_data_cache_ops_by_va((addr_t)&dl_status, CLEAN_AND_INVALIDATE); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", sec_pe_index); - val_print(ACS_PRINT_ERR, " Found = %d", dl_status); + val_print(ERROR, "\n **Timed out** for PE index = %d", sec_pe_index); + val_print(ERROR, " Found = %d", dl_status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } /* This will return invalid parameter */ if (dl_status != DRTM_ACS_DENIED) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed, Expected = %d", + val_print(ERROR, "\n DRTM Dynamic Launch failed, Expected = %d", DRTM_ACS_DENIED); - val_print(ACS_PRINT_ERR, " Found = %d", dl_status); + val_print(ERROR, " Found = %d", dl_status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); } } diff --git a/test_pool/drtm/dl011.c b/test_pool/drtm/dl011.c index d1eb497b..cd388947 100644 --- a/test_pool/drtm/dl011.c +++ b/test_pool/drtm/dl011.c @@ -48,7 +48,7 @@ payload(uint32_t num_pe) * regions not allowed through DRTM_PARAMETERS */ dma_protection_support = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7); if (dma_protection_support != DRTM_DMA_FEATURES_DMA_PROTECTION_REGION) { - val_print(ACS_PRINT_ERR, "\n Not valid for complete DMA protection. Skipping", 0); + val_print(ERROR, "\n Not valid for complete DMA protection. Skipping"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -57,7 +57,7 @@ payload(uint32_t num_pe) * are not allowed through DRTM_PARAMETERS */ max_mem_regions = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 8, 23); if (max_mem_regions == 0) { - val_print(ACS_PRINT_ERR, "\n No regions in DRTM_PARAMETERS allowed. Skipping", 0); + val_print(ERROR, "\n No regions in DRTM_PARAMETERS allowed. Skipping"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -65,14 +65,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -84,7 +84,7 @@ payload(uint32_t num_pe) mem_desc_table = (DRTM_MEMORY_REGION_DESCRIPTOR_TABLE *) ((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, mem_desc_table_size)); if (!mem_desc_table) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for Memory Descriptor Table", 0); + val_print(ERROR, "\n Failed to allocate memory for Memory Descriptor Table"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_drtm_params; } @@ -96,7 +96,7 @@ payload(uint32_t num_pe) region_address = (DRTM_MEMORY_REGION *) ((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, region_size)); if (!region_address) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for Memory Regions", 0); + val_print(ERROR, "\n Failed to allocate memory for Memory Regions"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_mem_desc_table; } @@ -118,12 +118,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_MEM_PROTECT_INVALID) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -6 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -6 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); } } @@ -134,7 +134,7 @@ payload(uint32_t num_pe) * overlap test is skipped */ max_mem_regions = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 8, 23); if (max_mem_regions > 1) { - val_print(ACS_PRINT_ERR, "\n Only one memory region is allowed. Skipping R313020", 0); + val_print(ERROR, "\n Only one memory region is allowed. Skipping R313020"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); goto free_memory_region; } @@ -159,12 +159,12 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return invalid parameter */ if (status != DRTM_ACS_MEM_PROTECT_INVALID) { - val_print(ACS_PRINT_ERR, "\n Incorrect Status. Expected = -6 Found = %d", status); + val_print(ERROR, "\n Incorrect Status. Expected = -6 Found = %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); } } diff --git a/test_pool/drtm/dl012.c b/test_pool/drtm/dl012.c index 00cdafa5..5f87cfe7 100644 --- a/test_pool/drtm/dl012.c +++ b/test_pool/drtm/dl012.c @@ -30,7 +30,7 @@ check_event_spec_signature(TCG_EFI_SPECID_EVENT *event_spec) /* Check Event Signature */ if (val_strncmp((char8_t *)event_spec->signature, "Spec ID Event03", EVENT_SPEC_ID_STR_LEN)) { - val_print(ACS_PRINT_ERR, " Event Specification mismatch", 0); + val_print(ERROR, " Event Specification mismatch"); return ACS_STATUS_FAIL; } @@ -64,8 +64,8 @@ payload(uint32_t num_pe) /* Verify if DLME img auth is supported. If not supported, the test is skipped */ drtm_feature = val_drtm_get_feature(DRTM_DRTM_FEATURES_DLME_IMG_AUTH); if (drtm_feature != DRTM_DLME_IMG_FEAT_DLME_IMG_AUTH_SUPP) { - val_print(ACS_PRINT_DEBUG, - "\n DRTM implementation does not support DLME Img Auth, skip check", 0); + val_print(DEBUG, + "\n DRTM implementation does not support DLME Img Auth, skip check"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -73,14 +73,14 @@ payload(uint32_t num_pe) /* Allocate Memory For DRTM Parameters 4KB Aligned */ drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DRTM Params", 0); + val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DRTM Init Params failed err=%d", status); + val_print(ERROR, "\n DRTM Init Params failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_drtm_params; } @@ -94,7 +94,7 @@ payload(uint32_t num_pe) status = val_drtm_dynamic_launch(drtm_params); /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Dynamic Launch failed err=%d", status); + val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_dlme_region; } @@ -102,7 +102,7 @@ payload(uint32_t num_pe) /* Call DRTM Unprotect Memory */ status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n Unprotect Memory failed err=%d", status); + val_print(ERROR, "\n Unprotect Memory failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_dlme_region; } @@ -120,7 +120,7 @@ payload(uint32_t num_pe) status = check_event_spec_signature(event_spec); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Event Log signature check failed", 0); + val_print(ERROR, "\n Event Log signature check failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); goto free_dlme_region; } @@ -139,10 +139,10 @@ payload(uint32_t num_pe) if ((event->pcr_index == 0) && (event->event_type == 0) && (event->digests.count == 0)) { break; } - val_print(ACS_PRINT_DEBUG, "\n EVENT2 : ", 0); - val_print(ACS_PRINT_DEBUG, "\n PCR Index : %d", event->pcr_index); - val_print(ACS_PRINT_DEBUG, "\n Event Type : 0x%x", event->event_type); - val_print(ACS_PRINT_DEBUG, "\n Digest Count : 0x%x", event->digests.count); + val_print(DEBUG, "\n EVENT2 : "); + val_print(DEBUG, "\n PCR Index : %d", event->pcr_index); + val_print(DEBUG, "\n Event Type : 0x%x", event->event_type); + val_print(DEBUG, "\n Digest Count : 0x%x", event->digests.count); if (event->event_type == DRTM_EVTYPE_ARM_DLME) { dlme_image_auth = ACS_STATUS_PASS; @@ -169,7 +169,7 @@ payload(uint32_t num_pe) } if (dlme_image_auth != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n DLME IMG AUTH not found in Event Log", 0); + val_print(ERROR, "\n DLME IMG AUTH not found in Event Log"); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); goto free_dlme_region; } diff --git a/test_pool/drtm/interface001.c b/test_pool/drtm/interface001.c index af10882e..89e38b83 100644 --- a/test_pool/drtm/interface001.c +++ b/test_pool/drtm/interface001.c @@ -31,21 +31,21 @@ payload(uint32_t num_pe) uint32_t status = g_drtm_features.version.status; if (status >> 31) { - val_print(ACS_PRINT_ERR, "\n DRTM get version failed err=%d", status); + val_print(ERROR, "\n DRTM get version failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } major = DRTM_VERSION_GET_MAJOR(g_drtm_features.version.value); if (major != 1) { - val_print(ACS_PRINT_ERR, "\n Major Version not as expected, Current version =%d", major); + val_print(INFO, "\n Major Version not as expected, Current version =%d", major); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } minor = DRTM_VERSION_GET_MINOR(g_drtm_features.version.value); if (minor != 1) { - val_print(ACS_PRINT_ERR, "\n Minor Version not as expected, Current version =%d", minor); + val_print(INFO, "\n Minor Version not as expected, Current version =%d", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/drtm/interface002.c b/test_pool/drtm/interface002.c index d73c2f3c..04bc80a6 100644 --- a/test_pool/drtm/interface002.c +++ b/test_pool/drtm/interface002.c @@ -34,7 +34,7 @@ static void payload(void) status = val_drtm_features(invalid_fid, &feat1, &feat2); if (status != DRTM_ACS_NOT_SUPPORTED) { - val_print(ACS_PRINT_ERR, "\n Invalid function ID test failed, status=%d", status); + val_print(ERROR, "\n Invalid function ID test failed, status=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -43,7 +43,7 @@ static void payload(void) invalid_fid = DRTM_1_0_DRTM_FEATURES_TPM | FEAT_ID_INVALID_RSVD; status = val_drtm_features(invalid_fid, &feat1, &feat2); if (status != DRTM_ACS_NOT_SUPPORTED) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n Feature ID Rsvd Bits:[62:8] not zero, status=%d", status); } @@ -51,7 +51,7 @@ static void payload(void) invalid_fid = DRTM_1_0_FN_DRTM_VERSION | FUNC_ID_INVALID_RSVD; status = val_drtm_features(invalid_fid, &feat1, &feat2); if (status != DRTM_ACS_NOT_SUPPORTED) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n Function ID Rsvd Bits:[62:32] not zero, status=%d", status); } diff --git a/test_pool/drtm/interface003.c b/test_pool/drtm/interface003.c index 01ec13e1..d7d37ae4 100644 --- a/test_pool/drtm/interface003.c +++ b/test_pool/drtm/interface003.c @@ -31,7 +31,7 @@ payload(uint32_t num_pe) status = g_drtm_features.unprotect_memory; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM query unprotect memory func check failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -39,7 +39,7 @@ payload(uint32_t num_pe) status = g_drtm_features.close_locality; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM query close locality func check failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -47,14 +47,14 @@ payload(uint32_t num_pe) status = g_drtm_features.get_error; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query get error func check failed err=%d", status); + val_print(ERROR, "\n DRTM query get error func check failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } status = g_drtm_features.set_error; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query set error func check failed err=%d", status); + val_print(ERROR, "\n DRTM query set error func check failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } diff --git a/test_pool/drtm/interface004.c b/test_pool/drtm/interface004.c index 50bfd648..34b731a7 100644 --- a/test_pool/drtm/interface004.c +++ b/test_pool/drtm/interface004.c @@ -32,7 +32,7 @@ payload(uint32_t num_pe) /*Status value lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query TCB hash feature failed err=%d", status); + val_print(ERROR, "\n DRTM query TCB hash feature failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -45,7 +45,7 @@ payload(uint32_t num_pe) return; } } else { - val_print(ACS_PRINT_ERR, "\n TCB hash feature value not available in return value", 0); + val_print(ERROR, "\n TCB hash feature value not available in return value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); } diff --git a/test_pool/drtm/interface005.c b/test_pool/drtm/interface005.c index d1b73fcb..8925adb9 100644 --- a/test_pool/drtm/interface005.c +++ b/test_pool/drtm/interface005.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) /*Status value less than zero are error case*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query DMA protection feature failed err=%d", status); + val_print(ERROR, "\n DRTM query DMA protection feature failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -48,13 +48,13 @@ payload(uint32_t num_pe) /* Check atleast 1 DMA Protection is supported */ dma_prot_support = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7); if (dma_prot_support == 0) { - val_print(ACS_PRINT_ERR, "\n DMA Protection Not Supported", 0); + val_print(ERROR, "\n DMA Protection Not Supported"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } } else { - val_print(ACS_PRINT_ERR, - "\n DMA protection feature value not available in return value", 0); + val_print(ERROR, + "\n DMA protection feature value not available in return value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } diff --git a/test_pool/drtm/interface006.c b/test_pool/drtm/interface006.c index 5e3d59f3..5739542d 100644 --- a/test_pool/drtm/interface006.c +++ b/test_pool/drtm/interface006.c @@ -32,7 +32,7 @@ payload(uint32_t num_pe) /*Statu value lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query TPM feature failed err=%d", status); + val_print(ERROR, "\n DRTM query TPM feature failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -46,8 +46,8 @@ payload(uint32_t num_pe) return; } } else { - val_print(ACS_PRINT_ERR, - "\n TPM feature value not available in return value", 0); + val_print(ERROR, + "\n TPM feature value not available in return value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); } diff --git a/test_pool/drtm/interface007.c b/test_pool/drtm/interface007.c index c00362f0..c22af04f 100644 --- a/test_pool/drtm/interface007.c +++ b/test_pool/drtm/interface007.c @@ -32,20 +32,20 @@ payload(uint32_t num_pe) /*Status lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM query Min memory req feature failed err=%d", status); + val_print(ERROR, "\n DRTM query Min memory req feature failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } /*Status grater than zero indicates availability of feature bits in return value*/ if (status > DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_DEBUG, "\n Minimum size of DLME data 0x%X 4KB pages", + val_print(DEBUG, "\n Minimum size of DLME data 0x%X 4KB pages", VAL_EXTRACT_BITS(features_mem_req, 0, 31)); - val_print(ACS_PRINT_DEBUG, "\n Minimum size of Normal World DCE 0x%X 4KB pages", + val_print(DEBUG, "\n Minimum size of Normal World DCE 0x%X 4KB pages", VAL_EXTRACT_BITS(features_mem_req, 32, 63)); } else { - val_print(ACS_PRINT_ERR, - "\n Min memory requirement feature value not available in return value", 0); + val_print(ERROR, + "\n Min memory requirement feature value not available in return value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); } val_set_status(index, RESULT_PASS(TEST_NUM, 1)); diff --git a/test_pool/drtm/interface008.c b/test_pool/drtm/interface008.c index 04f179c2..50cc4230 100644 --- a/test_pool/drtm/interface008.c +++ b/test_pool/drtm/interface008.c @@ -32,7 +32,7 @@ payload(uint32_t num_pe) psci_major_ver = PSCI_VERSION_GET_MAJOR(val_drtm_get_psci_ver()); if (psci_major_ver < 1) { - val_print(ACS_PRINT_ERR, "\n Version not as expected, Current version =%d", + val_print(ERROR, "\n Version not as expected, Current version =%d", psci_major_ver); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/drtm/interface009.c b/test_pool/drtm/interface009.c index a3dc4933..f45e083a 100644 --- a/test_pool/drtm/interface009.c +++ b/test_pool/drtm/interface009.c @@ -32,7 +32,7 @@ payload(uint32_t num_pe) smccc_major_ver = SMCCC_VERSION_GET_MAJOR(val_drtm_get_smccc_ver()); if (smccc_major_ver < 1) { - val_print(ACS_PRINT_ERR, "\n Version not as expected, Current version =%d", + val_print(ERROR, "\n Version not as expected, Current version =%d", smccc_major_ver); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/drtm/interface010.c b/test_pool/drtm/interface010.c index d90620fb..3b178922 100644 --- a/test_pool/drtm/interface010.c +++ b/test_pool/drtm/interface010.c @@ -42,10 +42,10 @@ payload(uint32_t num_pe) /* Get RDBase Address for current PE */ (void)num_pe; pe_rdbase = val_gic_get_pe_rdbase(index); - val_print(ACS_PRINT_DEBUG, "\n PE RD base address %llx", pe_rdbase); + val_print(DEBUG, "\n PE RD base address %llx", pe_rdbase); if (pe_rdbase == 0) { - val_print(ACS_PRINT_ERR, "\n Could not get RD Base Address", 0); + val_print(ERROR, "\n Could not get RD Base Address"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -57,14 +57,14 @@ payload(uint32_t num_pe) /* Check that LPI Support is disabled*/ if ((VAL_EXTRACT_BITS(gicr_ctrl_value, 0, 0) != 0) || (VAL_EXTRACT_BITS(gicr_ctrl_value, 3, 3) != 0)) { - val_print(ACS_PRINT_ERR, "\n LPI is not disabled", 0); + val_print(ERROR, "\n LPI is not disabled"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } num_its = val_gic_get_info(GIC_INFO_NUM_ITS); if (num_its == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ITS, Skipping Test.", 0); + val_print(DEBUG, "\n No ITS, Skipping Test."); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -72,7 +72,7 @@ payload(uint32_t num_pe) for (its_id = 0; its_id < num_its; its_id++) { /* Get ITS Base for current ITS */ if (val_gic_its_get_base(its_id, &its_base)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -83,7 +83,7 @@ payload(uint32_t num_pe) /* Check that ITS is disabled*/ if ((VAL_EXTRACT_BITS(gits_ctrl_value, 0, 0) != 0) || (VAL_EXTRACT_BITS(gits_ctrl_value, 31, 31) != 1)) { - val_print(ACS_PRINT_ERR, "\n ITS is not disabled", 0); + val_print(ERROR, "\n ITS is not disabled"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } diff --git a/test_pool/drtm/interface011.c b/test_pool/drtm/interface011.c index 9c851007..450e1b0e 100644 --- a/test_pool/drtm/interface011.c +++ b/test_pool/drtm/interface011.c @@ -41,10 +41,10 @@ payload(uint32_t num_pe) /* Get RDBase Address for current PE */ (void)num_pe; pe_rdbase = val_gic_get_pe_rdbase(index); - val_print(ACS_PRINT_DEBUG, "\n PE RD base address %llx", pe_rdbase); + val_print(DEBUG, "\n PE RD base address %llx", pe_rdbase); if (pe_rdbase == 0) { - val_print(ACS_PRINT_ERR, "\n Could not get RD Base Address", 0); + val_print(ERROR, "\n Could not get RD Base Address"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -56,7 +56,7 @@ payload(uint32_t num_pe) /* Check that LPI Support is enabled */ if ((VAL_EXTRACT_BITS(gicr_ctrl_value, 0, 0) == 0) && (VAL_EXTRACT_BITS(gicr_ctrl_value, 3, 3) == 0)) { - val_print(ACS_PRINT_ERR, "\n LPI is disabled", 0); + val_print(ERROR, "\n LPI is disabled"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -72,7 +72,7 @@ payload(uint32_t num_pe) /* Read back GICR_PENDBASER value and Fail if value is changed */ new_gicr_pendbaser = val_mmio_read(pe_rdbase + ARM_GICR_PENDBASER); if (gicr_pendbaser != new_gicr_pendbaser) { - val_print(ACS_PRINT_ERR, "\n GICR_PENDBASER value is changed when LPI is enable", 0); + val_print(ERROR, "\n GICR_PENDBASER value is changed when LPI is enable"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/drtm/interface012.c b/test_pool/drtm/interface012.c index 6bdb1d32..0bd45c2f 100644 --- a/test_pool/drtm/interface012.c +++ b/test_pool/drtm/interface012.c @@ -31,7 +31,7 @@ payload(uint32_t num_pe) /* Check if DRTM_SET_TCB_HASH is implemented */ if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; @@ -40,7 +40,7 @@ payload(uint32_t num_pe) /* If DRTM_SET_TCB_HASH is implemented then DRTM_LOCK_TCB_HASHES must be implemented */ status = g_drtm_features.lock_tcb_hashes; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/drtm/interface013.c b/test_pool/drtm/interface013.c index a9b5ee23..fc6bb036 100644 --- a/test_pool/drtm/interface013.c +++ b/test_pool/drtm/interface013.c @@ -60,7 +60,7 @@ payload(uint32_t num_pe) /* Check if DRTM_SET_TCB_HASH is implemented */ if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; @@ -69,7 +69,7 @@ payload(uint32_t num_pe) /* If DRTM_SET_TCB_HASH is implemented then DRTM_LOCK_TCB_HASHES must be implemented */ status = g_drtm_features.lock_tcb_hashes; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -77,7 +77,7 @@ payload(uint32_t num_pe) /* num_hashes value zero indicates that hashes cannot be recorded with DRTM_SET_TCB_HASH */ if (!num_hashes) { - val_print(ACS_PRINT_ERR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0", 0); + val_print(ERROR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); } @@ -87,7 +87,7 @@ payload(uint32_t num_pe) drtm_hash_table = (DRTM_TCB_HASH_TABLE *)val_memory_alloc(sizeof(DRTM_TCB_HASH_TABLE_HDR) + ((sizeof(uint32_t) + (sizeof(uint8_t) * SHA_256_DIGEST_SIZE_BYTES)) * num_hashes)); if (!drtm_hash_table) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate tcb hash table", 0); + val_print(ERROR, "\n Failed to allocate tcb hash table"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -96,7 +96,7 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_OUT_OF_RESOURCE) { - val_print(ACS_PRINT_ERR, "\n DRTM set invalid num of Hashes failed %d", status); + val_print(ERROR, "\n DRTM set invalid num of Hashes failed %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_tcb_hash; } diff --git a/test_pool/drtm/interface014.c b/test_pool/drtm/interface014.c index b125bec5..26f77545 100644 --- a/test_pool/drtm/interface014.c +++ b/test_pool/drtm/interface014.c @@ -57,7 +57,7 @@ payload(uint32_t num_pe) /* Check if DRTM_SET_TCB_HASH is implemented */ if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; @@ -66,7 +66,7 @@ payload(uint32_t num_pe) /* If DRTM_SET_TCB_HASH is implemented then DRTM_LOCK_TCB_HASHES must be implemented */ status = g_drtm_features.lock_tcb_hashes; if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -74,14 +74,14 @@ payload(uint32_t num_pe) /* num_hashes value zero indicates that hashes cannot be recorded with DRTM_SET_TCB_HASH */ if (!num_hashes) { - val_print(ACS_PRINT_ERR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0", 0); + val_print(ERROR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); } drtm_hash_table = (DRTM_TCB_HASH_TABLE *)val_memory_alloc(sizeof(DRTM_TCB_HASH_TABLE_HDR) + ((sizeof(uint32_t) + (sizeof(uint8_t) * SHA_256_DIGEST_SIZE_BYTES)) * NUM_OF_HASHES)); if (!drtm_hash_table) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate tcb hash table", 0); + val_print(ERROR, "\n Failed to allocate tcb hash table"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -91,7 +91,7 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n DRTM set invalid parameters failed %d", status); + val_print(ERROR, "\n DRTM set invalid parameters failed %d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); goto free_tcb_hash; } @@ -99,7 +99,7 @@ payload(uint32_t num_pe) /* CASE 2: Do Lock TCB Hashes and Set Tcb Hash to check return status as DENIED */ status = val_drtm_lock_tcb_hashes(); if (status != DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n DRTM Lock Hashes failed err=%d", status); + val_print(ERROR, "\n DRTM Lock Hashes failed err=%d", status); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); goto free_tcb_hash; } @@ -108,7 +108,7 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_DENIED) { - val_print(ACS_PRINT_ERR, "\n DRTM set Hash denied failed", 0); + val_print(ERROR, "\n DRTM set Hash denied failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); goto free_tcb_hash; } diff --git a/test_pool/drtm/interface015.c b/test_pool/drtm/interface015.c index aa3e9426..a266a9c2 100644 --- a/test_pool/drtm/interface015.c +++ b/test_pool/drtm/interface015.c @@ -32,7 +32,7 @@ payload(uint32_t num_pe) /*Status value less than zero are error case*/ if (status < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n DRTM query DLME Image Authentication feature not supported err=%d", status); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; @@ -46,8 +46,8 @@ payload(uint32_t num_pe) return; } } else { - val_print(ACS_PRINT_ERR, - "\n DLME Image Authentication feature value not available in return value", 0); + val_print(ERROR, + "\n DLME Image Authentication feature value not available in return value"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); } diff --git a/test_pool/ete/ete001.c b/test_pool/ete/ete001.c index 7fb7b2a9..82409231 100644 --- a/test_pool/ete/ete001.c +++ b/test_pool/ete/ete001.c @@ -32,7 +32,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceVer, bits [7:4] non-zero value indicate FEAT_ETE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 4, 7); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.TraceVer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.TraceVer = %llx", data, index); if (data == 0) { diff --git a/test_pool/ete/ete002.c b/test_pool/ete/ete002.c index 537c5855..bb0b51e3 100644 --- a/test_pool/ete/ete002.c +++ b/test_pool/ete/ete002.c @@ -35,7 +35,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceVer, bits [7:4] non-zero value indicate FEAT_ETE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 4, 7); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.TraceVer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.TraceVer = %llx", data, index); if (data == 0) { @@ -48,11 +48,11 @@ static void payload(void) * TRCIDR0.TRCCCI[7] == 1 indicates atleast 12 bit cycle counting implemented for trace unit */ reg_trcidr = val_pe_reg_read(TRCIDR0); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TRCIDR0 = %llx", reg_trcidr, index); + val_print_primary_pe(DEBUG, "\n TRCIDR0 = %llx", reg_trcidr, index); data = VAL_EXTRACT_BITS(reg_trcidr, 7, 7); if (data != 1) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Cycle counting not implemented", 0, index); + val_print_primary_pe(ERROR, "\n Cycle counting not implemented", 0, index); test_fail++; } @@ -60,11 +60,11 @@ static void payload(void) * TRCIDR4.NUMACPAIRS, bits [3:0] non-zero indicates at least one address comparator pair */ reg_trcidr = val_pe_reg_read(TRCIDR4); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TRCIDR4 = %llx", reg_trcidr, index); + val_print_primary_pe(DEBUG, "\n TRCIDR4 = %llx", reg_trcidr, index); data = VAL_EXTRACT_BITS(reg_trcidr, 0, 3); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Address comparator pair not present", + val_print_primary_pe(ERROR, "\n Address comparator pair not present", 0, index); test_fail++; } @@ -74,7 +74,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(reg_trcidr, 24, 27); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Context ID comparator not present", + val_print_primary_pe(ERROR, "\n Context ID comparator not present", 0, index); test_fail++; } @@ -87,7 +87,7 @@ static void payload(void) /* TRCIDR4.NUMVMIDC, bits [31:28] non-zero value indicates atleast one Virtual Context ID */ data = VAL_EXTRACT_BITS(reg_trcidr, 28, 31); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Virtual Context ID not present", + val_print_primary_pe(ERROR, "\n Virtual Context ID not present", 0, index); test_fail++; } @@ -98,7 +98,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(reg_trcidr, 20, 23); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n one single-shot comparator ctrl not present", + val_print_primary_pe(ERROR, "\n one single-shot comparator ctrl not present", 0, index); test_fail++; } @@ -109,7 +109,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(reg_trcidr, 16, 19); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n ETE Event not present in trace", 0, index); + val_print_primary_pe(ERROR, "\n ETE Event not present in trace", 0, index); test_fail++; } resource_selector_pair = data; @@ -118,11 +118,11 @@ static void payload(void) * TRCIDR5.NUMCNTR, bits [30:28] indicates no of Counters for trace */ reg_trcidr = val_pe_reg_read(TRCIDR5); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TRCIDR5 = %llx", reg_trcidr, index); + val_print_primary_pe(DEBUG, "\n TRCIDR5 = %llx", reg_trcidr, index); data = VAL_EXTRACT_BITS(reg_trcidr, 28, 30); if (data < 2) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Counters Expected >= 2 Actual = %d", + val_print_primary_pe(ERROR, "\n Counters Expected >= 2 Actual = %d", data, index); test_fail++; } @@ -132,13 +132,13 @@ static void payload(void) data = VAL_EXTRACT_BITS(reg_trcidr, 25, 27); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Sequencer not Implemented", 0, index); + val_print_primary_pe(ERROR, "\n Sequencer not Implemented", 0, index); test_fail++; } /* Check 9: At least four resource selection pairs */ if (resource_selector_pair < 3) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Selection Pair Expected > 3 Actual = %d", + val_print_primary_pe(ERROR, "\n Selection Pair Expected > 3 Actual = %d", resource_selector_pair + 1, index); test_fail++; } diff --git a/test_pool/ete/ete003.c b/test_pool/ete/ete003.c index 2f5f7253..45904430 100644 --- a/test_pool/ete/ete003.c +++ b/test_pool/ete/ete003.c @@ -53,7 +53,7 @@ void check_timestamp(uint32_t num_pe) /* Fail the test */ pe_timestamp_failed = 1; check_failed = 1; - val_print(ACS_PRINT_ERR, "\n Timestamp Fail for PE Index : %d", curr); + val_print(ERROR, "\n Timestamp Fail for PE Index : %d", curr); } if (curr == index) @@ -66,22 +66,22 @@ void check_timestamp(uint32_t num_pe) { /* Fail the test and continue */ pe_timestamp_failed = 1; - val_print(ACS_PRINT_ERR, "\n Timestamp Mismatch for PE : 0x%x", index); - val_print(ACS_PRINT_ERR, " and 0x%x", curr); + val_print(ERROR, "\n Timestamp Mismatch for PE : 0x%x", index); + val_print(ERROR, " and 0x%x", curr); } /* Debug Prints in case of failures */ if (pe_timestamp_failed) { check_failed = 1; - val_print(ACS_PRINT_INFO, "\n start_timestamp : %llx", start_timestamp[curr]); - val_print(ACS_PRINT_INFO, ", end_timestamp : %llx", end_timestamp[curr]); + val_print(TRACE, "\n start_timestamp : %llx", start_timestamp[curr]); + val_print(TRACE, ", end_timestamp : %llx", end_timestamp[curr]); } } if (check_failed) { - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n Primary PE start_timestamp : 0x%llx", start_timestamp[index]); - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n Primary PE end_timestamp : 0x%llx", end_timestamp[index]); val_set_status(index, RESULT_FAIL(0, 06)); } else @@ -101,7 +101,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(dfr0_value, 44, 47); if (data == 0) { test_fail = 1; - val_print_primary_pe(ACS_PRINT_ERR, "\n FEAT_TRBE not supported", 0, index); + val_print_primary_pe(ERROR, "\n FEAT_TRBE not supported", 0, index); val_set_status(index, RESULT_FAIL(0, 01)); return; } @@ -110,7 +110,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(dfr0_value, 40, 43); if (data == 0) { test_fail = 1; - val_print_primary_pe(ACS_PRINT_ERR, "\n FEAT_TRF not supported", 0, index); + val_print_primary_pe(ERROR, "\n FEAT_TRF not supported", 0, index); val_set_status(index, RESULT_FAIL(0, 02)); return; } @@ -124,12 +124,12 @@ static void payload(void) /* Store Start Timestamp values which will be used later */ start_timestamp[index] = read_cntpct_el0(); val_data_cache_ops_by_va((addr_t)(start_timestamp + index), CLEAN_AND_INVALIDATE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n Start Timestamp : 0x%llx", start_timestamp[index], index); /* Generate Trace when SelfHostedTraceEnabled = TRUE */ traced_timestamp = val_ete_generate_trace(buffer_addr, SH_TRACE_ENABLE_TRUE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n Traced Timestamp : 0x%llx", traced_timestamp, index); @@ -139,14 +139,14 @@ static void payload(void) /* Read Current Counter Value */ end_timestamp[index] = read_cntpct_el0(); val_data_cache_ops_by_va((addr_t)(end_timestamp + index), CLEAN_AND_INVALIDATE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n End Timestamp : 0x%llx", end_timestamp[index], index); /* If Trace is not generated or timestamp for current PE not updated */ if (traced_timestamp == ACS_STATUS_FAIL) { test_fail = 1; val_data_cache_ops_by_va((addr_t)(&test_fail), CLEAN_AND_INVALIDATE); - val_print_primary_pe(ACS_PRINT_ERR, "\n Trace Generation Failed", 0, index); + val_print_primary_pe(ERROR, "\n Trace Generation Failed", 0, index); val_set_status(index, RESULT_FAIL(0, 03)); return; } @@ -155,7 +155,7 @@ static void payload(void) /* Timestamp traced 0 or parsing failed*/ test_fail = 1; val_data_cache_ops_by_va((addr_t)(&test_fail), CLEAN_AND_INVALIDATE); - val_print_primary_pe(ACS_PRINT_ERR, "\n Traced Timestamp is 0", 0, index); + val_print_primary_pe(ERROR, "\n Traced Timestamp is 0", 0, index); val_set_status(index, RESULT_FAIL(0, 04)); return; } diff --git a/test_pool/ete/ete004.c b/test_pool/ete/ete004.c index 71263512..6d12151e 100644 --- a/test_pool/ete/ete004.c +++ b/test_pool/ete/ete004.c @@ -43,7 +43,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceBuffer, bits [47:44] non-zero value indicate FEAT_TRBE support */ data = VAL_EXTRACT_BITS(dfr0_value, 44, 47); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n FEAT_TRBE not supported", 0, index); + val_print_primary_pe(ERROR, "\n FEAT_TRBE not supported", 0, index); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -51,7 +51,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceFilt, bits [43:40] non-zero value indicate FEAT_TRF support */ data = VAL_EXTRACT_BITS(dfr0_value, 40, 43); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n FEAT_TRF not supported", 0, index); + val_print_primary_pe(ERROR, "\n FEAT_TRF not supported", 0, index); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -59,7 +59,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.ExtTrcBuff, bits [59:56] non-zero value indicate FEAT_TRBE_EXT support */ data = VAL_EXTRACT_BITS(dfr0_value, 56, 59); if (data == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n FEAT_TRBE_EXT not supported", 0, index); + val_print_primary_pe(ERROR, "\n FEAT_TRBE_EXT not supported", 0, index); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -73,19 +73,19 @@ static void payload(void) /* Generate Trace when SelfHostedTraceEnabled = TRUE */ traced_timestamp_1 = val_ete_generate_trace(trace_buffer_addr, SH_TRACE_ENABLE_TRUE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n traced_timestamp_1 : 0x%llx", traced_timestamp_1, index); /* Generate Trace when SelfHostedTraceEnabled = FALSE */ traced_timestamp_2 = val_ete_generate_trace(trace_buffer_addr, SH_TRACE_ENABLE_FALSE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n traced_timestamp_2 : 0x%llx", traced_timestamp_2, index); /* Generate Trace when SelfHostedTraceEnabled = TRUE */ traced_timestamp_3 = val_ete_generate_trace(trace_buffer_addr, SH_TRACE_ENABLE_TRUE); - val_print_primary_pe(ACS_PRINT_INFO, + val_print_primary_pe(TRACE, "\n traced_timestamp_3 : 0x%llx", traced_timestamp_3, index); /* Disable Timer */ @@ -94,13 +94,13 @@ static void payload(void) if ((traced_timestamp_1 == ACS_STATUS_FAIL) || (traced_timestamp_2 == ACS_STATUS_FAIL) || (traced_timestamp_3 == ACS_STATUS_FAIL)) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Trace Generation Failed", 0, index); + val_print_primary_pe(ERROR, "\n Trace Generation Failed", 0, index); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } if ((traced_timestamp_1 == 0) || (traced_timestamp_2 == 0) || (traced_timestamp_3 == 0)) { - val_print_primary_pe(ACS_PRINT_ERR, "\n Traced Timestamp is 0", 0, index); + val_print_primary_pe(ERROR, "\n Traced Timestamp is 0", 0, index); val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); return; } diff --git a/test_pool/ete/ete005.c b/test_pool/ete/ete005.c index 67920ccd..8d95cafa 100644 --- a/test_pool/ete/ete005.c +++ b/test_pool/ete/ete005.c @@ -31,7 +31,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceBuffer, bits [47:44] non-zero value indicate FEAT_TRBE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 44, 47); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", data, index); if (data == 0) { diff --git a/test_pool/ete/ete006.c b/test_pool/ete/ete006.c index 905d5ed1..6e17fd1a 100644 --- a/test_pool/ete/ete006.c +++ b/test_pool/ete/ete006.c @@ -34,7 +34,7 @@ static void payload(void) /* TRBIDR_EL1.TraceBuffer, bits [47:44] non-zero value indicate FEAT_TRBE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 44, 47); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", data, index); if (data == 0) { @@ -44,7 +44,7 @@ static void payload(void) /* TRBIDR_EL1.F[Bit 5] must be same for all TRBE trace buffers */ data = VAL_EXTRACT_BITS(val_pe_reg_read(TRBIDR_EL1), 5, 5); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TRBIDR_EL1.F = %llx", data, index); + val_print_primary_pe(DEBUG, "\n TRBIDR_EL1.F = %llx", data, index); if (index == primary_index) primary_pe_flag_updates = data; diff --git a/test_pool/ete/ete007.c b/test_pool/ete/ete007.c index ca496c5c..9ca92981 100644 --- a/test_pool/ete/ete007.c +++ b/test_pool/ete/ete007.c @@ -34,7 +34,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.TraceBuffer, bits [47:44] non-zero value indicate FEAT_TRBE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 44, 47); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.TraceBuffer = %llx", data, index); if (data == 0) { @@ -44,7 +44,7 @@ static void payload(void) /* TRBIDR_EL1.Align[3:0] must be same for all TRBE trace buffers */ data = VAL_EXTRACT_BITS(val_pe_reg_read(TRBIDR_EL1), 0, 3); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TRBIDR_EL1.Align = %llx", data, index); + val_print_primary_pe(DEBUG, "\n TRBIDR_EL1.Align = %llx", data, index); if (index == primary_index) min_trace_alignment = data; diff --git a/test_pool/ete/ete008.c b/test_pool/ete/ete008.c index da2441bb..aeed951a 100644 --- a/test_pool/ete/ete008.c +++ b/test_pool/ete/ete008.c @@ -34,13 +34,13 @@ static void payload(void) int_id = val_pe_get_gicc_trbe_interrupt(index); if (int_id == 1) { - val_print_primary_pe(ACS_PRINT_DEBUG, + val_print_primary_pe(DEBUG, "\n GICC TRBE interrupt field needs at least 6.5 ACPI table", 0, index); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } - val_print_primary_pe(ACS_PRINT_DEBUG, "\n GICC TRBE INTERRUPT GISV = %d", int_id, + val_print_primary_pe(DEBUG, "\n GICC TRBE INTERRUPT GISV = %d", int_id, index); if (val_gic_is_valid_ppi(int_id)) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/exerciser/e001.c b/test_pool/exerciser/e001.c index 0362e667..86c24bdc 100644 --- a/test_pool/exerciser/e001.c +++ b/test_pool/exerciser/e001.c @@ -75,7 +75,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, /* It ACS Not Supported, continue */ if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); + val_print(DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); continue; } @@ -84,14 +84,14 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); + val_print(ERROR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); goto clean_fail; } status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); + val_print(ERROR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); goto clean_fail; } @@ -138,7 +138,7 @@ check_source_validation (uint32_t req_instance, uint32_t req_rp_bdf, uint64_t ba /* DMA should be successful and not trigger Corr/Uncorr error, UR response, Sig Target Abort. */ if ((val_pcie_is_device_status_error(req_rp_bdf) != 0) || (val_pcie_is_sig_target_abort(req_rp_bdf) != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Src Validation unexpected Error on RootPort : 0x%x", req_rp_bdf); return ACS_STATUS_FAIL; } @@ -166,7 +166,7 @@ check_source_validation (uint32_t req_instance, uint32_t req_rp_bdf, uint64_t ba if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { /* Fail the part */ - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Src Validation Expected Error RootPort : 0x%x", req_rp_bdf); return ACS_STATUS_FAIL; } @@ -197,7 +197,7 @@ check_transaction_blocking (uint32_t req_instance, uint32_t req_rp_bdf, uint64_t if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { /* Fail the part */ - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Traxn Blocking Expected Error RootPort : 0x%x", req_rp_bdf); return ACS_STATUS_FAIL; } @@ -251,7 +251,7 @@ payload(void) continue; req_e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); + val_print(DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); /* Get RP of the exerciser */ if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) @@ -259,7 +259,7 @@ payload(void) /* It ACS Not Supported, Fail.*/ if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); + val_print(ERROR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); fail_cnt++; continue; } @@ -274,7 +274,7 @@ payload(void) if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base)) continue; - val_print(ACS_PRINT_DEBUG, "\n Target exerciser BDF - 0x%x", tgt_e_bdf); + val_print(DEBUG, "\n Target exerciser BDF - 0x%x", tgt_e_bdf); /* Enable Source Validation & Transaction Blocking */ val_pcie_read_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, ®_value); @@ -285,7 +285,7 @@ payload(void) /* Check For ACS Functionality */ status = check_source_validation(instance, req_rp_bdf, bar_base); if (status == ACS_STATUS_SKIP) - val_print(ACS_PRINT_DEBUG, "\n ACS Source Validation Skipped for 0x%x", req_rp_bdf); + val_print(DEBUG, "\n ACS Source Validation Skipped for 0x%x", req_rp_bdf); else if (status) curr_bdf_failed++; @@ -293,13 +293,13 @@ payload(void) status = check_transaction_blocking(instance, req_rp_bdf, bar_base); if (status == ACS_STATUS_SKIP) - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf); else if (status) curr_bdf_failed++; if (curr_bdf_failed > 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n ACS Functional Check Failed, RP Bdf : 0x%x", req_rp_bdf); curr_bdf_failed = 0; diff --git a/test_pool/exerciser/e002.c b/test_pool/exerciser/e002.c index df2435a6..c2f0919b 100644 --- a/test_pool/exerciser/e002.c +++ b/test_pool/exerciser/e002.c @@ -63,7 +63,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, /* It ACS Not Supported, continue */ if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); + val_print(DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); continue; } @@ -174,7 +174,7 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa, /* Configure SMMU tables for this exerciser to use this page table for VA to PA translations*/ if (val_smmu_map(master, *pgt_desc)) { - val_print(ACS_PRINT_DEBUG, "\n SMMU mapping failed (%x) ", e_bdf); + val_print(DEBUG, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } @@ -191,14 +191,14 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa, /* Corrupt the BAR and read the value before making a DMA transaction. */ val_mmio_write(txn_va, 0xABCDABCD); old_val = val_mmio_read((uint64_t)txn_va); - val_print(ACS_PRINT_DEBUG, "\n Bar value before DMA is %llx", old_val); + val_print(DEBUG, "\n Bar value before DMA is %llx", old_val); /* Trigger DMA from Exerciser to the target device. */ val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance); /* Read the memory location to check if DMA is successful or not. */ new_val = val_mmio_read((uint64_t)txn_va); - val_print(ACS_PRINT_DEBUG, "\n Bar value after DMA is %llx", new_val); + val_print(DEBUG, "\n Bar value after DMA is %llx", new_val); /* If the values of targeted reads are same, the DMA is failure. */ if (old_val == new_val) @@ -211,14 +211,14 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa, /* DMA must fail because Write permission not given */ if ((pgt_ap == PGT_STAGE1_AP_RO) && (dma_status != 0)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Seq1:DMA Write must not happen For : %4x", req_instance); goto test_fail; } /* DMA must not fail because Write permission given */ if ((pgt_ap == PGT_STAGE1_AP_RW) && (dma_status == 0)) { - val_print(ACS_PRINT_DEBUG, "\n Seq2:DMA Write must happen For : %4x", req_instance); + val_print(DEBUG, "\n Seq2:DMA Write must happen For : %4x", req_instance); goto test_fail; } status = ACS_STATUS_PASS; @@ -263,7 +263,7 @@ check_redirected_req_validation (uint32_t req_instance, uint32_t req_rp_bdf, uin &pgt_desc, req_instance, req_rp_bdf, PGT_STAGE1_AP_RO); if (status) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Seq1:SMMU Mapping Failed For : %4x", req_instance); goto test_fail; } @@ -273,7 +273,7 @@ check_redirected_req_validation (uint32_t req_instance, uint32_t req_rp_bdf, uin */ if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { - val_print(ACS_PRINT_DEBUG, "\n Seq1:Expected Error For RootPort : 0x%x", req_rp_bdf); + val_print(DEBUG, "\n Seq1:Expected Error For RootPort : 0x%x", req_rp_bdf); goto test_fail; } @@ -290,7 +290,7 @@ check_redirected_req_validation (uint32_t req_instance, uint32_t req_rp_bdf, uin &pgt_desc, req_instance, req_rp_bdf, PGT_STAGE1_AP_RW); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Seq2:SMMU Mapping Failed For : %4x", req_instance); + val_print(DEBUG, "\n Seq2:SMMU Mapping Failed For : %4x", req_instance); goto test_fail; } @@ -299,7 +299,7 @@ check_redirected_req_validation (uint32_t req_instance, uint32_t req_rp_bdf, uin */ if (val_pcie_is_device_status_error(req_rp_bdf) || val_pcie_is_sig_target_abort(req_rp_bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Seq2:Expected No Error For RootPort : 0x%x", req_rp_bdf); + val_print(DEBUG, "\n Seq2:Expected No Error For RootPort : 0x%x", req_rp_bdf); goto test_fail; } @@ -389,7 +389,7 @@ payload(void) continue; req_e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); + val_print(DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); /* Get RP of the exerciser */ if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) @@ -397,7 +397,7 @@ payload(void) /* It ACS Not Supported, Fail.*/ if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); + val_print(ERROR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); fail_cnt++; continue; } @@ -413,10 +413,10 @@ payload(void) /* Check For Redirected Request Validation Functionality */ status = check_redirected_req_validation(instance, req_rp_bdf, bar_base); if (status == ACS_STATUS_SKIP) - val_print(ACS_PRINT_ERR, "\n ACS Validation Check Skipped for 0x%x", req_rp_bdf); + val_print(ERROR, "\n ACS Validation Check Skipped for 0x%x", req_rp_bdf); else if (status) { fail_cnt++; - val_print(ACS_PRINT_ERR, "\n ACS Redirected Req Check Failed for 0x%x", req_rp_bdf); + val_print(ERROR, "\n ACS Redirected Req Check Failed for 0x%x", req_rp_bdf); } /* Check for Redirected Request Validation Functionality for the same device @@ -457,11 +457,11 @@ payload(void) /* Check For Redirected Request Validation Functionality */ status = check_redirected_req_validation(instance, req_rp_bdf, bar_base); if (status == ACS_STATUS_SKIP) - val_print(ACS_PRINT_ERR, "\n ACS Validation Check Skipped for 0x%x", + val_print(ERROR, "\n ACS Validation Check Skipped for 0x%x", req_rp_bdf); else if (status) { fail_cnt++; - val_print(ACS_PRINT_ERR, "\n ACS Redirected Req Check Failed for 0x%x", + val_print(ERROR, "\n ACS Redirected Req Check Failed for 0x%x", req_rp_bdf); } } diff --git a/test_pool/exerciser/e003.c b/test_pool/exerciser/e003.c index e1b7a39c..5673c386 100644 --- a/test_pool/exerciser/e003.c +++ b/test_pool/exerciser/e003.c @@ -61,14 +61,14 @@ static uint32_t test_sequence_check(uint32_t instance) for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { val_exerciser_get_param(TRANSACTION_TYPE, &idx, &transaction_type, instance); if (transaction_type != transaction_order[idx]) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d arrival order check failed", instance); + val_print(ERROR, "\n Exerciser %d arrival order check failed", instance); return 1; } } /* Get number of transactions captured from exerciser */ if (num_transactions != idx) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d gathering check failed", instance); + val_print(ERROR, "\n Exerciser %d gathering check failed", instance); return 1; } @@ -234,11 +234,11 @@ cfgspace_transactions_order_check(void) /* Get exerciser bdf */ bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", bdf); /* If exerciser doesn't have PCI_CAP skip the bdf */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cid_offset) == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n PCIe Express Capability not found. Skipping exerciser 0x%x", bdf); continue; } @@ -255,8 +255,8 @@ cfgspace_transactions_order_check(void) } if (status) { - val_print(ACS_PRINT_DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); + val_print(DEBUG, " Status :0x%x", status); continue; } @@ -300,21 +300,21 @@ barspace_transactions_order_check(void) /* Get exerciser bdf */ bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", bdf); /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); continue; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser 0x%x data read error ", bdf); + val_print(ERROR, "\n Exerciser 0x%x data read error ", bdf); continue; } /* If BAR region is not Prefetchable, skip the exerciser */ if (e_data.bar_space.type != MMIO_PREFETCHABLE) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n BAR region is not prefetchable. Skipping exerciser 0x%x", bdf); continue; } @@ -330,8 +330,8 @@ barspace_transactions_order_check(void) } if (status) { - val_print(ACS_PRINT_DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); + val_print(DEBUG, " Status :0x%x", status); continue; } diff --git a/test_pool/exerciser/e004.c b/test_pool/exerciser/e004.c index 0946652d..971763e8 100644 --- a/test_pool/exerciser/e004.c +++ b/test_pool/exerciser/e004.c @@ -39,7 +39,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id + instance); + val_print(TRACE, "\n Received MSI interrupt %x ", lpi_int_id + instance); val_gic_end_of_interrupt(lpi_int_id + instance); return; } @@ -67,7 +67,7 @@ payload (void) index = val_pe_get_index_mpid (val_pe_get_mpid()); if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ITS, Skipping Test.\n", 0); + val_print(DEBUG, "\n No ITS, Skipping Test.\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -89,12 +89,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI-X/MSI Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(DEBUG, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -105,7 +105,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -113,7 +113,7 @@ payload (void) status = val_gic_request_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -122,7 +122,7 @@ payload (void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -133,7 +133,7 @@ payload (void) /* Get ITS Base for current ITS */ if (val_gic_its_get_base(its_id, &its_base)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; @@ -149,7 +149,7 @@ payload (void) /* Interrupt must not be generated */ if (irq_pending == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Interrupt triggered from PE for bdf : 0x%x, ", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); diff --git a/test_pool/exerciser/e006.c b/test_pool/exerciser/e006.c index 26dda8a3..bad08a64 100644 --- a/test_pool/exerciser/e006.c +++ b/test_pool/exerciser/e006.c @@ -39,7 +39,7 @@ static void intr_handler(void) { if (e_intr_pending == 0) { - val_print(ACS_PRINT_ERR, "\n Multiple interrupts received", 0); + val_print(ERROR, "\n Multiple interrupts received"); test_fail++; return; } @@ -48,7 +48,7 @@ static void intr_handler(void) if (!val_pcie_check_interrupt_status(e_bdf)) { - val_print(ACS_PRINT_ERR, "\n No outstanding interrupt for bdf 0x%x", e_bdf); + val_print(ERROR, "\n No outstanding interrupt for bdf 0x%x", e_bdf); test_fail++; return; } @@ -62,7 +62,7 @@ static void intr_handler(void) /* Clear the interrupt pending state */ e_intr_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received legacy interrupt %d", e_intr_line); + val_print(TRACE, "\n Received legacy interrupt %d", e_intr_line); } @@ -84,7 +84,7 @@ payload (void) /* Allocate memory for interrupt mappings */ e_intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!e_intr_map) { - val_print(ACS_PRINT_ERR, "\n Memory allocation error", 00); + val_print(ERROR, "\n Memory allocation error", 00); val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 2)); return; } @@ -100,7 +100,7 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Check if the PCI interrupt request pins is connected INTA#-through-INTD */ val_pcie_read_cfg(e_bdf, PCIE_INTERRUPT_LINE, &e_intr_pin); @@ -130,7 +130,7 @@ payload (void) ret_val = val_gic_install_isr(e_intr_line, intr_handler); if (ret_val) { - val_print (ACS_PRINT_ERR, "\n Installing ISR failed for IRQ: %x", e_intr_line); + val_print (ERROR, "\n Installing ISR failed for IRQ: %x", e_intr_line); val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 02)); return; } @@ -150,7 +150,7 @@ payload (void) val_gic_end_of_interrupt(e_intr_line); val_gic_disableInterruptSource(e_intr_line); val_gic_free_irq(e_intr_line, 0); - val_print(ACS_PRINT_ERR, "\n Interrupt trigger failed for bdf 0x%lx", e_bdf); + val_print(ERROR, "\n Interrupt trigger failed for bdf 0x%lx", e_bdf); test_fail++; continue; } @@ -158,7 +158,7 @@ payload (void) /* Check if interrupt status bit is cleared in Status register */ if (val_pcie_check_interrupt_status(e_bdf)) { - val_print(ACS_PRINT_ERR, "\n Outstanding interrupt for bdf 0x%x", e_bdf); + val_print(ERROR, "\n Outstanding interrupt for bdf 0x%x", e_bdf); test_fail++; /* Deassert and uninstall ISR before moving to next */ val_exerciser_ops(CLEAR_INTR, e_intr_line, instance); @@ -177,7 +177,7 @@ payload (void) break; } else { - val_print(ACS_PRINT_DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping bdf: 0x%x", e_bdf); + val_print(DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping bdf: 0x%x", e_bdf); continue; } } diff --git a/test_pool/exerciser/e007.c b/test_pool/exerciser/e007.c index 8cadd0d1..b3089363 100644 --- a/test_pool/exerciser/e007.c +++ b/test_pool/exerciser/e007.c @@ -83,7 +83,7 @@ uint32_t test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t ins /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + val_print(ERROR, "\n I/O coherency failure for Exerciser %4x", instance); return 1; } @@ -124,7 +124,7 @@ uint32_t test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t ins /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + val_print(ERROR, "\n I/O coherency failure for Exerciser %4x", instance); return 1; } @@ -170,7 +170,7 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Find SMMU node index for this exerciser instance */ smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf), @@ -185,7 +185,7 @@ payload (void) */ if (smmu_index != ACS_INVALID_INDEX) { if (val_smmu_disable(smmu_index)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x smmu disable error", instance); + val_print(ERROR, "\n Exerciser %x smmu disable error", instance); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -194,7 +194,7 @@ payload (void) /* Get a WB, outer shareable DDR Buffer of size TEST_DATA_BLK_SIZE */ dram_buf1_virt = val_memory_alloc_cacheable(e_bdf, TEST_DATA_BLK_SIZE, &dram_buf1_phys); if (!dram_buf1_virt) { - val_print(ACS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 2); + val_print(ERROR, "\n WB and OSH mem alloc failure %x", 2); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -204,7 +204,7 @@ payload (void) * No snoop bit in exerciser control register. */ if (val_exerciser_ops(TXN_NO_SNOOP_DISABLE, 0, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x No Snoop disable error", instance); + val_print(ERROR, "\n Exerciser %x No Snoop disable error", instance); goto test_fail; } diff --git a/test_pool/exerciser/e008.c b/test_pool/exerciser/e008.c index e66e1ac1..6d49b708 100644 --- a/test_pool/exerciser/e008.c +++ b/test_pool/exerciser/e008.c @@ -76,7 +76,7 @@ test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3 /* Check if the transaction pending bit is cleared */ tp_bit = val_is_transaction_pending_set(e_bdf); if (tp_bit) { - val_print(ACS_PRINT_ERR, "\n Transaction still pending in function %4x", instance); + val_print(ERROR, "\n Transaction still pending in function %4x", instance); return 1; } @@ -86,7 +86,7 @@ test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3 /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + val_print(ERROR, "\n I/O coherency failure for Exerciser %4x", instance); return 1; } @@ -125,7 +125,7 @@ test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3 /* Check if the transaction pending bit is cleared */ tp_bit = val_is_transaction_pending_set(e_bdf); if (tp_bit) { - val_print(ACS_PRINT_ERR, "\n Transaction still pending in function %4x", instance); + val_print(ERROR, "\n Transaction still pending in function %4x", instance); return 1; } @@ -134,7 +134,7 @@ test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3 /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + val_print(ERROR, "\n I/O coherency failure for Exerciser %4x", instance); return 1; } @@ -174,7 +174,7 @@ payload (void *arg) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); dp_type = val_pcie_device_port_type(e_bdf); /* Check entry is RCiEP/ iEP_EP. Else move to next BDF. */ @@ -195,7 +195,7 @@ payload (void *arg) */ if (smmu_index != ACS_INVALID_INDEX) { if (val_smmu_disable(smmu_index)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x smmu disable error", instance); + val_print(ERROR, "\n Exerciser %x smmu disable error", instance); val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 1)); return; } @@ -206,7 +206,7 @@ payload (void *arg) if (!dram_buf1_virt) { - val_print(ACS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 2); + val_print(ERROR, "\n WB and OSH mem alloc failure %x", 2); val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 2)); return; } @@ -216,7 +216,7 @@ payload (void *arg) * No snoop bit in exerciser control register. */ if (val_exerciser_ops(TXN_NO_SNOOP_ENABLE, 0, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x No Snoop enable error", instance); + val_print(ERROR, "\n Exerciser %x No Snoop enable error", instance); goto test_fail; } diff --git a/test_pool/exerciser/e010.c b/test_pool/exerciser/e010.c index 4c7523c1..bb620c53 100644 --- a/test_pool/exerciser/e010.c +++ b/test_pool/exerciser/e010.c @@ -54,11 +54,11 @@ payload(void) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Check if exerciser is child of one of the rootports */ if (val_pcie_parent_is_rootport(e_bdf, &erp_bdf)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser not a downstream device to RP. Skipping 0x%x", e_bdf); continue; } @@ -71,7 +71,7 @@ payload(void) status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, "\n Unable to start transaction monitoring", 0); + val_print(DEBUG, "\n Unable to start transaction monitoring"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -80,7 +80,7 @@ payload(void) status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, "\n Unable to stop transaction monitoring", 0); + val_print(DEBUG, "\n Unable to stop transaction monitoring"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -88,7 +88,7 @@ payload(void) val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); if (header_type != TYPE0) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x Sec Bus Transaction failure", erp_bdf); + val_print(ERROR, "\n BDF 0x%x Sec Bus Transaction failure", erp_bdf); fail_cnt++; } diff --git a/test_pool/exerciser/e011.c b/test_pool/exerciser/e011.c index 5be89a44..c57f84b5 100644 --- a/test_pool/exerciser/e011.c +++ b/test_pool/exerciser/e011.c @@ -45,7 +45,7 @@ payload (void) index = val_pe_get_index_mpid (val_pe_get_mpid()); if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skipping Test as GIC ITS not available", 0); + val_print(DEBUG, "\n Skipping Test as GIC ITS not available"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -66,12 +66,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI-X Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(DEBUG, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -82,7 +82,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -91,7 +91,7 @@ payload (void) /* Get ITS Group Index for current device */ status = val_iovirt_get_its_info(ITS_GET_GRP_INDEX_FOR_ID, 0, its_id, &grp_id); if (status) { - val_print(ACS_PRINT_ERR, "\n Invalid ITS ID, Failed on BDF 0x%x", e_bdf); + val_print(ERROR, "\n Invalid ITS ID, Failed on BDF 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } diff --git a/test_pool/exerciser/e012.c b/test_pool/exerciser/e012.c index dee55874..55327eca 100644 --- a/test_pool/exerciser/e012.c +++ b/test_pool/exerciser/e012.c @@ -37,7 +37,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", base_lpi_id + instance); + val_print(TRACE, "\n Received MSI interrupt %x ", base_lpi_id + instance); val_gic_end_of_interrupt(base_lpi_id + instance); return; } @@ -65,7 +65,7 @@ payload (void) status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status || (num_group < 2)) { - val_print(ACS_PRINT_DEBUG, "\n Number of ITS Group < 2, Skipping Test", 0); + val_print(DEBUG, "\n Number of ITS Group < 2, Skipping Test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -87,12 +87,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI/MSI-X Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_INFO, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(TRACE, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -103,7 +103,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -112,7 +112,7 @@ payload (void) /* Get ITS Group Index for current device */ status = val_iovirt_get_its_info(ITS_GET_GRP_INDEX_FOR_ID, 0, its_id, &get_value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Invalid ITS ID, Skipping BDF 0x%x", e_bdf); + val_print(DEBUG, "\n Invalid ITS ID, Skipping BDF 0x%x", e_bdf); continue; } @@ -120,14 +120,14 @@ payload (void) status = val_iovirt_get_its_info(ITS_GET_ID_FOR_BLK_INDEX, ((get_value+1)%num_group), 0, &get_value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get other Group," + val_print(DEBUG, "\n Could not get other Group," " Skipping for BDF 0x%x", e_bdf); continue; } status = val_gic_request_msi(e_bdf, device_id, get_value, base_lpi_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -136,7 +136,7 @@ payload (void) status = val_gic_install_isr(base_lpi_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", base_lpi_id + instance); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -155,9 +155,9 @@ payload (void) /* Interrupt must not be generated */ if (irq_pending == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Interrupt triggered for int_id : 0x%x, ", base_lpi_id + instance); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "BDF : 0x%x ", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); val_gic_free_msi(e_bdf, device_id, get_value, base_lpi_id + instance, msi_index); diff --git a/test_pool/exerciser/e013.c b/test_pool/exerciser/e013.c index 49e9ff34..dde83446 100644 --- a/test_pool/exerciser/e013.c +++ b/test_pool/exerciser/e013.c @@ -38,7 +38,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id + instance); + val_print(TRACE, "\n Received MSI interrupt %x ", lpi_int_id + instance); val_gic_end_of_interrupt(lpi_int_id + instance); return; } @@ -68,7 +68,7 @@ get_exerciser_in_its_group(uint32_t its_id, uint32_t *req_instance) PCIE_EXTRACT_BDF_SEG(bdf), &device_id, NULL, &req_its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return 1; @@ -108,7 +108,7 @@ payload (void) index = val_pe_get_index_mpid (val_pe_get_mpid()); if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ITS, Skipping Test.\n", 0); + val_print(DEBUG, "\n No ITS, Skipping Test.\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -130,12 +130,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI/MSI-X Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_INFO, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(TRACE, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -144,7 +144,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -153,7 +153,7 @@ payload (void) /* Search for an exerciser within the same ITS Group */ status = get_exerciser_in_its_group(its_id, &req_instance); if (status) { - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n Could not find another exerciser : 0x%x", e_bdf); continue; } @@ -167,7 +167,7 @@ payload (void) * other exerciser = req_bdf's MSI Table */ status = val_gic_request_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", req_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -176,7 +176,7 @@ payload (void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; @@ -195,7 +195,7 @@ payload (void) /* Interrupt must not be generated */ if (irq_pending == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Interrupt triggered from diff exerciser : 0x%x, ", req_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); val_gic_free_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index); diff --git a/test_pool/exerciser/e014.c b/test_pool/exerciser/e014.c index 48f040b9..a8baa880 100644 --- a/test_pool/exerciser/e014.c +++ b/test_pool/exerciser/e014.c @@ -62,14 +62,14 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); + val_print(ERROR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); goto test_fail; } status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); + val_print(ERROR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); goto test_fail; } @@ -128,7 +128,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P. */ if (!val_pcie_p2p_support()) { - val_print(ACS_PRINT_DEBUG, "\n P2P is supported, Skipping Test", 0); + val_print(DEBUG, "\n P2P is supported, Skipping Test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -141,7 +141,7 @@ payload(void) continue; req_e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); + val_print(DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); /* Get RP of the exerciser */ if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) @@ -152,7 +152,7 @@ payload(void) if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base)) continue; - val_print(ACS_PRINT_DEBUG, "\n Target exerciser BDF - 0x%x", tgt_e_bdf); + val_print(DEBUG, "\n Target exerciser BDF - 0x%x", tgt_e_bdf); test_skip = 0; /* Check if P2P transaction causes any deadlock */ diff --git a/test_pool/exerciser/e015.c b/test_pool/exerciser/e015.c index c8066bea..dbaae132 100644 --- a/test_pool/exerciser/e015.c +++ b/test_pool/exerciser/e015.c @@ -63,7 +63,7 @@ payload(void) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* ARI Capability not applicable for RCiEP */ dp_type = val_pcie_device_port_type(e_bdf); @@ -72,7 +72,7 @@ payload(void) /* Check if exerciser is child of one of the rootports */ if (val_pcie_parent_is_rootport(e_bdf, &erp_bdf)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser not a downstream device to RP. Skipping 0x%x", e_bdf); continue; } @@ -85,8 +85,8 @@ payload(void) /* Skip the device if the RP does not support ARI forwarding */ if (status == 0) { - val_print(ACS_PRINT_WARN, "\n ARI Forwarding not supported for bdf 0x%x", erp_bdf); - val_print(ACS_PRINT_WARN, "\n Skipping test for exerciser bdf 0x%x", e_bdf); + val_print(WARN, "\n ARI Forwarding not supported for bdf 0x%x", erp_bdf); + val_print(WARN, "\n Skipping test for exerciser bdf 0x%x", e_bdf); continue; } @@ -106,8 +106,8 @@ payload(void) /* Fail the test if the bitfied does not respond to the write */ if (reg_value != 1) { - val_print(ACS_PRINT_ERR, "\n ARI Forwarding Enable bit not set for", 0); - val_print(ACS_PRINT_ERR, " bdf 0x%x", erp_bdf); + val_print(ERROR, "\n ARI Forwarding Enable bit not set for"); + val_print(ERROR, " bdf 0x%x", erp_bdf); fail_cnt++; continue; } @@ -138,7 +138,7 @@ payload(void) val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); if (header_type != TYPE0) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x Sec Bus Type 0 error", erp_bdf); + val_print(ERROR, "\n BDF 0x%x Sec Bus Type 0 error", erp_bdf); fail_cnt++; } val_exerciser_get_param(CLEAR_TXN, 0, 0, instance); @@ -176,7 +176,7 @@ payload(void) val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); if (header_type != TYPE1) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x Sec Bus Type 1 error", erp_bdf); + val_print(ERROR, "\n BDF 0x%x Sec Bus Type 1 error", erp_bdf); fail_cnt++; } } diff --git a/test_pool/exerciser/e016.c b/test_pool/exerciser/e016.c index 990486a1..cc1fcb4e 100644 --- a/test_pool/exerciser/e016.c +++ b/test_pool/exerciser/e016.c @@ -43,7 +43,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); } @@ -67,7 +67,7 @@ payload(void) branch_to_test = &&exception_return; if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -82,15 +82,15 @@ payload(void) continue; bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", bdf); /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); goto test_fail; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + val_print(ERROR, "\n Exerciser %d data read error ", instance); goto test_fail; } @@ -107,8 +107,8 @@ payload(void) } if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(ERROR, "\n Failed in BAR ioremap for instance %x", instance); + val_print(DEBUG, " Status :0x%x", status); goto test_fail; } @@ -124,7 +124,7 @@ payload(void) if ((old_value != new_value && new_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { - val_print(ACS_PRINT_ERR, "\n Memory access check failed for BDF 0x%x", bdf); + val_print(ERROR, "\n Memory access check failed for BDF 0x%x", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); val_pcie_clear_urd(bdf); return; diff --git a/test_pool/exerciser/e017.c b/test_pool/exerciser/e017.c index e4ffccfa..b6348ae5 100644 --- a/test_pool/exerciser/e017.c +++ b/test_pool/exerciser/e017.c @@ -51,7 +51,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_print(TRACE, "\n Received exception of type: %d", interrupt_type); } @@ -88,7 +88,7 @@ payload(void *arg) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 01)); return; } @@ -100,7 +100,7 @@ payload(void *arg) if (!dram_buf_virt) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Unable to allocate memory for buffer of %x pages", TEST_DATA_NUM_PAGES); val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 02)); return; @@ -116,12 +116,12 @@ payload(void *arg) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Skip this exerciser if it doesn't have mmio BAR */ val_pcie_get_mmio_bar(e_bdf, &bar_base); if (!bar_base) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser 0x%x does not have MMIO BAR. Skipping exerciser.", e_bdf); continue; } @@ -186,7 +186,7 @@ payload(void *arg) val_pcie_clear_urd(erp_bdf); } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Root Port BDF 0x%x BME functionality failure", erp_bdf); fail_cnt++; } @@ -199,7 +199,7 @@ payload(void *arg) val_pcie_read_cfg(e_bdf, COMMAND_REG_OFFSET, ®_value); if (!((reg_value & MASTER_ABORT_MASK) >> MASTER_ABORT_SHIFT)) { - val_print(ACS_PRINT_ERR, "\n Exerciser BDF 0x%x BME functionality failure", e_bdf); + val_print(ERROR, "\n Exerciser BDF 0x%x BME functionality failure", e_bdf); fail_cnt++; } diff --git a/test_pool/exerciser/e019.c b/test_pool/exerciser/e019.c index b363321a..720ca9b3 100644 --- a/test_pool/exerciser/e019.c +++ b/test_pool/exerciser/e019.c @@ -107,7 +107,7 @@ payload(void) */ pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { - val_print(ACS_PRINT_ERR, "\n mem alloc failure %x", 03); + val_print(ERROR, "\n mem alloc failure %x", 03); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -117,7 +117,7 @@ payload(void) /* Allocate a buffer to perform DMA tests on */ dram_buf_in_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES); if (!dram_buf_in_virt) { - val_print(ACS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 02); + val_print(ERROR, "\n Cacheable mem alloc failure %x", 02); val_memory_free_aligned(pgt_base_array); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; @@ -131,12 +131,12 @@ payload(void) /* Get translation attributes via TCR and translation table base via TTBR */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation attributes via TCR", 0); + val_print(ERROR, "\n Unable to get translation attributes via TCR"); goto test_fail; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation table via TBBR", 0); + val_print(ERROR, "\n Unable to get translation table via TBBR"); goto test_fail; } @@ -148,7 +148,7 @@ payload(void) * our own page table later. */ if (val_pgt_get_attributes(pgt_desc, (uint64_t)dram_buf_in_virt, &mem_desc->attributes)) { - val_print(ACS_PRINT_ERR, "\n Unable to get memory attributes of the test buffer", 0); + val_print(ERROR, "\n Unable to get memory attributes of the test buffer"); goto test_fail; } @@ -161,11 +161,11 @@ payload(void) bdf = bdf_tbl_ptr->device[tbl_index].bdf; dp_type = val_pcie_device_port_type(bdf); if ((dp_type != RCiEP) && (dp_type != iEP_EP) && (dp_type != iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x not an RCiEP/iEP device", bdf); + val_print(DEBUG, "\n BDF - 0x%x not an RCiEP/iEP device", bdf); continue; } - val_print(ACS_PRINT_DEBUG, "\n RCiEP/iEP BDF - 0x%x ", bdf); + val_print(DEBUG, "\n RCiEP/iEP BDF - 0x%x ", bdf); /* Get rc index of RCiEP/iEP in IOVIRT mapping*/ rc_index = val_iovirt_get_rc_index(PCIE_EXTRACT_BDF_SEG(bdf)); @@ -185,8 +185,8 @@ payload(void) /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); - val_print(ACS_PRINT_DEBUG, "\n rc_index - 0x%x", rc_index); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n rc_index - 0x%x", rc_index); /* Get SMMU node index for this exerciser instance */ master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf), @@ -218,14 +218,14 @@ payload(void) /* Need to know input and output address sizes before creating page table */ pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index); if (pgt_desc.ias == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Input address size of SMMU %d is 0", master.smmu_index); goto test_fail; } pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index); if (pgt_desc.oas == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Output address size of SMMU %d is 0", master.smmu_index); goto test_fail; } @@ -234,8 +234,8 @@ payload(void) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, - "\n Unable to create page table with given attributes", 0); + val_print(ERROR, + "\n Unable to create page table with given attributes"); goto test_fail; } @@ -245,7 +245,7 @@ payload(void) for VA to PA translations */ if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } @@ -258,7 +258,7 @@ payload(void) write_test_data(dram_buf_in_virt, dma_len); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -266,7 +266,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -274,7 +274,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); if (val_memory_compare(dram_buf_in_virt, dram_buf_out_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } @@ -282,7 +282,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RCiEP/iEP type devicefound, Skipping the test", 0); + val_print(DEBUG, "\n No RCiEP/iEP type devicefound, Skipping the test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); goto test_clean; } diff --git a/test_pool/exerciser/e020.c b/test_pool/exerciser/e020.c index 90cc4e7e..8608ef7d 100644 --- a/test_pool/exerciser/e020.c +++ b/test_pool/exerciser/e020.c @@ -112,7 +112,7 @@ payload(void) */ pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { - val_print(ACS_PRINT_ERR, "\n mem alloc failure", 0); + val_print(ERROR, "\n mem alloc failure"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -122,7 +122,7 @@ payload(void) /* Allocate a buffer to perform DMA tests on */ dram_buf_in_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES); if (!dram_buf_in_virt) { - val_print(ACS_PRINT_ERR, "\n Cacheable mem alloc failure", 0); + val_print(ERROR, "\n Cacheable mem alloc failure"); val_memory_free_aligned(pgt_base_array); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; @@ -137,13 +137,13 @@ payload(void) /* Get translation attributes via TCR and translation table base via TTBR */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { - val_print(ACS_PRINT_ERR, "\n TCR read failure", 0); + val_print(ERROR, "\n TCR read failure"); goto test_fail; } if (val_pe_reg_read_ttbr(0 /*for TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n TTBR0 read failure", 0); + val_print(ERROR, "\n TTBR0 read failure"); goto test_fail; } @@ -157,11 +157,11 @@ payload(void) bdf = bdf_tbl_ptr->device[tbl_index].bdf; dp_type = val_pcie_device_port_type(bdf); if ((dp_type != RCiEP) && (dp_type != iEP_EP) && (dp_type != iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x not an RCiEP/iEP device", bdf); + val_print(DEBUG, "\n BDF - 0x%x not an RCiEP/iEP device", bdf); continue; } - val_print(ACS_PRINT_DEBUG, "\n RCiEP/iEP BDF - 0x%x ", bdf); + val_print(DEBUG, "\n RCiEP/iEP BDF - 0x%x ", bdf); /* Get rc index of RCiEP in IOVIRT mapping*/ dev_rc_index = val_iovirt_get_rc_index(PCIE_EXTRACT_BDF_SEG(bdf)); @@ -181,7 +181,7 @@ payload(void) /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* If ATS Capability Not Present, Skip. */ if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) @@ -192,8 +192,8 @@ payload(void) if (rc_index == ACS_INVALID_INDEX) continue; - val_print(ACS_PRINT_INFO, "\n rc_index - 0x%x", rc_index); - val_print(ACS_PRINT_INFO, "\n dev_rc_index - 0x%x", dev_rc_index); + val_print(TRACE, "\n rc_index - 0x%x", rc_index); + val_print(TRACE, "\n dev_rc_index - 0x%x", dev_rc_index); /* Continue further only if RC supports ATS - this is not standard but information * based on the SOC design */ if (!val_iovirt_get_pcie_rc_info(RC_ATS_ATTRIBUTE, rc_index)) @@ -211,7 +211,7 @@ payload(void) * our own page table later. */ if (val_pgt_get_attributes(pgt_desc, (uint64_t)dram_buf_in_virt, &mem_desc->attributes)) { - val_print(ACS_PRINT_ERR, "\n Unable to get memory attributes of the test buffer", 0); + val_print(ERROR, "\n Unable to get memory attributes of the test buffer"); goto test_fail; } @@ -244,14 +244,14 @@ payload(void) /* Need to know input and output address sizes before creating page table */ pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index); if ((pgt_desc.ias) == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Input address size of SMMU %d is 0", master.smmu_index); goto test_fail; } pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index); if ((pgt_desc.oas) == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Output address size of SMMU %d is 0", master.smmu_index); goto test_fail; } @@ -260,8 +260,8 @@ payload(void) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, - "\n Unable to create page table with given attributes", 0); + val_print(ERROR, + "\n Unable to create page table with given attributes"); goto test_fail; } @@ -271,7 +271,7 @@ payload(void) for VA to PA translations*/ if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, "\n SMMU mapping failed (%x) ", e_bdf); + val_print(ERROR, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } @@ -287,20 +287,20 @@ payload(void) /* Send an ATS Translation Request for the VA */ if (val_exerciser_ops(ATS_TXN_REQ, (uint64_t)dram_buf_in_virt + instance * test_data_blk_size, instance)) { - val_print(ACS_PRINT_ERR, "\n ATS Translation Req Failed exerciser %4x", instance); + val_print(ERROR, "\n ATS Translation Req Failed exerciser %4x", instance); goto test_fail; } /* Get ATS Translation Response */ m_vir_addr = (uint64_t)dram_buf_in_virt + instance * test_data_blk_size; if (val_exerciser_get_param(ATS_RES_ATTRIBUTES, &translated_addr, &m_vir_addr, instance)) { - val_print(ACS_PRINT_ERR, "\n ATS Response failure %4x", instance); + val_print(ERROR, "\n ATS Response failure %4x", instance); goto test_fail; } /* Compare Translated Addr with Physical Address from the Mappings */ if (translated_addr != dram_buf_in_phys) { - val_print(ACS_PRINT_ERR, "\n ATS Translation failure %4x", instance); + val_print(ERROR, "\n ATS Translation failure %4x", instance); goto test_fail; } @@ -311,7 +311,7 @@ payload(void) val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_ADDR_TYPE, AT_TRANSLATED, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_phys, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -319,7 +319,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -327,7 +327,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); if (val_memory_compare(dram_buf_in_virt, dram_buf_out_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } diff --git a/test_pool/exerciser/e021.c b/test_pool/exerciser/e021.c index 89d0954a..5e7691c8 100644 --- a/test_pool/exerciser/e021.c +++ b/test_pool/exerciser/e021.c @@ -60,14 +60,14 @@ static uint32_t test_sequence_check(uint32_t instance) for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { val_exerciser_get_param(TRANSACTION_TYPE, &idx, &transaction_type, instance); if (transaction_type != transaction_order[idx]) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d arrival order check failed", instance); + val_print(ERROR, "\n Exerciser %d arrival order check failed", instance); return 1; } } /* Get number of transactions captured from exerciser */ if (num_transactions != idx) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d gathering check failed", instance); + val_print(ERROR, "\n Exerciser %d gathering check failed", instance); return 1; } @@ -88,7 +88,7 @@ static uint32_t test_sequence_1B(uint8_t *addr, uint8_t increment_addr, uint32_t /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -129,7 +129,7 @@ static uint32_t test_sequence_2B(uint16_t *addr, uint8_t increment_addr, uint32_ /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -168,7 +168,7 @@ static uint32_t test_sequence_4B(uint32_t *addr, uint8_t increment_addr, uint32_ /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -208,7 +208,7 @@ static uint32_t test_sequence_8B(uint64_t *addr, uint8_t increment_addr, uint32_ /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -297,7 +297,7 @@ cfgspace_transactions_order_check(void) if ((dp_type != RCiEP) && (dp_type != iEP_EP)) continue; - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", bdf); /* If exerciser doesn't have PCI_CAP skip the bdf */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cid_offset) == PCIE_CAP_NOT_FOUND) @@ -315,8 +315,8 @@ cfgspace_transactions_order_check(void) } if (status) { - val_print(ACS_PRINT_DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); + val_print(DEBUG, " Status :0x%x", status); continue; } @@ -329,8 +329,8 @@ cfgspace_transactions_order_check(void) status = val_memory_ioremap((void *)bdf_addr, 512, DEVICE_nGnRE, (void **)&baseptr); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(DEBUG, "\n Failed in config ioremap for instance 0x%x", instance); + val_print(DEBUG, " Status :0x%x", status); continue; } @@ -375,10 +375,10 @@ barspace_transactions_order_check(void) /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); continue; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + val_print(ERROR, "\n Exerciser %d data read error ", instance); continue; } @@ -397,8 +397,8 @@ barspace_transactions_order_check(void) } if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); - val_print(ACS_PRINT_ERR, " Status :0x%x", status); + val_print(ERROR, "\n Failed in BAR ioremap for instance %x", instance); + val_print(ERROR, " Status :0x%x", status); continue; } @@ -409,8 +409,8 @@ barspace_transactions_order_check(void) status = val_memory_ioremap((void *)e_data.bar_space.base_addr, 512, DEVICE_nGnRE, (void **)&baseptr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); - val_print(ACS_PRINT_ERR, " Status :0x%x", status); + val_print(ERROR, "\n Failed in BAR ioremap for instance %x", instance); + val_print(ERROR, " Status :0x%x", status); continue; } diff --git a/test_pool/exerciser/e022.c b/test_pool/exerciser/e022.c index 003db223..4ec25e24 100644 --- a/test_pool/exerciser/e022.c +++ b/test_pool/exerciser/e022.c @@ -40,7 +40,7 @@ static uint32_t test_sequence_check(uint32_t instance, uint64_t write_value) for (idx = 0; idx < transaction_size; idx++) { val_exerciser_get_param(DATA_ATTRIBUTES, &transaction_data, &idx, instance); if (transaction_data != write_value) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d arrival order check failed", instance); + val_print(ERROR, "\n Exerciser %d arrival order check failed", instance); return 1; } } @@ -59,7 +59,7 @@ static uint32_t test_sequence_2B(uint16_t *addr, uint32_t instance) /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -90,7 +90,7 @@ static uint32_t test_sequence_4B(uint32_t *addr, uint32_t instance) /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -120,7 +120,7 @@ static uint32_t test_sequence_8B(uint64_t *addr, uint32_t instance) /* Start monitoring exerciser transactions */ if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Exerciser BDF 0x%x - Unable to start transaction monitoring", e_bdf); return ACS_STATUS_SKIP; } @@ -173,17 +173,17 @@ barspace_transactions_order_check(void) /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); continue; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + val_print(ERROR, "\n Exerciser %d data read error ", instance); continue; } /* Map mmio space to ARM device memory in MMU page tables */ baseptr = (char *)e_data.bar_space.base_addr; if (!baseptr) { - val_print(ACS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); + val_print(ERROR, "\n Failed in BAR ioremap for instance %x", instance); continue; } diff --git a/test_pool/exerciser/e023.c b/test_pool/exerciser/e023.c index b7626f37..97bfaf68 100644 --- a/test_pool/exerciser/e023.c +++ b/test_pool/exerciser/e023.c @@ -46,7 +46,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id); + val_print(TRACE, "\n Received MSI interrupt %x ", lpi_int_id); val_gic_end_of_interrupt(lpi_int_id); return; } @@ -89,7 +89,7 @@ correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_cod val_pcie_read_cfg(e_bdf, aer_offset + AER_CORR_STATUS_OFFSET, &value); if (!((value >> err_bit) & 0x1)) { - val_print(ACS_PRINT_ERR, "\n Err bit for error not set", 0); + val_print(ERROR, "\n Err bit for error not set"); fail_cnt++; } @@ -97,13 +97,13 @@ correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_cod val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); if ((mask_value == 0) && ((value & 0x1) == 0)) { - val_print(ACS_PRINT_ERR, "\n Root error status not set", 0); + val_print(ERROR, "\n Root error status not set"); fail_cnt++; } if ((mask_value == 1) && ((value & 0x1) == 1)) { - val_print(ACS_PRINT_ERR, "\n Root error status set when error is masked", 0); + val_print(ERROR, "\n Root error status set when error is masked"); fail_cnt++; } @@ -112,7 +112,7 @@ correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_cod reg_bdf = PCIE_CREATE_BDF_PACKED(e_bdf); if ((mask_value == 0) && ((value & AER_SOURCE_ID_MASK) != reg_bdf)) { - val_print(ACS_PRINT_ERR, "\n Error source Identification failed", 0); + val_print(ERROR, "\n Error source Identification failed"); fail_cnt++; } @@ -121,7 +121,7 @@ correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_cod val_pcie_read_cfg(e_bdf, pciecs_base + DCTLR_OFFSET, ®_value); if (!((reg_value >> DSTS_SHIFT) & 0x1)) { - val_print(ACS_PRINT_ERR, "\n Device reg of EP not set %x ", reg_value); + val_print(ERROR, "\n Device reg of EP not set %x ", reg_value); fail_cnt++; } @@ -130,7 +130,7 @@ correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_cod val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); if ((value & 0x1)) { - val_print(ACS_PRINT_ERR, "\n Err bit is not cleared %x ", value); + val_print(ERROR, "\n Err bit is not cleared %x ", value); fail_cnt++; } @@ -156,7 +156,7 @@ uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) val_pcie_read_cfg(e_bdf, aer_offset + AER_UNCORR_STATUS_OFFSET, &value); if (!((value >> err_bit) & 0x1)) { - val_print(ACS_PRINT_ERR, "\n Err bit not set %x", value); + val_print(ERROR, "\n Err bit not set %x", value); fail_cnt++; } @@ -164,13 +164,13 @@ uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); if ((mask_value == 0) && ((value & 0x4) == 0)) { - val_print(ACS_PRINT_ERR, "\n Root Error status not set", 0); + val_print(ERROR, "\n Root Error status not set"); fail_cnt++; } if ((mask_value == 1) && ((value & 0x4) == 0x4)) { - val_print(ACS_PRINT_ERR, "\n Root error status set when error is masked", 0); + val_print(ERROR, "\n Root error status set when error is masked"); fail_cnt++; } @@ -179,7 +179,7 @@ uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) reg_bdf = PCIE_CREATE_BDF_PACKED(e_bdf); if ((mask_value == 0) && (((value >> AER_SOURCE_ID_SHIFT) & AER_SOURCE_ID_MASK) != reg_bdf)) { - val_print(ACS_PRINT_ERR, "\n Error source Identification failed", 0); + val_print(ERROR, "\n Error source Identification failed"); fail_cnt++; } @@ -188,7 +188,7 @@ uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) val_pcie_read_cfg(e_bdf, pciecs_base + DCTLR_OFFSET, ®_value); if (!((reg_value >> DSTS_SHIFT) & DS_UNCORR_MASK)) { - val_print(ACS_PRINT_ERR, "\n Device reg of EP not set", 0); + val_print(ERROR, "\n Device reg of EP not set"); fail_cnt++; } @@ -197,7 +197,7 @@ uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); if ((value & 0x7F)) { - val_print(ACS_PRINT_ERR, "\n Err bit is not cleared %x", value); + val_print(ERROR, "\n Err bit is not cleared %x", value); fail_cnt++; } @@ -235,7 +235,7 @@ inject_error(uint32_t e_bdf, uint32_t instance, uint32_t aer_offset) if (timeout == 0) { val_gic_free_irq(irq_pending, 0); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr not trigerred on err injection bdf 0x%x", e_bdf); return 1; } @@ -244,20 +244,20 @@ inject_error(uint32_t e_bdf, uint32_t instance, uint32_t aer_offset) /* Check if error injected is correctable or uncorrectable*/ if (status == ERR_CORR) { - val_print(ACS_PRINT_INFO, "\n Correctable error recieved", 0); + val_print(TRACE, "\n Correctable error recieved"); res = correctable_err_status_chk(e_bdf, aer_offset, value); if (res) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Correctable error check failed for bdf %x", e_bdf); return 1; } } else if (status == ERR_UNCORR) { - val_print(ACS_PRINT_INFO, "\n UnCorrectable error recieved", 0); + val_print(TRACE, "\n UnCorrectable error recieved"); res = uncorrectable_error_chk(e_bdf, aer_offset, value); if (res) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Uncorrectable error check failed for bdf %x", e_bdf); return 1; } @@ -301,7 +301,7 @@ payload(void) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); if (val_pcie_get_rootport(e_bdf, &erp_bdf)) @@ -312,12 +312,12 @@ payload(void) /*Check AER capability for exerciser and its RP */ if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_AER, &aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n No AER Capability, Skipping for Bdf : 0x%x", e_bdf); + val_print(ERROR, "\n No AER Capability, Skipping for Bdf : 0x%x", e_bdf); continue; } if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); + val_print(ERROR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -326,7 +326,7 @@ payload(void) status = val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, "\n ECID_DPC not found", 0); + val_print(ERROR, "\n ECID_DPC not found"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -334,17 +334,17 @@ payload(void) /* Warn if DPC enabled */ val_pcie_read_cfg(erp_bdf, dpc_cap_base + DPC_CTRL_OFFSET, ®_value); if ((reg_value & 0x3) != 0) - val_print(ACS_PRINT_WARN, "\n DPC enabled for bdf : 0x%x", erp_bdf); + val_print(WARN, "\n DPC enabled for bdf : 0x%x", erp_bdf); /* Search for MSI-X/MSI Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI-X Capability for Bdf 0x%x", e_bdf); + val_print(DEBUG, "\n No MSI-X Capability for Bdf 0x%x", e_bdf); } if ((val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI/MSI-X Capability for RP Bdf 0x%x", erp_bdf); + val_print(DEBUG, "\n No MSI/MSI-X Capability for RP Bdf 0x%x", erp_bdf); goto err_check; } @@ -355,7 +355,7 @@ payload(void) &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); + val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -363,7 +363,7 @@ payload(void) /* MSI assignment */ status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -371,7 +371,7 @@ payload(void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, "\n Intr handler registration failed: 0x%x", lpi_int_id); + val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } diff --git a/test_pool/exerciser/e024.c b/test_pool/exerciser/e024.c index c5adac34..3c12dafc 100644 --- a/test_pool/exerciser/e024.c +++ b/test_pool/exerciser/e024.c @@ -48,7 +48,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id); + val_print(TRACE, "\n Received MSI interrupt %x ", lpi_int_id); val_gic_end_of_interrupt(lpi_int_id); return; } @@ -100,10 +100,10 @@ save_config_space(uint32_t rp_bdf) pcie_device_bdf_table *bdf_tbl_ptr; bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if (bdf_tbl_ptr->num_entries > MAX_DEVICES) { - val_print(ACS_PRINT_WARN, "\n WARNING: Memory is allocated only for %d devices", MAX_DEVICES); - val_print(ACS_PRINT_WARN, "\n The number of PCIe devices is %d", bdf_tbl_ptr->num_entries); - val_print(ACS_PRINT_WARN, "\n for which the additional memory is not allocated", 0); - val_print(ACS_PRINT_WARN, "\n and test may fail\n", 0); + val_print(WARN, "\n WARNING: Memory is allocated only for %d devices", MAX_DEVICES); + val_print(WARN, "\n The number of PCIe devices is %d", bdf_tbl_ptr->num_entries); + val_print(WARN, "\n for which the additional memory is not allocated"); + val_print(WARN, "\n and test may fail\n"); } while (tbl_index < bdf_tbl_ptr->num_entries) @@ -123,7 +123,7 @@ save_config_space(uint32_t rp_bdf) cfg_space_buf[tbl_index] = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE); if (cfg_space_buf[tbl_index] == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed.", 0); + val_print(ERROR, "\n Memory allocation failed."); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return 1; } @@ -176,7 +176,7 @@ payload(void) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); @@ -188,25 +188,25 @@ payload(void) status = val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_DPC, &rp_dpc_cap_base); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, "\n ECID_DPC not found", 0); + val_print(ERROR, "\n ECID_DPC not found"); continue; } /* Check AER capability for both exerciser and RP */ if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_AER, &aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported, Bdf : 0x%x", e_bdf); + val_print(ERROR, "\n AER Capability not supported, Bdf : 0x%x", e_bdf); continue; } if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); + val_print(ERROR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); fail_cnt++; } /* Search for MSI/MSI-X Capability */ if ((val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_ERR, "\n No MSI/MSI-X Capability for Bdf 0x%x", erp_bdf); + val_print(ERROR, "\n No MSI/MSI-X Capability for Bdf 0x%x", erp_bdf); goto err_check; } @@ -217,7 +217,7 @@ payload(void) &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); + val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -225,7 +225,7 @@ payload(void) /* Get DeviceID & ITS_ID for this device */ status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -233,7 +233,7 @@ payload(void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, "\n Intr handler registration failed: 0x%x", lpi_int_id); + val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -241,7 +241,7 @@ payload(void) err_check: status = val_exerciser_set_param(ERROR_INJECT_TYPE, UNCORR_CMPT_TO, 1, instance); if (status != ERR_UNCORR) { - val_print(ACS_PRINT_ERR, "\n Error Injection failed, Bdf : 0x%x", e_bdf); + val_print(ERROR, "\n Error Injection failed, Bdf : 0x%x", e_bdf); continue; } @@ -255,7 +255,7 @@ payload(void) /* Save the config space of all the devices connected to the RP to restore after Secondary Bus Reset (SBR)*/ save_config_space(erp_bdf); - val_print(ACS_PRINT_INFO, " EP BDF : 0x%x\n", e_bdf); + val_print(TRACE, " EP BDF : 0x%x\n", e_bdf); irq_pending = 1; /* Enable DPC */ @@ -284,7 +284,7 @@ payload(void) val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); if (reg_value != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n EP not contained due to DPC", 0); + val_print(ERROR, "\n EP not contained due to DPC"); fail_cnt++; } @@ -293,7 +293,7 @@ payload(void) /* Check DPC Trigger status */ if ((reg_value & 1) == 0) { - val_print(ACS_PRINT_ERR, "\n DPC Trigger status bit not set %x", reg_value); + val_print(ERROR, "\n DPC Trigger status bit not set %x", reg_value); fail_cnt++; } @@ -302,13 +302,13 @@ payload(void) { if (dpc_trigger_reason != 2) { - val_print(ACS_PRINT_ERR, "\n DPC Trigger reason incorrect", 0); + val_print(ERROR, "\n DPC Trigger reason incorrect"); fail_cnt++; } } else { if (dpc_trigger_reason != 1) { - val_print(ACS_PRINT_ERR, "\n DPC Trigger reason incorrect", 0); + val_print(ERROR, "\n DPC Trigger reason incorrect"); fail_cnt++; } } @@ -317,7 +317,7 @@ payload(void) error_source_id = (reg_value >> DPC_SOURCE_ID_SHIFT); if (source_id != error_source_id) { - val_print(ACS_PRINT_ERR, "\n DPC Error source Identification failed", 0); + val_print(ERROR, "\n DPC Error source Identification failed"); fail_cnt++; } @@ -329,7 +329,7 @@ payload(void) if (timeout == 0) { val_gic_free_irq(irq_pending, 0); - val_print(ACS_PRINT_ERR, "\n Interrupt trigger failed for bdf 0x%x", e_bdf); + val_print(ERROR, "\n Interrupt trigger failed for bdf 0x%x", e_bdf); fail_cnt++; goto disable_dpc; } @@ -364,7 +364,7 @@ payload(void) uint32_t delay_status = val_time_delay_ms(100 * ONE_MILLISECOND); if (!delay_status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", erp_bdf); val_memory_free_aligned(cfg_space_buf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); @@ -377,7 +377,7 @@ payload(void) if (status == PCIE_DLL_LINK_STATUS_NOT_ACTIVE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n The link not active after reset for BDF 0x%x: ", erp_bdf); return ; } @@ -399,7 +399,7 @@ payload(void) val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); if (reg_value == PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n EP not recovered from DPC %x", e_bdf); + val_print(ERROR, "\n EP not recovered from DPC %x", e_bdf); fail_cnt++; } diff --git a/test_pool/exerciser/e025.c b/test_pool/exerciser/e025.c index 90e24a96..8a0ee080 100644 --- a/test_pool/exerciser/e025.c +++ b/test_pool/exerciser/e025.c @@ -67,7 +67,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); goto clean_fail; } @@ -75,7 +75,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index); if (status) { - val_print(ACS_PRINT_ERR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); + val_print(ERROR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); goto clean_fail; } @@ -124,7 +124,7 @@ check_sequence(uint64_t dma_addr, uint32_t tgt_instance, uint32_t req_instance, status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, tgt_instance); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, "\n Transaction Monitoring capability not found", 0); + val_print(ERROR, "\n Transaction Monitoring capability not found"); return 1; } @@ -135,7 +135,7 @@ check_sequence(uint64_t dma_addr, uint32_t tgt_instance, uint32_t req_instance, status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, tgt_instance); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, "\n Transaction Monitoring capability not found", 0); + val_print(ERROR, "\n Transaction Monitoring capability not found"); return 1; } @@ -143,9 +143,9 @@ check_sequence(uint64_t dma_addr, uint32_t tgt_instance, uint32_t req_instance, val_exerciser_get_param(DATA_ATTRIBUTES, &transaction_data, &idx, tgt_instance); if (val_memory_compare(&transaction_data, (void *)dma_addr, size)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Data mismatch for target exerciser instance: %x", tgt_instance); - val_print(ACS_PRINT_ERR, " with value: %x", transaction_data); + val_print(ERROR, " with value: %x", transaction_data); return 1; } @@ -186,7 +186,7 @@ payload(void) continue; req_e_bdf = val_exerciser_get_bdf(req_instance); - val_print(ACS_PRINT_DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); + val_print(DEBUG, "\n Requester exerciser BDF - 0x%x", req_e_bdf); /* Get RP of the exerciser */ if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) @@ -204,7 +204,7 @@ payload(void) status = check_sequence((uint64_t)&dma_buffer, tgt_instance, req_instance, bar_base, 2); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed for 2B transaction from exerciser: %x", req_instance); fail_cnt++; } @@ -212,7 +212,7 @@ payload(void) status = check_sequence((uint64_t)&dma_buffer, tgt_instance, req_instance, bar_base, 4); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed for 4B transaction from exerciser: %x", req_instance); fail_cnt++; } @@ -220,7 +220,7 @@ payload(void) status = check_sequence((uint64_t)&dma_buffer, tgt_instance, req_instance, bar_base, 8); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed for 8B transaction from exerciser: %x", req_instance); fail_cnt++; } diff --git a/test_pool/exerciser/e026.c b/test_pool/exerciser/e026.c index c22e320f..1ba0dee4 100644 --- a/test_pool/exerciser/e026.c +++ b/test_pool/exerciser/e026.c @@ -86,14 +86,14 @@ payload(void *arg) */ pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { - val_print(ACS_PRINT_ERR, "\n mem alloc failure for pgt_base_array", 0); + val_print(ERROR, "\n mem alloc failure for pgt_base_array"); val_set_status(pe_index, RESULT_FAIL(payload_data->test_num, 01)); return; } pgt_base = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base) { - val_print(ACS_PRINT_ERR, "\n mem alloc failure for pgt_base", 0); + val_print(ERROR, "\n mem alloc failure for pgt_base"); val_set_status(pe_index, RESULT_FAIL(payload_data->test_num, 02)); val_memory_free_aligned(pgt_base_array); return; @@ -113,7 +113,7 @@ payload(void *arg) /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exercise BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exercise BDF - 0x%x", e_bdf); /* S_PCIe_07 requires only the second part of the check, while S_PCIe_08 requires both the first and second parts. @@ -131,13 +131,13 @@ payload(void *arg) val_pcie_enable_ordering(e_bdf); val_mmio_write64((uint64_t)pgt_base_array, 0); if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)&dma_buffer, 8, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } /* Trigger DMA from input buffer to exerciser memory */ if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + val_print(ERROR, "\n DMA write failure to exerciser %4x", instance); goto test_fail; } @@ -146,13 +146,13 @@ payload(void *arg) if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)(pgt_base_array) + (uint8_t)i, 2, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } /* Trigger DMA from exerciser memory to output buffer*/ if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + val_print(ERROR, "\n DMA read failure from exerciser %4x", instance); goto test_fail; } i = i + 2; @@ -172,7 +172,7 @@ payload(void *arg) if (!payload_data->check2_only) { /* All the previous writes sent must be completed, before next transaction */ if (val_memory_compare(&test_data, pgt_base_array, 8)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } @@ -185,13 +185,13 @@ payload(void *arg) val_mmio_write64((uint64_t)pgt_base_array, 0); if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)&dma_buffer, 8, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } /* Trigger DMA from input buffer to exerciser memory */ if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + val_print(ERROR, "\n DMA write failure to exerciser %4x", instance); goto test_fail; } @@ -203,13 +203,13 @@ payload(void *arg) if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)(pgt_base_array) + (uint8_t)j, 8, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } /* Trigger DMA from exerciser memory to output buffer*/ if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + val_print(ERROR, "\n DMA read failure from exerciser %4x", instance); goto test_fail; } j = j + 2; @@ -217,7 +217,7 @@ payload(void *arg) j = 0x2; if (val_memory_compare(pgt_base, pgt_base_array, MAX_LEN)) { - val_print(ACS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } } diff --git a/test_pool/exerciser/e027.c b/test_pool/exerciser/e027.c index 09388c5a..3f90d3cd 100644 --- a/test_pool/exerciser/e027.c +++ b/test_pool/exerciser/e027.c @@ -47,7 +47,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x", lpi_int_id); + val_print(TRACE, "\n Received MSI interrupt %x", lpi_int_id); val_gic_end_of_interrupt(lpi_int_id); return; } @@ -99,10 +99,10 @@ save_config_space(uint32_t rp_bdf) pcie_device_bdf_table *bdf_tbl_ptr; bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if (bdf_tbl_ptr->num_entries > MAX_DEVICES) { - val_print(ACS_PRINT_WARN, "\n WARNING: Memory is allocated only for %d devices", MAX_DEVICES); - val_print(ACS_PRINT_WARN, "\n The number of PCIe devices is %d", bdf_tbl_ptr->num_entries); - val_print(ACS_PRINT_WARN, "\n for which the additional memory is not allocated", 0); - val_print(ACS_PRINT_WARN, "\n and test may fail\n", 0); + val_print(WARN, "\n WARNING: Memory is allocated only for %d devices", MAX_DEVICES); + val_print(WARN, "\n The number of PCIe devices is %d", bdf_tbl_ptr->num_entries); + val_print(WARN, "\n for which the additional memory is not allocated"); + val_print(WARN, "\n and test may fail\n"); } while (tbl_index < bdf_tbl_ptr->num_entries) @@ -122,7 +122,7 @@ save_config_space(uint32_t rp_bdf) cfg_space_buf[tbl_index] = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE); if (cfg_space_buf[tbl_index] == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed.", 0); + val_print(ERROR, "\n Memory allocation failed."); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return 1; } @@ -171,7 +171,7 @@ payload(void) continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); @@ -181,14 +181,14 @@ payload(void) /* Check AER capability for both exerciser and RP */ if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_AER, &aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported", 0); - val_print(ACS_PRINT_ERR, "\n Skipping for BDF : 0x%x", e_bdf); + val_print(ERROR, "\n AER Capability not supported"); + val_print(ERROR, "\n Skipping for BDF : 0x%x", e_bdf); continue; } if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported", 0); - val_print(ACS_PRINT_ERR, "\n Skipping for BDF : 0x%x", erp_bdf); + val_print(ERROR, "\n AER Capability not supported"); + val_print(ERROR, "\n Skipping for BDF : 0x%x", erp_bdf); continue; } @@ -196,8 +196,8 @@ payload(void) status = val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_DPC, &rp_dpc_cap_base); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, "\n ECID_DPC not found", 0); - val_print(ACS_PRINT_ERR, "\n Skipping for BDF : 0x%x", erp_bdf); + val_print(ERROR, "\n ECID_DPC not found"); + val_print(ERROR, "\n Skipping for BDF : 0x%x", erp_bdf); continue; } @@ -205,7 +205,7 @@ payload(void) val_exerciser_disable_rp_pio_register(erp_bdf); val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, ®_value); if ((reg_value >> DPC_RP_EXT_OFFSET) & DPC_RP_EXT_MASK) { - val_print(ACS_PRINT_ERR, "\n RP 0x%x supports RP extensions", erp_bdf); + val_print(ERROR, "\n RP 0x%x supports RP extensions", erp_bdf); continue; } @@ -215,7 +215,7 @@ payload(void) /* Search for MSI-X/MSI Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(DEBUG, "\n No MSI/MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -225,7 +225,7 @@ payload(void) &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); + val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -233,7 +233,7 @@ payload(void) /* Get DeviceID & ITS_ID for this device */ status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -241,7 +241,7 @@ payload(void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, "\n Intr handler registration failed: 0x%x", lpi_int_id); + val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -251,7 +251,7 @@ payload(void) { status = val_exerciser_set_param(ERROR_INJECT_TYPE, msg_type[i], 1, instance); if (status != ERR_UNCORR) { - val_print(ACS_PRINT_ERR, "\n Error Injection failed, Bdf : 0x%x", e_bdf); + val_print(ERROR, "\n Error Injection failed, Bdf : 0x%x", e_bdf); continue; } @@ -278,7 +278,7 @@ payload(void) val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); if (reg_value != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n EP not contained due to DPC", 0); + val_print(ERROR, "\n EP not contained due to DPC"); fail_cnt++; } @@ -287,7 +287,7 @@ payload(void) /* Check DPC Trigger status */ if ((reg_value & 1) == 0) { - val_print(ACS_PRINT_ERR, "\n DPC Trigger status bit not set %x", reg_value); + val_print(ERROR, "\n DPC Trigger status bit not set %x", reg_value); fail_cnt++; } @@ -297,7 +297,7 @@ payload(void) if (timeout == 0) { val_gic_free_irq(irq_pending, 0); - val_print(ACS_PRINT_ERR, "\n Interrupt trigger failed for bdf 0x%lx", e_bdf); + val_print(ERROR, "\n Interrupt trigger failed for bdf 0x%lx", e_bdf); fail_cnt++; continue; } @@ -328,7 +328,7 @@ payload(void) uint32_t delay_status = val_time_delay_ms(100 * ONE_MILLISECOND); if (!delay_status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", erp_bdf); val_memory_free_aligned(cfg_space_buf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); @@ -341,7 +341,7 @@ payload(void) if (status == PCIE_DLL_LINK_STATUS_NOT_ACTIVE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n The link not active after reset for BDF 0x%x: ", erp_bdf); return ; } @@ -362,7 +362,7 @@ payload(void) val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); if (reg_value == PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n EP not recovered from DPC %x", e_bdf); + val_print(ERROR, "\n EP not recovered from DPC %x", e_bdf); fail_cnt++; } } diff --git a/test_pool/exerciser/e028.c b/test_pool/exerciser/e028.c index 87d3bae4..ca23c167 100644 --- a/test_pool/exerciser/e028.c +++ b/test_pool/exerciser/e028.c @@ -55,7 +55,7 @@ payload() continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); val_pcie_enable_msa(e_bdf); @@ -74,14 +74,14 @@ payload() * Skip the RAS check if not supported */ poison_support = val_exerciser_check_poison_data_forwarding_support(); if (poison_support == 0) { - val_print(ACS_PRINT_DEBUG, "\n Poison forwarding not supported", 0); + val_print(DEBUG, "\n Poison forwarding not supported"); goto get_bar_data; } ras_node = val_exerciser_get_pcie_ras_compliant_err_node(e_bdf, erp_bdf); if (ras_node == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n No RAS compliant node to record PCIe Error", 0); - val_print(ACS_PRINT_ERR, "\n Skipping RAS check for BDF - 0x%x", e_bdf); + val_print(ERROR, "\n No RAS compliant node to record PCIe Error"); + val_print(ERROR, "\n Skipping RAS check for BDF - 0x%x", e_bdf); goto get_bar_data; } @@ -93,13 +93,13 @@ payload() /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_BAR0_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); /* Disable the Poison mode in the exerciser*/ val_exerciser_set_param(DISABLE_POISON_MODE, 0, 0, instance); continue; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error", instance); + val_print(ERROR, "\n Exerciser %d data read error", instance); /* Disable the Poison mode in the exerciser*/ val_exerciser_set_param(DISABLE_POISON_MODE, 0, 0, instance); @@ -112,12 +112,12 @@ payload() /* Read the BAR address should result in poisoned TLP being forwarded to the PE*/ bar_data = (*(volatile addr_t *)e_data.bar_space.base_addr); if (bar_data != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Memory reads not returning all 1's, BDF %x", e_bdf); + val_print(ERROR, "\n Memory reads not returning all 1's, BDF %x", e_bdf); fail_cnt++; } if (poison_support == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skippping RAS check for BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Skippping RAS check for BDF - 0x%x", e_bdf); /* Disable the Poison mode in the exerciser*/ val_exerciser_set_param(DISABLE_POISON_MODE, 0, 0, instance); @@ -127,7 +127,7 @@ payload() /* Get the RAS Error Status register value of the RAS node implemented*/ data = val_exerciser_get_ras_status(ras_node, e_bdf, erp_bdf); if (data == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n Couldn't read ERR STATUS reg for node %x", ras_node); + val_print(ERROR, "\n Couldn't read ERR STATUS reg for node %x", ras_node); fail_cnt++; /* Disable the Poison mode in the exerciser*/ @@ -137,31 +137,31 @@ payload() /* SERR code to be 0x19 for PCIe error */ if ((data & SERR_MASK) != 0x19) { - val_print(ACS_PRINT_ERR, "\n SERR bits did not record PCIe error, bdf %x", e_bdf); + val_print(ERROR, "\n SERR bits did not record PCIe error, bdf %x", e_bdf); fail_cnt++; } /* PN bit to be set if Poisoned value is detected */ if (!((data >> PN_SHIFT) & PN_MASK)) { - val_print(ACS_PRINT_ERR, "\n Poisoned(PN) bit not set, bdf %x", e_bdf); + val_print(ERROR, "\n Poisoned(PN) bit not set, bdf %x", e_bdf); fail_cnt++; } /* UE and ER bit to be set indicating Error is undeferred and reported */ if (((data >> UE_ER_SHIFT) & UE_ER_MASK) != 0x3) { - val_print(ACS_PRINT_ERR, "\n ER and UE bit not set, bdf %x", e_bdf); + val_print(ERROR, "\n ER and UE bit not set, bdf %x", e_bdf); fail_cnt++; } /* UET bit to be 0x3 for PCIe error Uncorrected error, Signaled or Recoverable error*/ if (((data >> UET_SHIFT) & UET_MASK) != 0x3) { - val_print(ACS_PRINT_ERR, "\n UET error not received, bdf %x", e_bdf); + val_print(ERROR, "\n UET error not received, bdf %x", e_bdf); fail_cnt++; } /* DE to be 0 indicating that no errors was deferred*/ if ((data >> DE_SHIFT) & DE_MASK) { - val_print(ACS_PRINT_ERR, "\n DE bit must not be set, bdf %x", e_bdf); + val_print(ERROR, "\n DE bit must not be set, bdf %x", e_bdf); fail_cnt++; } diff --git a/test_pool/exerciser/e029.c b/test_pool/exerciser/e029.c index 2e79cab2..70ef3791 100644 --- a/test_pool/exerciser/e029.c +++ b/test_pool/exerciser/e029.c @@ -38,7 +38,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_DEBUG, "\n Received exception of type: %d", interrupt_type); + val_print(DEBUG, "\n Received exception of type: %d", interrupt_type); exception = 1; } @@ -69,7 +69,7 @@ payload() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -83,7 +83,7 @@ payload() continue; e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); @@ -94,16 +94,16 @@ payload() status = val_exerciser_set_bar_response(instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_DEBUG, "\n System doesn't trigger an external abort", 0); - val_print(ACS_PRINT_DEBUG, "\n Skipping for bdf %x", e_bdf); + val_print(DEBUG, "\n System doesn't trigger an external abort"); + val_print(DEBUG, "\n Skipping for bdf %x", e_bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } ras_node = val_exerciser_get_pcie_ras_compliant_err_node(e_bdf, erp_bdf); if (ras_node == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_DEBUG, "\n No RAS compliant node to record PCIe Error", 0); - val_print(ACS_PRINT_DEBUG, "\n Skippping RAS check for BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n No RAS compliant node to record PCIe Error"); + val_print(DEBUG, "\n Skippping RAS check for BDF - 0x%x", e_bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -115,10 +115,10 @@ payload() /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_BAR0_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); continue; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error", instance); + val_print(ERROR, "\n Exerciser %d data read error", instance); continue; } @@ -140,16 +140,16 @@ payload() /* * Check if abort isn't received. */ - val_print(ACS_PRINT_DEBUG, " bar_data %x ", bar_data); + val_print(DEBUG, " bar_data %x ", bar_data); if (!(exception)) { - val_print(ACS_PRINT_ERR, "\n External Abort isnt recieved, BDF %x", e_bdf); + val_print(ERROR, "\n External Abort isnt recieved, BDF %x", e_bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); } /* Get the RAS Error Status register value of the RAS node implemented*/ data = val_exerciser_get_ras_status(ras_node, e_bdf, erp_bdf); if (data == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n Couldn't read ERR STATUS reg for node %x", ras_node); + val_print(ERROR, "\n Couldn't read ERR STATUS reg for node %x", ras_node); fail_cnt++; /* Enable memory space access to decode BAR addresses */ @@ -159,31 +159,31 @@ payload() /* SERR code to be 0x19 for PCIe error */ if ((data & SERR_MASK) != 0x19) { - val_print(ACS_PRINT_ERR, "\n SERR bits did not record PCIe error, bdf %x", e_bdf); + val_print(ERROR, "\n SERR bits did not record PCIe error, bdf %x", e_bdf); fail_cnt++; } /* PN bit to be 0 as Poisoned value is not detected */ if ((data >> PN_SHIFT) & PN_MASK) { - val_print(ACS_PRINT_ERR, "\n Poisoned(PN) bit set, bdf %x", e_bdf); + val_print(ERROR, "\n Poisoned(PN) bit set, bdf %x", e_bdf); fail_cnt++; } /* UE and ER bit to be set indicating Error is undeferred and reported */ if (((data >> UE_ER_SHIFT) & UE_ER_MASK) != 0x3) { - val_print(ACS_PRINT_ERR, "\n ER and UE bit not set, bdf %x", e_bdf); + val_print(ERROR, "\n ER and UE bit not set, bdf %x", e_bdf); fail_cnt++; } /* UET to be 3 for PCIe error Uncorrected error, Signaled or Recoverable error*/ if (((data >> UET_SHIFT) & UET_MASK) != 0x3) { - val_print(ACS_PRINT_ERR, "\n UET not received, bdf %x", e_bdf); + val_print(ERROR, "\n UET not received, bdf %x", e_bdf); fail_cnt++; } /* DE bit to be 0 indicating that no errors was deferred*/ if ((data >> DE_SHIFT) & DE_MASK) { - val_print(ACS_PRINT_ERR, "\n DE bit must not be set, bdf %x", e_bdf); + val_print(ERROR, "\n DE bit must not be set, bdf %x", e_bdf); fail_cnt++; } diff --git a/test_pool/exerciser/e030.c b/test_pool/exerciser/e030.c index a876a313..f605a2a4 100644 --- a/test_pool/exerciser/e030.c +++ b/test_pool/exerciser/e030.c @@ -63,7 +63,7 @@ payload(void) */ pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { - val_print(ACS_PRINT_ERR, "\n mem alloc failure %x", 03); + val_print(ERROR, "\n mem alloc failure %x", 03); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -72,12 +72,12 @@ payload(void) /* Get translation attributes via TCR and translation table base via TTBR */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation attributes via TCR", 0); + val_print(ERROR, "\n Unable to get translation attributes via TCR"); goto test_fail; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation table via TBBR", 0); + val_print(ERROR, "\n Unable to get translation table via TBBR"); goto test_fail; } @@ -97,7 +97,7 @@ payload(void) /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exercise BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exercise BDF - 0x%x", e_bdf); /* Get SMMU node index for this exerciser instance */ master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf), @@ -109,7 +109,7 @@ payload(void) /* DCP bit is RES0 for SMMUv3, hence check only for SMMU verion greater than 3.0 */ smmu_minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, master.smmu_index), 0, 3); if (smmu_minor == 0) { - val_print(ACS_PRINT_DEBUG, "\n SMMU version is v3.%d", smmu_minor); + val_print(DEBUG, "\n SMMU version is v3.%d", smmu_minor); continue; } @@ -124,14 +124,14 @@ payload(void) /* Need to know input and output address sizes before creating page table */ pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index); if (pgt_desc.ias == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Input address size of SMMU %d is 0", master.smmu_index); goto test_fail; } pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index); if (pgt_desc.oas == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Output address size of SMMU %d is 0", master.smmu_index); goto test_fail; } @@ -140,8 +140,8 @@ payload(void) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, - "\n Unable to create page table with given attributes", 0); + val_print(ERROR, + "\n Unable to create page table with given attributes"); goto test_fail; } @@ -151,7 +151,7 @@ payload(void) for VA to PA translations */ if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } @@ -161,7 +161,7 @@ payload(void) */ dcp_bit = val_smmu_config_ste_dcp(master, 1); if (!dcp_bit) { - val_print(ACS_PRINT_ERR, "\n STE.DCP bit not set", 0); + val_print(ERROR, "\n STE.DCP bit not set"); goto test_fail; } @@ -170,7 +170,7 @@ payload(void) */ dcp_bit = val_smmu_config_ste_dcp(master, 0); if (dcp_bit) { - val_print(ACS_PRINT_ERR, "\n STE.DCP bit set", 0); + val_print(ERROR, "\n STE.DCP bit set"); goto test_fail; } } diff --git a/test_pool/exerciser/e033.c b/test_pool/exerciser/e033.c index bdb71d0f..14c8d97f 100644 --- a/test_pool/exerciser/e033.c +++ b/test_pool/exerciser/e033.c @@ -38,7 +38,7 @@ intr_handler(void) { /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id + instance); + val_print(TRACE, "\n Received MSI interrupt %x ", lpi_int_id + instance); val_gic_end_of_interrupt(lpi_int_id + instance); return; } @@ -64,7 +64,7 @@ payload (void) index = val_pe_get_index_mpid (val_pe_get_mpid()); if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ITS, Skipping Test.\n", 0); + val_print(DEBUG, "\n No ITS, Skipping Test.\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -86,12 +86,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI-X Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_INFO, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(TRACE, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -102,7 +102,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -110,7 +110,7 @@ payload (void) status = val_gic_request_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -119,7 +119,7 @@ payload (void) status = val_gic_install_isr(lpi_int_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -130,7 +130,7 @@ payload (void) /* Get ITS Base for current ITS */ if (val_gic_its_get_base(its_id, &its_base)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; @@ -145,9 +145,9 @@ payload (void) {}; if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Interrupt trigger failed for : 0x%x, ", lpi_int_id + instance); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "BDF : 0x%x ", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); diff --git a/test_pool/exerciser/e035.c b/test_pool/exerciser/e035.c index 20fa65ce..d5f21f11 100644 --- a/test_pool/exerciser/e035.c +++ b/test_pool/exerciser/e035.c @@ -37,7 +37,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(ACS_PRINT_INFO, "\n Received MSI interrupt %x ", base_lpi_id + instance); + val_print(TRACE, "\n Received MSI interrupt %x ", base_lpi_id + instance); val_gic_end_of_interrupt(base_lpi_id + instance); return; } @@ -63,7 +63,7 @@ payload (void) index = val_pe_get_index_mpid (val_pe_get_mpid()); if (val_gic_get_info(GIC_INFO_NUM_ITS) < 2) { - val_print(ACS_PRINT_DEBUG, "\n Skipping Test as multiple ITS not available", 0); + val_print(DEBUG, "\n Skipping Test as multiple ITS not available"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -85,12 +85,12 @@ payload (void) /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Search for MSI-X Capability */ if ((val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) && (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); + val_print(DEBUG, "\n No MSI-X Capability, Skipping for 0x%x", e_bdf); continue; } @@ -99,7 +99,7 @@ payload (void) PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -108,14 +108,14 @@ payload (void) /* Get ITS Group Index for current device */ status = val_iovirt_get_its_info(ITS_GET_GRP_INDEX_FOR_ID, 0, its_id, &grp_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Invalid ITS ID, Skipping BDF 0x%x", e_bdf); + val_print(DEBUG, "\n Invalid ITS ID, Skipping BDF 0x%x", e_bdf); continue; } /* Get Number of ITS Blocks in this Group */ status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, grp_id, 0, &get_value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Invalid ITS Group, Skipping BDF 0x%x", e_bdf); + val_print(DEBUG, "\n Invalid ITS Group, Skipping BDF 0x%x", e_bdf); continue; } @@ -126,14 +126,14 @@ payload (void) /* Run for all the ITS Blocks inside current group */ status = val_iovirt_get_its_info(ITS_GET_ID_FOR_BLK_INDEX, grp_id, blk_index, &its_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Invalid ITS Index, Skipping BDF 0x%x", e_bdf); + val_print(DEBUG, "\n Invalid ITS Index, Skipping BDF 0x%x", e_bdf); continue; } - val_print(ACS_PRINT_DEBUG, "\n ITS Check for ITS ID : %x ", its_id); + val_print(DEBUG, "\n ITS Check for ITS ID : %x ", its_id); status = val_gic_request_msi(e_bdf, device_id, its_id, base_lpi_id + instance, msi_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -142,7 +142,7 @@ payload (void) status = val_gic_install_isr(base_lpi_id + instance, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Intr handler registration fail, Interrupt : 0x%x", base_lpi_id + instance); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -161,11 +161,11 @@ payload (void) /* Interrupt must not be generated */ if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Interrupt trigger failed int_id : 0x%x", base_lpi_id + instance); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n BDF : 0x%x, ", e_bdf); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "its_id : 0x%x", its_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); val_gic_free_msi(e_bdf, device_id, its_id, base_lpi_id + instance, msi_index); diff --git a/test_pool/exerciser/e036.c b/test_pool/exerciser/e036.c index 0668b82b..6cbaf103 100644 --- a/test_pool/exerciser/e036.c +++ b/test_pool/exerciser/e036.c @@ -119,7 +119,7 @@ payload(void) /* Allocate 2 test buffers, one for each pasid */ dram_buf_base_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES * 2); if (!dram_buf_base_virt) { - val_print(ACS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 2); + val_print(ERROR, "\n Cacheable mem alloc failure %x", 2); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -138,13 +138,13 @@ payload(void) /* Get translation attributes via TCR and translation table base via TTBR */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { - val_print(ACS_PRINT_ERR, "\n TCR read failure %x", 3); + val_print(ERROR, "\n TCR read failure %x", 3); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); return; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n TTBR0 read failure %x", 4); + val_print(ERROR, "\n TTBR0 read failure %x", 4); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); return; } @@ -176,7 +176,7 @@ payload(void) if ((dp_type != RCiEP) && (dp_type != iEP_EP)) continue; - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", e_bdf); /* Find SMMU node index for this pcie endpoint */ master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf), @@ -190,7 +190,7 @@ payload(void) if (smmu_ssid_bits < MIN_PASID_BITS || smmu_ssid_bits > MAX_PASID_BITS) { - val_print(ACS_PRINT_ERR, "\n SMMU substreamid support error %d", smmu_ssid_bits); + val_print(ERROR, "\n SMMU substreamid support error %d", smmu_ssid_bits); goto test_fail; } @@ -200,13 +200,13 @@ payload(void) status = val_pcie_get_max_pasid_width(e_bdf, &exerciser_ssid_bits); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n PASID extended capability not found for BDF: %x", e_bdf); continue; } else if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Error in obtaining the PASID max width for BDF: %x", e_bdf); goto test_fail; @@ -241,14 +241,14 @@ payload(void) /* Need to know input and output address sizes before creating page table */ pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index); if (pgt_desc.ias == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Input address size 0 for SMMU %d", master.smmu_index); goto test_fail; } pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index); if (pgt_desc.oas == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Output address size 0 for SMMU %d", master.smmu_index); goto test_fail; } @@ -257,8 +257,8 @@ payload(void) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, - "\n Unable to create page table with given attributes", 0); + val_print(ERROR, + "\n Unable to create page table with given attributes"); goto test_fail; } @@ -267,7 +267,7 @@ payload(void) master.substreamid = TEST_PASID1; if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, "\n SMMU mapping failed (%d) ", master.substreamid); + val_print(ERROR, "\n SMMU mapping failed (%d) ", master.substreamid); goto test_fail; } @@ -283,12 +283,12 @@ payload(void) * PASID Enable bit of the Root Port. */ if (val_exerciser_ops(PASID_TLP_START, (uint64_t)master.substreamid, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix enable error", instance); + val_print(ERROR, "\n Exerciser %x PASID TLP Prefix enable error", instance); goto test_fail; } if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -296,7 +296,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -304,12 +304,12 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); if (val_memory_compare(dram_buf_pasid1_in_virt, dram_buf_pasid1_out_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n Data Comparision failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparision failure for Exerciser %4x", instance); goto test_fail; } if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -319,7 +319,7 @@ payload(void) * in exerciser PASID Control register. */ if (val_exerciser_ops(PASID_TLP_STOP, (uint64_t)master.substreamid, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix disable error", instance); + val_print(ERROR, "\n Exerciser %x PASID TLP Prefix disable error", instance); goto test_fail; } @@ -333,8 +333,8 @@ payload(void) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, - "\n Unable to create page table with given attributes", 0); + val_print(ERROR, + "\n Unable to create page table with given attributes"); goto test_fail; } @@ -343,7 +343,7 @@ payload(void) master.substreamid = TEST_PASID2; if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, "\n SMMU mapping failed (%d) ", master.substreamid); + val_print(ERROR, "\n SMMU mapping failed (%d) ", master.substreamid); goto test_fail; } @@ -358,12 +358,12 @@ payload(void) * PASID Enable bit of the Root Port. */ if (val_exerciser_ops(PASID_TLP_START, (uint64_t)master.substreamid, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix enable error", instance); + val_print(ERROR, "\n Exerciser %x PASID TLP Prefix enable error", instance); goto test_fail; } if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -371,7 +371,7 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -379,12 +379,12 @@ payload(void) val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); if (val_exerciser_ops(PASID_TLP_STOP, (uint64_t)master.substreamid, instance)) { - val_print(ACS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix disable error", instance); + val_print(ERROR, "\n Exerciser %x PASID TLP Prefix disable error", instance); goto test_fail; } if (val_memory_compare(dram_buf_pasid2_in_virt, dram_buf_pasid2_out_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n Data Comparison failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparison failure for Exerciser %4x", instance); goto test_fail; } diff --git a/test_pool/exerciser/e039.c b/test_pool/exerciser/e039.c index 8fbf8c41..aa69cbf9 100644 --- a/test_pool/exerciser/e039.c +++ b/test_pool/exerciser/e039.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); } @@ -66,7 +66,7 @@ payload(void) branch_to_test = &&test_fail; if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -81,15 +81,15 @@ payload(void) continue; bdf = val_exerciser_get_bdf(instance); - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF - 0x%x", bdf); + val_print(DEBUG, "\n Exerciser BDF - 0x%x", bdf); /* Get BAR 0 details for this instance */ status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() for MMIO not implemented"); goto test_fail; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + val_print(ERROR, "\n Exerciser %d data read error ", instance); goto test_fail; } @@ -110,9 +110,9 @@ payload(void) } if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed in BAR ioremap for instance %x", instance); - val_print(ACS_PRINT_DEBUG, " Status :0x%x", status); + val_print(DEBUG, " Status :0x%x", status); goto test_fail; } @@ -122,7 +122,7 @@ payload(void) /* Write predefined data to an unaligned address in mmio space and read it back */ val_mmio_write((addr_t)(baseptr+3), TEST_DATA); if (TEST_DATA != val_mmio_read((addr_t)(baseptr+3))) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Exerciser BAR space access error %x", instance); goto test_fail; } @@ -134,8 +134,8 @@ payload(void) } if (test_skip) { - val_print(ACS_PRINT_DEBUG, - "\n No exerciser with prefetchable mmio space, Skipping test", 0); + val_print(DEBUG, + "\n No exerciser with prefetchable mmio space, Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } diff --git a/test_pool/exerciser/e040.c b/test_pool/exerciser/e040.c index 7dc64535..66ef8137 100644 --- a/test_pool/exerciser/e040.c +++ b/test_pool/exerciser/e040.c @@ -108,7 +108,7 @@ run_cxl_path_ats_dma(uint32_t e_bdf) dram_buf_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES); if (!dram_buf_virt) { - val_print(ACS_PRINT_ERR, "\n Cacheable mem alloc failure", 0); + val_print(ERROR, "\n Cacheable mem alloc failure"); goto test_fail; } @@ -117,7 +117,7 @@ run_cxl_path_ats_dma(uint32_t e_bdf) dram_buf_out_virt = dram_buf_virt + dma_len; if (val_pe_reg_read_tcr(0, &pgt_desc.tcr) || val_pe_reg_read_ttbr(0, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n TCR read failure", 0); + val_print(ERROR, "\n TCR read failure"); goto test_fail; } @@ -158,13 +158,13 @@ run_cxl_path_ats_dma(uint32_t e_bdf) will update pgt_desc.pgt_base to point to created translation table */ pgt_desc.pgt_base = 0; if (val_pgt_create(&mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, "\n Unable to create page table with given attributes", 0); + val_print(ERROR, "\n Unable to create page table with given attributes"); goto test_fail; } if (val_smmu_map(master, pgt_desc)) { - val_print(ACS_PRINT_ERR, "\n SMMU mapping failed (%x) ", e_bdf); + val_print(ERROR, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } smmu_mapped = 1; @@ -178,20 +178,20 @@ run_cxl_path_ats_dma(uint32_t e_bdf) /* Send an ATS Translation Request for the VA */ if (val_exerciser_ops(ATS_TXN_REQ, dram_buf_iova, instance)) { - val_print(ACS_PRINT_ERR, "\n ATS Translation Req Failed exerciser %4x", instance); + val_print(ERROR, "\n ATS Translation Req Failed exerciser %4x", instance); goto test_fail; } /* Get ATS Translation Response */ m_vir_addr = dram_buf_iova; if (val_exerciser_get_param(ATS_RES_ATTRIBUTES, &translated_addr, &m_vir_addr, instance)) { - val_print(ACS_PRINT_ERR, "\n ATS Response failure %4x", instance); + val_print(ERROR, "\n ATS Response failure %4x", instance); goto test_fail; } /* Compare Translated Addr with Physical Address from the Mappings */ if (translated_addr != dram_buf_phys) { - val_print(ACS_PRINT_ERR, "\n ATS Translation failure %4x", instance); + val_print(ERROR, "\n ATS Translation failure %4x", instance); goto test_fail; } @@ -202,7 +202,7 @@ run_cxl_path_ats_dma(uint32_t e_bdf) val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_ADDR_TYPE, AT_TRANSLATED, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_phys, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -210,7 +210,7 @@ run_cxl_path_ats_dma(uint32_t e_bdf) val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { - val_print(ACS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + val_print(ERROR, "\n DMA attributes setting failure %4x", instance); goto test_fail; } @@ -218,7 +218,7 @@ run_cxl_path_ats_dma(uint32_t e_bdf) val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); if (val_memory_compare(dram_buf_virt, dram_buf_out_virt, dma_len)) { - val_print(ACS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + val_print(ERROR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } @@ -297,14 +297,14 @@ payload(void) e_bdf = val_cxl_get_component_info(CXL_COMPONENT_INFO_BDF_INDEX, comp_idx); status = val_cxl_device_is_cxl(e_bdf); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_DEBUG, "\n No CXL Exerciser device BDF", 0); + val_print(DEBUG, "\n No CXL Exerciser device BDF"); continue; } test_skip = 1; if (run_cxl_path_ats_dma(e_bdf) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n CXL ATS+DMA functional test failed, BDF: 0x%x", e_bdf); + val_print(ERROR, "\n CXL ATS+DMA functional test failed, BDF: 0x%x", e_bdf); fail_cnt++; } } diff --git a/test_pool/exerciser/e041.c b/test_pool/exerciser/e041.c index 8916c12d..b1ce9986 100644 --- a/test_pool/exerciser/e041.c +++ b/test_pool/exerciser/e041.c @@ -79,7 +79,7 @@ cache_sequence(uint32_t instance, uint32_t e_bdf) test_data = 0xab; /* CPU writes Pattern A. Do not clean/invalidate this cache line. */ - val_print(ACS_PRINT_INFO, "\n STEP3: CPU writes Pattern A (0x%x) without cache clean", + val_print(TRACE, "\n STEP3: CPU writes Pattern A (0x%x) without cache clean", test_data); val_memory_set(target_va, TEST_SIZE, test_data); @@ -106,15 +106,15 @@ cache_sequence(uint32_t instance, uint32_t e_bdf) val_pe_cache_invalidate_range((uint64_t)dram_buf1_virt, TEST_SIZE); if (!compare_test_data(dram_buf1_virt, TEST_SIZE, test_data)) { - val_print(ACS_PRINT_ERR, "\n Exerciser did not observe Pattern A over coherent path", 0); - val_print(ACS_PRINT_ERR, "\n Expected 0x%x", test_data); - val_print(ACS_PRINT_ERR, "\n Observed first byte 0x%x", dram_buf1_virt[0]); + val_print(ERROR, "\n Exerciser did not observe Pattern A over coherent path"); + val_print(ERROR, "\n Expected 0x%x", test_data); + val_print(ERROR, "\n Observed first byte 0x%x", dram_buf1_virt[0]); val_memory_free_cacheable(e_bdf, SIZE_4KB, buf_va, buf_pa); return ACS_STATUS_FAIL; } test_data = 0xde; - val_print(ACS_PRINT_INFO, "\n Exerciser writes 0xDE CPU reads without invalidate", 0); + val_print(TRACE, "\n Exerciser writes 0xDE CPU reads without invalidate"); val_memory_set(dram_buf2_virt, TEST_SIZE, test_data); val_pe_cache_clean_invalidate_range((uint64_t)dram_buf2_virt, TEST_SIZE); @@ -138,9 +138,9 @@ cache_sequence(uint32_t instance, uint32_t e_bdf) /* CPU reads target without explicit invalidate. */ if (!compare_test_data(target_va, TEST_SIZE, test_data)) { - val_print(ACS_PRINT_ERR, "\n CPU did not observe pattern without explicit invalidate", 0); - val_print(ACS_PRINT_ERR, "\n Expected 0x%x", test_data); - val_print(ACS_PRINT_ERR, "\n Observed first byte 0x%x", target_va[0]); + val_print(ERROR, "\n CPU did not observe pattern without explicit invalidate"); + val_print(ERROR, "\n Expected 0x%x", test_data); + val_print(ERROR, "\n Observed first byte 0x%x", target_va[0]); val_memory_free_cacheable(e_bdf, SIZE_4KB, buf_va, buf_pa); return ACS_STATUS_FAIL; } @@ -180,11 +180,11 @@ payload(void) e_bdf = val_cxl_get_component_info(CXL_COMPONENT_INFO_BDF_INDEX, comp_idx); status = val_cxl_device_is_cxl(e_bdf); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_DEBUG, "\n No CXL Exerciser device BDF", 0); + val_print(DEBUG, "\n No CXL Exerciser device BDF"); continue; } if (!val_cxl_device_cache_capable(e_bdf)) { - val_print(ACS_PRINT_INFO, "CXL.cache not supported for component BDF 0x%x", e_bdf); + val_print(TRACE, "CXL.cache not supported for component BDF 0x%x", e_bdf); continue; } @@ -199,10 +199,10 @@ payload(void) if (val_exerciser_init(instance)) continue; - val_print(ACS_PRINT_DEBUG, "\n Exerciser BDF: 0x%x", e_bdf); + val_print(DEBUG, "\n Exerciser BDF: 0x%x", e_bdf); if (val_exerciser_set_param(ENABLE_CACHE_TXN, 1, 1, instance)) { - val_print(ACS_PRINT_DEBUG, "\n Enable CXL.cache Transaction from the Exerciser", 0); + val_print(DEBUG, "\n Enable CXL.cache Transaction from the Exerciser"); continue; } @@ -210,7 +210,7 @@ payload(void) test_skip = 0; status = cache_sequence(instance, e_bdf); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n CXL.cache exerciser sequence failed", 0); + val_print(ERROR, "\n CXL.cache exerciser sequence failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/exerciser/e043.c b/test_pool/exerciser/e043.c index 81c9edb6..52003e8a 100644 --- a/test_pool/exerciser/e043.c +++ b/test_pool/exerciser/e043.c @@ -41,7 +41,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); exception_observed = 1; } @@ -75,7 +75,7 @@ payload() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -93,7 +93,7 @@ payload() if (status == ACS_STATUS_ERR) continue; if (status == PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to probe CXL DVSEC for BDF 0x%x", e_bdf); fail_cnt++; continue; @@ -101,7 +101,7 @@ payload() if (status != ACS_STATUS_PASS) continue; - val_print(ACS_PRINT_INFO, "\n Exerciser BDF - 0x%x", e_bdf); + val_print(TRACE, "\n Exerciser BDF - 0x%x", e_bdf); val_pcie_enable_eru(e_bdf); val_pcie_enable_msa(e_bdf); @@ -127,7 +127,7 @@ payload() if (host_index == CXL_COMPONENT_INVALID_INDEX) continue; - val_print(ACS_PRINT_INFO, "\n host_index: %llx", host_index); + val_print(TRACE, "\n host_index: %llx", host_index); status = val_cxl_get_cfmws_window(host_index, &cfmws_base, &cfmws_size); if (status != ACS_STATUS_PASS) { val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); @@ -154,7 +154,7 @@ payload() exception_return: if (exception_observed) { - val_print(ACS_PRINT_ERR, "\n Exception obtained for CXL.mem write transaction", 0); + val_print(ERROR, "\n Exception obtained for CXL.mem write transaction"); fail_cnt++; } diff --git a/test_pool/exerciser/e044.c b/test_pool/exerciser/e044.c index 6a2a97a7..01f9d678 100644 --- a/test_pool/exerciser/e044.c +++ b/test_pool/exerciser/e044.c @@ -101,7 +101,7 @@ payload(void) continue; if (check_pm_state(e_bdf, &pm_state_before) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n PM capability missing for exerciser BDF 0x%x", e_bdf); + val_print(ERROR, "\n PM capability missing for exerciser BDF 0x%x", e_bdf); fail_cnt++; continue; } @@ -119,15 +119,15 @@ payload(void) val_time_delay_ms(1 * ONE_MILLISECOND); if (check_pm_state(e_bdf, &pm_state_after) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed to read PMCSR for exerciser BDF 0x%x", e_bdf); + val_print(ERROR, "\n Failed to read PMCSR for exerciser BDF 0x%x", e_bdf); fail_cnt++; continue; } if ((pm_state_after != PM_STATE_D3HOT) || (pm_state_after == pm_state_before)) { - val_print(ACS_PRINT_ERR, "\n PM state transition failed for BDF 0x%x", e_bdf); - val_print(ACS_PRINT_ERR, " (before 0x%x)", pm_state_before); - val_print(ACS_PRINT_ERR, " (after 0x%x)", pm_state_after); + val_print(ERROR, "\n PM state transition failed for BDF 0x%x", e_bdf); + val_print(ERROR, " (before 0x%x)", pm_state_before); + val_print(ERROR, " (after 0x%x)", pm_state_after); fail_cnt++; } } diff --git a/test_pool/exerciser/e045.c b/test_pool/exerciser/e045.c index dd51e487..89b9564c 100644 --- a/test_pool/exerciser/e045.c +++ b/test_pool/exerciser/e045.c @@ -35,7 +35,7 @@ esr(uint64_t interrupt_type, void *context) { /* Return to the test flow after handling the exception. */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); exception_observed = 1; } @@ -78,7 +78,7 @@ payload(void) status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -90,7 +90,7 @@ payload(void) } if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Firmware first handling not supported", 0); + val_print(ERROR, "\n Firmware first handling not supported"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -117,7 +117,7 @@ payload(void) status = val_exerciser_set_param(GENERATE_MEFN_VDM, 0, e_bdf, instance); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n MEFN trigger not succesful BDF 0x%x", e_bdf); + val_print(ERROR, "\n MEFN trigger not succesful BDF 0x%x", e_bdf); continue; } @@ -126,8 +126,8 @@ payload(void) exception_return: if (!exception_observed) { - val_print(ACS_PRINT_ERR, "\n MEFN trigger did not raise exception for BDF 0x%x", e_bdf); - val_print(ACS_PRINT_ERR, " RP BDF is 0x%x", rp_bdf); + val_print(ERROR, "\n MEFN trigger did not raise exception for BDF 0x%x", e_bdf); + val_print(ERROR, " RP BDF is 0x%x", rp_bdf); fail_count++; } } diff --git a/test_pool/gic/g001.c b/test_pool/gic/g001.c index 291f7322..75e95b3c 100644 --- a/test_pool/gic/g001.c +++ b/test_pool/gic/g001.c @@ -32,10 +32,10 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); gic_version = val_gic_get_info(GIC_INFO_VERSION); - val_print(ACS_PRINT_INFO, "\n Received GIC version = %4d ", gic_version); + val_print(TRACE, "\n Received GIC version = %4d ", gic_version); if (gic_version < 2) { - val_print(ACS_PRINT_ERR, "\n GIC version is %x ", gic_version); + val_print(ERROR, "\n GIC version is %x ", gic_version); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/gic/g002.c b/test_pool/gic/g002.c index edfbc80a..539897a2 100644 --- a/test_pool/gic/g002.c +++ b/test_pool/gic/g002.c @@ -43,11 +43,11 @@ payload() gic_version = val_gic_get_info(GIC_INFO_VERSION); num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); - val_print(ACS_PRINT_INFO, "\n Received GIC version = %4d ", gic_version); + val_print(TRACE, "\n Received GIC version = %4d ", gic_version); if (gic_version < 3) { if ((num_ecam > 0) && (num_msi_frame == 0)) { - val_print(ACS_PRINT_ERR, "\n GICv2 with PCIe : Invalid Configuration", 0); + val_print(ERROR, "\n GICv2 with PCIe : Invalid Configuration"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/gic/g003.c b/test_pool/gic/g003.c index 43c3201d..2413eb3c 100644 --- a/test_pool/gic/g003.c +++ b/test_pool/gic/g003.c @@ -42,7 +42,7 @@ payload() data = val_gic_get_info(GIC_INFO_NUM_ITS); if (data == 0) { - val_print(ACS_PRINT_ERR, "\n GICv3 and PCIe : ITS Not Present", 0); + val_print(ERROR, "\n GICv3 and PCIe : ITS Not Present"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -50,7 +50,7 @@ payload() data = VAL_EXTRACT_BITS(val_mmio_read(val_get_gicd_base() + GICD_TYPER), 17, 17); if (data == 0) { - val_print(ACS_PRINT_ERR, "\n GICv3 and PCIe : LPI Not Supported", 0); + val_print(ERROR, "\n GICv3 and PCIe : LPI Not Supported"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } diff --git a/test_pool/gic/g005.c b/test_pool/gic/g005.c index 0711f35c..65bbbb73 100644 --- a/test_pool/gic/g005.c +++ b/test_pool/gic/g005.c @@ -43,7 +43,7 @@ payload() uint64_t pe_rdbase; mpid = val_pe_get_mpid(); - val_print(ACS_PRINT_DEBUG, "\n PE MPIDR 0x%x", mpid); + val_print(DEBUG, "\n PE MPIDR 0x%x", mpid); index = val_pe_get_index_mpid(mpid); @@ -55,7 +55,7 @@ payload() // Distributor must forward NS Group 1 interrupt if (!enable_grp1ns) { - val_print(ACS_PRINT_ERR, "\n Non-secure SGIs not forwarded", 0); + val_print(ERROR, "\n Non-secure SGIs not forwarded"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -63,7 +63,7 @@ payload() if (are_ns) { /* Derive RDbase for PE */ pe_rdbase = val_gic_get_pe_rdbase(mpid); - val_print(ACS_PRINT_DEBUG, "\n PE RD base address %llx", pe_rdbase); + val_print(DEBUG, "\n PE RD base address %llx", pe_rdbase); if (pe_rdbase == 0) { val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -75,17 +75,17 @@ payload() This enables interrupts for the first 8 SGI lines in the GIC Redistributor */ val_mmio_write(pe_rdbase + RD_FRAME_SIZE + GICR_ISENABLER, data); data = val_mmio_read(pe_rdbase + RD_FRAME_SIZE + GICR_ISENABLER) & 0xFF; - val_print(ACS_PRINT_DEBUG, " data 0x%x", data); + val_print(DEBUG, " data 0x%x", data); data = VAL_EXTRACT_BITS(data, 0, 7); if (data == 0xFF) { val_set_status(index, RESULT_PASS(TEST_NUM, 1)); return; } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n GICR_ISENABLER0: %X\n ", data); - val_print(ACS_PRINT_ERR, - "\n INTID 0 - 7 not implemented as non-secure SGIs", 0); + val_print(ERROR, + "\n INTID 0 - 7 not implemented as non-secure SGIs"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -100,10 +100,10 @@ payload() return; } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n GICD_IENABLER: %X\n ", data); - val_print(ACS_PRINT_ERR, - "\n INTID 0 - 7 not implemented as non-secure SGIs", 0); + val_print(ERROR, + "\n INTID 0 - 7 not implemented as non-secure SGIs"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } diff --git a/test_pool/gic/g006.c b/test_pool/gic/g006.c index 7c8e2681..e530a43e 100644 --- a/test_pool/gic/g006.c +++ b/test_pool/gic/g006.c @@ -31,7 +31,7 @@ void isr_phy() { val_timer_set_phy_el1(0); - val_print(ACS_PRINT_INFO, "\n Received phy el1 interrupt ", 0); + val_print(TRACE, "\n Received phy el1 interrupt "); val_set_status(0, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(intid); } @@ -49,11 +49,11 @@ payload() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n EL0-Phy timer not mapped to PPI recommended range, INTID: %d ", intid); if (val_gic_install_isr(intid, isr_phy)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -65,7 +65,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Phy timer interrupt not received on INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; diff --git a/test_pool/gic/g007.c b/test_pool/gic/g007.c index 102a7f34..8a59068f 100644 --- a/test_pool/gic/g007.c +++ b/test_pool/gic/g007.c @@ -30,7 +30,7 @@ void isr_vir() { val_timer_set_vir_el1(0); - val_print(ACS_PRINT_INFO, "\n Received virt el1 interrupt ", 0); + val_print(TRACE, "\n Received virt el1 interrupt "); val_set_status(0, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(intid); } @@ -53,11 +53,11 @@ payload() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n EL0-Virtual timer not mapped to PPI recommended range, INTID: %d ", intid); if (val_gic_install_isr(intid, isr_vir)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -69,7 +69,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Virtual timer interrupt not received on INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; diff --git a/test_pool/gic/g008.c b/test_pool/gic/g008.c index 3bdce05c..f9a48f37 100644 --- a/test_pool/gic/g008.c +++ b/test_pool/gic/g008.c @@ -35,7 +35,7 @@ payload() intid = val_pe_get_gmain_gsiv(index); /*Recommended GIC maintenance interrupt ID is 25 as per BSA*/ if (intid != 25) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n GIC Maintenance interrupt not mapped to PPI ID 25, id %d", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -45,7 +45,7 @@ payload() intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); /*Recommended EL2 physical timer interrupt ID is 26 as per BSA*/ if (intid != 26) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI id 26, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -55,7 +55,7 @@ payload() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); /*Recommended non-secure virtual timer interrupt ID is 27 as per BSA*/ if (intid != 27) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Virtual timer not mapped to PPI ID 27, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -65,7 +65,7 @@ payload() intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0); /*Recommended EL2 virtual timer interrupt ID is 28 as per BSA*/ if (intid != 28) { - val_print(ACS_PRINT_ERR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", + val_print(ERROR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -75,7 +75,7 @@ payload() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); /*Recommended non-secure physical timer interrupt ID is 30 as per BSA*/ if (intid != 30) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Phy timer not mapped to PPI ID 30, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/gic/g009.c b/test_pool/gic/g009.c index 4251a57b..590ba467 100644 --- a/test_pool/gic/g009.c +++ b/test_pool/gic/g009.c @@ -36,7 +36,7 @@ isr_vir() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_vir_el2(0); - val_print(ACS_PRINT_INFO, "\n Received vir el2 interrupt ", 0); + val_print(TRACE, "\n Received vir el2 interrupt "); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(intid); } @@ -53,8 +53,8 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - val_print(ACS_PRINT_DEBUG, "\n Skipping. Test accesses EL2" - " Registers ", 0); + val_print(DEBUG, "\n Skipping. Test accesses EL2" + " Registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -68,7 +68,7 @@ payload() /* Check for EL2 virtual timer interrupt, if PE supports 8.1 or greater. * ID_AA64MMFR1_EL1 VH, bits [11:8] must be 0x1 */ if (!((data >> 8) & 0xF)) { - val_print(ACS_PRINT_DEBUG, "\n v8.1 VHE not supported on this PE ", 0); + val_print(DEBUG, "\n v8.1 VHE not supported on this PE "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -78,7 +78,7 @@ payload() /*Check if interrupt is in PPI INTID range*/ if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n NS EL2 virtual timer not mapped to PPI base range, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); @@ -86,7 +86,7 @@ payload() } if (val_gic_install_isr(intid, isr_vir)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -97,7 +97,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n NS EL2 Virtual timer interrupt %d not received", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } diff --git a/test_pool/gic/g010.c b/test_pool/gic/g010.c index 486d5ee4..931e65b8 100644 --- a/test_pool/gic/g010.c +++ b/test_pool/gic/g010.c @@ -36,7 +36,7 @@ isr_phy() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_phy_el2(0); - val_print(ACS_PRINT_INFO, "\n Received phy el2 interrupt ", 0); + val_print(TRACE, "\n Received phy el2 interrupt "); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(intid); } @@ -52,8 +52,8 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - val_print(ACS_PRINT_DEBUG, "\n Skipping. Test accesses EL2" - " Registers ", 0); + val_print(DEBUG, "\n Skipping. Test accesses EL2" + " Registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -65,14 +65,14 @@ payload() /*Check if interrupt is in PPI INTID range*/ if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI base range, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } if (val_gic_install_isr(intid, isr_phy)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -83,7 +83,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL2-Phy timer interrupt not received on INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); } diff --git a/test_pool/gic/g011.c b/test_pool/gic/g011.c index f0aef5b1..be4679a5 100644 --- a/test_pool/gic/g011.c +++ b/test_pool/gic/g011.c @@ -44,7 +44,7 @@ isr_mnt() val_gic_reg_write(ICH_HCR_EL2, data); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); - val_print(ACS_PRINT_INFO, "\n Received GIC maintenance interrupt ", 0); + val_print(TRACE, "\n Received GIC maintenance interrupt "); val_gic_end_of_interrupt(intid); } @@ -59,8 +59,8 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - val_print(ACS_PRINT_DEBUG, "\n Skipping. Test accesses EL2" - " Registers ", 0); + val_print(DEBUG, "\n Skipping. Test accesses EL2" + " Registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -72,7 +72,7 @@ payload() /*Check if interrupt is in PPI INTID range*/ if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n GIC Maintenance interrupt not mapped to PPI base range," "\n INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); @@ -80,7 +80,7 @@ payload() } if (val_gic_install_isr(intid, isr_mnt)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -96,7 +96,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt not received within timeout", 0); + val_print(ERROR, "\n Interrupt not received within timeout"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } diff --git a/test_pool/gic/g012.c b/test_pool/gic/g012.c index fd49832b..3a720905 100644 --- a/test_pool/gic/g012.c +++ b/test_pool/gic/g012.c @@ -36,10 +36,10 @@ payload(void) uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); gic_version = val_gic_get_info(GIC_INFO_VERSION); - val_print(ACS_PRINT_INFO, "\n Received GIC version = %4d ", gic_version); + val_print(TRACE, "\n Received GIC version = %4d ", gic_version); if (gic_version < 3) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n GIC version is %3x, expected GICv3 or higher version", gic_version); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); diff --git a/test_pool/gic/g013.c b/test_pool/gic/g013.c index 40f59f82..b36175e5 100644 --- a/test_pool/gic/g013.c +++ b/test_pool/gic/g013.c @@ -43,7 +43,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } @@ -52,7 +52,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } } @@ -61,7 +61,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } @@ -70,7 +70,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } @@ -79,7 +79,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } @@ -88,7 +88,7 @@ payload() if (IS_PPI_RESERVED(intid)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 06)); - val_print(ACS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); return; } diff --git a/test_pool/gic/g014.c b/test_pool/gic/g014.c index 0579a149..bdd6a1e9 100644 --- a/test_pool/gic/g014.c +++ b/test_pool/gic/g014.c @@ -40,7 +40,7 @@ static void payload(void) /* Check non-secure physical timer Private Peripheral Interrupt (PPI) assignment */ intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); if (intid != 30) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Phy timer not mapped to PPI ID 30, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -49,7 +49,7 @@ static void payload(void) /* Check non-secure virtual timer Private Peripheral Interrupt (PPI) assignment */ intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); if (intid != 27) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n EL0-Virtual timer not mapped to PPI ID 27, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; @@ -57,8 +57,8 @@ static void payload(void) // Check Exception Level ie. EL1, EL2 if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - val_print(ACS_PRINT_DEBUG, "\n Skipping. Test accesses EL2" - " Registers ", 0); + val_print(DEBUG, "\n Skipping. Test accesses EL2" + " Registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -69,7 +69,7 @@ static void payload(void) /* Check for EL2 virtual timer interrupt, if PE supports 8.1 or greater. * ID_AA64MMFR1_EL1 VH, bits [11:8] must be 0x1 */ if (!((data >> 8) & 0xF)) { - val_print(ACS_PRINT_DEBUG, "\n v8.1 VHE not supported on this PE ", 0); + val_print(DEBUG, "\n v8.1 VHE not supported on this PE "); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -79,7 +79,7 @@ static void payload(void) /*Recommended EL2 virtual timer interrupt ID is 28 as per SBSA*/ if (intid != 28) { - val_print(ACS_PRINT_ERR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", + val_print(ERROR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; @@ -90,7 +90,7 @@ static void payload(void) /*Recommended EL2 physical timer interrupt ID is 26 as per SBSA*/ if (intid != 26) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI id 26, INTID: %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; @@ -101,7 +101,7 @@ static void payload(void) /*Recommended GIC maintenance interrupt ID is 25 as per SBSA*/ if (intid != 25) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n GIC Maintenance interrupt not mapped to PPI ID 25, id %d", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; diff --git a/test_pool/gic/g015.c b/test_pool/gic/g015.c index f7f015b4..a8e85df9 100644 --- a/test_pool/gic/g015.c +++ b/test_pool/gic/g015.c @@ -37,25 +37,25 @@ payload(void) gic_version = val_gic_get_info(GIC_INFO_VERSION); - val_print(ACS_PRINT_INFO, "\n Received GIC Major version = %4d ", gic_version); + val_print(TRACE, "\n Received GIC Major version = %4d ", gic_version); /* Check the Major Version of GIC */ if (gic_version < 4) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Expected GICv4 or higher major version", gic_version); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } num_gicr_rd = val_gic_get_info(GIC_INFO_NUM_GICR_GICRD); - val_print(ACS_PRINT_INFO, "\n Redistributor count: %llx", num_gicr_rd); + val_print(TRACE, "\n Redistributor count: %llx", num_gicr_rd); for (i = 0; i < num_gicr_rd; i++) { gicrd_base = val_get_gicr_base(&gicrd_length, i); if (gicrd_base == 0) { - val_print(ACS_PRINT_INFO, "\n Invalid gicrd Base Address: %llx", gicrd_base); + val_print(TRACE, "\n Invalid gicrd Base Address: %llx", gicrd_base); continue; } @@ -64,8 +64,8 @@ payload(void) if (gicrd_rvpeid == 0x1) { - val_print(ACS_PRINT_INFO, - "\n Interrupt controller is compliant with Gicv4.1 or higher", 0); + val_print(TRACE, + "\n Interrupt controller is compliant with Gicv4.1 or higher"); val_set_status(index, RESULT_PASS(TEST_NUM, 01)); return; } diff --git a/test_pool/gic/g016.c b/test_pool/gic/g016.c index 8608ceb6..eb64f9f6 100644 --- a/test_pool/gic/g016.c +++ b/test_pool/gic/g016.c @@ -33,9 +33,9 @@ payload(void) num_non_gic = val_get_num_nongic_ctrl(); - val_print(ACS_PRINT_DEBUG, "\n Non GIC Interrupt count: %d", num_non_gic); + val_print(DEBUG, "\n Non GIC Interrupt count: %d", num_non_gic); if (num_non_gic > 0) { - val_print(ACS_PRINT_ERR, "\n Non GIC Interrupt found", 0); + val_print(ERROR, "\n Non GIC Interrupt found"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/gic/its001.c b/test_pool/gic/its001.c index 30cde8c6..aa3d2661 100644 --- a/test_pool/gic/its001.c +++ b/test_pool/gic/its001.c @@ -31,30 +31,30 @@ payload() status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status) { - val_print(ACS_PRINT_ERR, "\n ITS get group number failed ", 0); + val_print(ERROR, "\n ITS get group number failed "); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } if (!num_group) { - val_print(ACS_PRINT_DEBUG, "\n No ITS group found ", 0); + val_print(DEBUG, "\n No ITS group found "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } - val_print(ACS_PRINT_DEBUG, "\n Number of ITS groups = %d", num_group); + val_print(DEBUG, "\n Number of ITS groups = %d", num_group); for (i = 0; i < num_group; i++) { status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks); if (status) { - val_print(ACS_PRINT_ERR, "\n ITS get number of blocks failed ", 0); + val_print(ERROR, "\n ITS get number of blocks failed "); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } if (!num_blocks) { - val_print(ACS_PRINT_ERR, "\n No valid ITS Blocks found in group %d ", i); + val_print(ERROR, "\n No valid ITS Blocks found in group %d ", i); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } - val_print(ACS_PRINT_DEBUG, "\n Number of ITS Blocks = %d " + val_print(DEBUG, "\n Number of ITS Blocks = %d " " ", num_blocks); } val_set_status(index, RESULT_PASS(TEST_NUM, 1)); diff --git a/test_pool/gic/its002.c b/test_pool/gic/its002.c index 342c9b07..b87b1697 100644 --- a/test_pool/gic/its002.c +++ b/test_pool/gic/its002.c @@ -32,49 +32,49 @@ payload() status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status) { - val_print(ACS_PRINT_ERR, "\n ITS get group number failed ", 0); + val_print(ERROR, "\n ITS get group number failed "); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } if (!num_group) { - val_print(ACS_PRINT_DEBUG, "\n No ITS group found ", 0); + val_print(DEBUG, "\n No ITS group found "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } - val_print(ACS_PRINT_DEBUG, "\n Number of ITS groups = %d", num_group); + val_print(DEBUG, "\n Number of ITS groups = %d", num_group); for (i = 0; i < (num_group - 1); i++) { status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks); if (status) { - val_print(ACS_PRINT_ERR, "\n ITS get number of blocks failed ", 0); + val_print(ERROR, "\n ITS get number of blocks failed "); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } if (!num_blocks) { - val_print(ACS_PRINT_ERR, "\n No valid ITS Blocks found in group %d ", i); + val_print(ERROR, "\n No valid ITS Blocks found in group %d ", i); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } - val_print(ACS_PRINT_DEBUG, "\n ITS group index = %d", i); - val_print(ACS_PRINT_DEBUG, "\n Number of ITS Blocks = %d", num_blocks); + val_print(DEBUG, "\n ITS group index = %d", i); + val_print(DEBUG, "\n Number of ITS Blocks = %d", num_blocks); for (j = 0; j < num_blocks; j++) { status = val_iovirt_get_its_info(ITS_GET_ID_FOR_BLK_INDEX, i, j, &its_id); if (status) { - val_print(ACS_PRINT_ERR, "\n ITS get id failed ", 0); + val_print(ERROR, "\n ITS get id failed "); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } - val_print(ACS_PRINT_DEBUG, "\n ITS block index = %d " + val_print(DEBUG, "\n ITS block index = %d " " ", j); for (k = (i + 1); k < num_group; k++) { status = val_iovirt_get_its_info(ITS_GET_BLK_INDEX_FOR_ID, k, its_id, &blk_index); if (status != ACS_INVALID_INDEX) { - val_print(ACS_PRINT_ERR, "\n ITS ID (%d) repeated in multiple groups", + val_print(ERROR, "\n ITS ID (%d) repeated in multiple groups", its_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; diff --git a/test_pool/gic/its003.c b/test_pool/gic/its003.c index 9af3ffbf..10d8114d 100644 --- a/test_pool/gic/its003.c +++ b/test_pool/gic/its003.c @@ -48,13 +48,13 @@ payload() bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { - val_print(ACS_PRINT_DEBUG, "\n No entries in BDF table", 0); + val_print(DEBUG, "\n No entries in BDF table"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } if (val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0) == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU, Skipping Test", 0); + val_print(DEBUG, "\n No SMMU, Skipping Test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -62,7 +62,7 @@ payload() /* Allocate memory to store stream ID */ streamID = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!streamID) { - val_print(ACS_PRINT_DEBUG, "\n Stream ID memory allocation failed", 0); + val_print(DEBUG, "\n Stream ID memory allocation failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -70,7 +70,7 @@ payload() /* Allocate memory to store smmu_index */ smmu_index = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!smmu_index) { - val_print(ACS_PRINT_DEBUG, "\n Smmu index memory allocation failed", 0); + val_print(DEBUG, "\n Smmu index memory allocation failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -78,7 +78,7 @@ payload() /* Allocate memory to store dev_bdf */ dev_bdf = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!dev_bdf) { - val_print(ACS_PRINT_DEBUG, "\n Dev BDF memory allocation failed", 0); + val_print(DEBUG, "\n Dev BDF memory allocation failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -96,7 +96,7 @@ payload() smmu_id = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(bdf), PCIE_CREATE_BDF_PACKED(bdf)); if (smmu_id == ACS_INVALID_INDEX) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n BDF : 0x%llx Not Behind an SMMU, Skipping Device", bdf); continue; } @@ -109,7 +109,7 @@ payload() status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(bdf), &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); /* Free allocated memory before return*/ @@ -139,13 +139,13 @@ payload() for (i = 0; i < (dev_index - 1); i++) { for (j = (i + 1); j < dev_index; j++) { if ((streamID[i] == streamID[j]) && (smmu_index[i] == smmu_index[j])) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n StreamID not unique for dev bdf 0x%llx & ", dev_bdf[i]); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "0x%llx", dev_bdf[j]); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n StreamID values in order : 0x%llx & ", streamID[i]); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "0x%llx", streamID[j]); test_fail++; } diff --git a/test_pool/gic/its004.c b/test_pool/gic/its004.c index 213aa8ba..b9d14566 100644 --- a/test_pool/gic/its004.c +++ b/test_pool/gic/its004.c @@ -45,7 +45,7 @@ payload() pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { - val_print(ACS_PRINT_DEBUG, "\n No entries in BDF table", 0); + val_print(DEBUG, "\n No entries in BDF table"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -68,7 +68,7 @@ payload() seg_num, &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); + val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -77,11 +77,11 @@ payload() curr_grp_its_id = 0xFFFFFFFF; curr_smmu_id = 0xFFFFFFFF; curr_seg_num = 0xFFFFFFFF; - val_print(ACS_PRINT_INFO, "\n BDF is : 0x%x\n", bdf); + val_print(TRACE, "\n BDF is : 0x%x\n", bdf); smmu_id = val_iovirt_get_rc_smmu_index(seg_num, PCIE_CREATE_BDF_PACKED(bdf)); if (smmu_id == ACS_INVALID_INDEX) { - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n Skipping StreamID Association check, Bdf : 0x%llx Not Behind an SMMU", bdf); continue; } @@ -104,18 +104,18 @@ payload() continue; } - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Checking ReqID-StreamID-DeviceID Association, Bdf : %x", bdf); /* Check for stream_id & device_id */ if (curr_grp_sid_cons != (stream_id - req_id)) { /* StreamID Constant Base Failure */ - val_print(ACS_PRINT_ERR, "\n ReqID-StreamID Association Fail for Bdf : %x", bdf); + val_print(ERROR, "\n ReqID-StreamID Association Fail for Bdf : %x", bdf); test_fail++; } if (curr_grp_did_cons != (device_id - stream_id)) { /* DeviceID Constant Base Failure */ - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n StreamID-DeviceID Association Fail for Bdf : %x", bdf); test_fail++; } diff --git a/test_pool/gic/its005.c b/test_pool/gic/its005.c index 031f4d81..2eae2c34 100644 --- a/test_pool/gic/its005.c +++ b/test_pool/gic/its005.c @@ -45,7 +45,7 @@ payload() pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { - val_print(ACS_PRINT_DEBUG, "\n No entries in BDF table", 0); + val_print(DEBUG, "\n No entries in BDF table"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -68,7 +68,7 @@ payload() seg_num, &device_id, &stream_id, &its_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); + val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -93,12 +93,12 @@ payload() continue; } - val_print(ACS_PRINT_DEBUG, "\n Checking ReqID-DeviceID Association, Bdf : 0x%llx", bdf); + val_print(DEBUG, "\n Checking ReqID-DeviceID Association, Bdf : 0x%llx", bdf); /* No SMMU, Check only for device_id */ if (curr_grp_did_cons != (device_id - req_id)) { /* DeviceID Constant Base Failure */ - val_print(ACS_PRINT_ERR, "\n ReqID-DeviceID Association Fail for Bdf : %x", bdf); + val_print(ERROR, "\n ReqID-DeviceID Association Fail for Bdf : %x", bdf); test_fail++; } } diff --git a/test_pool/gic/v2m001.c b/test_pool/gic/v2m001.c index 678cc8f9..1e62ff8f 100644 --- a/test_pool/gic/v2m001.c +++ b/test_pool/gic/v2m001.c @@ -38,7 +38,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { - val_print(ACS_PRINT_DEBUG, "\n No MSI frame, Skipping ", 0); + val_print(DEBUG, "\n No MSI frame, Skipping "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -63,20 +63,20 @@ payload() } if (trigger_type != INTR_TRIGGER_INFO_EDGE_RISING) { - val_print(ACS_PRINT_DEBUG, "\n Error : SPI ID 0x%x Level Triggered ", spi_id); + val_print(DEBUG, "\n Error : SPI ID 0x%x Level Triggered ", spi_id); fail_cnt++; } } } if (test_skip) { - val_print(ACS_PRINT_WARN, "\n No SPI Information Found. Skipping ", 0); + val_print(WARN, "\n No SPI Information Found. Skipping "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } if (fail_cnt) { - val_print(ACS_PRINT_ERR, "\n SPI Trigger Type Check Failed", 0); + val_print(ERROR, "\n SPI Trigger Type Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } diff --git a/test_pool/gic/v2m002.c b/test_pool/gic/v2m002.c index e90159c9..de5a7a2a 100644 --- a/test_pool/gic/v2m002.c +++ b/test_pool/gic/v2m002.c @@ -37,7 +37,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { - val_print(ACS_PRINT_DEBUG, "\n No MSI frame, Skipping ", 0); + val_print(DEBUG, "\n No MSI frame, Skipping "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -56,7 +56,7 @@ payload() new_data = val_mmio_read(frame_base + GICv2m_MSI_TYPER); if (data != new_data) { fail_cnt++; - val_print(ACS_PRINT_DEBUG, "\n MSI_TYPER RO Check Failed for instance %d", instance); + val_print(DEBUG, "\n MSI_TYPER RO Check Failed for instance %d", instance); } /* Part 2 : Check SPI ID allocated is b/w 32-1020 */ @@ -65,7 +65,7 @@ payload() if ((min_spi_id < 32) || (min_spi_id + num_spi) > 1020) { fail_cnt++; - val_print(ACS_PRINT_DEBUG, "\n SPI ID Check Failed for instance %d", instance); + val_print(DEBUG, "\n SPI ID Check Failed for instance %d", instance); } /* Part 3 : GICv2m_MSI_IIDR Read Only Register */ @@ -77,13 +77,13 @@ payload() new_data = val_mmio_read(frame_base + GICv2m_MSI_IIDR); if (data != new_data) { fail_cnt++; - val_print(ACS_PRINT_DEBUG, "\n MSI_IIDR RO Check Failed for instance %d", instance); + val_print(DEBUG, "\n MSI_IIDR RO Check Failed for instance %d", instance); } } if (fail_cnt) { - val_print(ACS_PRINT_ERR, "\n MSI_TYPER Register Check Failed", 0); + val_print(ERROR, "\n MSI_TYPER Register Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/gic/v2m003.c b/test_pool/gic/v2m003.c index 823124a3..33219fa8 100644 --- a/test_pool/gic/v2m003.c +++ b/test_pool/gic/v2m003.c @@ -31,7 +31,7 @@ isr() { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_INFO, "\n Received SPI ", 0); + val_print(TRACE, "\n Received SPI "); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(int_id); @@ -52,7 +52,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { - val_print(ACS_PRINT_DEBUG, "\n No MSI frame, Skipping ", 0); + val_print(DEBUG, "\n No MSI frame, Skipping "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -67,7 +67,7 @@ payload() /* Register an interrupt handler to verify */ if (val_gic_install_isr(int_id, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -81,7 +81,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt not received within timeout", 0); + val_print(ERROR, "\n Interrupt not received within timeout"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -95,7 +95,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt not received within timeout", 0); + val_print(ERROR, "\n Interrupt not received within timeout"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/gic/v2m004.c b/test_pool/gic/v2m004.c index 2b8828bd..2f2c9e05 100644 --- a/test_pool/gic/v2m004.c +++ b/test_pool/gic/v2m004.c @@ -31,7 +31,7 @@ isr() { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_INFO, "\n Received SPI ", 0); + val_print(TRACE, "\n Received SPI "); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(int_id); @@ -54,7 +54,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { - val_print(ACS_PRINT_DEBUG, "\n No MSI frame, Skipping ", 0); + val_print(DEBUG, "\n No MSI frame, Skipping "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -69,7 +69,7 @@ payload() /* Register an interrupt handler to verify */ if (val_gic_install_isr(int_id, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -90,7 +90,7 @@ payload() /* If the Status is changed that means interrupt handler is called & test is failed. */ if (timeout != 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt generated by GICD registers", 0); + val_print(ERROR, "\n Interrupt generated by GICD registers"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -104,7 +104,7 @@ payload() } if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt not received within timeout", 0); + val_print(ERROR, "\n Interrupt not received within timeout"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/memory_map/m001.c b/test_pool/memory_map/m001.c index 789535a3..2c293bb2 100644 --- a/test_pool/memory_map/m001.c +++ b/test_pool/memory_map/m001.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received Exception of type %d", interrupt_type); + val_print(TRACE, "\n Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); } @@ -67,14 +67,13 @@ payload() /* Get the base address of unpopulated region */ status = val_memory_get_unpopulated_addr(&addr, instance); if (status == PCIE_NO_MAPPING) { - val_print(ACS_PRINT_INFO, - "\n All instances of unpopulated memory were obtained", - 0); + val_print(TRACE, + "\n All instances of unpopulated memory were obtained"); return; } if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Error in obtaining unpopulated memory for instance %d", instance); return; @@ -93,7 +92,7 @@ payload() exception_taken: /* if the access did not go to our exception handler, fail and exit */ if (IS_TEST_FAIL(val_get_status(index))) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory access check fails at address = 0x%llx ", addr); return; diff --git a/test_pool/memory_map/m002.c b/test_pool/memory_map/m002.c index 57baa703..1b177bcb 100644 --- a/test_pool/memory_map/m002.c +++ b/test_pool/memory_map/m002.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, branch_to_test); - val_print(ACS_PRINT_DEBUG, "\n Received Exception of type %d", interrupt_type); + val_print(DEBUG, "\n Received Exception of type %d", interrupt_type); } static @@ -59,8 +59,8 @@ payload() val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); if (g_el1skiptrap_mask & EL1SKIPTRAP_DEVMEM) { - val_print(ACS_PRINT_DEBUG, - "\n Skipping device memory access due to -el1skiptrap devmem", 0); + val_print(DEBUG, + "\n Skipping device memory access due to -el1skiptrap devmem"); goto normal_mem_test; } @@ -70,12 +70,12 @@ payload() /* Get the address of device memory region */ addr = val_memory_get_addr(MEM_TYPE_DEVICE, instance, &attr); if (!addr) { - val_print(ACS_PRINT_DEBUG, "\n Error in getting dev mem for" + val_print(DEBUG, "\n Error in getting dev mem for" " index %d ", instance); goto normal_mem_test; } - val_print(ACS_PRINT_DEBUG, "\n Device Mem Address : 0x%llx", addr); + val_print(DEBUG, "\n Device Mem Address : 0x%llx", addr); /* Access must not cause a deadlock */ original_value = *((volatile addr_t*)addr); *((volatile addr_t*)addr) = original_value; @@ -97,11 +97,11 @@ payload() /* Get the address of normal memory region */ addr = val_memory_get_addr((MEMORY_INFO_e)MEMORY_TYPE_NORMAL, instance, &attr); if (!addr) { - val_print(ACS_PRINT_DEBUG, "\n Error in obtaining normal memory for" + val_print(DEBUG, "\n Error in obtaining normal memory for" " instance %d", instance); return; } - val_print(ACS_PRINT_DEBUG, "\n Normal Mem Address : 0x%llx", addr); + val_print(DEBUG, "\n Normal Mem Address : 0x%llx", addr); /* Access must not cause a deadlock */ original_value = *((volatile addr_t*)addr); *((volatile addr_t*)addr) = original_value; diff --git a/test_pool/memory_map/m004.c b/test_pool/memory_map/m004.c index f8accde0..1873d68e 100644 --- a/test_pool/memory_map/m004.c +++ b/test_pool/memory_map/m004.c @@ -44,7 +44,7 @@ check_peripheral_dma_capability (void) pcie_bdf_list_t *pcie_peripherals_bdf_list = val_pcie_get_pcie_peripheral_bdf_list(); if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skip as no peripherals detected ", 0); + val_print(DEBUG, "\n Skip as no peripherals detected "); val_set_status(index, RESULT_SKIP (TEST_NUM, 1)); return; } @@ -54,7 +54,7 @@ check_peripheral_dma_capability (void) /* Fail the test if device isn't capable of DMA access */ if (!(val_pcie_is_devicedma_64bit(pcie_peripherals_bdf_list->dev_bdfs[i]) || val_pcie_is_device_behind_smmu(pcie_peripherals_bdf_list->dev_bdfs[i]))) { - val_print(ACS_PRINT_DEBUG, "\n Failed for BDF = 0x%x", + val_print(DEBUG, "\n Failed for BDF = 0x%x", pcie_peripherals_bdf_list->dev_bdfs[i]); fail_cnt++; } @@ -84,7 +84,7 @@ payload_check_dev_dma_if_behind_smmu (void) pcie_bdf_list_t *pcie_peripherals_bdf_list = val_pcie_get_pcie_peripheral_bdf_list(); if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skip as no peripherals detected ", 0); + val_print(DEBUG, "\n Skip as no peripherals detected "); val_set_status(index, RESULT_SKIP (TEST_NUM1, 1)); return; } @@ -97,7 +97,7 @@ payload_check_dev_dma_if_behind_smmu (void) device behind a SMMU */ test_run = 1; if (!(val_pcie_is_devicedma_64bit(pcie_peripherals_bdf_list->dev_bdfs[i]))) { - val_print(ACS_PRINT_DEBUG, "\n Failed for BDF = 0x%x", + val_print(DEBUG, "\n Failed for BDF = 0x%x", pcie_peripherals_bdf_list->dev_bdfs[i]); fail_cnt++; } @@ -127,7 +127,7 @@ payload_check_if_non_dma_dev_behind_smmu (void) pcie_bdf_list_t *pcie_peripherals_bdf_list = val_pcie_get_pcie_peripheral_bdf_list(); if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skip as no peripherals detected ", 0); + val_print(DEBUG, "\n Skip as no peripherals detected "); val_set_status(index, RESULT_SKIP (TEST_NUM2, 1)); return; } @@ -142,7 +142,7 @@ payload_check_if_non_dma_dev_behind_smmu (void) test_run = 1; /* Mark has fail if non DMA device not behind SMMU */ if (!(val_pcie_is_device_behind_smmu(pcie_peripherals_bdf_list->dev_bdfs[i]))) { - val_print(ACS_PRINT_DEBUG, "\n Failed for BDF = 0x%x", + val_print(DEBUG, "\n Failed for BDF = 0x%x", pcie_peripherals_bdf_list->dev_bdfs[i]); fail_cnt++; } diff --git a/test_pool/memory_map/m005.c b/test_pool/memory_map/m005.c index b4a15214..21d05ca1 100644 --- a/test_pool/memory_map/m005.c +++ b/test_pool/memory_map/m005.c @@ -45,7 +45,7 @@ static void payload_check_s2_64kb_granule_support(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 8, 11); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n EL2 not implemented, Skipping the test.", 0); + val_print(DEBUG, "\n EL2 not implemented, Skipping the test."); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -55,7 +55,7 @@ static void payload_check_s2_64kb_granule_support(void) implemented hence not checking ID_AA64MMFR0_EL1.TGran64 field.*/ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 36, 39); if (data != 0x2) { - val_print(ACS_PRINT_ERR, "\n 64KB granule not supported at stage 2.", 0); + val_print(ERROR, "\n 64KB granule not supported at stage 2."); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -77,7 +77,7 @@ static void payload_check_peripheral_addr_64kb_apart(void) peri_count = val_peripheral_get_info(NUM_ALL, 0); if (peri_count < 2) { - val_print(ACS_PRINT_DEBUG, "\n No or one peripherals reported by the system.", 0); + val_print(DEBUG, "\n No or one peripherals reported by the system."); val_set_status(pe_index, RESULT_SKIP(TEST_NUM1, 01)); return; } @@ -88,8 +88,8 @@ static void payload_check_peripheral_addr_64kb_apart(void) peri_addr1 = val_peripheral_get_info(ANY_BASE0, peri_index); peri_addr2 = val_peripheral_get_info(ANY_BASE0, peri_index1); - val_print(ACS_PRINT_INFO, "\n addr of Peripheral 1 is %llx", peri_addr1); - val_print(ACS_PRINT_INFO, "\n addr of Peripheral 2 is %llx", peri_addr2); + val_print(TRACE, "\n addr of Peripheral 1 is %llx", peri_addr1); + val_print(TRACE, "\n addr of Peripheral 2 is %llx", peri_addr2); if ((peri_addr1 == 0) || (peri_addr2 == 0)) { continue; @@ -99,7 +99,7 @@ static void payload_check_peripheral_addr_64kb_apart(void) peri_addr1 - peri_addr2 : peri_addr2 - peri_addr1; if (addr_diff < MEM_SIZE_64KB) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Peripheral base addresses isn't atleast 64Kb apart %llx", addr_diff); fail_cnt++; } diff --git a/test_pool/mpam/error001.c b/test_pool/mpam/error001.c index a68dd61f..502f1e46 100644 --- a/test_pool/mpam/error001.c +++ b/test_pool/mpam/error001.c @@ -42,7 +42,7 @@ static void payload(void) for (index = 0; index < total_nodes; index++) { if (!val_mpam_msc_supports_esr(index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", index); + val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; } @@ -68,12 +68,12 @@ static void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_PARTID_SEL_RANGE) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_PARTID_SEL_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_PARTID_SEL_RANGE); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error002.c b/test_pool/mpam/error002.c index 69587afe..3df10fb0 100644 --- a/test_pool/mpam/error002.c +++ b/test_pool/mpam/error002.c @@ -48,7 +48,7 @@ void payload(void) for (index = 0; index < total_nodes; index++) { if (!val_mpam_msc_supports_esr(index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", index); + val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; } @@ -66,7 +66,7 @@ void payload(void) if (status == ACS_STATUS_SKIP) { /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); - val_print(ACS_PRINT_WARN, "\n MSC PARTID range exceeds PE PARTID range \n", 0); + val_print(WARN, "\n MSC PARTID range exceeds PE PARTID range \n"); continue; } @@ -78,12 +78,12 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_Req_PARTID_Range) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_Req_PARTID_Range); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_Req_PARTID_Range); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error003.c b/test_pool/mpam/error003.c index 1af085e6..122b9b43 100644 --- a/test_pool/mpam/error003.c +++ b/test_pool/mpam/error003.c @@ -45,7 +45,7 @@ void payload(void) for (index = 0; index < total_nodes; index++) { if (!val_mpam_msc_supports_esr(index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", index); + val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; } @@ -62,13 +62,13 @@ void payload(void) if (val_mpam_msc_supports_mon(index)) { if (val_mpam_supports_csumon(index)) { mon_count += val_mpam_get_csumon_count(index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d CSU Monitors", mon_count); } if (val_mpam_msc_supports_mbwumon(index)) { mon_count += val_mpam_get_mbwumon_count(index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d MBWU Monitors", val_mpam_get_mbwumon_count(index)); } } @@ -87,13 +87,13 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_MSMONCFG_ID_RANGE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_MSMONCFG_ID_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error004.c b/test_pool/mpam/error004.c index 51fdfc5d..6a97e432 100644 --- a/test_pool/mpam/error004.c +++ b/test_pool/mpam/error004.c @@ -48,7 +48,7 @@ void payload(void) for (index = 0; index < total_nodes; index++) { if (!val_mpam_msc_supports_esr(index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", index); + val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; } @@ -66,7 +66,7 @@ void payload(void) if (status == ACS_STATUS_SKIP) { /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); - val_print(ACS_PRINT_WARN, "\n MSC PMG range exceeds PE PMG range", 0); + val_print(WARN, "\n MSC PMG range exceeds PE PMG range"); continue; } @@ -78,12 +78,12 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_REQ_PMG_RANGE) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_REQ_PMG_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_REQ_PMG_RANGE); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error005.c b/test_pool/mpam/error005.c index 7937aa3c..323e09e9 100644 --- a/test_pool/mpam/error005.c +++ b/test_pool/mpam/error005.c @@ -45,7 +45,7 @@ void payload(void) for (index = 0; index < total_nodes; index++) { if (!val_mpam_msc_supports_esr(index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", index); + val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; } @@ -53,13 +53,13 @@ void payload(void) if (val_mpam_msc_supports_mon(index)) { if (val_mpam_supports_csumon(index)) { mon_count += val_mpam_get_csumon_count(index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d CSU Monitors", mon_count); } if (val_mpam_msc_supports_mbwumon(index)) { mon_count += val_mpam_get_mbwumon_count(index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d MBWU Monitors", val_mpam_get_mbwumon_count(index)); } } @@ -69,7 +69,7 @@ void payload(void) * support (or) if it doesn't implement any monitors */ if ((mon_count == 0)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not implement any MSMON. Skipping MSC..", index); continue; } @@ -94,12 +94,12 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_MON_RANGE) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_MON_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_MON_RANGE); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error006.c b/test_pool/mpam/error006.c index 6c4bb2af..293f9b0c 100644 --- a/test_pool/mpam/error006.c +++ b/test_pool/mpam/error006.c @@ -47,12 +47,12 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_partid_nrw(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support PARTID narrowing", msc_index); continue; } @@ -75,26 +75,26 @@ void payload(void) /* Scenario 1: Map reqPARTID to out-of-range intPARTID */ partid = val_mpam_get_max_partid(msc_index); max_int_partid = val_mpam_get_max_intpartid(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Max Internal PARTID is 0x%lx", max_int_partid); + val_print(DEBUG, "\n Max Internal PARTID is 0x%lx", max_int_partid); /* Select valid partid and map it to max_int_partid + 1 to trigger the error */ data = (1 << MPAMCFG_INTPARTID_INTPARTID_INTERNAL_SHIFT) | (max_int_partid + 1); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, partid); val_mpam_mmr_write(msc_index, REG_MPAMCFG_INTPARTID, data); - val_print(ACS_PRINT_DEBUG, "\n Value write to MPAMCFG_INTPARTD is 0x%llx", data); + val_print(DEBUG, "\n Value write to MPAMCFG_INTPARTD is 0x%llx", data); /* Wait for some time for the error to be reflected in MPAMF_ESR */ val_time_delay_ms(100 * ONE_MILLISECOND); /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_INTPARTID_RANGE) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_INTPARTID_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_INTPARTID_RANGE); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error007.c b/test_pool/mpam/error007.c index 5e5480aa..4769664d 100644 --- a/test_pool/mpam/error007.c +++ b/test_pool/mpam/error007.c @@ -47,12 +47,12 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_partid_nrw(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support PARTID narrowing", msc_index); continue; } @@ -74,26 +74,26 @@ void payload(void) BITFIELD_SET(PART_SEL_PARTID_SEL, partid); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); + val_print(DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); max_int_partid = val_mpam_get_max_intpartid(msc_index); data = (1 << MPAMCFG_INTPARTID_INTPARTID_INTERNAL_SHIFT) | (max_int_partid); val_mpam_mmr_write(msc_index, REG_MPAMCFG_INTPARTID, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAMCFG_INTPARTD is 0x%llx", data); + val_print(DEBUG, "\n Value written to MPAMCFG_INTPARTD is 0x%llx", data); /* Wait for some time for the error to be reflected in MPAMF_ESR */ val_time_delay_ms(100 * ONE_MILLISECOND); /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_UNEXPECTED_INTERNAL) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_UNEXPECTED_INTERNAL); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } diff --git a/test_pool/mpam/error008.c b/test_pool/mpam/error008.c index bf37960c..51acca89 100644 --- a/test_pool/mpam/error008.c +++ b/test_pool/mpam/error008.c @@ -73,12 +73,12 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } @@ -102,7 +102,7 @@ void payload(void) BITFIELD_SET(PART_SEL_RIS, (max_ris_index + 1)); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); + val_print(DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); /* Access MPAMCFG_* register to cause the error */ val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); @@ -112,17 +112,17 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_UNDEF_RIS_PART_SEL) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_UNDEF_RIS_PART_SEL); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); status = check_for_raz_wi(msc_index, REG_MPAMCFG_PART_SEL); if (status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_ERR, - "\n MPAMCFG_PART_SEL is not RAZ/WI with out-of-range RIS programmed", 0); + val_print(ERROR, + "\n MPAMCFG_PART_SEL is not RAZ/WI with out-of-range RIS programmed"); test_fail++; } } diff --git a/test_pool/mpam/error009.c b/test_pool/mpam/error009.c index 58a45e3d..aa4548e9 100644 --- a/test_pool/mpam/error009.c +++ b/test_pool/mpam/error009.c @@ -69,12 +69,12 @@ configure_partitioning_reg(uint32_t reg_offset) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_RIS_NO_CTRL) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_CTRL); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_CTRL); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); /* Check for RAZ/ WI*/ status = check_for_raz_wi(reg_offset); @@ -131,12 +131,12 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } diff --git a/test_pool/mpam/error010.c b/test_pool/mpam/error010.c index 0cf36068..a8fb769e 100644 --- a/test_pool/mpam/error010.c +++ b/test_pool/mpam/error010.c @@ -72,19 +72,19 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } /* Error cannot be generated if MSMON_CFG_MON_SEL register is not implemented */ if (!val_mpam_msc_supports_mon(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not implement MSMON", msc_index); continue; } @@ -107,7 +107,7 @@ void payload(void) BITFIELD_SET(MON_SEL_RIS, (max_ris_index + 1)); val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MON_SEL, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %llx", data); + val_print(DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %llx", data); /* Access MSMON_CFG_* register to cause the error */ val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MON_SEL); @@ -117,17 +117,17 @@ void payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_UNDEF_RIS_MON_SEL) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_UNDEF_RIS_MON_SEL); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); status = check_for_raz_wi(msc_index, REG_MSMON_CFG_MON_SEL); if (status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_ERR, - "\n MSMON_CFG_MON_SEL is not RAZ/WI with out-of-range RIS programmed", 0); + val_print(ERROR, + "\n MSMON_CFG_MON_SEL is not RAZ/WI with out-of-range RIS programmed"); test_fail++; } } diff --git a/test_pool/mpam/error011.c b/test_pool/mpam/error011.c index 4736af51..15787730 100644 --- a/test_pool/mpam/error011.c +++ b/test_pool/mpam/error011.c @@ -69,12 +69,12 @@ configure_monitoring_reg(uint32_t reg_offset) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_RIS_NO_MON) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_MON); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_MON); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); /* Check for RAZ/ WI*/ status = check_for_raz_wi(reg_offset); @@ -126,12 +126,12 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } diff --git a/test_pool/mpam/error012.c b/test_pool/mpam/error012.c index 42b64c5c..c25e4404 100644 --- a/test_pool/mpam/error012.c +++ b/test_pool/mpam/error012.c @@ -48,15 +48,15 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { - val_print(ACS_PRINT_DEBUG, "\n MSC index : %d", msc_index); + val_print(DEBUG, "\n MSC index : %d", msc_index); if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support RIS", msc_index); + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } /* Check if Error Status Register Supported */ if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR/ECR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR/ECR", msc_index); continue; } @@ -65,7 +65,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_print(ACS_PRINT_DEBUG, "\n Error Code Reset Failed", 0); + val_print(DEBUG, "\n Error Code Reset Failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -84,7 +84,7 @@ void payload(void) val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); - val_print(ACS_PRINT_DEBUG, "\n Value Read Back from MPAMCFG_PART_SEL is %llx", data); + val_print(DEBUG, "\n Value Read Back from MPAMCFG_PART_SEL is %llx", data); /* Wait for some time for the error to be reflected in MPAMF_ESR */ val_time_delay_ms(100 * ONE_MILLISECOND); @@ -92,7 +92,7 @@ void payload(void) /* Reset Errorcode which might have updated after setting out of range RIS */ status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_print(ACS_PRINT_DEBUG, "\n Error Code Reset Failed after RIS", 0); + val_print(DEBUG, "\n Error Code Reset Failed after RIS"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -102,18 +102,18 @@ void payload(void) /* Check All HAS_* Fields read as 0 */ if (idr_value & MPAMF_IDR_HAS_MASK) { - val_print(ACS_PRINT_ERR, "\n ID Register HAS_* Field Non Zero : %llx", idr_value); + val_print(ERROR, "\n ID Register HAS_* Field Non Zero : %llx", idr_value); test_fail++; } /* Restore */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data_original); esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Error code read is %llx", esr_errcode); + val_print(DEBUG, "\n Error code read is %llx", esr_errcode); if (esr_errcode != ESR_ERRCODE_NO_ERROR) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_NO_ERROR); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_NO_ERROR); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } /* Restore Error Control Register original settings */ diff --git a/test_pool/mpam/error013.c b/test_pool/mpam/error013.c index 2127191e..078aa5d0 100644 --- a/test_pool/mpam/error013.c +++ b/test_pool/mpam/error013.c @@ -48,17 +48,17 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support RIS", msc_index); + val_print(DEBUG, "\n MSC index %d does not support RIS", msc_index); continue; } if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } if (!val_mpam_msc_supports_extd_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support EXTD_ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support EXTD_ESR", msc_index); continue; } @@ -76,7 +76,7 @@ void payload(void) max_ris_index = val_mpam_get_max_ris_count(msc_index); if (max_ris_index == 0xF) { /* Maximum RIS Supported, Skip This MSC */ - val_print(ACS_PRINT_DEBUG, "\n MSC index %d supports all RIS", msc_index); + val_print(DEBUG, "\n MSC index %d supports all RIS", msc_index); continue; } @@ -91,7 +91,7 @@ void payload(void) BITFIELD_SET(PART_SEL_RIS, programmed_ris); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); + val_print(DEBUG, "\n Value written to MPAMCFG_PART_SEL is %llx", data); /* Access MPAMCFG_* register to cause the error */ val_mpam_mmr_read(msc_index, REG_MPAMCFG_CMAX); @@ -104,15 +104,15 @@ void payload(void) if ((esr_value >> ESR_ERRCODE_SHIFT) & ESR_ERRCODE_MASK) { if (((esr_value >> ESR_RIS_SHIFT) & ESR_RIS_MASK) != programmed_ris) { - val_print(ACS_PRINT_ERR, "\n ESR.RIS mismatch MPAMCFG access: expected 0x%x", + val_print(ERROR, "\n ESR.RIS mismatch MPAMCFG access: expected 0x%x", programmed_ris); - val_print(ACS_PRINT_ERR, ", Received 0x%x", + val_print(ERROR, ", Received 0x%x", ((esr_value >> ESR_RIS_SHIFT) & ESR_RIS_MASK)); test_fail++; } } else { /* Print Warning for Mismatch in Error Code */ - val_print(ACS_PRINT_WARN, "\n ERRCODE mismatch MPAMCFG access: Received 0x%x", + val_print(WARN, "\n ERRCODE mismatch MPAMCFG access: Received 0x%x", ((esr_value >> ESR_ERRCODE_SHIFT) & ESR_ERRCODE_MASK)); } @@ -129,7 +129,7 @@ void payload(void) BITFIELD_SET(MON_SEL_RIS, programmed_ris); val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MON_SEL, data); - val_print(ACS_PRINT_DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %llx", data); + val_print(DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %llx", data); /* Access MSMON_CFG_* register to cause the error */ val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_FLT); @@ -142,15 +142,15 @@ void payload(void) if ((esr_value >> ESR_ERRCODE_SHIFT) & ESR_ERRCODE_MASK) { if (((esr_value >> ESR_RIS_SHIFT) & ESR_RIS_MASK) != programmed_ris) { - val_print(ACS_PRINT_ERR, "\n ESR.RIS mismatch MSMON_CFG access: expected 0x%x", + val_print(ERROR, "\n ESR.RIS mismatch MSMON_CFG access: expected 0x%x", programmed_ris); - val_print(ACS_PRINT_ERR, ", Received 0x%x", + val_print(ERROR, ", Received 0x%x", ((esr_value >> ESR_RIS_SHIFT) & ESR_RIS_MASK)); test_fail++; } } else { /* Print Warning for Mismatch in Error Code */ - val_print(ACS_PRINT_WARN, "\n ERRCODE mismatch MSMON_CFG access: Received 0x%x", + val_print(WARN, "\n ERRCODE mismatch MSMON_CFG access: Received 0x%x", ((esr_value >> ESR_ERRCODE_SHIFT) & ESR_ERRCODE_MASK)); } diff --git a/test_pool/mpam/error014.c b/test_pool/mpam/error014.c index c02311b0..5c8bdd68 100644 --- a/test_pool/mpam/error014.c +++ b/test_pool/mpam/error014.c @@ -48,7 +48,7 @@ payload(void) /* Check if Error Status Register Supported */ if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } @@ -66,13 +66,13 @@ payload(void) if (val_mpam_msc_supports_mon(msc_index)) { if (val_mpam_supports_csumon(msc_index)) { mon_count += val_mpam_get_csumon_count(msc_index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d CSU Monitors", mon_count); } if (val_mpam_msc_supports_mbwumon(msc_index)) { mon_count += val_mpam_get_mbwumon_count(msc_index); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC implements %d MBWU Monitors", val_mpam_get_mbwumon_count(msc_index)); } } @@ -80,7 +80,7 @@ payload(void) /* CSU/MBWU monitors are required to generate the second error. Skip MSC if mon not present */ if (mon_count == 0) { - val_print(ACS_PRINT_WARN, "\n Cannot generate second error. Skipping MSC\n", 0); + val_print(WARN, "\n Cannot generate second error. Skipping MSC\n"); continue; } @@ -97,19 +97,19 @@ payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Scenario 1 - Error code read is %d", esr_errcode); + val_print(DEBUG, "\n Scenario 1 - Error code read is %d", esr_errcode); if (esr_errcode != ESR_ERRCODE_PARTID_SEL_RANGE) { - val_print(ACS_PRINT_ERR, "\n Expected errcode: %d", ESR_ERRCODE_PARTID_SEL_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_PARTID_SEL_RANGE); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } /* Check OVRWR bit - should be 0 for first error */ if (val_mpam_msc_get_esr_ovrwr(msc_index)) { - val_print(ACS_PRINT_ERR, "\n OVRWR bit is set for first error", 0); + val_print(ERROR, "\n OVRWR bit is set for first error"); test_fail++; } @@ -121,20 +121,20 @@ payload(void) /* Read Error Status Register and check if the error code is recorded */ esr_errcode = val_mpam_msc_get_errcode(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Scenario 2 - Error code read is %d", esr_errcode); + val_print(DEBUG, "\n Scenario 2 - Error code read is %d", esr_errcode); if (esr_errcode != ESR_ERRCODE_MSMONCFG_ID_RANGE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_MSMONCFG_ID_RANGE); - val_print(ACS_PRINT_ERR, "\n Actual errcode: %d", esr_errcode); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); test_fail++; } /* Check OVRWR bit - should be 1 for second error */ if (val_mpam_msc_get_esr_ovrwr(msc_index) == 0) { - val_print(ACS_PRINT_ERR, "\n MPAMF_ESR.OVRWR bit is not set for second error", 0); + val_print(ERROR, "\n MPAMF_ESR.OVRWR bit is not set for second error"); test_fail++; } diff --git a/test_pool/mpam/feat001.c b/test_pool/mpam/feat001.c index 0b980a2a..cc10c0f9 100644 --- a/test_pool/mpam/feat001.c +++ b/test_pool/mpam/feat001.c @@ -77,7 +77,7 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n LLC not present, Skipping test", 0); + val_print(DEBUG, "\n LLC not present, Skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -85,7 +85,7 @@ payload(void) /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n Invalid LLC ID, skipping test", 0); + val_print(DEBUG, "\n Invalid LLC ID, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -96,7 +96,7 @@ payload(void) /* Check if the MSC supports PARTID Disable feature (MPAMCFG.HAS_ENDIS bit) */ if (!val_mpam_msc_supports_partid_endis(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC index %d does not support PARTID Enable/Disable, skipping...", msc_index); continue; @@ -120,7 +120,7 @@ payload(void) val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); if (val_mpam_get_max_partid(msc_index) < partid_y) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not support required PARTIDs, skipping MSC", msc_index); continue; } @@ -135,7 +135,7 @@ payload(void) num_mon = val_mpam_get_csumon_count(msc_index); if (num_mon == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not have CSU monitors, skipping MSC", msc_index); continue; } @@ -144,7 +144,7 @@ payload(void) Select Cache partitioning scheme based on the support */ if (val_mpam_supports_cpor(msc_index)) { cpart_flag = 1; - val_print(ACS_PRINT_DEBUG, "\n MSC %d supports CPOR partitioning", msc_index); + val_print(DEBUG, "\n MSC %d supports CPOR partitioning", msc_index); /* The test uses CPOR as cache partitioning scheme. Disable CCAP settings */ val_mpam_configure_ccap(msc_index, partid_x, 0, 100); @@ -153,14 +153,14 @@ payload(void) } else if (val_mpam_supports_ccap(msc_index)) { cpart_flag = 2; - val_print(ACS_PRINT_DEBUG, "\n MSC %d supports CCAP partitioning", msc_index); + val_print(DEBUG, "\n MSC %d supports CCAP partitioning", msc_index); /* The test uses CCAP as cache partitioning scheme. Disable CPOR settings */ val_mpam_configure_cpor(msc_index, partid_x, 100); val_mpam_configure_cpor(msc_index, partid_y, 100); } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not support CPOR/CCAP partitioning, skipping...", msc_index); continue; @@ -171,7 +171,7 @@ payload(void) dest_buf = (void *)val_aligned_alloc(MEM_ALIGN_4K, BUFFER_SIZE); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_aligned(dest_buf); @@ -206,7 +206,7 @@ payload(void) status = val_mpam_program_el2(partid_x, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); @@ -227,11 +227,11 @@ payload(void) /* Step 6 */ counter[0] = end_count; - val_print(ACS_PRINT_TEST, "\n PARTID_X Counter (Scenario 1)= 0x%lx", counter[0]); + val_print(INFO, "\n PARTID_X Counter (Scenario 1)= 0x%lx", counter[0]); /* Counter should be non-zero */ if (counter[0] == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Scenario 1: PARTID_X counter is zero, test failed for MSC %d", msc_index); test_fail++; goto cleanup; @@ -262,7 +262,7 @@ payload(void) status = val_mpam_program_el2(partid_y, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -294,14 +294,14 @@ payload(void) val_mpam_csumon_disable(msc_index); counter[1] = end_count; - val_print(ACS_PRINT_TEST, "\n PARTID_X Counter (Scenario 2)= 0x%lx", counter[1]); + val_print(INFO, "\n PARTID_X Counter (Scenario 2)= 0x%lx", counter[1]); /* Step 10: Validate Value B < Value A */ /* Txn tagged with PARTID_Y but monitor counts PARTID X. PARTID_X is disabled, so cache lines occupied previously by PARTID_X should have highest eviction priority. Buffer tagged with PARTID_Y should evict PARTID_X cache lines */ if (counter[1] >= counter[0]) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Scenario 2: Counter more than S1, test failed for MSC %d", msc_index); test_fail++; goto cleanup; @@ -323,7 +323,7 @@ payload(void) /* Step 12: Program MPAM2_EL2 with PARTID_X and perform bufcopy */ status = val_mpam_program_el2(partid_x, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -357,13 +357,13 @@ payload(void) val_mpam_csumon_disable(msc_index); counter[2] = end_count; - val_print(ACS_PRINT_TEST, "\n PARTID_X Counter (Scenario 3)= 0x%lx", counter[2]); + val_print(INFO, "\n PARTID_X Counter (Scenario 3)= 0x%lx", counter[2]); /* With PARTID_Y disabled and PARTID_X enabled, CPOR settings of PARTID_X must be restored by the H/W. PARTID_Y cache lines should be evicted by txn tagged with PARTID_X */ if (counter[1] >= counter[2]) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Scenario 3: Counter less than S2, test failed for MSC %d", msc_index); test_fail++; goto cleanup; diff --git a/test_pool/mpam/intr001.c b/test_pool/mpam/intr001.c index c1982724..ec00fae7 100644 --- a/test_pool/mpam/intr001.c +++ b/test_pool/mpam/intr001.c @@ -40,7 +40,7 @@ esr(uint64_t exception_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_WARN, "\n Received Exception of type %d", exception_type); + val_print(WARN, "\n Received Exception of type %d", exception_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); } @@ -48,7 +48,7 @@ static void intr_handler(void) { uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_DEBUG, "\n Received MSC Err interrupt %d", intr_num); + val_print(DEBUG, "\n Received MSC Err interrupt %d", intr_num); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); /* Restore Error Control Register original settings */ @@ -85,14 +85,14 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } intr_num = val_mpam_get_info(MPAM_MSC_ERR_INTR, msc_index, 0); intr_flags = val_mpam_get_info(MPAM_MSC_ERR_INTR_FLAGS, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n Error interrupt flags - 0x%llx", intr_flags); + val_print(DEBUG, "\n Error interrupt flags - 0x%llx", intr_flags); intr_type = intr_flags & MPAM_ACPI_ERR_INTR_TYPE_MASK; /* Read MPAMF_ECR before generating error. This will be used to restore to default later */ @@ -109,8 +109,8 @@ void payload(void) * or if its error interrupt is not of type level-trigger */ if ((intr_num == 0) || (intr_type != MPAM_ACPI_ERR_INTR_TYPE_LEVEL)) { - val_print(ACS_PRINT_DEBUG, - "\n MSC does not implement level triggered Error intr. Skipping MSC", 0); + val_print(DEBUG, + "\n MSC does not implement level triggered Error intr. Skipping MSC"); continue; } else { intr_count++; @@ -129,7 +129,7 @@ void payload(void) * Set the interrupt enable bit in MPAMF_ECR & raise * an interrupt by writing non-zero to MPAMF_ESR.ERRCODE */ - val_print(ACS_PRINT_DEBUG, "\n Triggering MSC Error interrupt %d", intr_num); + val_print(DEBUG, "\n Triggering MSC Error interrupt %d", intr_num); val_mpam_msc_trigger_intr(msc_index); /* PE busy polls to check the completion of interrupt service routine */ @@ -139,7 +139,7 @@ void payload(void) /* Restore Error Control Register original settings (safety net) */ val_mpam_mmr_write(msc_index, REG_MPAMF_ECR, mpamf_ecr_saved); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n MSC Err Interrupt not received on %d", intr_num); + val_print(ERROR, "\n MSC Err Interrupt not received on %d", intr_num); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } diff --git a/test_pool/mpam/intr002.c b/test_pool/mpam/intr002.c index aa8266b6..3c879c61 100644 --- a/test_pool/mpam/intr002.c +++ b/test_pool/mpam/intr002.c @@ -39,7 +39,7 @@ esr(uint64_t exception_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_WARN, "\n Received Exception of type %d", exception_type); + val_print(WARN, "\n Received Exception of type %d", exception_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); } @@ -47,7 +47,7 @@ static void intr_handler(void) { uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_ERR, "\n Received unexpected edge-trigger interrupt %d", intr_num); + val_print(ERROR, "\n Received unexpected edge-trigger interrupt %d", intr_num); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); /* Write 0b0000 into MPAMF_ESR.ERRCODE to clear the interrupt */ @@ -82,14 +82,14 @@ void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, "\n MSC index %d does not support ESR", msc_index); + val_print(DEBUG, "\n MSC index %d does not support ESR", msc_index); continue; } intr_num = val_mpam_get_info(MPAM_MSC_ERR_INTR, msc_index, 0); intr_flags = val_mpam_get_info(MPAM_MSC_ERR_INTR_FLAGS, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n Error interrupt flags - 0x%llx", intr_flags); + val_print(DEBUG, "\n Error interrupt flags - 0x%llx", intr_flags); intr_type = intr_flags & MPAM_ACPI_ERR_INTR_TYPE_MASK; /* Read MPAMF_ECR before generating error. This will be used to restore to default later */ @@ -106,8 +106,8 @@ void payload(void) * or if its error interrupt is of type level-trigger */ if ((intr_num == 0) || (intr_type != MPAM_ACPI_ERR_INTR_TYPE_EDGE)) { - val_print(ACS_PRINT_DEBUG, - "\n MSC does not implement edge triggered Error intr. Skipping MSC", 0); + val_print(DEBUG, + "\n MSC does not implement edge triggered Error intr. Skipping MSC"); continue; } else { intr_count++; @@ -126,7 +126,7 @@ void payload(void) * Set the interrupt enable bit in MPAMF_ECR & raise * an interrupt by writing non-zero to MPAMF_ESR.ERRCODE */ - val_print(ACS_PRINT_DEBUG, "\n Triggering MSC Error interrupt %d", intr_num); + val_print(DEBUG, "\n Triggering MSC Error interrupt %d", intr_num); val_mpam_msc_trigger_intr(msc_index); /* PE busy polls to check the completion of interrupt service routine */ diff --git a/test_pool/mpam/intr003.c b/test_pool/mpam/intr003.c index 397430b5..9ffa7210 100644 --- a/test_pool/mpam/intr003.c +++ b/test_pool/mpam/intr003.c @@ -36,7 +36,7 @@ void intr_handler(void) uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t ctl; - val_print(ACS_PRINT_DEBUG, "\n Received Oflow error interrupt %d ", intr_num); + val_print(DEBUG, "\n Received Oflow error interrupt %d ", intr_num); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); ctl = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); @@ -100,7 +100,7 @@ void payload(void) if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) != MPAM_RSRC_TYPE_MEMORY) { - val_print(ACS_PRINT_TEST, "\n MSC %d not a memory node. Skipping MSC", + val_print(INFO, "\n MSC %d not a memory node. Skipping MSC", msc_index); continue; } @@ -115,9 +115,9 @@ void payload(void) val_mpam_get_mbwumon_count(msc_index) : 0; } - val_print(ACS_PRINT_DEBUG, "\n MSC Index: %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n MBWU Monitors: %d", mon_count); - val_print(ACS_PRINT_DEBUG, "\n Overflow Interrupt: %d", intr_num); + val_print(DEBUG, "\n MSC Index: %d", msc_index); + val_print(DEBUG, "\n MBWU Monitors: %d", mon_count); + val_print(DEBUG, "\n Overflow Interrupt: %d", intr_num); /* * Skip this MSC if it doesn't implement overflow interrupt @@ -149,7 +149,7 @@ void payload(void) dest_buf = (void *)val_mem_alloc_at_address(base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation for buffers failed", 0x0); + val_print(ERROR, "\n Mem allocation for buffers failed", 0x0); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; @@ -158,9 +158,9 @@ void payload(void) data = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); data = data | (1 << MBWU_CTL_ENABLE_SHIFT); val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MBWU_CTL, data); - val_print(ACS_PRINT_DEBUG, "\n MSMON_CFG_MBWU_CTL is %llx", + val_print(DEBUG, "\n MSMON_CFG_MBWU_CTL is %llx", val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL)); - val_print(ACS_PRINT_DEBUG, "\n Monitor count is %llx", + val_print(DEBUG, "\n Monitor count is %llx", val_mpam_memory_mbwumon_read_count(msc_index)); /* wait for MAX_NRDY_USEC after msc config change */ @@ -178,9 +178,9 @@ void payload(void) timeout = TIMEOUT_LARGE; while ((--timeout > 0) && (isr_completion_flag == 0)); - val_print(ACS_PRINT_DEBUG, "\n MSMON_CFG_MBWU_CTL is %llx", + val_print(DEBUG, "\n MSMON_CFG_MBWU_CTL is %llx", val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL)); - val_print(ACS_PRINT_DEBUG, "\n Monitor count is %llx", + val_print(DEBUG, "\n Monitor count is %llx", val_mpam_memory_mbwumon_read_count(msc_index)); /* Free the buffers after return from overflow interrupt */ val_mem_free_at_address(base, buf_size); @@ -191,7 +191,7 @@ void payload(void) val_mpam_memory_mbwumon_reset(msc_index); if (isr_completion_flag == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSC MSMON Oflow Err Interrupt not received on %d", intr_num); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -203,7 +203,7 @@ void payload(void) if ((((esr_value >> ESR_ERRCODE_SHIFT) & ESR_ERRCODE_MASK) != 0) || (((esr_value >> ESR_OVRWR_SHIFT) & ESR_OVRWR_MASK) != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MPAMF_ESR.ERRCODE/OVRWR is not cleared by ISR for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); diff --git a/test_pool/mpam/intr004.c b/test_pool/mpam/intr004.c index b6e1a2c2..26a504e3 100644 --- a/test_pool/mpam/intr004.c +++ b/test_pool/mpam/intr004.c @@ -60,7 +60,7 @@ mbwu_prepare_overflow_intr(uint32_t msc_idx, val_mpam_memory_configure_mbwumon(msc_idx); if (val_mpam_mbwu_clear_overflow_status(msc_idx)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to clear overflow status before setup for MSC %d", msc_idx); return ACS_STATUS_FAIL; } @@ -98,7 +98,7 @@ mbwu_prepare_overflow_intr(uint32_t msc_idx, /* Overflow Status is Cleared in Handler */ if (val_mpam_mbwu_is_overflow_set(msc_idx)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not Cleared for MSC %d in Handler", msc_idx); return ACS_STATUS_FAIL; } @@ -119,16 +119,16 @@ void intr_handler(void) status_l_asserted = ctl & ((uint32_t)1 << MBWU_CTL_OFLOW_STATUS_L_SHIFT); if (!status_l_asserted) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n OFLOW_STATUS_L not set on overflow interrupt for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n OFLOW_STATUS_L observed set on interrupt for MSC %d", msc_index); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to clear overflow status via helper for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); } @@ -167,7 +167,7 @@ void payload(void) /* Program MPAM2_EL2 with DEFAULT_PARTID and default PMG */ status = val_mpam_program_el2(DEFAULT_PARTID, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); test_fail++; test_skip = 0; goto cleanup; @@ -206,7 +206,7 @@ void payload(void) /* Ensure the region can fit both source and destination buffers */ if ((base == SRAT_INVALID_INFO) || (mem_size == SRAT_INVALID_INFO) || (mem_size <= 2 * buf_size)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d memory range invalid for MBWU_L test", msc_index); continue; } @@ -217,7 +217,7 @@ void payload(void) if (!handler_installed) { status = val_gic_install_isr(intr_num, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to install ISR for interrupt %d", intr_num); test_fail++; goto monitor_cleanup; @@ -231,7 +231,7 @@ void payload(void) src_buf = (void *)val_mem_alloc_at_address(base, buf_size); dest_buf = (void *)val_mem_alloc_at_address(base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed for MSC %d", msc_index); + val_print(ERROR, "\n Mem allocation failed for MSC %d", msc_index); test_fail++; goto monitor_cleanup; } @@ -244,7 +244,7 @@ void payload(void) /* Configure overflow interrupt and drive the counter to overflow */ status = mbwu_prepare_overflow_intr(msc_index, src_buf, dest_buf, buf_size); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to configure overflow interrupt for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); test_fail++; @@ -255,7 +255,7 @@ void payload(void) while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(pe_index)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow interrupt not received for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -263,14 +263,14 @@ void payload(void) /* Verify the ISR ran and observed OFLOW_STATUS_L */ if (!handler_invoked) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Handler not invoked for MSC %d after overflow", msc_index); test_fail++; goto monitor_cleanup; } if (!status_l_asserted) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n OFLOW_STATUS_L not observed set for MSC %d", msc_index); test_fail++; goto monitor_cleanup; diff --git a/test_pool/mpam/intr005.c b/test_pool/mpam/intr005.c index 373a2207..8453ec20 100644 --- a/test_pool/mpam/intr005.c +++ b/test_pool/mpam/intr005.c @@ -53,7 +53,7 @@ mbwu_prepare_overflow_intr(uint32_t msc_idx, val_mpam_memory_configure_mbwumon(msc_idx); if (val_mpam_mbwu_clear_overflow_status(msc_idx)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to clear overflow status before setup for MSC %d", msc_idx); return ACS_STATUS_FAIL; } @@ -85,7 +85,7 @@ mbwu_prepare_overflow_intr(uint32_t msc_idx, /* Overflow is cleared in the handler */ if (val_mpam_mbwu_is_overflow_set(msc_idx)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared for MSC %d during setup", msc_idx); return ACS_STATUS_FAIL; } @@ -105,16 +105,16 @@ void intr_handler(void) status_asserted = ctl & ((uint32_t)1 << MBWU_CTL_OFLOW_STATUS_BIT_SHIFT); if (!status_asserted) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n OFLOW_STATUS not set on overflow MSI for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n OFLOW_STATUS observed set on MSI for MSC %d", msc_index); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to clear overflow status via helper for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 07)); } @@ -157,7 +157,7 @@ void payload(void) /* Program MPAM2_EL2 with DEFAULT_PARTID and default PMG */ status = val_mpam_program_el2(DEFAULT_PARTID, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); test_fail++; test_skip = 0; goto cleanup; @@ -180,14 +180,14 @@ void payload(void) msmon_idr = val_mpam_mmr_read(msc_index, REG_MPAMF_MSMON_IDR); if (!BITFIELD_READ(MSMON_IDR_HAS_OFLW_MSI, msmon_idr)) { /* Overflow MSI Not Supported for this MSC */ - val_print(ACS_PRINT_ERR, "\n OFLOW_MSI is not supported for MSC %d", msc_index); + val_print(ERROR, "\n OFLOW_MSI is not supported for MSC %d", msc_index); continue; } /* Get Device ID and ITS Id for this MSC */ status = val_mpam_get_msc_device_info(msc_index, &device_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device & ITS info for MSC %d", msc_index); test_fail++; break; @@ -209,7 +209,7 @@ void payload(void) if ((base == SRAT_INVALID_INFO) || (mem_size == SRAT_INVALID_INFO) || (mem_size <= 2 * buf_size)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d memory range invalid for MBWU MSI test", msc_index); continue; } @@ -219,7 +219,7 @@ void payload(void) status = val_mpam_msc_request_msi(msc_index, device_id, its_id, msi_intr_num, 1 /* oflow_msi */); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -228,7 +228,7 @@ void payload(void) if (!handler_installed) { status = val_gic_install_isr(msi_intr_num, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to install ISR for interrupt %d", msi_intr_num); test_fail++; goto monitor_cleanup; @@ -241,7 +241,7 @@ void payload(void) src_buf = (void *)val_mem_alloc_at_address(base, buf_size); dest_buf = (void *)val_mem_alloc_at_address(base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed for MSC %d", msc_index); + val_print(ERROR, "\n Mem allocation failed for MSC %d", msc_index); test_fail++; goto monitor_cleanup; } @@ -253,7 +253,7 @@ void payload(void) status = val_mpam_msc_enable_msi(msc_index, 1); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to enable OFLOW_MSI for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -261,7 +261,7 @@ void payload(void) status = mbwu_prepare_overflow_intr(msc_index, src_buf, dest_buf, buf_size); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to configure overflow MSI for MSC %d", msc_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 06)); test_fail++; @@ -272,21 +272,21 @@ void payload(void) while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(pe_index)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow MSI not received for MSC %d", msc_index); test_fail++; goto monitor_cleanup; } if (!handler_invoked) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Handler not invoked for MSC %d after overflow", msc_index); test_fail++; goto monitor_cleanup; } if (!status_asserted) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n OFLOW_STATUS not observed set for MSC %d", msc_index); test_fail++; goto monitor_cleanup; diff --git a/test_pool/mpam/intr006.c b/test_pool/mpam/intr006.c index a495fe2d..b4cef9bf 100644 --- a/test_pool/mpam/intr006.c +++ b/test_pool/mpam/intr006.c @@ -56,7 +56,7 @@ void intr_handler(void) uint32_t errcode; uint32_t data; - val_print(ACS_PRINT_DEBUG, "\n MSC Index %d Handler Code", msc_index); + val_print(DEBUG, "\n MSC Index %d Handler Code", msc_index); /* Mark handler entry for timeout/flow checks. */ handler_invoked = 1; @@ -73,9 +73,9 @@ void intr_handler(void) /* Validate the error code generated by the MSC. */ errcode = val_mpam_msc_get_errcode(msc_index); if (errcode != ESR_ERRCODE_UNDEF_RIS_MON_SEL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_UNDEF_RIS_MON_SEL); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Actual errcode: %d", errcode); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); } else { @@ -115,21 +115,21 @@ void payload(void) /* Skip MSCs without ESR support. */ if (!val_mpam_msc_supports_esr(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d doesn't support ESR, skipping MSC", msc_index); continue; } /* Skip MSCs without RIS support. */ if (!val_mpam_msc_supports_ris(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d doesn't support RIS, skipping MSC", msc_index); continue; } /* Skip MSCs without MON support. */ if (!val_mpam_msc_supports_mon(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d doesn't support MON, skipping MSC", msc_index); continue; } @@ -137,7 +137,7 @@ void payload(void) mpamf_idr = val_mpam_mmr_read64(msc_index, REG_MPAMF_IDR); /* Skip MSCs without ERR_MSI support. */ if (!BITFIELD_READ(IDR_HAS_ERR_MSI, mpamf_idr)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d doesn't support ERR_MSI, skipping MSC", msc_index); continue; } @@ -145,7 +145,7 @@ void payload(void) /* Resolve device and ITS IDs for MSI programming. */ status = val_mpam_get_msc_device_info(msc_index, &device_id, &its_id); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Could not get device & ITS info for MSC %d", msc_index); test_fail++; break; @@ -155,7 +155,7 @@ void payload(void) if (!handler_installed) { status = val_gic_install_isr(msi_intr_num, intr_handler); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to install ISR for interrupt %d", msi_intr_num); test_fail++; break; @@ -168,7 +168,7 @@ void payload(void) /* Assign the MSI to the MSC. */ status = val_mpam_msc_request_msi(msc_index, device_id, its_id, msi_intr_num, 0); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n MSI Assignment failed for MSC %d", msc_index); test_fail++; break; @@ -197,7 +197,7 @@ void payload(void) /* Enable ERR_MSI to capture the injected error. */ status = val_mpam_msc_enable_msi(msc_index, 0); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to enable ERR_MSI for MSC %d", msc_index); test_fail++; goto msc_cleanup; @@ -220,21 +220,21 @@ void payload(void) while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(pe_index)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Error MSI not received for MSC %d", msc_index); test_fail++; goto msc_cleanup; } if (!handler_invoked) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Handler not invoked for MSC %d after error", msc_index); test_fail++; goto msc_cleanup; } if (!errcode_valid) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Expected errcode not observed for MSC %d", msc_index); test_fail++; goto msc_cleanup; diff --git a/test_pool/mpam/mem001.c b/test_pool/mpam/mem001.c index 6cdbf0c3..3e3d92af 100644 --- a/test_pool/mpam/mem001.c +++ b/test_pool/mpam/mem001.c @@ -51,15 +51,15 @@ get_buffer_size(uint32_t msc_index, uint32_t rsrc_index, uint64_t addr_len, uint membw = val_mpam_msc_get_mscbw(msc_index, rsrc_index); if (membw == HMAT_INVALID_INFO) { - val_print(ACS_PRINT_WARN, "\n Using default buffer sizes for memcpy", 0); + val_print(WARN, "\n Using default buffer sizes for memcpy"); buffer_size = mbwpbm_config_data[index].memcopy_size; - val_print(ACS_PRINT_WARN, " buffer_size: %llx", buffer_size); + val_print(WARN, " buffer_size: %llx", buffer_size); return buffer_size; } - val_print(ACS_PRINT_DEBUG, "\n Channel BW - %d MB/s", membw); + val_print(DEBUG, "\n Channel BW - %d MB/s", membw); limited_bw = membw / (mbwpbm_config_data[index].partition_percent); - val_print(ACS_PRINT_DEBUG, "\n Restricting Channel BW to %d MB/s", limited_bw); + val_print(DEBUG, "\n Restricting Channel BW to %d MB/s", limited_bw); /* Calculate required buffer to index 0 and use the same for other variations of partition percentage */ @@ -68,11 +68,11 @@ get_buffer_size(uint32_t msc_index, uint32_t rsrc_index, uint64_t addr_len, uint else buffer_size = mbwpbm_config_data[0].memcopy_size; - val_print(ACS_PRINT_DEBUG, "\n Buffer Size - 0x%llx", buffer_size); + val_print(DEBUG, "\n Buffer Size - 0x%llx", buffer_size); /* Check if this buffer is possible to allocate */ if (addr_len < (2 * buffer_size)) { - val_print(ACS_PRINT_WARN, "\n Insufficient buffer size to validate the test", 0); + val_print(WARN, "\n Insufficient buffer size to validate the test"); return ACS_STATUS_SKIP; } @@ -113,8 +113,8 @@ void payload(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d ", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -135,7 +135,7 @@ void payload(void) minmax_partid = GET_MIN_VALUE(minmax_partid, val_mpam_get_max_partid(msc_index)); } - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n %d MSC Memory Nodes support MBW Portion Partitioning", mbwpbm_node_cnt); /* Skip this test if no MBWPBM supported MSC present in the system */ @@ -144,7 +144,7 @@ void payload(void) return; } - val_print(ACS_PRINT_DEBUG, "\n MinMax PARTID = %d\n", minmax_partid); + val_print(DEBUG, "\n MinMax PARTID = %d\n", minmax_partid); /* Disable all types of partitioning for all other nodes */ for (msc_index = 0; msc_index < total_nodes; msc_index++) { @@ -188,7 +188,7 @@ void payload(void) /* Iterate through various partition settings and gather MBWU monitor count for each */ for (index = 0; index < sizeof(mbwpbm_config_data)/sizeof(mbwpbm_config_t); index++) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Programming MSC with %d percent of MBW Portion partitioning", mbwpbm_config_data[index].partition_percent); @@ -199,13 +199,13 @@ void payload(void) if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) != MPAM_RSRC_TYPE_MEMORY) { - val_print(ACS_PRINT_WARN, "\n MSC %d not a memory node. Skipping MSC", + val_print(WARN, "\n MSC %d not a memory node. Skipping MSC", msc_index); continue; } - val_print(ACS_PRINT_DEBUG, "\n MSC Index: %d", msc_index); - val_print(ACS_PRINT_DEBUG, " RIS Index: %d", rsrc_index); + val_print(DEBUG, "\n MSC Index: %d", msc_index); + val_print(DEBUG, " RIS Index: %d", rsrc_index); if (val_mpam_msc_supports_ris(msc_index)) val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); @@ -231,8 +231,8 @@ void payload(void) addr_base = val_mpam_memory_get_base(msc_index, rsrc_index); addr_len = val_mpam_memory_get_size(msc_index, rsrc_index); - val_print(ACS_PRINT_DEBUG, "\n addr_base is %llx", addr_base); - val_print(ACS_PRINT_DEBUG, "\n addr_len is %llx", addr_len); + val_print(DEBUG, "\n addr_base is %llx", addr_base); + val_print(DEBUG, "\n addr_len is %llx", addr_len); buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { @@ -242,7 +242,7 @@ void payload(void) if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * buf_size)) { /* src and dst buffer size */ - val_print(ACS_PRINT_ERR, "\n No SRAT mem range info found", 0); + val_print(ERROR, "\n No SRAT mem range info found"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); /* Restore MPAM2_EL2 settings */ @@ -254,7 +254,7 @@ void payload(void) dest_buf = (void *)val_mem_alloc_at_address(addr_base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Memory allocation of buffers failed", 0); + val_print(ERROR, "\n Memory allocation of buffers failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); /* Restore MPAM2_EL2 settings */ @@ -263,14 +263,14 @@ void payload(void) } if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(ACS_PRINT_TEST, - "\n No MBWU Monitor found to validate the test. Skipping test", 0); + val_print(INFO, + "\n No MBWU Monitor found to validate the test. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); return; } - val_print(ACS_PRINT_DEBUG, - "\n Using MBWU monitor to measure MBW count during buffer copy", 0); + val_print(DEBUG, + "\n Using MBWU monitor to measure MBW count during buffer copy"); /* configure MBWU Monitor for this memory resource node */ val_mpam_memory_configure_mbwumon(msc_index); @@ -285,7 +285,7 @@ void payload(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n Start count is %llx", start_count); + val_print(INFO, "\n Start count is %llx", start_count); /* perform memory operation */ val_memcpy(src_buf, dest_buf, buf_size); @@ -297,7 +297,7 @@ void payload(void) }; end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n End count is %llx", end_count); + val_print(INFO, "\n End count is %llx", end_count); /* read the memory bandwidth usage monitor */ counter[enabled_scenarios++][msc_index][rsrc_index] = @@ -307,7 +307,7 @@ void payload(void) val_mpam_memory_mbwumon_disable(msc_index); val_mpam_memory_mbwumon_reset(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n byte_count = 0x%llx bytes", end_count - start_count); /* Free the buffers to the heap manager */ @@ -334,8 +334,8 @@ void payload(void) if (val_mpam_msc_supports_mbwpbm(msc_index)) { if (counter[index][msc_index][rsrc_index] > counter[index-1][msc_index][rsrc_index]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", index); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n cfg_index : %d", index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/mpam/mem002.c b/test_pool/mpam/mem002.c index bbab87d8..1947a668 100644 --- a/test_pool/mpam/mem002.c +++ b/test_pool/mpam/mem002.c @@ -45,7 +45,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); } @@ -77,7 +77,7 @@ static int wait_for_secondary_off(uint32_t primary_pe_index) for (pe_index = 0; pe_index < num_pe_cont; pe_index++) { if ((pe_index != primary_pe_index) && IS_RESULT_PENDING(val_get_status(pe_index))) { - val_print(ACS_PRINT_ERR, " Secondary PE %x OFF time-out \n", pe_index); + val_print(ERROR, " Secondary PE %x OFF time-out \n", pe_index); } } return 1; @@ -194,7 +194,7 @@ get_buffer_size(uint32_t msc_index, uint32_t rsrc_index, uint32_t num_pe_cont) else buf_size = (mem_length / NUM_PE_CONT); - val_print(ACS_PRINT_DEBUG, "\n Chosen Buffer Size is 0x%llx", buf_size); + val_print(DEBUG, "\n Chosen Buffer Size is 0x%llx", buf_size); return buf_size; } @@ -235,8 +235,8 @@ payload_primary(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d ", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -259,7 +259,7 @@ payload_primary(void) /* Skip this test if no MIN BW supported MPAM memory node present in the system */ if (mbwmin_node_cnt == 0) { - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n %d MSC Memory Nodes support MBW Min Limit Partitioning", mbwmin_node_cnt); val_set_status(primary_pe_index, RESULT_SKIP(TEST_NUM, 01)); return; @@ -277,7 +277,7 @@ payload_primary(void) branch_to_test = &&exception_return; if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(primary_pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -350,15 +350,15 @@ payload_primary(void) } if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(ACS_PRINT_TEST, - "\n No MBWU Monitor found to validate the test. Skipping test", 0); + val_print(INFO, + "\n No MBWU Monitor found to validate the test. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); contend_flag = 0; return; } - val_print(ACS_PRINT_DEBUG, - "\n Using MBWU monitor to measure MBW during buffer copy", 0); + val_print(DEBUG, + "\n Using MBWU monitor to measure MBW during buffer copy"); /* configure MBWU Monitor for this memory resource node */ val_mpam_memory_configure_mbwumon(msc_index); @@ -372,18 +372,18 @@ payload_primary(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n Start Count = 0x%llx", start_count); + val_print(INFO, "\n Start Count = 0x%llx", start_count); /* perform memory operation */ val_memcpy((void *)src_buf, (void *)dest_buf, buf_size); /* Wait for some time before the memcpy settles and counters update */ val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n End Count = 0x%llx", end_count); + val_print(INFO, "\n End Count = 0x%llx", end_count); /* read the memory bandwidth usage monitor */ counter[msc_index][rsrc_index][scenario_cnt] = end_count - start_count; - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n Byte count = 0x%llx", end_count - start_count); /* disable and reset the MBWU monitor */ @@ -428,19 +428,19 @@ payload_primary(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n Start Count = 0x%llx", start_count); + val_print(INFO, "\n Start Count = 0x%llx", start_count); /* perform memory operation */ val_memcpy((void *)src_buf, (void *)dest_buf, buf_size); /* Wait for some time before the memcpy settles and counters update */ val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n End Count = 0x%llx", end_count); + val_print(INFO, "\n End Count = 0x%llx", end_count); /* read the memory bandwidth usage monitor */ counter[msc_index][rsrc_index][scenario_cnt] = end_count - start_count; - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n Byte Count = 0x%llx", end_count - start_count); /* disable and reset the MBWU monitor */ @@ -477,7 +477,7 @@ payload_primary(void) scenario_cnt = 0; if (counter[msc_index][rsrc_index][scenario_cnt] < counter[msc_index][rsrc_index][scenario_cnt + 1]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); val_set_status(primary_pe_index, RESULT_FAIL(TEST_NUM, 05)); return; } diff --git a/test_pool/mpam/mem003.c b/test_pool/mpam/mem003.c index 18c6f190..0e349b85 100644 --- a/test_pool/mpam/mem003.c +++ b/test_pool/mpam/mem003.c @@ -51,15 +51,15 @@ get_buffer_size(uint32_t msc_index, uint32_t rsrc_index, uint64_t addr_len, uint membw = val_mpam_msc_get_mscbw(msc_index, rsrc_index); if (membw == HMAT_INVALID_INFO) { - val_print(ACS_PRINT_WARN, "\n Using default buffer sizes for memcpy", 0); + val_print(WARN, "\n Using default buffer sizes for memcpy"); buffer_size = mbwmax_config_data[index].memcopy_size; - val_print(ACS_PRINT_WARN, " buffer_size: %llx", buffer_size); + val_print(WARN, " buffer_size: %llx", buffer_size); return buffer_size; } - val_print(ACS_PRINT_DEBUG, "\n Channel BW - %d MB/s", membw); + val_print(DEBUG, "\n Channel BW - %d MB/s", membw); limited_bw = membw / (mbwmax_config_data[index].partition_percent); - val_print(ACS_PRINT_DEBUG, "\n Restricting Channel BW to %d MB/s", limited_bw); + val_print(DEBUG, "\n Restricting Channel BW to %d MB/s", limited_bw); /* Calculate required buffer to index 0 and use the same for other variations of partition percentage */ @@ -68,11 +68,11 @@ get_buffer_size(uint32_t msc_index, uint32_t rsrc_index, uint64_t addr_len, uint else buffer_size = mbwmax_config_data[0].memcopy_size; - val_print(ACS_PRINT_DEBUG, "\n Buffer Size - 0x%llx", buffer_size); + val_print(DEBUG, "\n Buffer Size - 0x%llx", buffer_size); /* Check if this buffer is possible to allocate */ if (addr_len < (2 * buffer_size)) { - val_print(ACS_PRINT_WARN, "\n Insufficient buffer size to validate the test", 0); + val_print(WARN, "\n Insufficient buffer size to validate the test"); return ACS_STATUS_SKIP; } @@ -112,8 +112,8 @@ void payload(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d ", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -134,7 +134,7 @@ void payload(void) minmax_partid = GET_MIN_VALUE(minmax_partid, val_mpam_get_max_partid(msc_index)); } - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n %d MSC Memory Nodes support MBW Max Limit Partitioning", mbwmax_node_cnt); /* Skip this test if no MBWMAX supported MSC present in the system */ @@ -143,7 +143,7 @@ void payload(void) return; } - val_print(ACS_PRINT_DEBUG, "\n MinMax PARTID = %d\n", minmax_partid); + val_print(DEBUG, "\n MinMax PARTID = %d\n", minmax_partid); /* Disable all types of partitioning for all other nodes */ for (msc_index = 0; msc_index < total_nodes; msc_index++) { @@ -187,7 +187,7 @@ void payload(void) /* Iterate through various partition settings and gather latency/MBWU monitor count for each */ for (index = 0; index < sizeof(mbwmax_config_data)/sizeof(mbwmaxconfig_t); index++) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Programming MSC with %d percent of Max BW Limit partitioning", mbwmax_config_data[index].partition_percent); @@ -198,13 +198,13 @@ void payload(void) if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) != MPAM_RSRC_TYPE_MEMORY) { - val_print(ACS_PRINT_WARN, "\n MSC %d not a memory node. Skipping MSC", + val_print(WARN, "\n MSC %d not a memory node. Skipping MSC", msc_index); continue; } - val_print(ACS_PRINT_DEBUG, "\n MSC Index: %d", msc_index); - val_print(ACS_PRINT_DEBUG, " RIS Index: %d", rsrc_index); + val_print(DEBUG, "\n MSC Index: %d", msc_index); + val_print(DEBUG, " RIS Index: %d", rsrc_index); if (val_mpam_msc_supports_ris(msc_index)) val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); @@ -230,8 +230,8 @@ void payload(void) addr_base = val_mpam_memory_get_base(msc_index, rsrc_index); addr_len = val_mpam_memory_get_size(msc_index, rsrc_index); - val_print(ACS_PRINT_DEBUG, "\n addr_base is %llx", addr_base); - val_print(ACS_PRINT_DEBUG, "\n addr_len is %llx", addr_len); + val_print(DEBUG, "\n addr_base is %llx", addr_base); + val_print(DEBUG, "\n addr_len is %llx", addr_len); buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { @@ -241,7 +241,7 @@ void payload(void) if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * buf_size)) { /* src and dst buffer size */ - val_print(ACS_PRINT_ERR, "\n No SRAT mem range info found", 0); + val_print(ERROR, "\n No SRAT mem range info found"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); /* Restore MPAM2_EL2 settings */ @@ -253,7 +253,7 @@ void payload(void) dest_buf = (void *)val_mem_alloc_at_address(addr_base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Memory allocation of buffers failed", 0); + val_print(ERROR, "\n Memory allocation of buffers failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); /* Restore MPAM2_EL2 settings */ @@ -262,14 +262,14 @@ void payload(void) } if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(ACS_PRINT_TEST, - "\n No MBWU Monitor found to validate the test. Skipping test", 0); + val_print(INFO, + "\n No MBWU Monitor found to validate the test. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); return; } - val_print(ACS_PRINT_DEBUG, - "\n Using MBWU monitor to measure MBW count during buffer copy", 0); + val_print(DEBUG, + "\n Using MBWU monitor to measure MBW count during buffer copy"); /* configure MBWU Monitor for this memory resource node */ val_mpam_memory_configure_mbwumon(msc_index); @@ -284,7 +284,7 @@ void payload(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n Start count is %llx", start_count); + val_print(INFO, "\n Start count is %llx", start_count); /* perform memory operation */ val_memcpy(src_buf, dest_buf, buf_size); @@ -296,7 +296,7 @@ void payload(void) }; end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(ACS_PRINT_TEST, "\n End count is %llx", end_count); + val_print(INFO, "\n End count is %llx", end_count); /* read the memory bandwidth usage monitor */ counter[enabled_scenarios++][msc_index][rsrc_index] = @@ -306,7 +306,7 @@ void payload(void) val_mpam_memory_mbwumon_disable(msc_index); val_mpam_memory_mbwumon_reset(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n byte_count = 0x%llx bytes", end_count - start_count); /* Free the buffers to the heap manager */ @@ -333,8 +333,8 @@ void payload(void) if (val_mpam_msc_supports_mbw_max(msc_index)) { if (counter[index][msc_index][rsrc_index] > counter[index-1][msc_index][rsrc_index]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", index); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n cfg_index : %d", index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/mpam/monitor001.c b/test_pool/mpam/monitor001.c index 2dc5a59b..97ae13ed 100644 --- a/test_pool/mpam/monitor001.c +++ b/test_pool/mpam/monitor001.c @@ -61,7 +61,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -69,7 +69,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -105,11 +105,11 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CPOR Nodes = %d", cpor_nodes); - val_print(ACS_PRINT_DEBUG, "\n Max PMG = %d", max_pmg); - val_print(ACS_PRINT_DEBUG, "\n Test PARTID = %d", test_partid); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CPOR Nodes = %d", cpor_nodes); + val_print(DEBUG, "\n Max PMG = %d", max_pmg); + val_print(DEBUG, "\n Test PARTID = %d", test_partid); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ @@ -184,10 +184,10 @@ static void payload(void) src_buf = (void *)val_memory_alloc_pages(num_pages); dest_buf = (void *)val_memory_alloc_pages(num_pages); - val_print(ACS_PRINT_DEBUG, "\n buf_size = 0x%x", buf_size); + val_print(DEBUG, "\n buf_size = 0x%x", buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -201,7 +201,7 @@ static void payload(void) val_mpam_configure_csu_mon(msc_index, test_partid, pmg1, 0); storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -219,7 +219,7 @@ static void payload(void) /* Read Cache storage value */ storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); val_pe_cache_invalidate_range((uint64_t)dest_buf, buf_size); @@ -231,7 +231,7 @@ static void payload(void) /* Read Cache storage value */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -249,7 +249,7 @@ static void payload(void) /* Read Cache storage value for PMG2 */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); /* Disable the monitor */ val_mpam_csumon_disable(msc_index); diff --git a/test_pool/mpam/monitor002.c b/test_pool/mpam/monitor002.c index c68fa103..ae10514f 100644 --- a/test_pool/mpam/monitor002.c +++ b/test_pool/mpam/monitor002.c @@ -61,7 +61,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -69,7 +69,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -105,11 +105,11 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CCAP Nodes = %d", ccap_nodes); - val_print(ACS_PRINT_DEBUG, "\n Max PMG = %d", max_pmg); - val_print(ACS_PRINT_DEBUG, "\n Test PARTID = %d", test_partid); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CCAP Nodes = %d", ccap_nodes); + val_print(DEBUG, "\n Max PMG = %d", max_pmg); + val_print(DEBUG, "\n Test PARTID = %d", test_partid); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ @@ -184,10 +184,10 @@ static void payload(void) src_buf = (void *)val_memory_alloc_pages(num_pages); dest_buf = (void *)val_memory_alloc_pages(num_pages); - val_print(ACS_PRINT_DEBUG, "\n buf_size = 0x%x", buf_size); + val_print(DEBUG, "\n buf_size = 0x%x", buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (src_buf != NULL) val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); @@ -209,7 +209,7 @@ static void payload(void) val_mpam_configure_csu_mon(msc_index, test_partid, pmg1, 0); storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -227,7 +227,7 @@ static void payload(void) /* Read Cache storage value */ storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); val_pe_cache_invalidate_range((uint64_t)dest_buf, buf_size); @@ -239,7 +239,7 @@ static void payload(void) /* Read Cache storage value */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -257,7 +257,7 @@ static void payload(void) /* Read Cache storage value for PMG2 */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); /* Disable the monitor */ val_mpam_csumon_disable(msc_index); diff --git a/test_pool/mpam/monitor003.c b/test_pool/mpam/monitor003.c index 925f2b78..3817faa8 100644 --- a/test_pool/mpam/monitor003.c +++ b/test_pool/mpam/monitor003.c @@ -60,7 +60,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -68,7 +68,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -101,9 +101,9 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CPOR Nodes = %d", cpor_nodes); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CPOR Nodes = %d", cpor_nodes); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ @@ -178,10 +178,10 @@ static void payload(void) src_buf = (void *)val_memory_alloc_pages(num_pages); dest_buf = (void *)val_memory_alloc_pages(num_pages); - val_print(ACS_PRINT_DEBUG, "\n buf_size = 0x%x", buf_size); + val_print(DEBUG, "\n buf_size = 0x%x", buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); @@ -195,7 +195,7 @@ static void payload(void) val_mpam_configure_csu_mon(msc_index, partid1, DEFAULT_PMG, 0); storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -213,7 +213,7 @@ static void payload(void) /* Read Cache storage value */ storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); val_pe_cache_invalidate_range((uint64_t)dest_buf, buf_size); @@ -225,7 +225,7 @@ static void payload(void) /* Read Cache storage value */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -243,7 +243,7 @@ static void payload(void) /* Read Cache storage value for PMG2 */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); /* Disable the monitor */ val_mpam_csumon_disable(msc_index); diff --git a/test_pool/mpam/monitor004.c b/test_pool/mpam/monitor004.c index 7bdcd840..060e73ee 100644 --- a/test_pool/mpam/monitor004.c +++ b/test_pool/mpam/monitor004.c @@ -59,7 +59,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -67,7 +67,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -100,9 +100,9 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CCAP Nodes = %d", ccap_nodes); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CCAP Nodes = %d", ccap_nodes); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ @@ -178,10 +178,10 @@ static void payload(void) src_buf = (void *)val_memory_alloc_pages(num_pages); dest_buf = (void *)val_memory_alloc_pages(num_pages); - val_print(ACS_PRINT_DEBUG, "\n buf_size = 0x%x", buf_size); + val_print(DEBUG, "\n buf_size = 0x%x", buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); @@ -195,7 +195,7 @@ static void payload(void) val_mpam_configure_csu_mon(msc_index, partid1, DEFAULT_PMG, 0); storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Initial Value 1 = 0x%x", storage_value1); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -213,7 +213,7 @@ static void payload(void) /* Read Cache storage value */ storage_value1 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); + val_print(DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); val_pe_cache_invalidate_range((uint64_t)dest_buf, buf_size); @@ -225,7 +225,7 @@ static void payload(void) /* Read Cache storage value */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Initial Value 2 = 0x%x", storage_value2); /* Enable CSU monitoring */ val_mpam_csumon_enable(msc_index); @@ -243,7 +243,7 @@ static void payload(void) /* Read Cache storage value for PMG2 */ storage_value2 = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); + val_print(DEBUG, "\n Storage Value 2 = 0x%x", storage_value2); /* Disable the monitor */ val_mpam_csumon_disable(msc_index); diff --git a/test_pool/mpam/monitor005.c b/test_pool/mpam/monitor005.c index ee37f0d0..2bf668ec 100644 --- a/test_pool/mpam/monitor005.c +++ b/test_pool/mpam/monitor005.c @@ -55,7 +55,7 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n No LLC found, skipping test", 0); + val_print(DEBUG, "\n No LLC found, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -63,7 +63,7 @@ payload(void) /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n Invalid LLC ID, skipping test", 0); + val_print(DEBUG, "\n Invalid LLC ID, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -72,7 +72,7 @@ payload(void) for (msc_index = 0; msc_index < msc_cnt; msc_index++) { max_partid = val_mpam_get_max_partid(msc_index); if (max_partid == 0) { - val_print(ACS_PRINT_DEBUG, "\n MSC %d has no PARTID support", msc_index); + val_print(DEBUG, "\n MSC %d has no PARTID support", msc_index); continue; } @@ -81,7 +81,7 @@ payload(void) GET_MIN_VALUE(test_partid, max_partid - 1); } - val_print(ACS_PRINT_TEST, "\n Selected PARTID = %d", test_partid); + val_print(INFO, "\n Selected PARTID = %d", test_partid); /* Iterate through all available LLC MSCs and their resources */ for (msc_index = 0; msc_index < msc_cnt; msc_index++) { @@ -110,7 +110,7 @@ payload(void) num_mon = val_mpam_get_csumon_count(msc_index); if (num_mon == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not have CSU monitors, skipping MSC", msc_index); continue; } @@ -130,7 +130,7 @@ payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); @@ -157,7 +157,7 @@ payload(void) /* Program MPAM2_EL2 with test_partid and default PMG */ status = val_mpam_program_el2(test_partid, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -171,7 +171,7 @@ payload(void) val_time_delay_ms(100 * ONE_MILLISECOND); start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, BUFFER_SIZE); @@ -182,12 +182,12 @@ payload(void) val_time_delay_ms(100 * ONE_MILLISECOND); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); if (start_count != end_count) { - val_print(ACS_PRINT_ERR, "\n Unexpected cache usage behavior observed", 0); - val_print(ACS_PRINT_ERR, "\n Start count = 0x%lx", start_count); - val_print(ACS_PRINT_ERR, "\n End count = 0x%lx", end_count); + val_print(ERROR, "\n Unexpected cache usage behavior observed"); + val_print(ERROR, "\n Start count = 0x%lx", start_count); + val_print(ERROR, "\n End count = 0x%lx", end_count); test_fail++; } @@ -198,14 +198,14 @@ payload(void) if (TEST_CSUMON_VALUE != end_count) { /* Fail the test */ - val_print(ACS_PRINT_ERR, "\n Unexpected CSUMON Value after Write", 0); - val_print(ACS_PRINT_ERR, "\n Expected = 0x%lx", TEST_CSUMON_VALUE); - val_print(ACS_PRINT_ERR, "\n Found = 0x%lx", end_count); + val_print(ERROR, "\n Unexpected CSUMON Value after Write"); + val_print(ERROR, "\n Expected = 0x%lx", TEST_CSUMON_VALUE); + val_print(ERROR, "\n Found = 0x%lx", end_count); test_fail++; } } else { /* CSU is Read Only, Skipping CSUMON Value RW Check */ - val_print(ACS_PRINT_DEBUG, "\n CSU Read Only, Skipping Write Check", 0); + val_print(DEBUG, "\n CSU Read Only, Skipping Write Check"); } /* Restore MPAM2_EL2 settings */ diff --git a/test_pool/mpam/monitor006.c b/test_pool/mpam/monitor006.c index 61ce83fb..78be64cd 100644 --- a/test_pool/mpam/monitor006.c +++ b/test_pool/mpam/monitor006.c @@ -61,7 +61,7 @@ mbwu_prepare_overflow(uint32_t msc_index, void *src_buf, void *dest_buf, uint64_ val_mpam_mbwu_wait_for_update(msc_index); if (!val_mpam_mbwu_is_overflow_set(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not set during setup for MSC %d", msc_index); goto exit_fail; } @@ -98,7 +98,7 @@ payload(void) /* Program MPAM2_EL2 with DEFAULT_PARTID and default PMG */ status = val_mpam_program_el2(DEFAULT_PARTID, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); test_fail++; test_skip = 0; goto cleanup; @@ -131,7 +131,7 @@ payload(void) if ((mem_base == SRAT_INVALID_INFO) || (mem_size == SRAT_INVALID_INFO) || (mem_size <= 2 * buf_size)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d memory range invalid for MBWU test", msc_index); continue; } @@ -142,7 +142,7 @@ payload(void) src_buf = (void *)val_mem_alloc_at_address(mem_base, buf_size); dest_buf = (void *)val_mem_alloc_at_address(mem_base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed for MSC %d", msc_index); + val_print(ERROR, "\n Mem allocation failed for MSC %d", msc_index); test_fail++; goto cleanup; } @@ -154,7 +154,7 @@ payload(void) /* Ensure software clear deasserts overflow indication */ if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared for MSC %d", msc_index); test_fail++; } diff --git a/test_pool/mpam/monitor007.c b/test_pool/mpam/monitor007.c index eff8bdde..7d596dfc 100644 --- a/test_pool/mpam/monitor007.c +++ b/test_pool/mpam/monitor007.c @@ -72,7 +72,7 @@ payload(void) /* Program MPAM2_EL2 with DEFAULT_PARTID and default PMG */ status = val_mpam_program_el2(DEFAULT_PARTID, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); test_fail++; test_skip = 0; goto cleanup; @@ -105,7 +105,7 @@ payload(void) if ((mem_base == SRAT_INVALID_INFO) || (mem_size == SRAT_INVALID_INFO) || (mem_size <= 2 * buf_size)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d memory range invalid for OFLOW_FRZ test", msc_index); continue; } @@ -116,7 +116,7 @@ payload(void) src_buf = (void *)val_mem_alloc_at_address(mem_base, buf_size); dest_buf = (void *)val_mem_alloc_at_address(mem_base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed for MSC %d", msc_index); + val_print(ERROR, "\n Mem allocation failed for MSC %d", msc_index); test_fail++; goto cleanup; } @@ -145,7 +145,7 @@ payload(void) val_mpam_mbwu_wait_for_update(msc_index); if (!val_mpam_mbwu_is_overflow_set(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not set for MSC %d with freeze set", msc_index); test_fail++; goto post_freeze_cleanup; @@ -154,7 +154,7 @@ payload(void) freeze_overflow_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (freeze_overflow_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after overflow for MSC %d", msc_index); test_fail++; goto post_freeze_cleanup; @@ -168,7 +168,7 @@ payload(void) freeze_post_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Compare Count when OFLOW_FRZ is set */ if (freeze_post_count != freeze_overflow_count) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Counter changed with OFLOW_FRZ=1 for MSC %d", msc_index); test_fail++; } @@ -176,7 +176,7 @@ payload(void) post_freeze_cleanup: /* Return Overflow Status */ if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared for MSC %d", msc_index); test_fail++; } @@ -206,7 +206,7 @@ payload(void) val_mpam_mbwu_wait_for_update(msc_index); if (!val_mpam_mbwu_is_overflow_set(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not set for MSC %d with freeze cleared", msc_index); test_fail++; goto post_run_cleanup; @@ -215,7 +215,7 @@ payload(void) run_overflow_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (run_overflow_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready post overflow (freeze=0) for MSC %d", msc_index); test_fail++; goto post_run_cleanup; @@ -229,12 +229,12 @@ payload(void) run_post_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (run_post_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after extra traffic (freeze=0) for MSC %d", msc_index); test_fail++; } else if (run_post_count == run_overflow_count) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Counter did not advance with OFLOW_FRZ=0 for MSC %d", msc_index); test_fail++; } @@ -242,7 +242,7 @@ payload(void) post_run_cleanup: /* Return Overflow Status */ if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared (freeze=0) for MSC %d", msc_index); test_fail++; } diff --git a/test_pool/mpam/monitor008.c b/test_pool/mpam/monitor008.c index c898e75f..348548c3 100644 --- a/test_pool/mpam/monitor008.c +++ b/test_pool/mpam/monitor008.c @@ -73,7 +73,7 @@ mbwu_prepare_overflow(uint32_t msc_index, void *src_buf, void *dest_buf, uint64_ val_mpam_mbwu_wait_for_update(msc_index); if (!val_mpam_mbwu_is_overflow_set(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not set during setup for MSC %d", msc_index); goto exit_fail; } @@ -112,7 +112,7 @@ payload(void) /* Program MPAM2_EL2 with DEFAULT_PARTID and default PMG */ status = val_mpam_program_el2(DEFAULT_PARTID, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); test_skip = 0; test_fail++; goto cleanup; @@ -143,7 +143,7 @@ payload(void) if ((mem_base == SRAT_INVALID_INFO) || (mem_size == SRAT_INVALID_INFO) || (mem_size <= 2 * buf_size)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d memory range invalid for MBWU test", msc_index); continue; } @@ -153,7 +153,7 @@ payload(void) src_buf = (void *)val_mem_alloc_at_address(mem_base, buf_size); dest_buf = (void *)val_mem_alloc_at_address(mem_base + buf_size, buf_size); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed for MSC %d", msc_index); + val_print(ERROR, "\n Mem allocation failed for MSC %d", msc_index); test_fail++; goto cleanup; } @@ -166,7 +166,7 @@ payload(void) /* Clear overflow via control register and ensure counter resumes */ if (val_mpam_mbwu_clear_overflow_status(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared via control write for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -176,7 +176,7 @@ payload(void) post_clear_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (post_clear_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after clearing via control write for MSC %d", msc_index); test_fail++; @@ -192,13 +192,13 @@ payload(void) resumed_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (resumed_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after resume traffic (control clear) for MSC %d", msc_index); test_fail++; goto monitor_cleanup; } else if (resumed_count <= post_clear_count) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Counter did not advance after control clear for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -218,7 +218,7 @@ payload(void) val_mpam_mbwu_wait_for_update(msc_index); if (val_mpam_mbwu_is_overflow_set(msc_index)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Overflow status not cleared by counter write for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -227,7 +227,7 @@ payload(void) post_clear_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (post_clear_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after counter write for MSC %d", msc_index); test_fail++; goto monitor_cleanup; @@ -242,12 +242,12 @@ payload(void) resumed_count = val_mpam_memory_mbwumon_read_count(msc_index); /* Check if Monitor Read Failed */ if (resumed_count == (uint64_t)MPAM_MON_NOT_READY) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Monitor not ready after resume traffic (counter write) for MSC %d", msc_index); test_fail++; } else if (resumed_count <= post_clear_count) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Counter did not advance after counter write clear for MSC %d", msc_index); test_fail++; diff --git a/test_pool/mpam/mpam002.c b/test_pool/mpam/mpam002.c index 9133678b..c6cdad4b 100644 --- a/test_pool/mpam/mpam002.c +++ b/test_pool/mpam/mpam002.c @@ -46,7 +46,7 @@ static uint32_t get_llc_msc_index(void) /* If parsing had passed in last call, return the cached value */ if (llc_msc_index != LLC_MSC_INDEX_UNKNOWN) { - val_print(ACS_PRINT_DEBUG, "\n Returning parsed LLC MPAM MSC index = %d", + val_print(DEBUG, "\n Returning parsed LLC MPAM MSC index = %d", llc_msc_index); return llc_msc_index; } @@ -55,33 +55,33 @@ static uint32_t get_llc_msc_index(void) /* Re-run even if previous parse was failed for ERROR prints */ /* Find the LLC cache identifier */ - val_print(ACS_PRINT_DEBUG, "\n Parsing for LLC MPAM MSC index", 0); + val_print(DEBUG, "\n Parsing for LLC MPAM MSC index"); llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); return LLC_MSC_INDEX_UNKNOWN; } cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); return LLC_MSC_INDEX_UNKNOWN; } /* Check in the MPAM table which MSC is attached to the LLC */ msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { - val_print(ACS_PRINT_ERR, "\n MPAM MSC count is zero", 0); + val_print(ERROR, "\n MPAM MSC count is zero"); return LLC_MSC_INDEX_UNKNOWN; } /* visit each MSC node and check for cache resources */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n MSC index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n MSC index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { /* check whether the resource location is cache */ if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == @@ -89,8 +89,8 @@ static uint32_t get_llc_msc_index(void) if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == cache_identifier) { /* We have MSC which controls/monitors the LLC cache */ - val_print(ACS_PRINT_DEBUG, "\n Resource index = %d", rsrc_index); - val_print(ACS_PRINT_DEBUG, "\n MSC index of LLC = %d", msc_index); + val_print(DEBUG, "\n Resource index = %d", rsrc_index); + val_print(DEBUG, "\n MSC index of LLC = %d", msc_index); /* Store the LLC MSC index in static variable */ llc_msc_index = msc_index; @@ -116,14 +116,14 @@ static void payload_check_mpam_llc_csu_support(void) /* Check if msc_index in valid, else mark test as FAIL */ if (llc_msc_index == LLC_MSC_INDEX_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n MSC on LLC not found ", 0); + val_print(ERROR, "\n MSC on LLC not found "); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } /* Check if LLC supports CSU monitor */ if (!val_mpam_supports_csumon(llc_msc_index)) { - val_print(ACS_PRINT_ERR, "\n CSU MON unsupported by LLC", 0); + val_print(ERROR, "\n CSU MON unsupported by LLC"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } else { @@ -144,7 +144,7 @@ static void payload_check_llc_csu_mon_count(void) /* Check if msc_index in valid, else mark test as FAIL */ if (llc_msc_index == LLC_MSC_INDEX_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n MSC on LLC not found ", 0); + val_print(ERROR, "\n MSC on LLC not found "); val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); return; } @@ -152,7 +152,7 @@ static void payload_check_llc_csu_mon_count(void) /* Check if atleast 16 CSU monitor are present */ csumon_count = val_mpam_get_csumon_count(llc_msc_index); if (csumon_count < 16) { - val_print(ACS_PRINT_ERR, "\n CSU MON %d less than 16", csumon_count); + val_print(ERROR, "\n CSU MON %d less than 16", csumon_count); val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); return; } else { diff --git a/test_pool/mpam/mpam003.c b/test_pool/mpam/mpam003.c index fcd3fc36..2222c5e3 100644 --- a/test_pool/mpam/mpam003.c +++ b/test_pool/mpam/mpam003.c @@ -58,7 +58,7 @@ static void payload(void) /* get total number of MSCs reported by MPAM ACPI table */ msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (!msc_node_cnt) { val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); @@ -75,15 +75,15 @@ static void payload(void) mpam2_el2 = (mpam2_el2 & ~(MPAMn_ELx_PMG_D_MASK << MPAMn_ELx_PMG_D_SHIFT)) | DEFAULT_PMG << MPAMn_ELx_PMG_D_SHIFT; - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAM2_EL2 = 0x%llx", mpam2_el2); + val_print(DEBUG, "\n Value written to MPAM2_EL2 = 0x%llx", mpam2_el2); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); /* visit each MSC node and check for memory resources */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -93,7 +93,7 @@ static void payload(void) /* As per S_L7MP_05, MBWU monitoring must be supported for general purpose mem */ if (!val_mpam_msc_supports_mbwumon(msc_index)) { - val_print(ACS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + val_print(ERROR, "\n MBWU MON unsupported by MSC %d", msc_index); test_fails++; break; } @@ -103,7 +103,7 @@ static void payload(void) if (val_mpam_msc_supports_ris(msc_index)) val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); - val_print(ACS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + val_print(DEBUG, "\n rsrc index = %d", rsrc_index); /* Allocate source and destination memory buffers*/ addr_base = val_mpam_memory_get_base(msc_index, rsrc_index); @@ -111,7 +111,7 @@ static void payload(void) if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * BUFFER_SIZE)) { /* src and dst buffer size */ - val_print(ACS_PRINT_ERR, "\n No SRAT mem range info found", 0); + val_print(ERROR, "\n No SRAT mem range info found"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); /* Restore MPAM2_EL2 settings */ @@ -124,7 +124,7 @@ static void payload(void) dest_buf = (void *)val_mem_alloc_at_address(addr_base + BUFFER_SIZE, BUFFER_SIZE); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Memory allocation of buffers failed", 0); + val_print(ERROR, "\n Memory allocation of buffers failed"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); /* Restore MPAM2_EL2 settings */ @@ -155,7 +155,7 @@ static void payload(void) val_mpam_memory_mbwumon_disable(msc_index); val_mpam_memory_mbwumon_reset(msc_index); - val_print(ACS_PRINT_DEBUG, "\n byte_count = 0x%llx bytes", byte_count); + val_print(DEBUG, "\n byte_count = 0x%llx bytes", byte_count); /* the monitor must count both read and write bandwidth, hence count must be twice of the buffer size @@ -164,9 +164,9 @@ static void payload(void) /* Report fail if the monitor count does not belong within permitted range */ if (!((byte_count > byte_count_min) && (byte_count <= 2 * BUFFER_SIZE))) { - val_print(ACS_PRINT_ERR, "\n Monitor count incorrect for MSC %d", + val_print(ERROR, "\n Monitor count incorrect for MSC %d", msc_index); - val_print(ACS_PRINT_ERR, " rsrc node %d", rsrc_index); + val_print(ERROR, " rsrc node %d", rsrc_index); test_fails++; } diff --git a/test_pool/mpam/mpam004.c b/test_pool/mpam/mpam004.c index 9ba261de..a7beac5d 100644 --- a/test_pool/mpam/mpam004.c +++ b/test_pool/mpam/mpam004.c @@ -50,7 +50,7 @@ static void payload(void) /* get total number of MSCs reported by MPAM ACPI table */ msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (!msc_node_cnt) { val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); @@ -61,8 +61,8 @@ static void payload(void) for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -72,7 +72,7 @@ static void payload(void) /* As per S_L7MP_05, MBWU monitoring must be supported for general purpose mem */ if (!val_mpam_msc_supports_mbwumon(msc_index)) { - val_print(ACS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + val_print(ERROR, "\n MBWU MON unsupported by MSC %d", msc_index); test_fails++; break; } @@ -83,25 +83,25 @@ static void payload(void) else 66 bit. Check MBWUMON_IDR HAS_LONG[30] and LWD[29] bits. The reg is present only if mbwumon is supported */ if (!val_mpam_msc_supports_mbwumon(msc_index)) { - val_print(ACS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + val_print(ERROR, "\n MBWU MON unsupported by MSC %d", msc_index); test_fails++; break; } if (!val_mpam_mbwu_supports_long(msc_index)) { - val_print(ACS_PRINT_ERR, "\n MBWU long unsupported MSC %d", msc_index); + val_print(ERROR, "\n MBWU long unsupported MSC %d", msc_index); test_fails++; break; } mbwu_bw = val_mpam_msc_get_mscbw(msc_index, rsrc_index); if (mbwu_bw == HMAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n No HMAT info ", 0); + val_print(ERROR, "\n No HMAT info "); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } if ((val_mpam_mbwu_supports_lwd(msc_index) == MBWU_COUNTER_44BIT) && (mbwu_bw >= MAX_44BIT_COUNTER_BW)) { - val_print(ACS_PRINT_ERR, "\n MBWU supported b/w %d", mbwu_bw); + val_print(ERROR, "\n MBWU supported b/w %d", mbwu_bw); test_fails++; break; } diff --git a/test_pool/mpam/mpam005.c b/test_pool/mpam/mpam005.c index c93b9fe3..9e7def2b 100644 --- a/test_pool/mpam/mpam005.c +++ b/test_pool/mpam/mpam005.c @@ -41,7 +41,7 @@ static void payload(void) msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); @@ -57,8 +57,8 @@ static void payload(void) msc_addr1 = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index1, 0); if (msc_addr1 >= msc_addr && msc_addr1 <= (msc_addr + msc_len)) { - val_print(ACS_PRINT_ERR, "\n MSC %d and", msc_index); - val_print(ACS_PRINT_ERR, " %d memory layout overlapping", msc_index1); + val_print(ERROR, "\n MSC %d and", msc_index); + val_print(ERROR, " %d memory layout overlapping", msc_index1); test_fails++; } } @@ -67,11 +67,11 @@ static void payload(void) peri_count = val_peripheral_get_info(NUM_USB, 0); while (peri_count) { --peri_count; //array index starts from 0, so subtract 1 from count - val_print(ACS_PRINT_DEBUG, "\n USB index %d", peri_count); + val_print(DEBUG, "\n USB index %d", peri_count); peripheral_base = val_peripheral_get_info(USB_BASE0, peri_count); if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { - val_print(ACS_PRINT_ERR, "\n MSC %d and", msc_index); - val_print(ACS_PRINT_ERR, " USB %d memory layout overlapping", peri_count); + val_print(ERROR, "\n MSC %d and", msc_index); + val_print(ERROR, " USB %d memory layout overlapping", peri_count); test_fails++; } } @@ -81,11 +81,11 @@ static void payload(void) peri_count = val_peripheral_get_info(NUM_UART, 0); while (peri_count) { --peri_count; //array index starts from 0, so subtract 1 from count - val_print(ACS_PRINT_DEBUG, "\n UART index %d", peri_count); + val_print(DEBUG, "\n UART index %d", peri_count); peripheral_base = val_peripheral_get_info(UART_BASE0, peri_count); if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { - val_print(ACS_PRINT_ERR, "\n MSC %d and", msc_index); - val_print(ACS_PRINT_ERR, " UART %d memory layout overlapping", peri_count); + val_print(ERROR, "\n MSC %d and", msc_index); + val_print(ERROR, " UART %d memory layout overlapping", peri_count); test_fails++; } } @@ -94,11 +94,11 @@ static void payload(void) peri_count = val_peripheral_get_info(NUM_SATA, 0); while (peri_count) { --peri_count; //array index starts from 0, so subtract 1 from count - val_print(ACS_PRINT_DEBUG, "\n SATA index %d", peri_count); + val_print(DEBUG, "\n SATA index %d", peri_count); peripheral_base = val_peripheral_get_info(SATA_BASE0, peri_count); if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { - val_print(ACS_PRINT_ERR, "\n MSC %d and", msc_index); - val_print(ACS_PRINT_ERR, " SATA %d memory layout overlapping", peri_count); + val_print(ERROR, "\n MSC %d and", msc_index); + val_print(ERROR, " SATA %d memory layout overlapping", peri_count); test_fails++; } } diff --git a/test_pool/mpam/mpam006.c b/test_pool/mpam/mpam006.c index 9afefb78..bb705fdf 100644 --- a/test_pool/mpam/mpam006.c +++ b/test_pool/mpam/mpam006.c @@ -43,13 +43,13 @@ program_all_monitors_with_pmg(uint16_t partid, uint8_t pmg) uint32_t csumon_count = 0; uint32_t rsrc_node_cnt, rsrc_index; - val_print(ACS_PRINT_TEST, "\n Programming all MSCs to filter PMG value %d", pmg); + val_print(INFO, "\n Programming all MSCs to filter PMG value %d", pmg); for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -78,7 +78,7 @@ program_all_monitors_with_pmg(uint16_t partid, uint8_t pmg) /* Skip if the MSC's resource does not implement CSUMON or has max_pmg < programmable PMG */ if (csumon_count == 0 || max_pmg < pmg) { - val_print(ACS_PRINT_TEST, "\n Skipping MSC resource %d", rsrc_index); + val_print(INFO, "\n Skipping MSC resource %d", rsrc_index); continue; } @@ -99,13 +99,13 @@ set_status_for_all_csumon(uint32_t status) uint32_t csumon_count = 0; uint32_t nrdy_timeout = 0; - val_print(ACS_PRINT_DEBUG, "\n Setting CSUMON status of all MSC to %d", status); + val_print(DEBUG, "\n Setting CSUMON status of all MSC to %d", status); for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d ", rsrc_node_cnt); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -129,7 +129,7 @@ set_status_for_all_csumon(uint32_t status) continue; if (csumon_count == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skipping MSC resource %d", rsrc_index); + val_print(DEBUG, "\n Skipping MSC resource %d", rsrc_index); continue; } @@ -158,7 +158,7 @@ read_all_msc_csu_counters(uint32_t expected_count) uint32_t csumon_count; uint32_t storage_count; - val_print(ACS_PRINT_DEBUG, "\n Reading the CSUMON counter of all MSC", 0); + val_print(DEBUG, "\n Reading the CSUMON counter of all MSC"); for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); @@ -185,13 +185,13 @@ read_all_msc_csu_counters(uint32_t expected_count) continue; if (csumon_count == 0) { - val_print(ACS_PRINT_DEBUG, "\n Skipping MSC resource %d", rsrc_index); + val_print(DEBUG, "\n Skipping MSC resource %d", rsrc_index); continue; } storage_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n msc index = %d", msc_index); - val_print(ACS_PRINT_TEST, " storage count = %d", storage_count); + val_print(INFO, "\n msc index = %d", msc_index); + val_print(INFO, " storage count = %d", storage_count); /* Expected count || Storage count -> Status */ /* 0 || 0 -> 1 */ @@ -200,7 +200,7 @@ read_all_msc_csu_counters(uint32_t expected_count) /* 1 || 1 -> 1 */ if (!((expected_count && storage_count) || (!expected_count && !storage_count))) { - val_print(ACS_PRINT_ERR, "\n MSC Storage value mismatch. Failure!", 0); + val_print(ERROR, "\n MSC Storage value mismatch. Failure!"); fail_cnt++; } } @@ -226,7 +226,7 @@ payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -234,14 +234,14 @@ payload(void) /* Get the cache identifier for LLC */ llc_identifier = val_cache_get_info(CACHE_ID, llc_index); if (llc_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } /* Get total number of MSCs reported by MPAM ACPI table */ msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); @@ -253,7 +253,7 @@ payload(void) dest_buf = (void *)val_aligned_alloc(MEM_ALIGN_4K, BUFFER_SIZE); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); if (dest_buf != NULL) val_memory_free_aligned(dest_buf); @@ -278,7 +278,7 @@ payload(void) mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PMG_D_SHIFT+7, MPAMn_ELx_PMG_D_SHIFT); - val_print(ACS_PRINT_TEST, "\n Programming mpam2_el2 with PMG=0 %d", pmg0); + val_print(INFO, "\n Programming mpam2_el2 with PMG=0 %d", pmg0); mpam2_el2 |= (((uint64_t)pmg0 << MPAMn_ELx_PMG_D_SHIFT) | ((uint64_t)partid << MPAMn_ELx_PARTID_D_SHIFT)); @@ -314,7 +314,7 @@ payload(void) mpam2_el2 |= (((uint64_t)pmg1 << MPAMn_ELx_PMG_D_SHIFT) | ((uint64_t)partid << MPAMn_ELx_PARTID_D_SHIFT)); - val_print(ACS_PRINT_TEST, "\n Programming mpam2_el2 with PMG=1 %d", pmg1); + val_print(INFO, "\n Programming mpam2_el2 with PMG=1 %d", pmg1); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); diff --git a/test_pool/mpam/mpam007.c b/test_pool/mpam/mpam007.c index 4ee9fdcd..9154bedd 100644 --- a/test_pool/mpam/mpam007.c +++ b/test_pool/mpam/mpam007.c @@ -60,10 +60,10 @@ static void payload(void) /* If MPAM table not present, or no MSC found in table fail the test */ msc_node_cnt = val_mpam_get_msc_count(); - val_print(ACS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { - val_print(ACS_PRINT_ERR, "\n MSC count is 0", 0); + val_print(ERROR, "\n MSC count is 0"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -71,32 +71,32 @@ static void payload(void) /* Find the PPTT LLC cache identifier */ pptt_llc_index = val_cache_get_llc_index(); if (pptt_llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n PPTT table empty", 0); + val_print(DEBUG, "\n PPTT table empty"); } else { pptt_cache_id = val_cache_get_info(CACHE_ID, pptt_llc_index); if (pptt_cache_id == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n LLC invalid in PPTT", 0); + val_print(DEBUG, "\n LLC invalid in PPTT"); } else { /* visit each MSC node and check for PPTT cache resources */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n MSC index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n MSC index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); ris_supported = val_mpam_msc_supports_ris(msc_index); - val_print(ACS_PRINT_INFO, "\n RIS support = %d", ris_supported); + val_print(TRACE, "\n RIS support = %d", ris_supported); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { /* check whether the resource location is PPTT cache */ if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == MPAM_RSRC_TYPE_PE_CACHE) { - val_print(ACS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + val_print(DEBUG, "\n rsrc index = %d", rsrc_index); desc1 = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); /* match pptt llc cache id */ - val_print(ACS_PRINT_DEBUG, "\n rsrc descriptor 1 = %llx", desc1); + val_print(DEBUG, "\n rsrc descriptor 1 = %llx", desc1); if (desc1 == pptt_cache_id) { pptt_llc_msc_found = 1; /* Select resource instance if RIS feature implemented */ @@ -105,12 +105,12 @@ static void payload(void) /* Check CPOR are present */ if (val_mpam_supports_cpor(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n CPOR Supported by LLC for rsrc_index %d", rsrc_index); pptt_llc_cpor_supported = 1; break; } - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n CPOR Not Supported by LLC for rsrc_index %d", rsrc_index); } } @@ -122,33 +122,33 @@ static void payload(void) } if (!pptt_llc_msc_found) { - val_print(ACS_PRINT_DEBUG, "\n No MSC found on PPTT LLC", 0); + val_print(DEBUG, "\n No MSC found on PPTT LLC"); } else if (!pptt_llc_cpor_supported) { - val_print(ACS_PRINT_DEBUG, "\n CPOR unsupported by PPTT LLC", 0); + val_print(DEBUG, "\n CPOR unsupported by PPTT LLC"); } /* test mem-side cache for cpor support */ - val_print(ACS_PRINT_DEBUG, "\n\n Testing mem-side caches for CPOR support", 0); + val_print(DEBUG, "\n\n Testing mem-side caches for CPOR support"); pe_prox_domain = val_srat_get_info(SRAT_GICC_PROX_DOMAIN, val_pe_get_uid(index)); /* visit each MSC node and check for mem cache resources */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); - val_print(ACS_PRINT_DEBUG, "\n MSC index = %d", msc_index); - val_print(ACS_PRINT_DEBUG, "\n Resource count = %d", rsrc_node_cnt); + val_print(DEBUG, "\n MSC index = %d", msc_index); + val_print(DEBUG, "\n Resource count = %d", rsrc_node_cnt); ris_supported = val_mpam_msc_supports_ris(msc_index); - val_print(ACS_PRINT_INFO, "\n RIS support = %d", ris_supported); + val_print(TRACE, "\n RIS support = %d", ris_supported); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { /* check whether the resource type is a mem-cache */ if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == MPAM_RSRC_TYPE_MEM_SIDE_CACHE) { - val_print(ACS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + val_print(DEBUG, "\n rsrc index = %d", rsrc_index); desc1 = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); desc2 = val_mpam_get_info(MPAM_MSC_RSRC_DESC2, msc_index, rsrc_index); - val_print(ACS_PRINT_DEBUG, "\n rsrc descriptor 1 = %llx", desc1); - val_print(ACS_PRINT_DEBUG, "\n rsrc descriptor 2 = %llx", desc2); + val_print(DEBUG, "\n rsrc descriptor 1 = %llx", desc1); + val_print(DEBUG, "\n rsrc descriptor 2 = %llx", desc2); /* check if mem-side cache matches with PE proximity domain and cache level == 1 for mem-side LLC (based on assumption that @@ -162,13 +162,13 @@ static void payload(void) /* Check CPOR are present */ if (val_mpam_supports_cpor(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n CPOR Supported by mem-side cache with rsrc_index %d", rsrc_index); memside_llc_cpor_supported = 1; break; } - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n CPOR Not Supported by mem-side cache with rsrc_index %d", rsrc_index); } @@ -179,17 +179,17 @@ static void payload(void) } if (!mem_llc_msc_found) { - val_print(ACS_PRINT_DEBUG, "\n No MSC found on mem-side LLC", 0); + val_print(DEBUG, "\n No MSC found on mem-side LLC"); } else if (!memside_llc_cpor_supported) { - val_print(ACS_PRINT_DEBUG, "\n CPOR unsupported by mem-side LLC", 0); + val_print(DEBUG, "\n CPOR unsupported by mem-side LLC"); } /* if both PPTT LLC and mem-side cache MSCs found, read user input to know which should be considered as Last level System Cache */ if (pptt_llc_msc_found && mem_llc_msc_found) { if (g_sys_last_lvl_cache == SLC_TYPE_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n PPTT and memside LLC MSC found, Please provide" - "System Last-Level cache info via -slc cmdline option \n", 0); + val_print(ERROR, "\n PPTT and memside LLC MSC found, Please provide" + "System Last-Level cache info via -slc cmdline option \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } else if (g_sys_last_lvl_cache == SLC_TYPE_PPTT_CACHE && pptt_llc_cpor_supported) { @@ -200,7 +200,7 @@ static void payload(void) return; } else { val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); - val_print(ACS_PRINT_ERR, "\n CPOR unsupported by System last-level cache", 0); + val_print(ERROR, "\n CPOR unsupported by System last-level cache"); return; } } diff --git a/test_pool/mpam/partition001.c b/test_pool/mpam/partition001.c index 57e8afcf..b2ac9799 100644 --- a/test_pool/mpam/partition001.c +++ b/test_pool/mpam/partition001.c @@ -73,7 +73,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -81,7 +81,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -111,10 +111,10 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CPOR Nodes = %d", cpor_nodes); - val_print(ACS_PRINT_DEBUG, "\n Test PARTID = %d", test_partid); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CPOR Nodes = %d", cpor_nodes); + val_print(DEBUG, "\n Test PARTID = %d", test_partid); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if ((cpor_nodes == 0) || (csumon_count == 0)) { @@ -151,8 +151,8 @@ static void payload(void) if (cpor_config_data[cfg_index].config_enable) { /* Configure CPOR settings for nodes supporting CPOR */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { - val_print(ACS_PRINT_DEBUG, "\n Running for cfg_index = %d", cfg_index); - val_print(ACS_PRINT_DEBUG, ", msc_index = %d", msc_index); + val_print(DEBUG, "\n Running for cfg_index = %d", cfg_index); + val_print(DEBUG, ", msc_index = %d", msc_index); rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -187,7 +187,7 @@ static void payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -209,7 +209,7 @@ static void payload(void) }; start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, buf_size); @@ -217,7 +217,7 @@ static void payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -249,11 +249,11 @@ static void payload(void) for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { for (cfg_index = 1; cfg_index < enabled_scenarios; cfg_index++) { if (counter[cfg_index][msc_index] > counter[cfg_index-1][msc_index]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index-1); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n cfg_index : %d", cfg_index-1); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); + val_print(ERROR, "\n cfg_index : %d", cfg_index); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); test_fail++; } } diff --git a/test_pool/mpam/partition002.c b/test_pool/mpam/partition002.c index 29b7351a..d80a7554 100644 --- a/test_pool/mpam/partition002.c +++ b/test_pool/mpam/partition002.c @@ -73,7 +73,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -81,7 +81,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -111,10 +111,10 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CCAP Nodes = %d", ccap_nodes); - val_print(ACS_PRINT_DEBUG, "\n Test PARTID = %d", test_partid); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CCAP Nodes = %d", ccap_nodes); + val_print(DEBUG, "\n Test PARTID = %d", test_partid); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if ((ccap_nodes == 0) || (csumon_count == 0)) { @@ -152,8 +152,8 @@ static void payload(void) if (ccap_config_data[cfg_index].config_enable) { /* Configure CCAP settings for nodes supporting CCAP */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { - val_print(ACS_PRINT_DEBUG, "\n Running for cfg_index = %d", cfg_index); - val_print(ACS_PRINT_DEBUG, ", msc_index = %d", msc_index); + val_print(DEBUG, "\n Running for cfg_index = %d", cfg_index); + val_print(DEBUG, ", msc_index = %d", msc_index); rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -189,7 +189,7 @@ static void payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -211,7 +211,7 @@ static void payload(void) }; start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, buf_size); @@ -219,7 +219,7 @@ static void payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -251,11 +251,11 @@ static void payload(void) for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { for (cfg_index = 1; cfg_index < enabled_scenarios; cfg_index++) { if (counter[cfg_index][msc_index] > counter[cfg_index-1][msc_index]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index-1); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n cfg_index : %d", cfg_index-1); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); + val_print(ERROR, "\n cfg_index : %d", cfg_index); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); test_fail++; } } diff --git a/test_pool/mpam/partition003.c b/test_pool/mpam/partition003.c index 156eec9e..c2c8813d 100644 --- a/test_pool/mpam/partition003.c +++ b/test_pool/mpam/partition003.c @@ -74,7 +74,7 @@ static void payload(void) /* Get the Index for LLC */ llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_ERR, "\n Cache info table empty", 0); + val_print(ERROR, "\n Cache info table empty"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -82,7 +82,7 @@ static void payload(void) /* Get the cache identifier for LLC */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_print(ERROR, "\n LLC invalid in PPTT"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -112,10 +112,10 @@ static void payload(void) } } - val_print(ACS_PRINT_DEBUG, "\n CCAP CPOR Nodes = %d", ccap_cpor_nodes); - val_print(ACS_PRINT_DEBUG, "\n Test PARTID = %d", test_partid); - val_print(ACS_PRINT_DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); - val_print(ACS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + val_print(DEBUG, "\n CCAP CPOR Nodes = %d", ccap_cpor_nodes); + val_print(DEBUG, "\n Test PARTID = %d", test_partid); + val_print(DEBUG, "\n Cache Max Size = 0x%x", cache_maxsize); + val_print(DEBUG, "\n Number of CSU Monitors = %d", csumon_count); /* Skip the test if CSU monitors/ nodes supporting CCAP & CPOR are 0 */ if ((ccap_cpor_nodes == 0) || (csumon_count == 0)) { @@ -152,8 +152,8 @@ static void payload(void) if (test_config_data[cfg_index].config_enable) { /* Configure settings for nodes supporting */ for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { - val_print(ACS_PRINT_DEBUG, "\n Running for cfg_index = %d", cfg_index); - val_print(ACS_PRINT_DEBUG, ", msc_index = %d", msc_index); + val_print(DEBUG, "\n Running for cfg_index = %d", cfg_index); + val_print(DEBUG, ", msc_index = %d", msc_index); rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { @@ -194,7 +194,7 @@ static void payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -216,7 +216,7 @@ static void payload(void) }; start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, buf_size); @@ -224,7 +224,7 @@ static void payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -256,11 +256,11 @@ static void payload(void) for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { for (cfg_index = 1; cfg_index < enabled_scenarios; cfg_index++) { if (counter[cfg_index][msc_index] > counter[cfg_index-1][msc_index]) { - val_print(ACS_PRINT_ERR, "\n Failed for msc_index : %d", msc_index); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index-1); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); - val_print(ACS_PRINT_ERR, "\n cfg_index : %d", cfg_index); - val_print(ACS_PRINT_ERR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); + val_print(ERROR, "\n Failed for msc_index : %d", msc_index); + val_print(ERROR, "\n cfg_index : %d", cfg_index-1); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index-1][msc_index]); + val_print(ERROR, "\n cfg_index : %d", cfg_index); + val_print(ERROR, ", CSU Mon Count :0x%lx", counter[cfg_index][msc_index]); test_fail++; } } diff --git a/test_pool/mpam/partition004.c b/test_pool/mpam/partition004.c index 733382ee..230c24ec 100644 --- a/test_pool/mpam/partition004.c +++ b/test_pool/mpam/partition004.c @@ -80,7 +80,7 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n No LLC found, skipping test", 0); + val_print(DEBUG, "\n No LLC found, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -88,7 +88,7 @@ payload(void) /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n Invalid LLC ID, skipping test", 0); + val_print(DEBUG, "\n Invalid LLC ID, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -97,7 +97,7 @@ payload(void) for (msc_index = 0; msc_index < msc_cnt; msc_index++) { max_partid = val_mpam_get_max_partid(msc_index); if (max_partid == 0) { - val_print(ACS_PRINT_DEBUG, "\n MSC %d has no PARTID support", msc_index); + val_print(DEBUG, "\n MSC %d has no PARTID support", msc_index); continue; } @@ -106,7 +106,7 @@ payload(void) GET_MIN_VALUE(test_partid, max_partid - 1); } - val_print(ACS_PRINT_TEST, "\n Selected PARTID = %d", test_partid); + val_print(INFO, "\n Selected PARTID = %d", test_partid); /* Iterate through all available LLC MSCs and their resources */ for (msc_index = 0; msc_index < msc_cnt; msc_index++) { @@ -127,8 +127,8 @@ payload(void) in unexpected behavior in the test */ if (val_cache_get_associativity(cache_identifier) < 4) { - val_print(ACS_PRINT_TEST, - "\n LLC is less than 4-way, skipping MSC", 0); + val_print(INFO, + "\n LLC is less than 4-way, skipping MSC"); continue; } @@ -142,7 +142,7 @@ payload(void) /* Check if MSC supports CASSOC */ if (!val_mpam_supports_cassoc(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not support CASSOC partitioning, skipping", msc_index); continue; } @@ -152,7 +152,7 @@ payload(void) num_mon = val_mpam_get_csumon_count(msc_index); if (num_mon == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not have CSU monitors, skipping MSC", msc_index); continue; } @@ -171,7 +171,7 @@ payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -202,12 +202,12 @@ payload(void) saved_el2 = val_mpam_reg_read(MPAM2_EL2); /*** Scenario 1: Buffer copy with 100% CASSOC settings ***/ - val_print(ACS_PRINT_DEBUG, "\n Scenario 1: 100 percent CASSOC setting", 0); + val_print(DEBUG, "\n Scenario 1: 100 percent CASSOC setting"); /* Program MPAM2_EL2 with test_partid and default PMG */ status = val_mpam_program_el2(test_partid, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -220,7 +220,7 @@ payload(void) } start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, BUFFER_SIZE); @@ -228,7 +228,7 @@ payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -241,7 +241,7 @@ payload(void) val_mem_issue_dsb(); /*** Scenario 2: Buffer copy with 50% CASSOC settings ***/ - val_print(ACS_PRINT_DEBUG, "\n Scenario 2: 50 percent CASSOC setting", 0); + val_print(DEBUG, "\n Scenario 2: 50 percent CASSOC setting"); /* Disable CCAP and CPOR settings -> Set them to max */ if (val_mpam_supports_cpor(msc_index)) @@ -268,7 +268,7 @@ payload(void) /* Program MPAM2_EL2 with test_partid-1 and default PMG */ status = val_mpam_program_el2(test_partid - 1, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -281,7 +281,7 @@ payload(void) } start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, BUFFER_SIZE); @@ -289,7 +289,7 @@ payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -302,7 +302,7 @@ payload(void) val_mem_issue_dsb(); /*** Scenario 3: Buffer copy with 25% CASSOC settings ***/ - val_print(ACS_PRINT_DEBUG, "\n Scenario 3: 25 percent CASSOC setting", 0); + val_print(DEBUG, "\n Scenario 3: 25 percent CASSOC setting"); /* Disable CCAP and CPOR settings -> Set them to max */ if (val_mpam_supports_cpor(msc_index)) @@ -329,7 +329,7 @@ payload(void) /* Program MPAM2_EL2 with test_partid-2 and default PMG */ status = val_mpam_program_el2(test_partid - 2, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -342,7 +342,7 @@ payload(void) } start_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Start Count = 0x%lx", start_count); + val_print(DEBUG, "\n Start Count = 0x%lx", start_count); /* Start mem copy */ val_memcpy(src_buf, dest_buf, BUFFER_SIZE); @@ -350,7 +350,7 @@ payload(void) val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_DEBUG, "\n End Count = 0x%lx", end_count); + val_print(DEBUG, "\n End Count = 0x%lx", end_count); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -364,10 +364,10 @@ payload(void) expected to decrease in each scenario, resulting in reduced CSU MON counter */ if (!((counter[0] > counter[1]) && (counter[1] > counter[2]))) { - val_print(ACS_PRINT_ERR, "\n Unexpected cache usage behavior observed", 0); - val_print(ACS_PRINT_ERR, "\n CASSOC 100 percent count = 0x%lx", counter[0]); - val_print(ACS_PRINT_ERR, "\n CASSOC 50 percent count = 0x%lx", counter[1]); - val_print(ACS_PRINT_ERR, "\n CASSOC 25 percent count = 0x%lx", counter[2]); + val_print(ERROR, "\n Unexpected cache usage behavior observed"); + val_print(ERROR, "\n CASSOC 100 percent count = 0x%lx", counter[0]); + val_print(ERROR, "\n CASSOC 50 percent count = 0x%lx", counter[1]); + val_print(ERROR, "\n CASSOC 25 percent count = 0x%lx", counter[2]); test_fail++; } diff --git a/test_pool/mpam/partition005.c b/test_pool/mpam/partition005.c index 5f9542fe..d2e3a367 100644 --- a/test_pool/mpam/partition005.c +++ b/test_pool/mpam/partition005.c @@ -82,7 +82,7 @@ payload(void) /* Check if LLC is valid */ if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n No LLC found, skipping test", 0); + val_print(DEBUG, "\n No LLC found, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -90,7 +90,7 @@ payload(void) /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n Invalid LLC ID, skipping test", 0); + val_print(DEBUG, "\n Invalid LLC ID, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -112,7 +112,7 @@ payload(void) /* Check if the MSC support selected PARTIDs (max_partid >= 2) */ max_partid = val_mpam_get_max_partid(msc_index); if (max_partid < partid_y) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %u does not support required PARTIDs, skipping", msc_index); continue; @@ -121,7 +121,7 @@ payload(void) /* Step 1: Identify an MSC that supports cache maximum-capacity control and soft limit functionality */ if (!(val_mpam_msc_supports_cmax_softlim(msc_index))) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %u doesn't support CMAX with softlimit, skipping MSC", msc_index); continue; @@ -130,7 +130,7 @@ payload(void) /* Skip the MSC if no CSU MON are present */ num_mon = val_mpam_get_csumon_count(msc_index); if (num_mon == 0) { - val_print(ACS_PRINT_DEBUG, "\n MSC %u has no CSU MON, skipping MSC", + val_print(DEBUG, "\n MSC %u has no CSU MON, skipping MSC", msc_index); continue; } @@ -138,7 +138,7 @@ payload(void) /* Check if PARTID Disabling is supported. The test relies on this feature. Skip the MSC if endis not present */ if (!val_mpam_msc_supports_partid_endis(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %u doesn't support PARTID disable, skipping MSC", msc_index); continue; @@ -161,7 +161,7 @@ payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -185,12 +185,12 @@ payload(void) /* Save the current MPAM2_EL2 settings */ saved_el2 = val_mpam_reg_read(MPAM2_EL2); - val_print(ACS_PRINT_TEST, "\n Scenario 1: PARTID_X without SOFTLIM", 0); + val_print(INFO, "\n Scenario 1: PARTID_X without SOFTLIM"); /* Step 4: Program MPAM2_EL2 with partid_x and default PMG */ status = val_mpam_program_el2(partid_x, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); goto cleanup; } @@ -210,7 +210,7 @@ payload(void) /* Step 6 - Read the Cache line count used by PARTID X from CSU MON */ counter[0] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n Scenario 1: End Count = 0x%lx", counter[0]); + val_print(INFO, "\n Scenario 1: End Count = 0x%lx", counter[0]); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -223,7 +223,7 @@ payload(void) No need to monitor the transactions */ status = val_mpam_program_el2(partid_y, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); goto cleanup; } @@ -247,7 +247,7 @@ payload(void) /* Step 9: Re-program the PE with PARTID_X again and set SOFTLIM = 1 for PARTID_X.*/ status = val_mpam_program_el2(partid_x, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); /* Re-enable PARTID-Y for the next tests to behave properly */ val_mpam_msc_endis_partid(msc_index, @@ -282,13 +282,13 @@ payload(void) /* Step 11: Measure cache usage again with the CSU monitor */ counter[1] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n Scenario 2: End Count = 0x%lx", counter[1]); + val_print(INFO, "\n Scenario 2: End Count = 0x%lx", counter[1]); /* Compare the result. Counter[1] should be more than Counter[0]. The softlimiting should allow some of the disabled PARTID_Y's cache lines to be used by PARTID_X */ if (counter[0] >= counter[1]) { - val_print(ACS_PRINT_ERR, - "\n Test Failed: Softlimit not working as expected", 0); + val_print(ERROR, + "\n Test Failed: Softlimit not working as expected"); test_fail = 1; } diff --git a/test_pool/mpam/partition006.c b/test_pool/mpam/partition006.c index 7a59d78d..3d9df4b4 100644 --- a/test_pool/mpam/partition006.c +++ b/test_pool/mpam/partition006.c @@ -89,7 +89,7 @@ payload(void) /* Check if LLC is valid */ if (llc_index == CACHE_TABLE_EMPTY) { - val_print(ACS_PRINT_DEBUG, "\n No LLC found, skipping test", 0); + val_print(DEBUG, "\n No LLC found, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -97,7 +97,7 @@ payload(void) /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { - val_print(ACS_PRINT_DEBUG, "\n Invalid LLC ID, skipping test", 0); + val_print(DEBUG, "\n Invalid LLC ID, skipping test"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -119,7 +119,7 @@ payload(void) /* Check if the MSC support selected PARTIDs (max_partid >= 2) */ max_partid = val_mpam_get_max_partid(msc_index); if (max_partid < partid_z) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not support required PARTIDs, skipping", msc_index); continue; @@ -128,7 +128,7 @@ payload(void) /* Skip the MSC if no CSU MON are present */ num_mon = val_mpam_get_csumon_count(msc_index); if (num_mon == 0) { - val_print(ACS_PRINT_DEBUG, "\n MSC %u has no CSU MON, skipping MSC", + val_print(DEBUG, "\n MSC %u has no CSU MON, skipping MSC", msc_index); continue; } @@ -136,7 +136,7 @@ payload(void) /* Check if PARTID Disabling is supported. The test relies on this feature. Skip the MSC if endis not present */ if (!val_mpam_msc_supports_partid_endis(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d doesn't support PARTID disable, skipping MSC", msc_index); continue; @@ -144,7 +144,7 @@ payload(void) /* Step 1: Check if the MSC supports Cache Minimum-Capacity resource control */ if (!val_mpam_msc_supports_cmin(msc_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n MSC %d does not support CMIN-Capacity control, skipping", msc_index); continue; @@ -159,7 +159,7 @@ payload(void) dest_buf = (void *)val_memory_alloc_pages(num_pages); if ((src_buf == NULL) || (dest_buf == NULL)) { - val_print(ACS_PRINT_ERR, "\n Mem allocation failed", 0); + val_print(ERROR, "\n Mem allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); @@ -173,7 +173,7 @@ payload(void) status = val_mpam_program_el2(partid_x, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); goto cleanup; } @@ -199,7 +199,7 @@ payload(void) /* Read the monitor counter for PARTID_X */ counter[0] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n PARTID_X Counter: 0x%x", counter[0]); + val_print(INFO, "\n PARTID_X Counter: 0x%x", counter[0]); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -214,7 +214,7 @@ payload(void) /* Step 5: Perform a memory workload for PARTID_Y */ status = val_mpam_program_el2(partid_y, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); goto cleanup; } @@ -237,18 +237,18 @@ payload(void) /* Read the monitor counter for PARTID_Y */ counter[1] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n PARTID_Y Counter: 0x%x", counter[1]); + val_print(INFO, "\n PARTID_Y Counter: 0x%x", counter[1]); /* Read PARTID_X counter after the second buffer copy */ val_mpam_configure_csu_mon(msc_index, partid_x, DEFAULT_PMG, 0); if (val_mpam_read_csumon(msc_index) > counter[0]) { - val_print(ACS_PRINT_ERR, - "\n PARTID_X usage increased after PARTID_Y workload, failing test", 0); + val_print(ERROR, + "\n PARTID_X usage increased after PARTID_Y workload, failing test"); test_fail = 1; } counter[0] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n PARTID_X Counter after PARTID_Y workload: 0x%x", counter[0]); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -271,13 +271,13 @@ payload(void) val_mpam_configure_csu_mon(msc_index, partid_z, DEFAULT_PMG, 0); counter[2] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n PARTID_Z Counter before workload: 0x%x", counter[2]); /* Step 8: Perform a memory workload for PARTID_Z */ status = val_mpam_program_el2(partid_z, DEFAULT_PMG); if (status) { - val_print(ACS_PRINT_ERR, "\n MPAM2_EL2 programming failed", 0); + val_print(ERROR, "\n MPAM2_EL2 programming failed"); goto cleanup; } @@ -289,40 +289,40 @@ payload(void) /* Read the monitor counter for PARTID_Z */ if (val_mpam_read_csumon(msc_index) <= counter[2]) { - val_print(ACS_PRINT_ERR, - "\n PARTID_Z usage did not increase after workload, failing test", 0); + val_print(ERROR, + "\n PARTID_Z usage did not increase after workload, failing test"); test_fail = 1; } counter[2] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, "\n PARTID_Z Counter after workload: %x", counter[2]); + val_print(INFO, "\n PARTID_Z Counter after workload: %x", counter[2]); /* Read PARTID_X and PARTID_Y counters after PARTID_Z workload */ val_mpam_configure_csu_mon(msc_index, partid_x, DEFAULT_PMG, 0); if (val_mpam_read_csumon(msc_index) > counter[0]) { - val_print(ACS_PRINT_ERR, - "\n PARTID_X usage increased after PARTID_Z workload, failing test", 0); + val_print(ERROR, + "\n PARTID_X usage increased after PARTID_Z workload, failing test"); test_fail = 1; } counter[0] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n PARTID_X Counter after PARTID_Z workload: 0x%x", counter[0]); val_mpam_configure_csu_mon(msc_index, partid_y, DEFAULT_PMG, 0); if (val_mpam_read_csumon(msc_index) > counter[1]) { - val_print(ACS_PRINT_ERR, - "\n PARTID_Y usage increased after PARTID_Z workload, failing test", 0); + val_print(ERROR, + "\n PARTID_Y usage increased after PARTID_Z workload, failing test"); test_fail = 1; } counter[1] = val_mpam_read_csumon(msc_index); - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n PARTID_Y Counter after PARTID_Z workload: 0x%x", counter[1]); if (counter[1] > counter[0]) { - val_print(ACS_PRINT_ERR, - "\n PARTID_Y usage higher than PARTID_X, failing test", 0); + val_print(ERROR, + "\n PARTID_Y usage higher than PARTID_X, failing test"); test_fail = 1; } diff --git a/test_pool/mpam/reg001.c b/test_pool/mpam/reg001.c index 51cd1a13..f34e0278 100644 --- a/test_pool/mpam/reg001.c +++ b/test_pool/mpam/reg001.c @@ -41,15 +41,15 @@ static void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { version = val_mpam_msc_get_version(msc_index); - val_print(ACS_PRINT_INFO, "\n MSC Node Index : %d", msc_index); - val_print(ACS_PRINT_INFO, ", Version : 0x%x", version); + val_print(TRACE, "\n MSC Node Index : %d", msc_index); + val_print(TRACE, ", Version : 0x%x", version); if (version == MPAM_VERSION_1_0) { /* if MPAMv1.0 Check MPAMF_IDR.EXT = 0 */ ext = BITFIELD_READ(IDR_EXT, val_mpam_mmr_read64(msc_index, REG_MPAMF_IDR)); if (ext != 0) { /* Fail the test */ - val_print(ACS_PRINT_ERR, "\n MPAMF_IDR.EXT value is not 0", 0); + val_print(ERROR, "\n MPAMF_IDR.EXT value is not 0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -59,7 +59,7 @@ static void payload(void) ext = BITFIELD_READ(IDR_EXT, val_mpam_mmr_read64(msc_index, REG_MPAMF_IDR)); if (ext != 1) { /* Fail the test */ - val_print(ACS_PRINT_ERR, "\n MPAMF_IDR.EXT value is not 1", 0); + val_print(ERROR, "\n MPAMF_IDR.EXT value is not 1"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -67,7 +67,7 @@ static void payload(void) else { /* Invalid */ /* TODO : Check for v0.1 */ - val_print(ACS_PRINT_ERR, "\n MSC Version not valid", 0); + val_print(ERROR, "\n MSC Version not valid"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } diff --git a/test_pool/mpam/reg002.c b/test_pool/mpam/reg002.c index 5e07f585..8180fb2a 100644 --- a/test_pool/mpam/reg002.c +++ b/test_pool/mpam/reg002.c @@ -48,7 +48,7 @@ static void payload(void) if (BITFIELD_READ(IDR_HAS_EXTD_ESR, idr_value) == 0) { /* Fail The Test */ - val_print(ACS_PRINT_ERR, "\n MPAMF_IDR.HAS_EXTD_ESR value is 0", 0); + val_print(ERROR, "\n MPAMF_IDR.HAS_EXTD_ESR value is 0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/mpam/reg003.c b/test_pool/mpam/reg003.c index 427e8e4b..ed98e36c 100644 --- a/test_pool/mpam/reg003.c +++ b/test_pool/mpam/reg003.c @@ -46,8 +46,8 @@ static void payload(void) for (msc_index = 0; msc_index < total_nodes; msc_index++) { version = val_mpam_msc_get_version(msc_index); - val_print(ACS_PRINT_INFO, "\n MPAM version : v%x", (version >> 4)); - val_print(ACS_PRINT_INFO, ".%x", (version & 0xF)); + val_print(TRACE, "\n MPAM version : v%x", (version >> 4)); + val_print(TRACE, ".%x", (version & 0xF)); idr_value = val_mpam_mmr_read64(msc_index, REG_MPAMF_IDR); ccap_idr_value = val_mpam_mmr_read(msc_index, REG_MPAMF_CCAP_IDR); csumon_idr_value = val_mpam_mmr_read(msc_index, REG_MPAMF_CSUMON_IDR); @@ -59,154 +59,154 @@ static void payload(void) /* Minimum cache capacity partitioning Prohibited */ if (BITFIELD_READ(CCAP_IDR_HAS_CMIN, ccap_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_CCAP_IDR.HAS_CMIN is Prohibited", 0); + val_print(ERROR, "\n MPAMF_CCAP_IDR.HAS_CMIN is Prohibited"); test_fail++; } /* No maximum cache capacity partitioning Prohibited */ if (BITFIELD_READ(CCAP_IDR_NO_CMAX, ccap_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_CCAP_IDR.NO_CMAX is Prohibited", 0); + val_print(ERROR, "\n MPAMF_CCAP_IDR.NO_CMAX is Prohibited"); test_fail++; } /* Cache maximum associativity partitioning Prohibited */ if (BITFIELD_READ(CCAP_IDR_HAS_CASSOC, ccap_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_CCAP_IDR.HAS_CASSOC is Prohibited", 0); + val_print(ERROR, "\n MPAMF_CCAP_IDR.HAS_CASSOC is Prohibited"); test_fail++; } /* Cache maximum SOFT_LIM Prohibited */ if (BITFIELD_READ(CCAP_IDR_HAS_CMAX_SOFTLIM, ccap_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_CCAP_IDR.HAS_CMAX_SOFTLIM is Prohibited", 0); + val_print(ERROR, "\n MPAMF_CCAP_IDR.HAS_CMAX_SOFTLIM is Prohibited"); test_fail++; } /* PARTID Disable Prohibited */ if (BITFIELD_READ(IDR_HAS_ENDIS, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_IDR.HAS_ENDIS is Prohibited", 0); + val_print(ERROR, "\n MPAMF_IDR.HAS_ENDIS is Prohibited"); test_fail++; } /* No Future Use Prohibited */ if (BITFIELD_READ(IDR_HAS_NFU, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MPAMF_IDR.HAS_NFU is Prohibited", 0); + val_print(ERROR, "\n MPAMF_IDR.HAS_NFU is Prohibited"); test_fail++; } /* CSU monitor XCL Prohibited */ if (BITFIELD_READ(CSUMON_IDR_HAS_XCL, csumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n CSUMON_IDR_HAS_XCL is Prohibited", 0); + val_print(ERROR, "\n CSUMON_IDR_HAS_XCL is Prohibited"); test_fail++; } /* CSU monitor overflow linkage Prohibited */ if (BITFIELD_READ(CSUMON_IDR_HAS_OFLOW_LNKG, csumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n CSUMON_IDR_HAS_OFLOW_LNKG is Prohibited", 0); + val_print(ERROR, "\n CSUMON_IDR_HAS_OFLOW_LNKG is Prohibited"); test_fail++; } /* CSU monitor overflow status Reg Prohibited */ if (BITFIELD_READ(CSUMON_IDR_HAS_OFSR, csumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n CSUMON_IDR_HAS_OFSR is Prohibited", 0); + val_print(ERROR, "\n CSUMON_IDR_HAS_OFSR is Prohibited"); test_fail++; } /* CSU monitor overflow capture Prohibited */ if (BITFIELD_READ(CSUMON_IDR_HAS_CEVNT_OFLW, csumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n CSUMON_IDR_HAS_CEVNT_OFLW is Prohibited", 0); + val_print(ERROR, "\n CSUMON_IDR_HAS_CEVNT_OFLW is Prohibited"); test_fail++; } /* MBWU monitor overflow linkage Prohibited */ if (BITFIELD_READ(MBWUMON_IDR_HAS_OFLOW_LNKG, mbwumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MBWUMON_IDR_HAS_OFLOW_LNKG is Prohibited", 0); + val_print(ERROR, "\n MBWUMON_IDR_HAS_OFLOW_LNKG is Prohibited"); test_fail++; } /* MBWU monitor overflow status Reg Prohibited */ if (BITFIELD_READ(MBWUMON_IDR_HAS_OFSR, mbwumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MBWUMON_IDR_HAS_OFSR is Prohibited", 0); + val_print(ERROR, "\n MBWUMON_IDR_HAS_OFSR is Prohibited"); test_fail++; } /* MBWU monitor overflow capture Prohibited */ if (BITFIELD_READ(MBWUMON_IDR_HAS_CAPTURE, mbwumon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MBWUMON_IDR_HAS_CAPTURE is Prohibited", 0); + val_print(ERROR, "\n MBWUMON_IDR_HAS_CAPTURE is Prohibited"); test_fail++; } /* Monitor overflow status register Prohibited */ if (BITFIELD_READ(MSMON_IDR_HAS_OFLOW_SR, msmon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MSMON_IDR_HAS_OFLOW_SR is Prohibited", 0); + val_print(ERROR, "\n MSMON_IDR_HAS_OFLOW_SR is Prohibited"); test_fail++; } /* Monitor overflow MSI Prohibited */ if (BITFIELD_READ(MSMON_IDR_HAS_OFLW_MSI, msmon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MSMON_IDR_HAS_OFLW_MSI is Prohibited", 0); + val_print(ERROR, "\n MSMON_IDR_HAS_OFLW_MSI is Prohibited"); test_fail++; } /* No hardwired overflow interrupt Prohibited */ if (BITFIELD_READ(MSMON_IDR_NO_OFLW_INTR, msmon_idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n MSMON_IDR_NO_OFLW_INTR is Prohibited", 0); + val_print(ERROR, "\n MSMON_IDR_NO_OFLW_INTR is Prohibited"); test_fail++; } /* Impl IDR no partitioning Prohibited in v1.0, Required in others*/ if (BITFIELD_READ(IDR_NO_IMPL_PART, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_NO_IMPL_PART is Prohibited", 0); + val_print(ERROR, "\n IDR_NO_IMPL_PART is Prohibited"); test_fail++; } /* Impl IDR no monitoring Prohibited in v1.0, Required in others */ if (BITFIELD_READ(IDR_NO_IMPL_MSMON, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_NO_IMPL_MSMON is Prohibited", 0); + val_print(ERROR, "\n IDR_NO_IMPL_MSMON is Prohibited"); test_fail++; } /* Extended ID register Prohibited in v1.0, Required in others */ if (BITFIELD_READ(IDR_EXT, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_EXT is Prohibited", 0); + val_print(ERROR, "\n IDR_EXT is Prohibited"); test_fail++; } /* Resource instance selector Prohibited */ if (BITFIELD_READ(IDR_HAS_RIS, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_HAS_RIS is Prohibited", 0); + val_print(ERROR, "\n IDR_HAS_RIS is Prohibited"); test_fail++; } /* Error status register Prohibited */ if (BITFIELD_READ(IDR_HAS_ESR, idr_value) || BITFIELD_READ(IDR_HAS_EXTD_ESR, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n HAS_ESR & HAS_EXTD_ESR is Prohibited", 0); + val_print(ERROR, "\n HAS_ESR & HAS_EXTD_ESR is Prohibited"); test_fail++; } /* Error MSI Prohibited */ if (BITFIELD_READ(IDR_HAS_ERR_MSI, idr_value)) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_HAS_ERR_MSI is Prohibited", 0); + val_print(ERROR, "\n IDR_HAS_ERR_MSI is Prohibited"); test_fail++; } } else if ((version == MPAM_VERSION_1_1) || (version == MPAM_VERSION_0_1)) { @@ -216,14 +216,14 @@ static void payload(void) /* Impl IDR no partitioning Required */ if (BITFIELD_READ(IDR_NO_IMPL_PART, idr_value) == 0) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_NO_IMPL_PART is Required", 0); + val_print(ERROR, "\n IDR_NO_IMPL_PART is Required"); test_fail++; } /* Impl IDR no monitoring Required */ if (BITFIELD_READ(IDR_NO_IMPL_MSMON, idr_value) == 0) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_NO_IMPL_MSMON is Required", 0); + val_print(ERROR, "\n IDR_NO_IMPL_MSMON is Required"); test_fail++; } } @@ -231,12 +231,12 @@ static void payload(void) /* Extended ID register Required */ if (BITFIELD_READ(IDR_EXT, idr_value) == 0) { /* fail the test*/ - val_print(ACS_PRINT_ERR, "\n IDR_EXT is Required", 0); + val_print(ERROR, "\n IDR_EXT is Required"); test_fail++; } } else { /* Invalid */ - val_print(ACS_PRINT_ERR, "\n MSC Version not valid", 0); + val_print(ERROR, "\n MSC Version not valid"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/mpam/reg004.c b/test_pool/mpam/reg004.c index 53de09d4..510d3bbd 100644 --- a/test_pool/mpam/reg004.c +++ b/test_pool/mpam/reg004.c @@ -45,7 +45,7 @@ static void payload(void) if (val_pe_feat_check(PE_FEAT_RME)) { /* Skip the test */ - val_print_primary_pe(ACS_PRINT_INFO, "\n PE Does not Support RME", 0, pe_index); + val_print_primary_pe(TRACE, "\n PE Does not Support RME", 0, pe_index); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -53,7 +53,7 @@ static void payload(void) if ((mpam_major == 0) && (mpam_minor == 0)) { /* Skip the test */ - val_print_primary_pe(ACS_PRINT_INFO, "\n PE Does not Support MPAM", 0, pe_index); + val_print_primary_pe(TRACE, "\n PE Does not Support MPAM", 0, pe_index); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -61,7 +61,7 @@ static void payload(void) /* Check Support for MPAM v1.1 */ if ((mpam_major < 1) || ((mpam_major == 1) && (mpam_minor < 1))) { - val_print_primary_pe(ACS_PRINT_ERR, "\n PE Does not Support MPAMv1.1", 0, pe_index); + val_print_primary_pe(ERROR, "\n PE Does not Support MPAMv1.1", 0, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -69,7 +69,7 @@ static void payload(void) /* Check PE Supports 4 PARTID Spaces */ mpamidr_val = val_mpam_reg_read(MPAMIDR_EL1); if (VAL_EXTRACT_BITS(mpamidr_val, MPAMIDR_SP4, MPAMIDR_SP4) == 0) { - val_print_primary_pe(ACS_PRINT_ERR, + val_print_primary_pe(ERROR, "\n PE Does not Support 4 PARTID Spaces", 0, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; @@ -77,7 +77,7 @@ static void payload(void) /* Check alternative space, ALTSP feature */ if (VAL_EXTRACT_BITS(mpamidr_val, MPAMIDR_HAS_ALTSP, MPAMIDR_HAS_ALTSP) == 0) { - val_print_primary_pe(ACS_PRINT_ERR, "\n PE Does not Support ALTSP", 0, pe_index); + val_print_primary_pe(ERROR, "\n PE Does not Support ALTSP", 0, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } diff --git a/test_pool/mpam/reg005.c b/test_pool/mpam/reg005.c index a5d221d8..6c76c292 100644 --- a/test_pool/mpam/reg005.c +++ b/test_pool/mpam/reg005.c @@ -40,7 +40,7 @@ static void payload(void) if (val_pe_feat_check(PE_FEAT_RME) || val_pe_feat_check(PE_FEAT_MPAM)) { /* Skip the test */ - val_print(ACS_PRINT_INFO, "\n PE Does not Support MPAM for RME", 0); + val_print(TRACE, "\n PE Does not Support MPAM for RME"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -59,7 +59,7 @@ static void payload(void) if (num_sp4 == 0) { /* Fail The Test */ - val_print(ACS_PRINT_ERR, "\n Four Space Region Number is 0", 0); + val_print(ERROR, "\n Four Space Region Number is 0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/mpam/reg006.c b/test_pool/mpam/reg006.c index 473af6d1..3b38b6fd 100644 --- a/test_pool/mpam/reg006.c +++ b/test_pool/mpam/reg006.c @@ -39,7 +39,7 @@ static void payload(void) if (!val_mpam_msc_supports_partid_nrw(msc_index)) continue; - val_print(ACS_PRINT_DEBUG, "\n MSC %d supports PARTID NRW", msc_index); + val_print(DEBUG, "\n MSC %d supports PARTID NRW", msc_index); /* Read MPAMF_IDR register */ mpamf_idr = val_mpam_mmr_read64(msc_index, REG_MPAMF_IDR); @@ -51,7 +51,7 @@ static void payload(void) /* If PARTID narrowing is supported, MPAMCFG_DIS.NFU must not be implemented. Check for MPAMF_IDR.HAS_NFU = 0 */ if (BITFIELD_READ(IDR_HAS_NFU, mpamf_idr)) { - val_print(ACS_PRINT_ERR, "\n MSC %d has NFU bit implemented", msc_index); + val_print(ERROR, "\n MSC %d has NFU bit implemented", msc_index); nfu_bit++; } } diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c index 89d7daa5..077269d7 100644 --- a/test_pool/nist_sts/test_n001.c +++ b/test_pool/nist_sts/test_n001.c @@ -68,7 +68,7 @@ check_prerequisite_nist(void) snprintf(file_name[i], 20, "tmp_%d.txt", i); fp[i] = fopen(file_name[i], "wb"); if (fp[i] == NULL) { - val_print(ACS_PRINT_ERR, "\nMax # of opened files has been reached. " + val_print(ERROR, "\nMax # of opened files has been reached. " "NIST prerequistite failed: %d", i); status = ACS_STATUS_FAIL; break; @@ -82,7 +82,7 @@ check_prerequisite_nist(void) } remove(result_file); - val_print(ACS_PRINT_INFO, "\nAll NIST Prerequistite were met", 0); + val_print(TRACE, "\nAll NIST Prerequistite were met"); return status; } @@ -99,7 +99,7 @@ print_nist_result(void) fptr = fopen(filename, "r"); if (fptr == NULL) { - val_print(ACS_PRINT_ERR, "Cannot open file\n", 0); + val_print(ERROR, "Cannot open file\n"); return ACS_STATUS_FAIL; } @@ -115,7 +115,7 @@ print_nist_result(void) /* Print line read on cosole*/ //ToDo: Print using val_print - //val_print(ACS_PRINT_TEST, "%s\n", buffer); + //val_print(INFO, "%s\n", buffer); printf("%s\n", buffer); } @@ -136,7 +136,7 @@ create_random_file(void) fp = fopen(str, "wb"); if (fp == NULL) { - val_print(ACS_PRINT_ERR, "\n Unable to create file", 0); + val_print(ERROR, "\n Unable to create file"); return ACS_STATUS_FAIL; } @@ -145,13 +145,13 @@ create_random_file(void) /* Get a 32-bit random number */ status = val_nist_generate_rng(&buffer); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n PAL API pal_nist_generate_rng is unimplemented", 0); - val_print(ACS_PRINT_ERR, "\n Implement the PAL API for the test to run", 0); + val_print(ERROR, "\n PAL API pal_nist_generate_rng is unimplemented"); + val_print(ERROR, "\n Implement the PAL API for the test to run"); return ACS_STATUS_SKIP; } if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Random number generation failed", 0); + val_print(ERROR, "\n Random number generation failed"); fclose(fp); return ACS_STATUS_FAIL; } @@ -169,7 +169,7 @@ create_random_file(void) } fclose(fp); - val_print(ACS_PRINT_INFO, "\nA random file with sequence of ASCII 0's and 1's created", 0); + val_print(TRACE, "\nA random file with sequence of ASCII 0's and 1's created"); return ACS_STATUS_PASS; } static @@ -187,7 +187,7 @@ payload() if (status != ACS_STATUS_PASS) { /* Omitting tests 8, 9 and 13 */ test_select = MIN_NIST_TEST; - val_print(ACS_PRINT_INFO, "\nSkipping test 8, 9 and 13 of NIST test suite", 0); + val_print(TRACE, "\nSkipping test 8, 9 and 13 of NIST test suite"); } /* Generate a Random file with binary ASCII values */ @@ -232,12 +232,12 @@ payload() dirname = "experiments/AlgorithmTesting/Universal"; status |= mkdir(dirname, 0777); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Directory not created", 0); + val_print(ERROR, "\n Directory not created"); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; } else - val_print(ACS_PRINT_INFO, "\n Directory created", 0); + val_print(TRACE, "\n Directory created"); if (test_select == MIN_NIST_TEST) { /* Run the NIST test suite 1 and 2 as the prerequisite conditions diff --git a/test_pool/pcie/p001.c b/test_pool/pcie/p001.c index d43a1770..17299328 100644 --- a/test_pool/pcie/p001.c +++ b/test_pool/pcie/p001.c @@ -33,7 +33,7 @@ payload(void) num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_ERR, "\n No ECAMs discovered ", 0); + val_print(ERROR, "\n No ECAMs discovered "); if (g_build_sbsa) val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); else diff --git a/test_pool/pcie/p002.c b/test_pool/pcie/p002.c index a6cd1f38..a94983a9 100644 --- a/test_pool/pcie/p002.c +++ b/test_pool/pcie/p002.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_print(TRACE, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); } @@ -64,27 +64,27 @@ calculate_vf(uint32_t seg, uint32_t bdf, uint32_t sriov_base) val_pcie_read_cfg(bdf, sriov_base + SRIOV_VF_OFF_STR, ®_value); first_vf_offset = reg_value & SRIOV_FIRST_VF_SHIFT; vf_stride = (reg_value >> SRIOV_STRIDE_SHIFT) & SRIOV_STRIDE_MASK; - val_print(ACS_PRINT_INFO, "\n First vf offset is 0x%x", first_vf_offset); - val_print(ACS_PRINT_INFO, "\n vf stride is 0x%x", vf_stride); + val_print(TRACE, "\n First vf offset is 0x%x", first_vf_offset); + val_print(TRACE, "\n vf stride is 0x%x", vf_stride); val_pcie_read_cfg(bdf, sriov_base + SRIOV_VF_COUNT, ®_value); num_vf = (reg_value >> SRIOV_NUM_VF_SHIFT) & SRIOV_NUM_VF_MASK; - val_print(ACS_PRINT_INFO, "\n Number of VF's is 0x%x", num_vf); + val_print(TRACE, "\n Number of VF's is 0x%x", num_vf); vf_rid = pf_rid + first_vf_offset; if (num_vf > MAX_VFS) - val_print(ACS_PRINT_WARN, "\n Number of VF's present is more than 256", 0); + val_print(WARN, "\n Number of VF's present is more than 256"); for (index = 0; index < num_vf; index++) { vf_bdf = PCIE_CREATE_BDF_FROM_PACKED(seg, vf_rid); - val_print(ACS_PRINT_INFO, "\n Seg is 0x%x", seg); - val_print(ACS_PRINT_INFO, "\n vf rid is 0x%x", vf_rid); - val_print(ACS_PRINT_INFO, "\n vf bdf is 0x%x", vf_bdf); + val_print(TRACE, "\n Seg is 0x%x", seg); + val_print(TRACE, "\n vf rid is 0x%x", vf_rid); + val_print(TRACE, "\n vf bdf is 0x%x", vf_bdf); skip_rid_list[index] = vf_bdf; vf_rid += vf_stride; if (index > MAX_VFS) - val_print(ACS_PRINT_WARN, "\n Index value is more than 255", 0); + val_print(WARN, "\n Index value is more than 255"); } } @@ -116,7 +116,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -126,7 +126,7 @@ payload(void) num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ECAM in MCFG. Skipping test ", 0); + val_print(DEBUG, "\n No ECAM in MCFG. Skipping test "); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -135,7 +135,7 @@ payload(void) num_ecam--; ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, num_ecam); if (ecam_base == 0) { - val_print(ACS_PRINT_ERR, "\n ECAM Base in MCFG is 0 ", 0); + val_print(ERROR, "\n ECAM Base in MCFG is 0 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -153,8 +153,8 @@ payload(void) //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 if (ret == PCIE_NO_MAPPING || (data == 0)) { - val_print(ACS_PRINT_ERR, "\n Incorrect data at ECAM Base %4x ", data); - val_print(ACS_PRINT_ERR, "\n BDF is %x ", bdf); + val_print(ERROR, "\n Incorrect data at ECAM Base %4x ", data); + val_print(ERROR, "\n BDF is %x ", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -164,18 +164,18 @@ payload(void) { if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &data) != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Skipping legacy PCI device with BDF 0x%x", bdf); continue; } - val_print(ACS_PRINT_INFO, "\n Valid BDF is %x", bdf); + val_print(TRACE, "\n Valid BDF is %x", bdf); if (val_pcie_function_header_type(bdf) == TYPE0_HEADER) { if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_SRIOV, &sriov_base) == PCIE_SUCCESS) { - val_print(ACS_PRINT_INFO, "\n SR-IOV capability present", 0); - val_print(ACS_PRINT_INFO, "\n Check for VF's to skip", 0); + val_print(TRACE, "\n SR-IOV capability present"); + val_print(TRACE, "\n Check for VF's to skip"); calculate_vf(segment, bdf, sriov_base); } } @@ -188,7 +188,7 @@ payload(void) /* if data read from next ECAP offset is 0xFFFF-FFFF, report failure */ if (data == PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid data read from ECAP offset 0x%x", next_offset); val_memory_set(skip_rid_list, sizeof(uint32_t) * MAX_VFS, 0); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); @@ -211,7 +211,7 @@ payload(void) give valid response. Hence skipping the VF's */ for (vf_index = 0; vf_index < num_vf; vf_index++) { if (bdf == skip_rid_list[vf_index]) { - val_print(ACS_PRINT_INFO, "\n BDF 0x%x is a VF. Hence skipping", bdf); + val_print(TRACE, "\n BDF 0x%x is a VF. Hence skipping", bdf); continue; } } @@ -220,7 +220,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Incorrect data for Bdf 0x%x ", bdf); + val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << PCIE_BUS_SHIFT)|dev_index)); return; @@ -230,7 +230,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Incorrect data for Bdf 0x%x ", bdf); + val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << PCIE_BUS_SHIFT)|dev_index)); return; diff --git a/test_pool/pcie/p003.c b/test_pool/pcie/p003.c index e0ff8471..dbf3e325 100644 --- a/test_pool/pcie/p003.c +++ b/test_pool/pcie/p003.c @@ -100,7 +100,7 @@ payload(void) * is same as its RootPort ECAM. */ bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); dp_type = val_pcie_device_port_type(bdf); if (dp_type == EP || dp_type == UP || dp_type == DP) { @@ -109,12 +109,12 @@ payload(void) status = func_ecam_is_rp_ecam(bdf); if (status) { - val_print(ACS_PRINT_ERR, " dp_type: 0x%x ", dp_type); + val_print(ERROR, " dp_type: 0x%x ", dp_type); if (status == PCIE_RP_NOT_FOUND) - val_print(ACS_PRINT_ERR, " No RP found to the EP", 0); + val_print(ERROR, " No RP found to the EP"); else - val_print(ACS_PRINT_ERR, " RP and EP does not share same ECAM region", 0); + val_print(ERROR, " RP and EP does not share same ECAM region"); fail_cnt++; } @@ -122,8 +122,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No EP/ DP/ UP type device found. Skipping test", 0); + val_print(DEBUG, + "\n No EP/ DP/ UP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } diff --git a/test_pool/pcie/p004.c b/test_pool/pcie/p004.c index 4aea6bb0..e006f91f 100644 --- a/test_pool/pcie/p004.c +++ b/test_pool/pcie/p004.c @@ -38,7 +38,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); } @@ -75,7 +75,7 @@ check_bdf_under_rp(uint32_t rp_bdf) if ((dev_seg == rp_seg) && ((dev_bus >= rp_sec_bus) && (dev_bus <= rp_sub_bus))) { val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) @@ -117,7 +117,7 @@ payload(void) branch_to_test = &&exception_return; if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -152,20 +152,20 @@ payload(void) /* Read Function's NP Memory Base Limit Register */ val_pcie_read_cfg(bdf, TYPE1_NP_MEM, &read_value); - val_print(ACS_PRINT_DEBUG, "\n BDF is 0x%x", bdf); + val_print(DEBUG, "\n BDF is 0x%x", bdf); if (read_value == 0) continue; mem_base = (read_value & MEM_BA_MASK) << MEM_BA_SHIFT; mem_lim = (read_value & MEM_LIM_MASK) | MEM_LIM_LOWER_BITS; - val_print(ACS_PRINT_DEBUG, "\n Memory base is 0x%llx", mem_base); - val_print(ACS_PRINT_DEBUG, " Memory lim is 0x%llx", mem_lim); + val_print(DEBUG, "\n Memory base is 0x%llx", mem_base); + val_print(DEBUG, " Memory lim is 0x%llx", mem_lim); /* If Memory Limit is programmed with value less the Base, then Skip.*/ if (mem_lim < mem_base) { - val_print(ACS_PRINT_DEBUG, "\n No NP memory on secondary side of the Bridge", 0); - val_print(ACS_PRINT_DEBUG, "\n Skipping Bdf - 0x%x", bdf); + val_print(DEBUG, "\n No NP memory on secondary side of the Bridge"); + val_print(DEBUG, "\n Skipping Bdf - 0x%x", bdf); continue; } @@ -176,9 +176,9 @@ payload(void) if ((mem_base + mem_offset) > mem_lim) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory offset + base 0x%llx", mem_base + mem_offset); - val_print(ACS_PRINT_ERR, " exceeds the memory limit 0x%llx", mem_lim); + val_print(ERROR, " exceeds the memory limit 0x%llx", mem_lim); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -197,9 +197,9 @@ payload(void) if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); - val_print(ACS_PRINT_DEBUG, "\n Value in memory after write - 0x%x", read_value); - val_print(ACS_PRINT_ERR, "\n Memory access check failed for BDF 0x%x", bdf); + val_print(DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); + val_print(DEBUG, "\n Value in memory after write - 0x%x", read_value); + val_print(ERROR, "\n Memory access check failed for BDF 0x%x", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); val_pcie_clear_urd(bdf); return; @@ -210,7 +210,7 @@ payload(void) **/ if (check_bdf_under_rp(bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for RP BDF 0x%x", bdf); + val_print(DEBUG, "\n Skipping for RP BDF 0x%x", bdf); continue; } @@ -223,19 +223,19 @@ payload(void) if ((mem_lim >> MEM_SHIFT) > (mem_base >> MEM_SHIFT)) { - val_print(ACS_PRINT_DEBUG, "\n Entered Check_2 for bdf 0x%x", bdf); + val_print(DEBUG, "\n Entered Check_2 for bdf 0x%x", bdf); new_mem_lim = mem_base + MEM_OFFSET_LARGE; mem_base = mem_base | (mem_base >> 16); val_pcie_write_cfg(bdf, TYPE1_NP_MEM, mem_base); val_pcie_read_cfg(bdf, TYPE1_NP_MEM, &read_value); val_pcie_bar_mem_read(bdf, new_mem_lim + MEM_OFFSET_SMALL, &value); - val_print(ACS_PRINT_DEBUG, " Value read is 0x%llx", value); + val_print(DEBUG, " Value read is 0x%llx", value); if (value != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Memory range for bdf 0x%x", bdf); - val_print(ACS_PRINT_ERR, " is 0x%x", read_value); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory range for bdf 0x%x", bdf); + val_print(ERROR, " is 0x%x", read_value); + val_print(ERROR, "\n Out of range 0x%x", (new_mem_lim + MEM_OFFSET_SMALL)); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); } @@ -253,7 +253,7 @@ payload(void) * So not checking for Read-Write Data mismatch. */ if (IS_TEST_FAIL(val_get_status(pe_index))) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed. Exception on Memory Access For Bdf : 0x%x", bdf); val_pcie_clear_urd(bdf); return; @@ -263,9 +263,9 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n No RP/iEP_RP type device found with valid Memory Base/Limit Reg." - " Skipping the test.", 0); + " Skipping the test."); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else diff --git a/test_pool/pcie/p005.c b/test_pool/pcie/p005.c index b384f5fa..bb129f2a 100644 --- a/test_pool/pcie/p005.c +++ b/test_pool/pcie/p005.c @@ -38,7 +38,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); } @@ -75,7 +75,7 @@ check_bdf_under_rp(uint32_t rp_bdf) if ((dev_seg == rp_seg) && ((dev_bus >= rp_sec_bus) && (dev_bus <= rp_sub_bus))) { val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) @@ -117,7 +117,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -154,7 +154,7 @@ payload(void) /* Read Function's Memory Base Limit Register */ val_pcie_read_cfg(bdf, TYPE1_P_MEM, &read_value); - val_print(ACS_PRINT_DEBUG, "\n BDF is 0x%x", bdf); + val_print(DEBUG, "\n BDF is 0x%x", bdf); if (read_value == 0) continue; @@ -172,13 +172,13 @@ payload(void) mem_base |= (mem_base_upper << P_MEM_BU_SHIFT); mem_lim |= (mem_lim_upper << P_MEM_LU_SHIFT); - val_print(ACS_PRINT_DEBUG, "\n Memory base is 0x%llx", mem_base); - val_print(ACS_PRINT_DEBUG, " Memory lim is 0x%llx", mem_lim); + val_print(DEBUG, "\n Memory base is 0x%llx", mem_base); + val_print(DEBUG, " Memory lim is 0x%llx", mem_lim); /* If Memory Limit is programmed with value less the Base, then Skip.*/ if (mem_lim < mem_base) { - val_print(ACS_PRINT_DEBUG, "\n No P memory on secondary side of the Bridge", 0); - val_print(ACS_PRINT_DEBUG, "\n Skipping Bdf - 0x%x", bdf); + val_print(DEBUG, "\n No P memory on secondary side of the Bridge"); + val_print(DEBUG, "\n Skipping Bdf - 0x%x", bdf); continue; } @@ -189,9 +189,9 @@ payload(void) if ((mem_base + mem_offset) > mem_lim) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory offset + base 0x%llx", mem_base + mem_offset); - val_print(ACS_PRINT_ERR, " exceeds the memory limit 0x%llx", mem_lim); + val_print(ERROR, " exceeds the memory limit 0x%llx", mem_lim); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -210,9 +210,9 @@ payload(void) if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); - val_print(ACS_PRINT_DEBUG, "\n Value in memory after write - 0x%x", read_value); - val_print(ACS_PRINT_ERR, "\n Memory access check failed for BDF 0x%x\n", bdf); + val_print(DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); + val_print(DEBUG, "\n Value in memory after write - 0x%x", read_value); + val_print(ERROR, "\n Memory access check failed for BDF 0x%x\n", bdf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); val_pcie_clear_urd(bdf); return; @@ -223,7 +223,7 @@ payload(void) **/ if (check_bdf_under_rp(bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for RP BDF 0x%x", bdf); + val_print(DEBUG, "\n Skipping for RP BDF 0x%x", bdf); continue; } @@ -236,7 +236,7 @@ payload(void) if ((mem_lim >> MEM_SHIFT) > (mem_base >> MEM_SHIFT)) { - val_print(ACS_PRINT_DEBUG, "\n Entered Check_2 for bdf 0x%x", bdf); + val_print(DEBUG, "\n Entered Check_2 for bdf 0x%x", bdf); new_mem_lim = mem_base + MEM_OFFSET_LARGE; val_pcie_read_cfg(bdf, TYPE1_P_MEM, &new_value); @@ -244,7 +244,7 @@ payload(void) val_pcie_write_cfg(bdf, TYPE1_P_MEM_LU, (mem_base >> 32)); mem_base = ((uint32_t)mem_base) | ((uint32_t)mem_base >> 16); - val_print(ACS_PRINT_INFO, " mem_base new is 0x%llx", mem_base); + val_print(TRACE, " mem_base new is 0x%llx", mem_base); val_pcie_write_cfg(bdf, TYPE1_P_MEM, mem_base); val_pcie_read_cfg(bdf, TYPE1_P_MEM, &read_value); @@ -263,13 +263,13 @@ payload(void) updated_mem_lim |= (mem_lim_upper << P_MEM_LU_SHIFT); val_pcie_bar_mem_read(bdf, new_mem_lim + MEM_OFFSET_SMALL, &value); - val_print(ACS_PRINT_DEBUG, " Value read is 0x%llx", value); + val_print(DEBUG, " Value read is 0x%llx", value); if (value != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Memory range for bdf 0x%x", bdf); - val_print(ACS_PRINT_ERR, " is 0x%llx", updated_mem_base); - val_print(ACS_PRINT_ERR, " 0x%llx", updated_mem_lim); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory range for bdf 0x%x", bdf); + val_print(ERROR, " is 0x%llx", updated_mem_base); + val_print(ERROR, " 0x%llx", updated_mem_lim); + val_print(ERROR, "\n Out of range 0x%llx", (new_mem_lim + MEM_OFFSET_SMALL)); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); } @@ -288,7 +288,7 @@ payload(void) * So not checking for Read-Write Data mismatch. */ if (IS_TEST_FAIL(val_get_status(pe_index))) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed exception on Memory Access For Bdf : 0x%x", bdf); val_pcie_clear_urd(bdf); return; @@ -297,8 +297,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No RP/iEP_RP type device found with valid Memory Base/Limit Reg.", 0); + val_print(DEBUG, + "\n No RP/iEP_RP type device found with valid Memory Base/Limit Reg."); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else diff --git a/test_pool/pcie/p006.c b/test_pool/pcie/p006.c index 676c5f6c..dad82257 100644 --- a/test_pool/pcie/p006.c +++ b/test_pool/pcie/p006.c @@ -45,7 +45,7 @@ payload(void) /* Allocate memory for interrupt mappings */ intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { - val_print(ACS_PRINT_ERR, "\n Memory allocation error", 0); + val_print(ERROR, "\n Memory allocation error"); val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 1)); return; } @@ -62,7 +62,7 @@ payload(void) if ((dp_type != RP) && (dp_type != EP) && (dp_type != DP) && (dp_type != UP)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read Interrupt Line Register */ val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); @@ -78,7 +78,7 @@ payload(void) val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); return; } else { - val_print (ACS_PRINT_DEBUG, + val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); continue; @@ -94,10 +94,10 @@ payload(void) if ((intr_line >= 32 && intr_line <= 1019) || (val_gic_espi_supported() && (intr_line >= 4096 && intr_line <= val_gic_max_espi_val()))) { - val_print(ACS_PRINT_INFO, "\n Int is SPI", 0); + val_print(TRACE, "\n Int is SPI"); } else { - val_print(ACS_PRINT_ERR, "\n Int id %d is not SPI", intr_line); + val_print(ERROR, "\n Int id %d is not SPI", intr_line); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/pcie/p007.c b/test_pool/pcie/p007.c index 60411a84..815669d1 100644 --- a/test_pool/pcie/p007.c +++ b/test_pool/pcie/p007.c @@ -53,18 +53,18 @@ payload(void) { /* Test runs for atleast one RP/iEP_RP */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Fail if DPC is not supported. */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x: DPC Cap unsupported", bdf); + val_print(ERROR, "\n BDF 0x%x: DPC Cap unsupported", bdf); test_fails++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP/iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); } else if (test_fails) diff --git a/test_pool/pcie/p008.c b/test_pool/pcie/p008.c index 55d051aa..76c9b9d9 100644 --- a/test_pool/pcie/p008.c +++ b/test_pool/pcie/p008.c @@ -37,7 +37,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_print(TRACE, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); } @@ -63,7 +63,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -73,7 +73,7 @@ payload(void) num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ECAM in MCFG. Skipping test ", 0); + val_print(DEBUG, "\n No ECAM in MCFG. Skipping test "); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -94,8 +94,8 @@ payload(void) //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 if (ret == PCIE_NO_MAPPING || (data == 0)) { - val_print(ACS_PRINT_ERR, "\n Incorrect data at ECAM Base %4x ", data); - val_print(ACS_PRINT_ERR, "\n BDF is %x ", bdf); + val_print(ERROR, "\n Incorrect data at ECAM Base %4x ", data); + val_print(ERROR, "\n BDF is %x ", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << PCIE_BUS_SHIFT)|dev_index)); return; @@ -109,7 +109,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { - val_print(ACS_PRINT_ERR, "\n Incorrect data for Bdf 0x%x ", bdf); + val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << PCIE_BUS_SHIFT)|dev_index)); return; diff --git a/test_pool/pcie/p009.c b/test_pool/pcie/p009.c index 2177ca88..77ed06c7 100644 --- a/test_pool/pcie/p009.c +++ b/test_pool/pcie/p009.c @@ -52,7 +52,7 @@ check_pcie_cfg_space(uint32_t bdf) // Check PCIe Cap IDs are in range if (cid > PCIE_CAP_ID_END) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid Cap ID: 0x%x found in regular cfg space", cid); err = 1; } @@ -69,7 +69,7 @@ check_pcie_cfg_space(uint32_t bdf) // Check PCIe Ext Cap IDs are in range if (cid > PCIE_ECAP_ID_END) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid Cap ID: 0x%x found in extended cfg space", cid); err = 1; } @@ -104,9 +104,9 @@ payload(void) // Only check for Root Ports if (dp_type == RP) { test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); if (check_pcie_cfg_space(bdf)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid PCIe capability found on dev: %d", tbl_index); test_fail++; } diff --git a/test_pool/pcie/p010.c b/test_pool/pcie/p010.c index 2c47566f..87962c54 100644 --- a/test_pool/pcie/p010.c +++ b/test_pool/pcie/p010.c @@ -53,18 +53,18 @@ payload(void) { /* Test runs for atleast one RP/iEP_RP */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Fail if AER is not supported. */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x: AER Cap unsupported", bdf); + val_print(ERROR, "\n BDF 0x%x: AER Cap unsupported", bdf); test_fails++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP/iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); } else if (test_fails) diff --git a/test_pool/pcie/p011.c b/test_pool/pcie/p011.c index e97cc4b3..86a7224e 100644 --- a/test_pool/pcie/p011.c +++ b/test_pool/pcie/p011.c @@ -58,7 +58,7 @@ payload(void) if (dp_type == RP || dp_type == iEP_RP) { /* If test runs for atleast an endpoint */ - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); test_skip = 0; /* Get the offset for bus number register in the config header which has @@ -84,7 +84,7 @@ payload(void) if ((ecam_cr != ecam_cr_8) || (ecam_cr_8 != ecam_cr_16)) { - val_print(ACS_PRINT_ERR, "\n Byte Enable Read Failed for Bdf: 0x%x", bdf); + val_print(ERROR, "\n Byte Enable Read Failed for Bdf: 0x%x", bdf); test_fail++; } @@ -100,7 +100,7 @@ payload(void) ecam_cr_new = val_mmio_read8(ecam_base + busnum_offset + i); if (write_value != ecam_cr_new) { - val_print(ACS_PRINT_ERR, "\n 8 Bit Write Failed for Bdf: 0x%x", bdf); + val_print(ERROR, "\n 8 Bit Write Failed for Bdf: 0x%x", bdf); test_fail++; } } @@ -116,7 +116,7 @@ payload(void) ecam_cr_new = val_mmio_read16(ecam_base + busnum_offset); if (write_value != ecam_cr_new) { - val_print(ACS_PRINT_ERR, "\n 16 Bit Write Failed for Bdf: 0x%x", bdf); + val_print(ERROR, "\n 16 Bit Write Failed for Bdf: 0x%x", bdf); test_fail++; } @@ -131,7 +131,7 @@ payload(void) } if (test_skip) { - val_print(ACS_PRINT_DEBUG, "\n No RP/iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } if (test_fail) diff --git a/test_pool/pcie/p017.c b/test_pool/pcie/p017.c index ecac51c5..9c429ebb 100644 --- a/test_pool/pcie/p017.c +++ b/test_pool/pcie/p017.c @@ -61,7 +61,7 @@ payload(void) /* Get the number of Root Complex in the system */ if (!num_pcie_rc) { - val_print(ACS_PRINT_DEBUG, "\n Skip because no PCIe RC detected ", 0); + val_print(DEBUG, "\n Skip because no PCIe RC detected "); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -78,7 +78,7 @@ payload(void) if (!rc_ats_supp) { - val_print(ACS_PRINT_DEBUG, "\n ATS Capability Not Present for RC: %x", num_pcie_rc); + val_print(DEBUG, "\n ATS Capability Not Present for RC: %x", num_pcie_rc); continue; } } @@ -104,11 +104,11 @@ payload(void) /* If test runs for atleast one RP */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n For BDF : 0x%x", bdf); + val_print(DEBUG, "\n For BDF : 0x%x", bdf); /* Read the ACS Capability */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); + val_print(ERROR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); test_fails++; continue; } @@ -118,7 +118,7 @@ payload(void) /* Extract ACS directed translated p2p bit */ data = VAL_EXTRACT_BITS(acs_data, 6, 6); if (data == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Directed Translated P2P not supported, Bdf : 0x%x", bdf); test_fails++; } @@ -126,8 +126,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No RP type device found with P2P and ATS Support. Skipping test", 0); + val_print(DEBUG, + "\n No RP type device found with P2P and ATS Support. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); } else if (test_fails) diff --git a/test_pool/pcie/p018.c b/test_pool/pcie/p018.c index f529fe8d..715f4e21 100644 --- a/test_pool/pcie/p018.c +++ b/test_pool/pcie/p018.c @@ -70,25 +70,25 @@ payload(void) /* Test runs for atleast one Root Port */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* It ACS Not Supported, Fail. */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x: ACS Cap unsupported", bdf); + val_print(ERROR, "\n BDF 0x%x: ACS Cap unsupported", bdf); test_fails++; continue; } /* If AER Not Supported, Fail. */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x: AER Cap unsupported", bdf); + val_print(ERROR, "\n BDF 0x%x: AER Cap unsupported", bdf); test_fails++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (test_fails) diff --git a/test_pool/pcie/p019.c b/test_pool/pcie/p019.c index b829ce2b..734abd01 100644 --- a/test_pool/pcie/p019.c +++ b/test_pool/pcie/p019.c @@ -62,11 +62,11 @@ payload(void) { /* Test runs for atleast one Root Port */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read the ACS Capability */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); test_fails++; continue; @@ -77,41 +77,41 @@ payload(void) /* Extract ACS source validation bit */ data = VAL_EXTRACT_BITS(acs_data, 0, 0); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Source validation not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS translation blocking bit */ data = VAL_EXTRACT_BITS(acs_data, 1, 1); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Translation blocking not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS P2P request redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 2, 2); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS P2P completion redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 3, 3); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n P2P completion redirect not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS upstream forwarding bit */ data = VAL_EXTRACT_BITS(acs_data, 4, 4); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } if (curr_bdf_failed > 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n ACS Capability Check Failed, Bdf : 0x%x", bdf); curr_bdf_failed = 0; test_fails++; @@ -120,7 +120,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP type device found. Skipping device", 0); + val_print(DEBUG, "\n No RP type device found. Skipping device"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); } else if (test_fails) diff --git a/test_pool/pcie/p021.c b/test_pool/pcie/p021.c index 4babca40..913430d0 100644 --- a/test_pool/pcie/p021.c +++ b/test_pool/pcie/p021.c @@ -35,7 +35,7 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0) == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ECAMs discovered, Skipping test", 0); + val_print(DEBUG, "\n No ECAMs discovered, Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } diff --git a/test_pool/pcie/p023.c b/test_pool/pcie/p023.c index c36cf7b9..46ce4c2f 100644 --- a/test_pool/pcie/p023.c +++ b/test_pool/pcie/p023.c @@ -47,7 +47,7 @@ payload(void) /* Allocate memory for interrupt mappings */ intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { - val_print(ACS_PRINT_ERR, "\n Memory allocation error", 0); + val_print(ERROR, "\n Memory allocation error"); val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 1)); return; } @@ -64,7 +64,7 @@ payload(void) if ((dp_type != RP) && (dp_type != EP) && (dp_type != DP) && (dp_type != UP)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read Interrupt Line Register */ val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); @@ -80,7 +80,7 @@ payload(void) val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); return; } else { - val_print (ACS_PRINT_DEBUG, + val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); continue; @@ -96,10 +96,10 @@ payload(void) if ((intr_line >= 32 && intr_line <= 1019) || (val_gic_espi_supported() && (intr_line >= 4096 && intr_line <= val_gic_max_espi_val()))) { - val_print(ACS_PRINT_INFO, "\n Int is SPI", 0); + val_print(TRACE, "\n Int is SPI"); } else { - val_print(ACS_PRINT_ERR, "\n Int id %d is not SPI", intr_line); + val_print(ERROR, "\n Int id %d is not SPI", intr_line); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -116,8 +116,8 @@ payload(void) } if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) { - val_print(ACS_PRINT_ERR, - "\n Legacy interrupt programmed with incorrect trigger type", 0); + val_print(ERROR, + "\n Legacy interrupt programmed with incorrect trigger type"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); return; } diff --git a/test_pool/pcie/p030.c b/test_pool/pcie/p030.c index f9fb1638..bee28c8f 100644 --- a/test_pool/pcie/p030.c +++ b/test_pool/pcie/p030.c @@ -37,7 +37,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_print(TRACE, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); } @@ -77,12 +77,12 @@ get_dsf_bdf(uint32_t rp_bdf, uint32_t *target_bdf) if ((dev_seg == rp_seg) && (dev_bus >= rp_sec_bus) && (dev_bus <= rp_sub_bus)) { val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Downstream class code is 0x%x", reg_value); + val_print(DEBUG, "\n Downstream class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping downstream BDF 0x%x", dev_bdf); + val_print(DEBUG, "\n Skipping downstream BDF 0x%x", dev_bdf); continue; } *target_bdf = dev_bdf; @@ -122,7 +122,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -136,8 +136,8 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n tbl_index %x", tbl_index - 1); - val_print(ACS_PRINT_DEBUG, " BDF %x", bdf); + val_print(DEBUG, "\n tbl_index %x", tbl_index - 1); + val_print(DEBUG, " BDF %x", bdf); dp_type = val_pcie_device_port_type(bdf); /* Check entry is RP/EP/DP/UP. Else move to next BDF. */ @@ -159,12 +159,12 @@ payload(void) } else { val_pcie_read_cfg(bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for BDF 0x%x", bdf); + val_print(DEBUG, "\n Skipping for BDF 0x%x", bdf); continue; } @@ -172,7 +172,7 @@ payload(void) } /* Skip this function if it doesn't have mmio BAR */ - val_print(ACS_PRINT_DEBUG, " Bar Base %x", bar_base); + val_print(DEBUG, " Bar Base %x", bar_base); if (!bar_base) continue; @@ -215,11 +215,11 @@ payload(void) * - All 1's response received * - Abort is not received. */ - val_print(ACS_PRINT_DEBUG, " bar_data %x ", bar_data); + val_print(DEBUG, " bar_data %x ", bar_data); if (!(IS_TEST_PASS(val_get_status(pe_index)) || (bar_data == PCIE_UNKNOWN_RESPONSE) || (val_pcie_is_urd(bdf)))) { - val_print(ACS_PRINT_ERR, "\n BDF %x MSE functionality failure", bdf); + val_print(ERROR, "\n BDF %x MSE functionality failure", bdf); test_fails++; } diff --git a/test_pool/pcie/p031.c b/test_pool/pcie/p031.c index ef7d0090..f37628c0 100644 --- a/test_pool/pcie/p031.c +++ b/test_pool/pcie/p031.c @@ -46,7 +46,7 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); dp_type = val_pcie_device_port_type(bdf); /* Check entry is RP/EP/DP/UP. Else move to next BDF. */ @@ -70,8 +70,8 @@ payload(void) if (((reg_value & BIST_BC_MASK) == 0x00) && (((reg_value & BIST_CC_MASK) != 0x00) || ((reg_value & BIST_SB_MASK) != 0x00))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x", bdf); - val_print(ACS_PRINT_ERR, " BIST Reg Value : %d", reg_value); + val_print(ERROR, "\n BDF 0x%x", bdf); + val_print(ERROR, " BIST Reg Value : %d", reg_value); test_fails++; } } diff --git a/test_pool/pcie/p032.c b/test_pool/pcie/p032.c index f7bea77c..7a9836ae 100644 --- a/test_pool/pcie/p032.c +++ b/test_pool/pcie/p032.c @@ -47,7 +47,7 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); dp_type = val_pcie_device_port_type(bdf); /* Check entry is RP/EP/DP/UP. Else move to next BDF. */ @@ -67,8 +67,8 @@ payload(void) /* Check Capabilities Pointer is not NULL and is between 40h and FCh */ if (!((cap_ptr_value != 0x00) && ((cap_ptr_value >= 0x40) && (cap_ptr_value <= 0xFC)))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x", bdf); - val_print(ACS_PRINT_ERR, " Cap Ptr Value: 0x%x", cap_ptr_value); + val_print(ERROR, "\n BDF 0x%x", bdf); + val_print(ERROR, " Cap Ptr Value: 0x%x", cap_ptr_value); test_fails++; } } diff --git a/test_pool/pcie/p033.c b/test_pool/pcie/p033.c index 577df2c5..3888c4f5 100644 --- a/test_pool/pcie/p033.c +++ b/test_pool/pcie/p033.c @@ -48,7 +48,7 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); dp_type = val_pcie_device_port_type(bdf); /* Check entry is RP/EP/DP/UP. Else move to next BDF. */ @@ -58,7 +58,7 @@ payload(void) /* Retrieve the addr of PCI express capability (10h) */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_INFO, "\n PCIe Express Capability not present ", 0); + val_print(TRACE, "\n PCIe Express Capability not present "); continue; } @@ -74,8 +74,8 @@ payload(void) /* Valid payload size between 000b (129-bytes) to 101b (4096 bytes) */ if (!((max_payload_value >= 0x00) && (max_payload_value <= 0x05))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x", bdf); - val_print(ACS_PRINT_ERR, " Cap Ptr Value: 0x%x", max_payload_value); + val_print(ERROR, "\n BDF 0x%x", bdf); + val_print(ERROR, " Cap Ptr Value: 0x%x", max_payload_value); test_fails++; } } diff --git a/test_pool/pcie/p035.c b/test_pool/pcie/p035.c index e54a6bf4..1b691ef4 100644 --- a/test_pool/pcie/p035.c +++ b/test_pool/pcie/p035.c @@ -38,7 +38,7 @@ uint32_t is_flr_failed(uint32_t bdf) val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); if (((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) { - val_print(ACS_PRINT_ERR, "\n BME is not cleared", 0); + val_print(ERROR, "\n BME is not cleared"); check_failed++; } @@ -46,7 +46,7 @@ uint32_t is_flr_failed(uint32_t bdf) val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); if (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0) { - val_print(ACS_PRINT_ERR, "\n MSE is not cleared", 0); + val_print(ERROR, "\n MSE is not cleared"); check_failed++; } @@ -98,8 +98,8 @@ payload(void) ((base_cc == UNCLAS_CC) || (base_cc == MAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for BDF - 0x%x ", bdf); - val_print(ACS_PRINT_DEBUG, " Classcode is : 0x%x ", base_cc); + val_print(DEBUG, "\n Skipping for BDF - 0x%x ", bdf); + val_print(DEBUG, " Classcode is : 0x%x ", base_cc); continue; } @@ -107,11 +107,11 @@ payload(void) if (dp_type == EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF 0x%x ", bdf); + val_print(DEBUG, "\n BDF 0x%x ", bdf); /* Read FLR capability bit value */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, "\n PCIe Express Capability not present ", 0); + val_print(DEBUG, "\n PCIe Express Capability not present "); continue; } val_pcie_read_cfg(bdf, cap_base + DCAPR_OFFSET, ®_value); @@ -128,14 +128,14 @@ payload(void) /* If memory allocation fail, fail the test */ if (func_config_space == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation fail", 0); + val_print(ERROR, "\n Memory allocation fail"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); return; } /* Get function configuration space address */ config_space_addr = val_pcie_get_bdf_config_addr(bdf); - val_print(ACS_PRINT_INFO, " config space addr 0x%x", config_space_addr); + val_print(TRACE, " config space addr 0x%x", config_space_addr); /* Save the function config space to restore after FLR */ for (idx = 0; idx < PCIE_CFG_SIZE / 4; idx++) { @@ -151,7 +151,7 @@ payload(void) status = val_time_delay_ms(100 * ONE_MILLISECOND); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to time delay for BDF 0x%x ", bdf); + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(func_config_space); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; @@ -189,7 +189,7 @@ payload(void) if ((device_id == DIDR_RRS_MASK) && ((vendor_id == TYPE01_VIDR_MASK) || (vendor_id == VIDR_RRS_MASK))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x not present", bdf); + val_print(ERROR, "\n BDF 0x%x not present", bdf); test_fails++; val_memory_free_aligned(func_config_space); continue; @@ -208,8 +208,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No EP type device found with PCIe Express Cap support. Skipping test", 0); + val_print(DEBUG, + "\n No EP type device found with PCIe Express Cap support. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (test_fails) diff --git a/test_pool/pcie/p036.c b/test_pool/pcie/p036.c index 3aef5cfc..8a0852ff 100644 --- a/test_pool/pcie/p036.c +++ b/test_pool/pcie/p036.c @@ -59,7 +59,7 @@ payload(void) /* Check entry is Downstream port or RP */ if ((dp_type == DP) || (dp_type == RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read the secondary and subordinate bus number */ val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); @@ -89,7 +89,7 @@ payload(void) /* If the RP/DP does not support ARI forwarding, print a warning. Continue the test since this validates the disabled ARI forwarding case. */ if (status == 0) - val_print(ACS_PRINT_WARN, "\n ARI Forwarding not supported for bdf 0x%x", bdf); + val_print(WARN, "\n ARI Forwarding not supported for bdf 0x%x", bdf); /* If test runs on atleast one device */ test_skip = 0; @@ -106,8 +106,8 @@ payload(void) /* Fail the test if the bitfied does not respond to the write */ if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n ARI Forwarding Enable bit not cleared for", 0); - val_print(ACS_PRINT_ERR, " bdf 0x%x", bdf); + val_print(ERROR, "\n ARI Forwarding Enable bit not cleared for"); + val_print(ERROR, " bdf 0x%x", bdf); test_fails++; continue; } @@ -118,8 +118,8 @@ payload(void) if (status || (reg_value == PCIE_UNKNOWN_RESPONSE)) { test_fails++; - val_print(ACS_PRINT_ERR, "\n Dev 0x%x found under", dev_bdf); - val_print(ACS_PRINT_ERR, " RP bdf 0x%x", bdf); + val_print(ERROR, "\n Dev 0x%x found under", dev_bdf); + val_print(ERROR, " RP bdf 0x%x", bdf); } /* Configuration Requests specifying Device Numbers (1-31) must be terminated by the @@ -134,8 +134,8 @@ payload(void) if (reg_value != PCIE_UNKNOWN_RESPONSE) { test_fails++; - val_print(ACS_PRINT_ERR, "\n Dev 0x%x found under", dev_bdf); - val_print(ACS_PRINT_ERR, " RP bdf 0x%x", bdf); + val_print(ERROR, "\n Dev 0x%x found under", dev_bdf); + val_print(ERROR, " RP bdf 0x%x", bdf); } } } diff --git a/test_pool/pcie/p037.c b/test_pool/pcie/p037.c index ea4a867b..3254ec60 100644 --- a/test_pool/pcie/p037.c +++ b/test_pool/pcie/p037.c @@ -57,7 +57,7 @@ payload(void) /* BSA -> PCI_IN_13 SBSA(iEP_RP) -> RHVZJY */ if (dp_type == RP || dp_type == iEP_RP) { /* Read Vendor ID of RP with ECAM based mechanism, and compare it with the */ - val_print(ACS_PRINT_DEBUG, "\n BDF 0x%x", bdf); + val_print(DEBUG, "\n BDF 0x%x", bdf); ecam_base = val_pcie_get_ecam_base(bdf); /* If test runs for atleast an endpoint */ @@ -73,21 +73,21 @@ payload(void) /* Read Function's Class Code through Pciio Protocol method */ Status = val_pcie_io_read_cfg(bdf, TYPE01_RIDR, &pciio_proto_cc); if (Status == PCIE_NO_MAPPING) { - val_print(ACS_PRINT_ERR, "\n PciIo protocol failed for BDF 0x%x", bdf); + val_print(ERROR, "\n PciIo protocol failed for BDF 0x%x", bdf); fail_cnt++; continue; } if (ecam_cc != pciio_proto_cc) { - val_print(ACS_PRINT_ERR, "\n Config Txn Error : 0x%x ", bdf); + val_print(ERROR, "\n Config Txn Error : 0x%x ", bdf); fail_cnt++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP/iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (fail_cnt) diff --git a/test_pool/pcie/p038.c b/test_pool/pcie/p038.c index 1aa88636..19057d64 100644 --- a/test_pool/pcie/p038.c +++ b/test_pool/pcie/p038.c @@ -67,9 +67,9 @@ payload(void) val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value); device_id = (reg_value >> TYPE01_DIDR_SHIFT) & TYPE01_DIDR_MASK; vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK; - val_print(ACS_PRINT_DEBUG, "\n BDF 0x%x ", bdf); - val_print(ACS_PRINT_DEBUG, "Dev ID 0x%x ", device_id); - val_print(ACS_PRINT_DEBUG, "Vendor ID 0x%x", vendor_id); + val_print(DEBUG, "\n BDF 0x%x ", bdf); + val_print(DEBUG, "Dev ID 0x%x ", device_id); + val_print(DEBUG, "Vendor ID 0x%x", vendor_id); rp_ecam_base = val_pcie_get_ecam_base(bdf); rp_segment = PCIE_EXTRACT_BDF_SEG(bdf); @@ -81,7 +81,7 @@ payload(void) if (ecam_base == rp_ecam_base && segment == rp_segment) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n ECAM base 0x%llx matches with RPs base address ", ecam_base); goto next_bdf; } @@ -89,13 +89,13 @@ payload(void) ecam_index++; } - val_print(ACS_PRINT_ERR, "\n RP BDF 0x%x not under any HB", bdf); + val_print(ERROR, "\n RP BDF 0x%x not under any HB", bdf); test_fail++; } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RP or iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No RP or iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fail) diff --git a/test_pool/pcie/p039.c b/test_pool/pcie/p039.c index 88a0bf58..d58c09ee 100644 --- a/test_pool/pcie/p039.c +++ b/test_pool/pcie/p039.c @@ -54,15 +54,15 @@ payload(void) /* Check entry is endpoint */ if (dp_type == EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF 0x%x", bdf); + val_print(DEBUG, "\n BDF 0x%x", bdf); val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); int_pin = VAL_EXTRACT_BITS(reg_value, TYPE01_IPR_SHIFT, TYPE01_IPR_SHIFT + 7); - val_print(ACS_PRINT_DEBUG, " int pin value %d", int_pin); + val_print(DEBUG, " int pin value %d", int_pin); - val_print(ACS_PRINT_DEBUG, " MSI cap %d", + val_print(DEBUG, " MSI cap %d", val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base)); - val_print(ACS_PRINT_DEBUG, " MSIX cap %d", + val_print(DEBUG, " MSIX cap %d", val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base)); /* If test runs for atleast an endpoint */ @@ -72,7 +72,7 @@ payload(void) if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) && (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND) && ((int_pin >= 1) && (int_pin <= 4))) { - val_print(ACS_PRINT_ERR, "\n INTx supported but MSI/MSI-X not supported", 0); + val_print(ERROR, "\n INTx supported but MSI/MSI-X not supported"); test_fails++; } } diff --git a/test_pool/pcie/p042.c b/test_pool/pcie/p042.c index 2ad70d1a..74369dda 100644 --- a/test_pool/pcie/p042.c +++ b/test_pool/pcie/p042.c @@ -49,25 +49,25 @@ static void payload(void) /* Skip the device if PASID extended capability not supported */ if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, "\n PASID extended capability not supported.", 0); - val_print(ACS_PRINT_DEBUG, " Skipping for BDF: 0x%x", bdf); + val_print(DEBUG, "\n PASID extended capability not supported."); + val_print(DEBUG, " Skipping for BDF: 0x%x", bdf); continue; } /* Raise an error if any failure in obtaining the PASID max width */ else if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Error in obtaining the PASID max width for BDF: 0x%x", bdf); fail_cnt++; } - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); - val_print(ACS_PRINT_DEBUG, "- Max PASID bits - 0x%x", max_pasids); + val_print(DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "- Max PASID bits - 0x%x", max_pasids); if (max_pasids > 0) { skip = 0; if (max_pasids < MIN_PASID_SUPPORT) { - val_print(ACS_PRINT_ERR, "\n Max PASID support less than 16 bits ", 0); + val_print(ERROR, "\n Max PASID support less than 16 bits "); fail_cnt++; } } @@ -81,13 +81,13 @@ static void payload(void) if (val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { max_pasids = val_smmu_max_pasids(num_smmu); - val_print(ACS_PRINT_DEBUG, "\n SMMU check- Max PASID bits- 0x%x", max_pasids); + val_print(DEBUG, "\n SMMU check- Max PASID bits- 0x%x", max_pasids); if (max_pasids > 0) { skip = 0; if (max_pasids < MIN_PASID_SUPPORT) { - val_print(ACS_PRINT_ERR, "\n Max PASID support less than 16 bits ", 0); + val_print(ERROR, "\n Max PASID support less than 16 bits "); fail_cnt++; } } diff --git a/test_pool/pcie/p045.c b/test_pool/pcie/p045.c index e7febb9d..c1d11f93 100644 --- a/test_pool/pcie/p045.c +++ b/test_pool/pcie/p045.c @@ -45,7 +45,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received Exception %d", interrupt_type); + val_print(ERROR, "\n Received Exception %d", interrupt_type); val_set_status(index, RESULT_FAIL(test_num, 02)); } @@ -86,7 +86,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to install exception handler", 0); + val_print(ERROR, "\n Failed to install exception handler"); val_set_status(index, RESULT_FAIL(test_num, 01)); return; } @@ -117,45 +117,45 @@ payload(void) offset = BAR0_OFFSET; - val_print(ACS_PRINT_DEBUG, "\n BDF under check %.6x", bdf); + val_print(DEBUG, "\n BDF under check %.6x", bdf); while (offset <= max_bar_offset) { val_pcie_read_cfg(bdf, offset, &bar_value); - val_print(ACS_PRINT_DEBUG, "\n The BAR value of bdf %.6x", bdf); - val_print(ACS_PRINT_DEBUG, " is %x ", bar_value); + val_print(DEBUG, "\n The BAR value of bdf %.6x", bdf); + val_print(DEBUG, " is %x ", bar_value); base = 0; if (bar_value == 0) { /** This BAR is not implemented **/ - val_print(ACS_PRINT_DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf); + val_print(DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf); tbl_index++; goto next_bdf; } /* Skip for IO address space */ if (bar_value & 0x1) { - val_print(ACS_PRINT_DEBUG, "\n BAR is used for IO address space request", 0); - val_print(ACS_PRINT_DEBUG, " for BDF 0x%x", bdf); + val_print(DEBUG, "\n BAR is used for IO address space request"); + val_print(DEBUG, " for BDF 0x%x", bdf); tbl_index++; goto next_bdf; } val_pcie_read_cfg(bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping BDF as 0x%x", bdf); + val_print(DEBUG, "\n Skipping BDF as 0x%x", bdf); tbl_index++; goto next_bdf; } if (BAR_REG(bar_value) == BAR_64_BIT) { - val_print(ACS_PRINT_INFO, - "\n The BAR supports 64-bit address decoding capability", 0); + val_print(TRACE, + "\n The BAR supports 64-bit address decoding capability"); val_pcie_read_cfg(bdf, offset+4, &bar_value_1); base = bar_value_1; @@ -178,8 +178,8 @@ payload(void) } else { - val_print(ACS_PRINT_INFO, - "\n The BAR supports 32-bit address decoding capability", 0); + val_print(TRACE, + "\n The BAR supports 32-bit address decoding capability"); /* BAR supports 32-bit address. Write all 1's * to BARn and identify the size requested @@ -194,11 +194,11 @@ payload(void) base = bar_value; } - val_print(ACS_PRINT_DEBUG, "\n BAR size is %x", bar_size); + val_print(DEBUG, "\n BAR size is %x", bar_size); /* Check if bar supports the remap size */ if (bar_size < 1024) { - val_print(ACS_PRINT_ERR, "\n Bar size less than remap requested size", 0); + val_print(ERROR, "\n Bar size less than remap requested size"); goto next_bar; } @@ -222,7 +222,7 @@ payload(void) break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in ioremap with status %x", status); + val_print(ERROR, "\n Failed in ioremap with status %x", status); test_fail++; val_set_status(index, RESULT_FAIL(test_num, test_fail)); goto next_bar; @@ -234,12 +234,12 @@ payload(void) old_data = *(uint32_t *)(baseptr); *(uint32_t *)(baseptr) = DATA; data = *(uint32_t *)(baseptr); - val_print(ACS_PRINT_DEBUG, "\n Value read: %llx", data); + val_print(DEBUG, "\n Value read: %llx", data); *(uint32_t *)(baseptr) = old_data; exception_return_device: if (IS_TEST_FAIL(val_get_status(index))) { - val_print(ACS_PRINT_ERR, "\n Device memory access failed for Bdf: 0x%x", bdf); + val_print(ERROR, "\n Device memory access failed for Bdf: 0x%x", bdf); /* Setting the status to Pass to enable test for next BDF. * Failure has been recorded with test_fail. */ diff --git a/test_pool/pcie/p046.c b/test_pool/pcie/p046.c index c805c17a..aa6c4613 100644 --- a/test_pool/pcie/p046.c +++ b/test_pool/pcie/p046.c @@ -103,7 +103,7 @@ payload (void) /* Get BDF of a device */ dev_bdf = val_peripheral_get_info (ANY_BDF, count - 1); if (dev_bdf) { - val_print (ACS_PRINT_INFO, " Checking PCI device with BDF %4X\n", dev_bdf); + val_print (TRACE, " Checking PCI device with BDF %4X\n", dev_bdf); /* Read MSI(X) vectors */ ret = val_get_msi_vectors (dev_bdf, &dev_mvec); @@ -117,12 +117,12 @@ payload (void) mvec = dev_mvec; while(mvec) { if(mvec->vector.vector_irq_base < LPI_BASE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, " MSI vector irq %llx is not an LPI\n", mvec->vector.vector_irq_base); val_set_status (index, RESULT_FAIL (TEST_NUM, mvec->vector.vector_irq_base)); status = 1; }else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " MSI vector irq %llx is an LPI\n", mvec->vector.vector_irq_base); } mvec = mvec->next; @@ -137,7 +137,7 @@ payload (void) } if (test_skip) { - val_print(ACS_PRINT_DEBUG, "\n No MSI vectors found ", 0); + val_print(DEBUG, "\n No MSI vectors found "); val_set_status (index, RESULT_SKIP(TEST_NUM, 0)); } else if (!status) { val_set_status (index, RESULT_PASS(TEST_NUM, 0)); diff --git a/test_pool/pcie/p047.c b/test_pool/pcie/p047.c index 7a729f6d..acf1039a 100644 --- a/test_pool/pcie/p047.c +++ b/test_pool/pcie/p047.c @@ -53,7 +53,7 @@ static void payload(void) && (dp_type != RCEC) && (dp_type != RCiEP)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", dev_bdf); + val_print(DEBUG, "\n BDF - 0x%x", dev_bdf); dev_type = val_pcie_get_device_type(dev_bdf); /* Allow only type-1 headers and skip others */ @@ -69,7 +69,7 @@ static void payload(void) /* Extract mem type */ data = VAL_EXTRACT_BITS(bar_data, 1, 2); if (data != 0) { - val_print(ACS_PRINT_ERR, "\n NP type-1 pcie is not 32-bit mem type", 0); + val_print(ERROR, "\n NP type-1 pcie is not 32-bit mem type"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); status = 2; break; @@ -78,8 +78,8 @@ static void payload(void) /* Scan the all PCIe bridge devices and check memory type */ ret = val_pcie_scan_bridge_devices_and_check_memtype(dev_bdf); if (ret) { - val_print(ACS_PRINT_ERR, "\n NP type-1 pcie bridge end device" - "is not 32-bit mem type", 0); + val_print(ERROR, "\n NP type-1 pcie bridge end device" + "is not 32-bit mem type"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); status = 2; break; @@ -94,8 +94,8 @@ static void payload(void) } if (!status) { - val_print(ACS_PRINT_DEBUG, - "\n No Type1 Non Prefetcable BAR Detected. Skipping test", 0); + val_print(DEBUG, + "\n No Type1 Non Prefetcable BAR Detected. Skipping test"); val_set_status(index, RESULT_SKIP (TEST_NUM, 3)); } else if (status == 1) diff --git a/test_pool/pcie/p051.c b/test_pool/pcie/p051.c index ae3742e9..d6c79f22 100644 --- a/test_pool/pcie/p051.c +++ b/test_pool/pcie/p051.c @@ -41,7 +41,7 @@ payload(void) if (ret == ACS_STATUS_SKIP) val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); else if (ret) { - val_print(ACS_PRINT_ERR, "\nCheck failed - Slot Implemented[8] PCI Express Capabilities", 0); + val_print(ERROR, "\nCheck failed - Slot Implemented[8] PCI Express Capabilities"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); } else diff --git a/test_pool/pcie/p058.c b/test_pool/pcie/p058.c index e9d0e429..15571927 100644 --- a/test_pool/pcie/p058.c +++ b/test_pool/pcie/p058.c @@ -49,7 +49,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_DEBUG, "\n Received exception of type: %d", interrupt_type); + val_print(DEBUG, "\n Received exception of type: %d", interrupt_type); val_set_status(pe_index, RESULT_PASS(test_num, 01)); } @@ -90,12 +90,12 @@ get_dsf_bdf(uint32_t rp_bdf, uint32_t *target_bdf) if ((dev_seg == rp_seg) && (dev_bus >= rp_sec_bus) && (dev_bus <= rp_sub_bus)) { val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Downstream class code is 0x%x", reg_value); + val_print(DEBUG, "\n Downstream class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping downstream BDF 0x%x", dev_bdf); + val_print(DEBUG, "\n Skipping downstream BDF 0x%x", dev_bdf); continue; } *target_bdf = dev_bdf; @@ -136,7 +136,7 @@ payload(void *arg) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(test_num, 01)); return; } @@ -150,7 +150,7 @@ payload(void *arg) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n tbl_index %x", tbl_index - 1); + val_print(DEBUG, "\n tbl_index %x", tbl_index - 1); dp_type = val_pcie_device_port_type(bdf); @@ -158,7 +158,7 @@ payload(void *arg) if ((dp_type != test_data->dev_type1) && (dp_type != test_data->dev_type2)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Get BIST register value */ reg_value = val_pcie_get_bist(bdf); @@ -168,8 +168,8 @@ payload(void *arg) if (((reg_value & BIST_BC_MASK) == 0x00) && (((reg_value & BIST_CC_MASK) != 0x00) || ((reg_value & BIST_SB_MASK) != 0x00))) { - val_print(ACS_PRINT_ERR, "\n BDF - 0x%x", bdf); - val_print(ACS_PRINT_ERR, " BIST Reg Value : %d", reg_value); + val_print(ERROR, "\n BDF - 0x%x", bdf); + val_print(ERROR, " BIST Reg Value : %d", reg_value); test_fails++; } @@ -179,8 +179,8 @@ payload(void *arg) /* Check Capabilities Pointer is not NULL and is between 40h and FCh */ if (!((reg_value != 0x00) && ((reg_value >= 0x40) && (reg_value <= 0xFC)))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x", bdf); - val_print(ACS_PRINT_ERR, " Cap Ptr Value: 0x%x", reg_value); + val_print(ERROR, "\n BDF 0x%x", bdf); + val_print(ERROR, " Cap Ptr Value: 0x%x", reg_value); test_fails++; } @@ -198,12 +198,12 @@ payload(void *arg) val_pcie_get_mmio_bar(dsf_bdf, &bar_base); } else { val_pcie_read_cfg(bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for BDF 0x%x", bdf); + val_print(DEBUG, "\n Skipping for BDF 0x%x", bdf); continue; } @@ -211,7 +211,7 @@ payload(void *arg) } /* Skip this function if it doesn't have mmio BAR */ - val_print(ACS_PRINT_DEBUG, " Bar Base %x", bar_base); + val_print(DEBUG, " Bar Base %x", bar_base); if (!bar_base) continue; @@ -254,11 +254,11 @@ payload(void *arg) * - All 1's response received * - Abort is not received. */ - val_print(ACS_PRINT_DEBUG, " bar_data %x ", bar_data); + val_print(DEBUG, " bar_data %x ", bar_data); if (!(IS_TEST_PASS(val_get_status(pe_index)) || (bar_data == PCIE_UNKNOWN_RESPONSE) || (val_pcie_is_urd(bdf)))) { - val_print(ACS_PRINT_ERR, "\n BDF %x MSE functionality failure", bdf); + val_print(ERROR, "\n BDF %x MSE functionality failure", bdf); test_fails++; } @@ -270,8 +270,8 @@ payload(void *arg) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n Found no target device type with MMIO BAR. Skipping test.", 0); + val_print(DEBUG, + "\n Found no target device type with MMIO BAR. Skipping test."); val_set_status(pe_index, RESULT_SKIP(test_num, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p061.c b/test_pool/pcie/p061.c index c8158445..ed61c4d8 100644 --- a/test_pool/pcie/p061.c +++ b/test_pool/pcie/p061.c @@ -66,8 +66,8 @@ payload(void *arg) if (dp_type != test_data->dev_type) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); - val_print(ACS_PRINT_DEBUG, " dp_type is %llx", dp_type); + val_print(DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, " dp_type is %llx", dp_type); /* Retrieve the addr of PCI express capability (10h) */ val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); @@ -84,8 +84,8 @@ payload(void *arg) /* Valid payload size between 000b (129-bytes) to 101b (4096 bytes) */ if (!((max_payload_value >= 0x00) && (max_payload_value <= 0x05))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x", bdf); - val_print(ACS_PRINT_ERR, " Cap Ptr Value: 0x%x", max_payload_value); + val_print(ERROR, "\n BDF 0x%x", bdf); + val_print(ERROR, " Cap Ptr Value: 0x%x", max_payload_value); test_fails++; } } diff --git a/test_pool/pcie/p062.c b/test_pool/pcie/p062.c index 16941f12..c8449f74 100644 --- a/test_pool/pcie/p062.c +++ b/test_pool/pcie/p062.c @@ -57,10 +57,10 @@ payload(void) /* Check for RCiEP, iEP_EP and iEP_RP type devices */ if (dp_type == RCiEP || dp_type == iEP_EP || dp_type == iEP_RP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x ", bdf); + val_print(DEBUG, "\n BDF - 0x%x ", bdf); /* Extract Hdr Type */ hdr_type = val_pcie_function_header_type(bdf); - val_print(ACS_PRINT_INFO, "\n HDR TYPE 0x%x ", hdr_type); + val_print(TRACE, "\n HDR TYPE 0x%x ", hdr_type); max_bar = 0; /* For Type0 header max bars 6, type1 header max bars 2 */ @@ -68,7 +68,7 @@ payload(void) max_bar = TYPE0_MAX_BARS; else if (hdr_type == TYPE1_HEADER) max_bar = TYPE1_MAX_BARS; - val_print(ACS_PRINT_INFO, "\n MAX BARS 0x%x ", max_bar); + val_print(TRACE, "\n MAX BARS 0x%x ", max_bar); for (bar_index = 0; bar_index < max_bar; bar_index++) { @@ -86,8 +86,8 @@ payload(void) addr_type = (reg_value >> BAR_MDT_SHIFT) & BAR_MDT_MASK; if ((addr_type != BITS_32) && (addr_type != BITS_64)) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x ", bdf); - val_print(ACS_PRINT_ERR, " Addr Type: 0x%x", addr_type); + val_print(ERROR, "\n BDF 0x%x ", bdf); + val_print(ERROR, " Addr Type: 0x%x", addr_type); test_fails++; continue; } @@ -99,7 +99,7 @@ payload(void) /* Check BAR must be MMIO */ if (reg_value & BAR_MIT_MASK) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x Not MMIO", 0); + val_print(ERROR, "\n BDF 0x%x Not MMIO"); test_fails++; } } diff --git a/test_pool/pcie/p063.c b/test_pool/pcie/p063.c index aea93303..cf618db2 100644 --- a/test_pool/pcie/p063.c +++ b/test_pool/pcie/p063.c @@ -39,7 +39,7 @@ uint32_t is_flr_failed(uint32_t bdf) val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); if (((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) { - val_print(ACS_PRINT_ERR, "\n BME is not cleared", 0); + val_print(ERROR, "\n BME is not cleared"); check_failed++; } @@ -47,7 +47,7 @@ uint32_t is_flr_failed(uint32_t bdf) val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); if (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0) { - val_print(ACS_PRINT_ERR, "\n MSE is not cleared", 0); + val_print(ERROR, "\n MSE is not cleared"); check_failed++; } @@ -99,8 +99,8 @@ payload(void) ((base_cc == UNCLAS_CC) || (base_cc == MAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping for BDF - 0x%x ", bdf); - val_print(ACS_PRINT_DEBUG, " Classcode is : 0x%x ", base_cc); + val_print(DEBUG, "\n Skipping for BDF - 0x%x ", bdf); + val_print(DEBUG, " Classcode is : 0x%x ", base_cc); continue; } @@ -123,15 +123,15 @@ payload(void) /* If memory allocation fail, fail the test */ if (func_config_space == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation fail", 0); + val_print(ERROR, "\n Memory allocation fail"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); return; } /* Get function configuration space address */ config_space_addr = val_pcie_get_bdf_config_addr(bdf); - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x ", bdf); - val_print(ACS_PRINT_INFO, "config space addr 0x%x", config_space_addr); + val_print(DEBUG, "\n BDF - 0x%x ", bdf); + val_print(TRACE, "config space addr 0x%x", config_space_addr); /* Save the function config space to restore after FLR */ for (idx = 0; idx < PCIE_CFG_SIZE / 4; idx ++) { @@ -147,7 +147,7 @@ payload(void) status = val_time_delay_ms(100 * ONE_MILLISECOND); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to time delay for BDF 0x%x ", bdf); + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(func_config_space); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; @@ -185,7 +185,7 @@ payload(void) if ((device_id == DIDR_RRS_MASK) && ((vendor_id == TYPE01_VIDR_MASK) || (vendor_id == VIDR_RRS_MASK))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x not present", bdf); + val_print(ERROR, "\n BDF 0x%x not present", bdf); test_fails++; val_memory_free_aligned(func_config_space); continue; @@ -204,8 +204,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No target device type with FLR Cap found. Skipping test", 0); + val_print(DEBUG, + "\n No target device type with FLR Cap found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p064.c b/test_pool/pcie/p064.c index 88e8244b..a9a7ebf8 100644 --- a/test_pool/pcie/p064.c +++ b/test_pool/pcie/p064.c @@ -56,7 +56,7 @@ payload(void) /* Check entry is iEP */ if (dp_type == iEP_EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Check ARI capability support */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ARICS, &cap_base) == PCIE_CAP_NOT_FOUND) @@ -75,7 +75,7 @@ payload(void) /* If root port not support ARI forwarding, fail the test */ if (!ari_frwd_support) { - val_print(ACS_PRINT_ERR, "\n BDF - 0x%x does not support ARI Forwarding. ", bdf); + val_print(ERROR, "\n BDF - 0x%x does not support ARI Forwarding. ", bdf); test_fails++; } @@ -83,8 +83,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No iEP_EP found with ARI Capability Support. Skipping test", 0); + val_print(DEBUG, + "\n No iEP_EP found with ARI Capability Support. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p065.c b/test_pool/pcie/p065.c index 132f5129..75cb6f70 100644 --- a/test_pool/pcie/p065.c +++ b/test_pool/pcie/p065.c @@ -57,7 +57,7 @@ payload(void) /* Check entry is iEP endpoint */ if (dp_type == iEP_EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read endpoint OBFF supported bit value */ val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); @@ -78,18 +78,18 @@ payload(void) /* As per SBSA spec iRP must have same value as of iEP */ if (ep_obff_support != rp_obff_support) { - val_print(ACS_PRINT_ERR, "\n OBFF Support level of iEP and it's iRP is not same", 0); - val_print(ACS_PRINT_DEBUG, "\n iEP 0x%x", bdf); - val_print(ACS_PRINT_DEBUG, " OBFF support %d", ep_obff_support); - val_print(ACS_PRINT_DEBUG, "\n iRP 0x%x", rp_bdf); - val_print(ACS_PRINT_DEBUG, " OBFF support %d", rp_obff_support); + val_print(ERROR, "\n OBFF Support level of iEP and it's iRP is not same"); + val_print(DEBUG, "\n iEP 0x%x", bdf); + val_print(DEBUG, " OBFF support %d", ep_obff_support); + val_print(DEBUG, "\n iRP 0x%x", rp_bdf); + val_print(DEBUG, " OBFF support %d", rp_obff_support); test_fails++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No iEP_EP type device found. Skipping test", 0); + val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p066.c b/test_pool/pcie/p066.c index 1d711e7c..a32de49f 100644 --- a/test_pool/pcie/p066.c +++ b/test_pool/pcie/p066.c @@ -59,7 +59,7 @@ payload(void) /* Check entry is iRP endpoint */ if (dp_type == iEP_RP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); iep_rp_found = 1; /* If rootport invovled in transaction forwarding, move to next */ @@ -80,9 +80,9 @@ payload(void) /* CTRS and CTDS bit is handwired to 0, if transaction forwarding not support */ if ((ctrs_value != 0) || (ctds_value !=0)) { - val_print(ACS_PRINT_ERR, "\n CTRS and/or CTDS bits not hardwired to 0", 0); - val_print(ACS_PRINT_DEBUG, " ctrs %d", ctrs_value); - val_print(ACS_PRINT_DEBUG, " ctds %d", ctds_value); + val_print(ERROR, "\n CTRS and/or CTDS bits not hardwired to 0"); + val_print(DEBUG, " ctrs %d", ctrs_value); + val_print(DEBUG, " ctds %d", ctds_value); test_fails++; } } @@ -90,7 +90,7 @@ payload(void) /* Skip the test if no iEP_RP found */ if (iep_rp_found == 0) { - val_print(ACS_PRINT_DEBUG, "\n No iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } diff --git a/test_pool/pcie/p067.c b/test_pool/pcie/p067.c index fb1753c5..3e65b858 100644 --- a/test_pool/pcie/p067.c +++ b/test_pool/pcie/p067.c @@ -62,7 +62,7 @@ payload(void) /* Check entry is i-EP */ if (dp_type == iEP_EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read iEP atomicop completer bits */ val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); @@ -86,7 +86,7 @@ payload(void) if ((atomicop_32_cap || atomicop_64_cap || atomicop_128_cap) && ((rp_routing_cap == 0) && (rp_requester_cap == 0))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x atomicop completer fail", bdf); + val_print(ERROR, "\n BDF 0x%x atomicop completer fail", bdf); test_fails++; } @@ -96,14 +96,14 @@ payload(void) if ((ep_requester_cap) && ((rp_routing_cap == 0) && (rp_requester_cap == 0))) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x atomicop requester fail", bdf); + val_print(ERROR, "\n BDF 0x%x atomicop requester fail", bdf); test_fails++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No iEP_EP type device found. Skipping test", 0); + val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p068.c b/test_pool/pcie/p068.c index 4f52727c..ddeeaa39 100644 --- a/test_pool/pcie/p068.c +++ b/test_pool/pcie/p068.c @@ -34,7 +34,7 @@ payload(void) num_pcie_rc = val_iovirt_get_pcie_rc_info(NUM_PCIE_RC, 0); if (!num_pcie_rc) { - val_print(ACS_PRINT_DEBUG, "\n Skip because no PCIe RC detected ", 0); + val_print(DEBUG, "\n Skip because no PCIe RC detected "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -46,7 +46,7 @@ payload(void) if (mem_attr == INNER_SHAREABLE) val_set_status(index, RESULT_PASS(TEST_NUM, 1)); else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed mem attribute check for PCIe RC %d", num_pcie_rc); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/pcie/p069.c b/test_pool/pcie/p069.c index d4597486..685fa6d9 100644 --- a/test_pool/pcie/p069.c +++ b/test_pool/pcie/p069.c @@ -59,15 +59,15 @@ payload(void) /* Check entry is iEP pair or RCiEP based on the rule the test covers */ if ((dp_type == RCiEP) || (dp_type == iEP_EP) || (dp_type == iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); int_pin = VAL_EXTRACT_BITS(reg_value, TYPE01_IPR_SHIFT, TYPE01_IPR_SHIFT + 7); - val_print(ACS_PRINT_DEBUG, " int pin value %d", int_pin); + val_print(DEBUG, " int pin value %d", int_pin); - val_print(ACS_PRINT_DEBUG, " MSI cap %d", + val_print(DEBUG, " MSI cap %d", val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base)); - val_print(ACS_PRINT_DEBUG, " MSIX cap %d", + val_print(DEBUG, " MSIX cap %d", val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base)); /* If test runs for atleast an endpoint */ @@ -77,7 +77,7 @@ payload(void) if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) && (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND) && ((int_pin >= 1) && (int_pin <= 4))) { - val_print(ACS_PRINT_ERR, "\n BDF - 0x%x supports INTx but not MSI/MSI-X", bdf); + val_print(ERROR, "\n BDF - 0x%x supports INTx but not MSI/MSI-X", bdf); test_fails++; } @@ -85,7 +85,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No target device type found. Skipping test", 0); + val_print(DEBUG, "\n No target device type found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p070.c b/test_pool/pcie/p070.c index de093f7b..c79b5397 100644 --- a/test_pool/pcie/p070.c +++ b/test_pool/pcie/p070.c @@ -53,14 +53,14 @@ payload(void) /* Check entry is onchip peripherals */ if (dp_type == RCiEP || dp_type == iEP_EP || dp_type == iEP_RP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; /* If Power Management capability not supported, test fails */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PMC, &cap_base) == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n BDF - %x does not support Power Management Capability", bdf); test_fails++; } @@ -68,7 +68,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n No target device type found. Skipping test", bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } diff --git a/test_pool/pcie/p071.c b/test_pool/pcie/p071.c index 02fefd83..2e3f729d 100644 --- a/test_pool/pcie/p071.c +++ b/test_pool/pcie/p071.c @@ -61,7 +61,7 @@ payload(void) if ((dp_type == DP) || (dp_type == iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read the secondary and subordinate bus number */ val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); @@ -91,7 +91,7 @@ payload(void) /* If the iEP_RP/ DP does not support ARI forwarding, print a warning. Continue the test since this validates the disabled ARI forwarding case. */ if (status == 0) - val_print(ACS_PRINT_WARN, "\n ARI Forwarding not supported for bdf 0x%x", bdf); + val_print(WARN, "\n ARI Forwarding not supported for bdf 0x%x", bdf); /* If test runs on atleast one device */ test_skip = 0; @@ -108,8 +108,8 @@ payload(void) /* Fail the test if the bitfied does not respond to the write */ if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n ARI Forwarding Enable bit not cleared for", 0); - val_print(ACS_PRINT_ERR, " bdf 0x%x", bdf); + val_print(ERROR, "\n ARI Forwarding Enable bit not cleared for"); + val_print(ERROR, " bdf 0x%x", bdf); test_fails++; continue; } @@ -120,8 +120,8 @@ payload(void) if (status || (reg_value == PCIE_UNKNOWN_RESPONSE)) { test_fails++; - val_print(ACS_PRINT_ERR, "\n Dev 0x%x found under", dev_bdf); - val_print(ACS_PRINT_ERR, " RP bdf 0x%x", bdf); + val_print(ERROR, "\n Dev 0x%x found under", dev_bdf); + val_print(ERROR, " RP bdf 0x%x", bdf); } /* Configuration Requests specifying Device Numbers (1-31) must be terminated by the @@ -135,15 +135,15 @@ payload(void) if (reg_value != PCIE_UNKNOWN_RESPONSE) { test_fails++; - val_print(ACS_PRINT_ERR, "\n Dev 0x%x found under", dev_bdf); - val_print(ACS_PRINT_ERR, " RP bdf 0x%x", bdf); + val_print(ERROR, "\n Dev 0x%x found under", dev_bdf); + val_print(ERROR, " RP bdf 0x%x", bdf); } } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No DP/ iEP_RP type device found.Skipping test", bdf); + val_print(DEBUG, "\n No DP/ iEP_RP type device found.Skipping test", bdf); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } diff --git a/test_pool/pcie/p072.c b/test_pool/pcie/p072.c index 09bf7d59..25b1c602 100644 --- a/test_pool/pcie/p072.c +++ b/test_pool/pcie/p072.c @@ -110,20 +110,20 @@ payload(void) bdf = bdf_tbl_ptr->device[tbl_index++].bdf; dp_type = val_pcie_device_port_type(bdf); if (dp_type == iEP_EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x ", bdf); + val_print(DEBUG, "\n BDF - 0x%x ", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; if (func_ecam_is_rp_ecam(bdf)) { - val_print(ACS_PRINT_ERR, "dp_type: 0x%x ", dp_type); + val_print(ERROR, "dp_type: 0x%x ", dp_type); fail_cnt++; } } } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No iEP_EP type device found. Skipping test", 0); + val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (fail_cnt) diff --git a/test_pool/pcie/p078.c b/test_pool/pcie/p078.c index b72330de..f8dfe0d0 100644 --- a/test_pool/pcie/p078.c +++ b/test_pool/pcie/p078.c @@ -54,7 +54,7 @@ payload_primary(void) /* Allocate memory for interrupt mappings */ intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { - val_print (ACS_PRINT_ERR, "\n Memory allocation error", 0); + val_print (ERROR, "\n Memory allocation error"); val_set_status(pe_index, RESULT_FAIL (test_num, 01)); return; } @@ -71,7 +71,7 @@ payload_primary(void) if ((dp_type != RCEC) && (dp_type != RCiEP)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read Interrupt Line Register */ val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); @@ -89,7 +89,7 @@ payload_primary(void) return; } else { - val_print (ACS_PRINT_DEBUG, + val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); val_set_status(pe_index, RESULT_SKIP(test_num, 2)); continue; @@ -104,10 +104,10 @@ payload_primary(void) if ((intr_line >= 32 && intr_line <= 1019) || (val_gic_espi_supported() && (intr_line >= 4096 && intr_line <= val_gic_max_espi_val()))) { - val_print(ACS_PRINT_INFO, "\n Int is SPI", 0); + val_print(TRACE, "\n Int is SPI"); } else { - val_print(ACS_PRINT_ERR, "\n Int id %d is not SPI", intr_line); + val_print(ERROR, "\n Int id %d is not SPI", intr_line); val_memory_free_aligned(intr_map); val_set_status(pe_index, RESULT_FAIL(test_num, 02)); return; @@ -149,7 +149,7 @@ payload_secondary(void) if ((dp_type != RCEC) && (dp_type != RCiEP)) continue; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -166,8 +166,8 @@ payload_secondary(void) } if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) { - val_print(ACS_PRINT_ERR, - "\n Legacy interrupt programmed with incorrect trigger type", 0); + val_print(ERROR, + "\n Legacy interrupt programmed with incorrect trigger type"); val_set_status(pe_index, RESULT_FAIL(test_num, 02)); return; } @@ -220,4 +220,4 @@ p078_entry(uint32_t num_pe) val_report_status(0, ACS_END(test_num), test_entries[1].rule); return status; -} \ No newline at end of file +} diff --git a/test_pool/pcie/p079.c b/test_pool/pcie/p079.c index 58020c01..60625633 100644 --- a/test_pool/pcie/p079.c +++ b/test_pool/pcie/p079.c @@ -74,7 +74,7 @@ is_sbr_failed (uint32_t bdf) val_pcie_read_cfg(bdf, TYPE01_BAR + (index * BAR_BASE_SHIFT), ®_value); if ((reg_value >> BAR_BASE_SHIFT) != 0) { - val_print(ACS_PRINT_ERR, "\n BAR%d base addr not cleared", index); + val_print(ERROR, "\n BAR%d base addr not cleared", index); check_failed++; } } @@ -86,7 +86,7 @@ is_sbr_failed (uint32_t bdf) if ((((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) || (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0)) { - val_print(ACS_PRINT_ERR, "\n BME/MSE not cleared", 0); + val_print(ERROR, "\n BME/MSE not cleared"); check_failed++; } @@ -135,7 +135,7 @@ payload(void) /* Get BDF for iEP_EP under iEP_RP */ iep_bdf = get_iep_bdf_under_rp(bdf); if (iep_bdf == 0x0) { - val_print(ACS_PRINT_ERR, "\n Could Not Find iEP_EP under iEP_RP.", 0); + val_print(ERROR, "\n Could Not Find iEP_EP under iEP_RP."); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -145,15 +145,15 @@ payload(void) cfg_space_buf = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE); if (cfg_space_buf == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed.", 0); + val_print(ERROR, "\n Memory allocation failed."); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } /* Get configuration space address for iEP_EP */ cfg_space_addr = val_pcie_get_bdf_config_addr(iep_bdf); - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x : ", iep_bdf); - val_print(ACS_PRINT_INFO, "Config space addr 0x%x", cfg_space_addr); + val_print(DEBUG, "\n BDF - 0x%x : ", iep_bdf); + val_print(TRACE, "Config space addr 0x%x", cfg_space_addr); /* Save the iEP_EP config space to restore after Secondary Bus Reset */ for (idx = 0; idx < PCIE_CFG_SIZE / 4; idx ++) { @@ -171,7 +171,7 @@ payload(void) delay_status = val_time_delay_ms(100 * ONE_MILLISECOND); if (delay_status) { - val_print(ACS_PRINT_ERR, "\n Failed to time delay for BDF 0x%x ", bdf); + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(cfg_space_buf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; @@ -186,7 +186,7 @@ payload(void) delay_status = val_time_delay_ms(100 * ONE_MILLISECOND); if (delay_status) { - val_print(ACS_PRINT_ERR, "\n Failed to time delay for BDF 0x%x ", bdf); + val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(cfg_space_buf); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; @@ -198,7 +198,7 @@ payload(void) if (status == PCIE_DLL_LINK_STATUS_NOT_ACTIVE) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n The link is not active after reset for BDF 0x%x : ", bdf); test_fails++; goto free_cfg; @@ -221,7 +221,7 @@ payload(void) /* Skip the test if no iEP_RP found */ if (iep_rp_found == 0) { - val_print(ACS_PRINT_DEBUG, "\n No iEP_RP type device found. Skipping test", 0); + val_print(DEBUG, "\n No iEP_RP type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); } else if (test_fails) diff --git a/test_pool/pcie/p080.c b/test_pool/pcie/p080.c index ff90e181..66ed7d45 100644 --- a/test_pool/pcie/p080.c +++ b/test_pool/pcie/p080.c @@ -61,7 +61,7 @@ payload(void) /* Check entry is integrated endpoint or rciep */ if ((dp_type == RCiEP) || (dp_type == iEP_EP) || (dp_type == iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Check if Address Translation Cache is Present in this device. */ /* If ATC Not present or capabilty not filled, skip the test.*/ status = val_pcie_is_cache_present(bdf); @@ -79,7 +79,7 @@ payload(void) /* If ATC Present, ATS Capability must be present. */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ATS Capability Not Present, Bdf : 0x%x", bdf); + val_print(ERROR, "\n ATS Capability Not Present, Bdf : 0x%x", bdf); test_fails++; } } @@ -88,8 +88,8 @@ payload(void) if (warn_cnt) val_set_status(pe_index, RESULT_WARN(TEST_NUM, warn_cnt)); else if (test_skip) { - val_print(ACS_PRINT_DEBUG, - "\n No target device type found with ATC available. Skipping test", 0); + val_print(DEBUG, + "\n No target device type found with ATC available. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p081.c b/test_pool/pcie/p081.c index 33b2ae26..2b5e6c54 100644 --- a/test_pool/pcie/p081.c +++ b/test_pool/pcie/p081.c @@ -64,7 +64,7 @@ payload(void) /* Check entry is iEP_EP */ if (dp_type == iEP_EP) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Check If iEP_EP supports P2P with others. */ status = val_pcie_dev_p2p_support(bdf); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { @@ -80,7 +80,7 @@ payload(void) /* Find iEP_RP for this iEP_EP */ if (val_pcie_get_rootport(bdf, &iep_rp_bdf)) { - val_print(ACS_PRINT_ERR, "\n Root Port Not found for iEP_EP 0x%x", bdf); + val_print(ERROR, "\n Root Port Not found for iEP_EP 0x%x", bdf); test_fails++; continue; } @@ -88,7 +88,7 @@ payload(void) /* Read the ACS Capability */ if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x" + val_print(ERROR, "\n ACS Capability not supported, Bdf : 0x%x" , iep_rp_bdf); test_fails++; continue; @@ -99,7 +99,7 @@ payload(void) /* Extract ACS source validation bit */ data = VAL_EXTRACT_BITS(acs_data, 0, 0); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Source validation not supported, Bdf : 0x%x" + val_print(DEBUG, "\n Source validation not supported, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed++; } @@ -107,7 +107,7 @@ payload(void) /* Extract ACS translation blocking bit */ data = VAL_EXTRACT_BITS(acs_data, 1, 1); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Translation blocking not supported, Bdf : 0x%x" + val_print(DEBUG, "\n Translation blocking not supported, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed++; } @@ -115,7 +115,7 @@ payload(void) /* Extract ACS P2P request redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 2, 2); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x" + val_print(DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed++; } @@ -123,7 +123,7 @@ payload(void) /* Extract ACS P2P completion redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 3, 3); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n P2P completion redirect not supported, " + val_print(DEBUG, "\n P2P completion redirect not supported, " "Bdf : 0x%x", iep_rp_bdf); curr_bdf_failed++; } @@ -131,7 +131,7 @@ payload(void) /* Extract ACS upstream forwarding bit */ data = VAL_EXTRACT_BITS(acs_data, 4, 4); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x" + val_print(DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed++; } @@ -139,13 +139,13 @@ payload(void) /* If iEP_RP supports ACS then it must have AER Capability */ if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, "\n AER Capability not supported, Bdf : 0x%x" + val_print(DEBUG, "\n AER Capability not supported, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed++; } if(curr_bdf_failed > 0) { - val_print(ACS_PRINT_ERR, "\n ACS Capability Check Failed, Bdf : 0x%x" + val_print(ERROR, "\n ACS Capability Check Failed, Bdf : 0x%x" , iep_rp_bdf); curr_bdf_failed = 0; test_fails++; @@ -154,8 +154,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No iEP_EP type device found with P2P support. Skipping test", 0); + val_print(DEBUG, + "\n No iEP_EP type device found with P2P support. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p082.c b/test_pool/pcie/p082.c index 7f13b543..a252c2d3 100644 --- a/test_pool/pcie/p082.c +++ b/test_pool/pcie/p082.c @@ -97,7 +97,7 @@ payload(void *arg) /* Check entry is RCiEP or iEP end point */ if ((dp_type == RCiEP) || (dp_type == iEP_EP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Check if the EP Supports Multifunction */ if (val_pcie_multifunction_support(bdf)) @@ -118,7 +118,7 @@ payload(void *arg) /* Read the ACS Capability */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); + val_print(ERROR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); test_fails++; continue; } @@ -128,33 +128,33 @@ payload(void *arg) /* Extract ACS p2p Request Redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 2, 2); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Request Redirect P2P not supported", 0); + val_print(DEBUG, "\n Request Redirect P2P not supported"); p2p_support_flag++; } /* Extract ACS p2p Completion Redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 3, 3); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Completion Redirect P2P not supported", 0); + val_print(DEBUG, "\n Completion Redirect P2P not supported"); p2p_support_flag++; } /* Extract ACS p2p Direct Translated bit */ data = VAL_EXTRACT_BITS(acs_data, 6, 6); if (data == 0) { - val_print(ACS_PRINT_DEBUG, "\n Direct Translated P2P not supported", 0); + val_print(DEBUG, "\n Direct Translated P2P not supported"); p2p_support_flag++; } if (p2p_support_flag > 0) { - val_print(ACS_PRINT_ERR, "\n P2P not supported for bdf: %d", bdf); + val_print(ERROR, "\n P2P not supported for bdf: %d", bdf); p2p_support_flag = 0; test_fails++; } /* If device supports ACS then it must have AER Capability */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n AER Capability not supported, Bdf : 0x%x", bdf); + val_print(ERROR, "\n AER Capability not supported, Bdf : 0x%x", bdf); aer_cap_fail++; } } @@ -168,8 +168,8 @@ payload(void *arg) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No target device type with Multifunction and P2P support.Skipping test", 0); + val_print(DEBUG, + "\n No target device type with Multifunction and P2P support.Skipping test"); val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); } else if (test_fails + aer_cap_fail) diff --git a/test_pool/pcie/p083.c b/test_pool/pcie/p083.c index ff4a4745..1fb187d4 100644 --- a/test_pool/pcie/p083.c +++ b/test_pool/pcie/p083.c @@ -64,9 +64,9 @@ payload(void) while (offset <= BAR_TYPE_1_MAX_OFFSET) { val_pcie_read_cfg(bdf, offset, &bar_value); - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x ", bdf); - val_print(ACS_PRINT_DEBUG, "BAR offset0x%x value", offset); - val_print(ACS_PRINT_DEBUG, " is 0x%x ", bar_value); + val_print(DEBUG, "\n BDF - 0x%x ", bdf); + val_print(DEBUG, "BAR offset0x%x value", offset); + val_print(DEBUG, " is 0x%x ", bar_value); bar_orig = 0; bar_new = 0; @@ -79,8 +79,8 @@ payload(void) if (BAR_REG(bar_value) == BAR_64_BIT) { - val_print(ACS_PRINT_INFO, - "\n The BAR supports 64-bit address capability", 0); + val_print(TRACE, + "\n The BAR supports 64-bit address capability"); val_pcie_read_cfg(bdf, offset+4, &bar_value_1); base_upper = bar_value_1; @@ -102,8 +102,8 @@ payload(void) bar_upper_bits = bar_reg_value; bar_new = (bar_upper_bits << 32) | bar_value; if (bar_orig == bar_new) { - val_print(ACS_PRINT_DEBUG, "\n Value read from BAR 0x%llx", bar_new); - val_print(ACS_PRINT_ERR, + val_print(DEBUG, "\n Value read from BAR 0x%llx", bar_new); + val_print(ERROR, "\n Read write to BAR reg not supported bdf %x", bdf); fail_cnt++; } @@ -115,8 +115,8 @@ payload(void) } else { - val_print(ACS_PRINT_INFO, - "\n The BAR supports 32-bit address capability", 0); + val_print(TRACE, + "\n The BAR supports 32-bit address capability"); /* BAR supports 32-bit address. Write all 1's * to BARn and identify the size requested @@ -128,10 +128,10 @@ payload(void) val_pcie_read_cfg(bdf, offset, &bar_reg_value); bar_new = bar_reg_value; if (bar_orig == bar_new) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Value written into BAR 0x%x", TEST_DATA_1); - val_print(ACS_PRINT_DEBUG, " Value read from BAR 0x%x", bar_new); - val_print(ACS_PRINT_ERR, + val_print(DEBUG, " Value read from BAR 0x%x", bar_new); + val_print(ERROR, "\n Read write to BAR reg not supported bdf %x", bdf); fail_cnt++; } @@ -145,7 +145,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No target device type found. Skipping test", 0); + val_print(DEBUG, "\n No target device type found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (fail_cnt) diff --git a/test_pool/pcie/p084.c b/test_pool/pcie/p084.c index 84c25649..00156351 100644 --- a/test_pool/pcie/p084.c +++ b/test_pool/pcie/p084.c @@ -49,7 +49,7 @@ payload(void) bdf = bdf_tbl_ptr->device[tbl_index++].bdf; dp_type = val_pcie_device_port_type(bdf); if (dp_type == RCEC) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -60,16 +60,16 @@ payload(void) (RCEC_SUB_CLASS != ((reg_value >> CC_SUB_SHIFT) & CC_SUB_MASK)) || (RCEC_PGMING_IF != ((reg_value >> CC_PGM_IF_SHIFT) & CC_PGM_IF_MASK))) { - val_print(ACS_PRINT_ERR, " Class code mismatch for bdf: 0x%x\n", bdf); - val_print(ACS_PRINT_ERR, " dp_type: 0x%x\n", dp_type); - val_print(ACS_PRINT_ERR, " CCR: 0x%x\n", reg_value); + val_print(ERROR, " Class code mismatch for bdf: 0x%x\n", bdf); + val_print(ERROR, " dp_type: 0x%x\n", dp_type); + val_print(ERROR, " CCR: 0x%x\n", reg_value); fail_cnt++; } /* If Root Complex Event Collector Endpoint Association Extended Capability not supported for RCEC, test fails*/ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_RCECEA, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n BDF - 0x%x does not support RCEC Endpoint Association Capability", bdf); fail_cnt++; continue; @@ -79,7 +79,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RCEC type device found. Skipping test", 0); + val_print(DEBUG, "\n No RCEC type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (fail_cnt) diff --git a/test_pool/pcie/p085.c b/test_pool/pcie/p085.c index 08af9529..dc8df26e 100644 --- a/test_pool/pcie/p085.c +++ b/test_pool/pcie/p085.c @@ -50,7 +50,7 @@ payload(void) dp_type = val_pcie_device_port_type(bdf); if ((dp_type == RCiEP) || (dp_type == RCEC)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -58,14 +58,14 @@ payload(void) hdr_type = val_pcie_function_header_type(bdf); /* Type must be 0 for RCiEP*/ if (hdr_type != TYPE0_HEADER) { - val_print(ACS_PRINT_ERR, "\n Invalid HDR TYPE 0x%x", hdr_type); + val_print(ERROR, "\n Invalid HDR TYPE 0x%x", hdr_type); fail_cnt++; continue; } link_cap_sup = val_pcie_link_cap_support(bdf); if (link_cap_sup != 0) { - val_print(ACS_PRINT_ERR, "\n Invalid Link Capabilities 0x%x", link_cap_sup); + val_print(ERROR, "\n Invalid Link Capabilities 0x%x", link_cap_sup); fail_cnt++; } @@ -73,7 +73,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No RCiEP/ RCEC type device found. Skipping test", 0); + val_print(DEBUG, "\n No RCiEP/ RCEC type device found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (fail_cnt) diff --git a/test_pool/pcie/p086.c b/test_pool/pcie/p086.c index 2a540ada..2b9a240a 100644 --- a/test_pool/pcie/p086.c +++ b/test_pool/pcie/p086.c @@ -41,7 +41,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_INFO, "\n Received exception of type in test 861: %d", interrupt_type); + val_print(TRACE, "\n Received exception of type in test 861: %d", interrupt_type); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); } @@ -51,14 +51,14 @@ static uint32_t test_sequence_1B(uint8_t *addr) uint32_t read_value, old_value; uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_INFO, "\n testing 1B test sequence", 0); + val_print(TRACE, "\n testing 1B test sequence"); for (int idx = 0; idx < 8; idx++) { old_value = val_mmio_read8((addr_t)addr); val_mmio_write8((addr_t)addr, write_val); read_value = val_mmio_read8((addr_t)addr); if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { - val_print(ACS_PRINT_ERR, "\n Error in read and write 1B", 0); + val_print(ERROR, "\n Error in read and write 1B"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return 1; } @@ -76,14 +76,14 @@ uint32_t test_sequence_2B(uint16_t *addr) uint32_t read_value, old_value; uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_INFO, "\n testing 2B test sequence", 0); + val_print(TRACE, "\n testing 2B test sequence"); for (int idx = 0; idx < 4; idx++) { old_value = val_mmio_read16((addr_t)addr); val_mmio_write16((addr_t)addr, write_val); read_value = val_mmio_read16((addr_t)addr); if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { - val_print(ACS_PRINT_ERR, "\n Error in read and write 2B", 0); + val_print(ERROR, "\n Error in read and write 2B"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return 1; } @@ -114,7 +114,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -127,23 +127,23 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { - val_print(ACS_PRINT_DEBUG, "\n tbl_index - 0x%x", tbl_index); + val_print(DEBUG, "\n tbl_index - 0x%x", tbl_index); bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* * For Function with Type 1 config space header, obtain * base address of the its own BAR address. */ if (val_pcie_function_header_type(bdf) == TYPE0_HEADER) { - val_print(ACS_PRINT_DEBUG, "\n Skipping not a RP, BDF - 0x%x", bdf); + val_print(DEBUG, "\n Skipping not a RP, BDF - 0x%x", bdf); continue; } val_pcie_get_mmio_bar(bdf, &bar_base); /* Skip this function if it doesn't have mmio BAR */ if (!bar_base) { - val_print(ACS_PRINT_DEBUG, "\n Skipping as no MMIO BAR, RP BDF - 0x%x", bdf); + val_print(DEBUG, "\n Skipping as no MMIO BAR, RP BDF - 0x%x", bdf); continue; } @@ -153,20 +153,20 @@ payload(void) bar_data = val_mmio_read(bar_base); if (test_sequence_1B((uint8_t *)bar_base)) { - val_print(ACS_PRINT_ERR, "\n Failed check for Bdf 0x%x", bdf); + val_print(ERROR, "\n Failed check for Bdf 0x%x", bdf); test_fails++; } if (test_sequence_2B((uint16_t *)bar_base)) { - val_print(ACS_PRINT_ERR, "\n Failed check for Bdf 0x%x", bdf); + val_print(ERROR, "\n Failed check for Bdf 0x%x", bdf); test_fails++; } - val_print(ACS_PRINT_DEBUG, "\n Doing write of bar base Bdf 0x%x", bdf); + val_print(DEBUG, "\n Doing write of bar base Bdf 0x%x", bdf); val_mmio_write(bar_base, bar_data); exception_return861: if (IS_TEST_FAIL(val_get_status(pe_index))) { - val_print(ACS_PRINT_ERR, "\n Failed. Exception on Memory Access For Bdf 0x%x", bdf); + val_print(ERROR, "\n Failed. Exception on Memory Access For Bdf 0x%x", bdf); val_pcie_clear_urd(bdf); test_fails++; } @@ -176,7 +176,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No MMIO BARs detected. Skipping test", 0); + val_print(DEBUG, "\n No MMIO BARs detected. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p087.c b/test_pool/pcie/p087.c index 672ca483..d2dd6883 100644 --- a/test_pool/pcie/p087.c +++ b/test_pool/pcie/p087.c @@ -58,7 +58,7 @@ payload(void) num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_ERR, "\n No ECAMs discovered ", 0); + val_print(ERROR, "\n No ECAMs discovered "); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -66,7 +66,7 @@ payload(void) while (tbl_index < bdf_tbl_ptr->num_entries) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -93,7 +93,7 @@ payload(void) entry_type_offset += PCIE_DWORD_SIZE; for (entry = 0; entry < num_entries; entry++) { - val_print(ACS_PRINT_DEBUG, "\n Reading entry at offset %llx", entry_type_offset); + val_print(DEBUG, "\n Reading entry at offset %llx", entry_type_offset); /* Read Entry type register present in Enhanced Allocation capability struct(14h) */ val_pcie_read_cfg(bdf, cap_base + entry_type_offset, ®_value); @@ -102,7 +102,7 @@ payload(void) enable_value = (reg_value >> EA_ENTRY_TYPE_ENABLE_SHIFT) & EA_ENTRY_TYPE_ENABLE_MASK; if (enable_value) { - val_print(ACS_PRINT_ERR, "\n Enhanced Allocation enabled for BDF 0x%x", bdf); + val_print(ERROR, "\n Enhanced Allocation enabled for BDF 0x%x", bdf); test_fails++; } @@ -114,8 +114,8 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n Found no Endpoint with PCIe Capability. Skipping test", 0); + val_print(DEBUG, + "\n Found no Endpoint with PCIe Capability. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p089.c b/test_pool/pcie/p089.c index 556563c5..d729cad7 100644 --- a/test_pool/pcie/p089.c +++ b/test_pool/pcie/p089.c @@ -41,7 +41,7 @@ static void payload(void) /* Get the number of Root Complex in the system */ if (!num_pcie_rc) { - val_print(ACS_PRINT_DEBUG, "\n Skip because no PCIe RC detected ", 0); + val_print(DEBUG, "\n Skip because no PCIe RC detected "); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -57,7 +57,7 @@ static void payload(void) if (!rc_ats_supp) { - val_print(ACS_PRINT_ERR, "\n ATS Capability Not Present for RC: %x", num_pcie_rc); + val_print(ERROR, "\n ATS Capability Not Present for RC: %x", num_pcie_rc); test_fails++; } } diff --git a/test_pool/pcie/p090.c b/test_pool/pcie/p090.c index 8be4f3bd..8c80d227 100644 --- a/test_pool/pcie/p090.c +++ b/test_pool/pcie/p090.c @@ -55,7 +55,7 @@ payload(void) if ((dp_type == RP) || (dp_type == iEP_RP)) { - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Retrieve the addr of Downstream Port Containment (1Dh) and check if the * capability structure is supported. @@ -80,8 +80,8 @@ payload(void) val_pcie_read_cfg(bdf, cap_base + DPC_CTRL_OFFSET, &new_reg_value); if (new_reg_value != reg_value) { - val_print(ACS_PRINT_ERR, "\n Failed. BDF - 0x%x ", bdf); - val_print(ACS_PRINT_ERR, "RP Extension for DPC has incorrect access permission", 0); + val_print(ERROR, "\n Failed. BDF - 0x%x ", bdf); + val_print(ERROR, "RP Extension for DPC has incorrect access permission"); test_fails++; } } @@ -89,8 +89,8 @@ payload(void) if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n Found no RP with DPC Capability. Skipping test", 0); + val_print(DEBUG, + "\n Found no RP with DPC Capability. Skipping test"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); } else if (test_fails) diff --git a/test_pool/pcie/p091.c b/test_pool/pcie/p091.c index 38d08e3b..72661041 100644 --- a/test_pool/pcie/p091.c +++ b/test_pool/pcie/p091.c @@ -33,14 +33,14 @@ payload(void) /* Obtain the STE values from PAL using _DSM Method */ status = val_pcie_dsm_ste_tags(); - val_print(ACS_PRINT_DEBUG, "\n STE tag value is %x", status); + val_print(DEBUG, "\n STE tag value is %x", status); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { val_set_status(index, RESULT_WARN(TEST_NUM, 0)); } else if (status == 0) { - val_print(ACS_PRINT_ERR, "\n STE tag value should not be 0\n", 0); + val_print(ERROR, "\n STE tag value should not be 0\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); } else diff --git a/test_pool/pcie/p092.c b/test_pool/pcie/p092.c index 6ef6810a..4db12a32 100644 --- a/test_pool/pcie/p092.c +++ b/test_pool/pcie/p092.c @@ -63,7 +63,7 @@ payload(void *arg) { bdf = bdf_tbl_ptr->device[tbl_index++].bdf; dp_type = val_pcie_device_port_type(bdf); - val_print(ACS_PRINT_INFO, "\n BDF - 0x%x", bdf); + val_print(TRACE, "\n BDF - 0x%x", bdf); if ((dp_type == iEP_EP) || (dp_type == iEP_RP)) { @@ -85,7 +85,7 @@ payload(void *arg) if (status == PCIE_CAP_NOT_FOUND) { test_fails++; - val_print(ACS_PRINT_ERR, "\n No Sec PCI ECS found for BDF: 0x%x", bdf); + val_print(ERROR, "\n No Sec PCI ECS found for BDF: 0x%x", bdf); } } continue; @@ -99,7 +99,7 @@ payload(void *arg) if (status == PCIE_CAP_NOT_FOUND) { test_fails++; - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n No DL feature ECS found for BDF: 0x%x", bdf); } continue; @@ -111,7 +111,7 @@ payload(void *arg) if (status == PCIE_CAP_NOT_FOUND) { test_fails++; - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n No PL 16GT/s ECS found for BDF: 0x%x", bdf); } else if (status == PCIE_SUCCESS) @@ -120,21 +120,21 @@ payload(void *arg) if (reg_value != 0) { test_fails++; - val_print(ACS_PRINT_ERR, "\n 16GT/s LDP not 0 for BDF: 0x%x", bdf); + val_print(ERROR, "\n 16GT/s LDP not 0 for BDF: 0x%x", bdf); } val_pcie_read_cfg(bdf, cap_base + 0x14, ®_value); if (reg_value != 0) { test_fails++; - val_print(ACS_PRINT_ERR, "\n 16GT/s FRDP not 0 for BDF: 0x%x", bdf); + val_print(ERROR, "\n 16GT/s FRDP not 0 for BDF: 0x%x", bdf); } val_pcie_read_cfg(bdf, cap_base + 0x18, ®_value); if (reg_value != 0) { test_fails++; - val_print(ACS_PRINT_ERR, "\n 16GT/s SRDP not 0 for BDF: 0x%x", bdf); + val_print(ERROR, "\n 16GT/s SRDP not 0 for BDF: 0x%x", bdf); } } continue; @@ -146,7 +146,7 @@ payload(void *arg) if (status == PCIE_CAP_NOT_FOUND) { test_fails++; - val_print(ACS_PRINT_ERR, "\n No LM at Rx EC found for BDF: 0x%x", bdf); + val_print(ERROR, "\n No LM at Rx EC found for BDF: 0x%x", bdf); } else if (status == PCIE_SUCCESS) { @@ -155,7 +155,7 @@ payload(void *arg) if (driver_sw != 0) { test_fails++; - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Margining drv sw not 0 for BDF: 0x%x", bdf); } } @@ -166,8 +166,8 @@ payload(void *arg) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, - "\n No target device type with required extended cap found. Skipping test", 0); + val_print(DEBUG, + "\n No target device type with required extended cap found. Skipping test"); val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); } else if (test_fails) diff --git a/test_pool/pcie/p093.c b/test_pool/pcie/p093.c index cd21d47f..5bc12470 100644 --- a/test_pool/pcie/p093.c +++ b/test_pool/pcie/p093.c @@ -68,11 +68,11 @@ payload(void) { /* Test runs for atleast one device */ test_skip = 0; - val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf); + val_print(DEBUG, "\n BDF - 0x%x", bdf); /* Read the ACS Capability */ if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); test_fails++; continue; @@ -83,35 +83,35 @@ payload(void) /* Extract ACS source validation bit */ data = VAL_EXTRACT_BITS(acs_data, 0, 0); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Source validation not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS translation blocking bit */ data = VAL_EXTRACT_BITS(acs_data, 1, 1); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Translation blocking not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS P2P request redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 2, 2); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS P2P completion redirect bit */ data = VAL_EXTRACT_BITS(acs_data, 3, 3); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n P2P completion redirect not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } /* Extract ACS upstream forwarding bit */ data = VAL_EXTRACT_BITS(acs_data, 4, 4); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } @@ -119,13 +119,13 @@ payload(void) /* Extract ACS Direct Translated P2P bit */ data = VAL_EXTRACT_BITS(acs_data, 6, 6); if (data == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Direct Translated P2P not supported, Bdf : 0x%x", bdf); curr_bdf_failed++; } if (curr_bdf_failed > 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n ACS Capability Check Failed, Bdf : 0x%x", bdf); curr_bdf_failed = 0; test_fails++; @@ -134,7 +134,7 @@ payload(void) } if (test_skip == 1) { - val_print(ACS_PRINT_DEBUG, "\n No Downstream Port of Switch found. Skipping device", 0); + val_print(DEBUG, "\n No Downstream Port of Switch found. Skipping device"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); } else if (test_fails) diff --git a/test_pool/pcie/p094.c b/test_pool/pcie/p094.c index 5d4a674d..adf233a2 100644 --- a/test_pool/pcie/p094.c +++ b/test_pool/pcie/p094.c @@ -45,7 +45,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_FAIL(test_num, 02)); } @@ -86,7 +86,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to install exception handler", 0); + val_print(ERROR, "\n Failed to install exception handler"); val_set_status(index, RESULT_FAIL(test_num, 01)); return; } @@ -118,45 +118,45 @@ payload(void) offset = BAR0_OFFSET; - val_print(ACS_PRINT_DEBUG, "\n BDF under check %.6x", bdf); + val_print(DEBUG, "\n BDF under check %.6x", bdf); while (offset <= max_bar_offset) { val_pcie_read_cfg(bdf, offset, &bar_value); - val_print(ACS_PRINT_DEBUG, "\n The BAR value of bdf %.6x", bdf); - val_print(ACS_PRINT_DEBUG, " is %x ", bar_value); + val_print(DEBUG, "\n The BAR value of bdf %.6x", bdf); + val_print(DEBUG, " is %x ", bar_value); base = 0; if (bar_value == 0) { /** This BAR is not implemented **/ - val_print(ACS_PRINT_DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf); + val_print(DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf); tbl_index++; goto next_bdf; } /* Skip for IO address space */ if (bar_value & BAR_VALUE_IO_MASK) { - val_print(ACS_PRINT_DEBUG, "\n BAR is used for IO address space request", 0); - val_print(ACS_PRINT_DEBUG, " for BDF 0x%x", bdf); + val_print(DEBUG, "\n BAR is used for IO address space request"); + val_print(DEBUG, " for BDF 0x%x", bdf); tbl_index++; goto next_bdf; } val_pcie_read_cfg(bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", reg_value); + val_print(DEBUG, "\n Class code is 0x%x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (g_pcie_skip_dp_nic_ms && ((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) { - val_print(ACS_PRINT_DEBUG, "\n Skipping BDF as 0x%x", bdf); + val_print(DEBUG, "\n Skipping BDF as 0x%x", bdf); tbl_index++; goto next_bdf; } if (BAR_REG(bar_value) == BAR_64_BIT) { - val_print(ACS_PRINT_INFO, - "\n BAR supports 64-bit address decoding capability", 0); + val_print(TRACE, + "\n BAR supports 64-bit address decoding capability"); val_pcie_read_cfg(bdf, offset+4, &bar_value_1); base = bar_value_1; @@ -179,8 +179,8 @@ payload(void) } else { - val_print(ACS_PRINT_INFO, - "\n The BAR supports 32-bit address decoding capability", 0); + val_print(TRACE, + "\n The BAR supports 32-bit address decoding capability"); /* BAR supports 32-bit address. Write all 1's * to BARn and identify the size requested @@ -195,12 +195,12 @@ payload(void) base = bar_value; } - val_print(ACS_PRINT_DEBUG, "\n BAR size is %x", bar_size); - val_print(ACS_PRINT_DEBUG, "\n BAR base is 0x%llx", base); + val_print(DEBUG, "\n BAR size is %x", bar_size); + val_print(DEBUG, "\n BAR base is 0x%llx", base); /* Check if bar supports the remap size */ if (bar_size < 1024) { - val_print(ACS_PRINT_ERR, "\n Bar size less than remap requested size", 0); + val_print(ERROR, "\n Bar size less than remap requested size"); goto next_bar; } @@ -224,7 +224,7 @@ payload(void) else if (status) { test_fail++; - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n pal_memory_ioremap failed, status: 0x%x", status); val_set_status(index, RESULT_FAIL(test_num, test_fail)); goto next_bar; @@ -238,13 +238,13 @@ payload(void) old_data = *(uint32_t *)(baseptr); *(uint32_t *)(baseptr) = DATA; data = *(char *)(baseptr+3); - val_print(ACS_PRINT_DEBUG, "\n Value read: %llx", data); + val_print(DEBUG, "\n Value read: %llx", data); *(uint32_t *)(baseptr) = old_data; exception_return_normal: val_memory_unmap(baseptr); if (IS_TEST_FAIL(val_get_status(index))) { - val_print(ACS_PRINT_ERR, "\n Normal memory access failed for Bdf: 0x%x", bdf); + val_print(ERROR, "\n Normal memory access failed for Bdf: 0x%x", bdf); /* Setting the status to Pass to enable next check for current BDF. * Failure has been recorded with test_fail. diff --git a/test_pool/pcie/p095.c b/test_pool/pcie/p095.c index e43b5398..fcf58ed3 100644 --- a/test_pool/pcie/p095.c +++ b/test_pool/pcie/p095.c @@ -43,7 +43,7 @@ payload(void) target_dev_index = val_dma_get_info(DMA_NUM_CTRL, 0); if (!target_dev_index) { - val_print(ACS_PRINT_DEBUG, "\n No DMA controllers detected... ", 0); + val_print(DEBUG, "\n No DMA controllers detected... "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -57,7 +57,7 @@ payload(void) iommu_flag++; val_dma_device_get_dma_addr(target_dev_index, &dma_addr, &dma_len); if (dma_addr == 0 || dma_len == 0) { - val_print(ACS_PRINT_ERR, "\n No active or valid ata command or " + val_print(ERROR, "\n No active or valid ata command or " "scatterlist for device at index : %d", target_dev_index); continue; } @@ -66,8 +66,8 @@ payload(void) if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { goto test_warn_unimplemented; } - val_print(ACS_PRINT_ERR, "\n The DMA address %lx used by device ", dma_addr); - val_print(ACS_PRINT_ERR, "\n is not present in the SMMU IOVA table\n", 0); + val_print(ERROR, "\n The DMA address %lx used by device ", dma_addr); + val_print(ERROR, "\n is not present in the SMMU IOVA table\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index)); return; } diff --git a/test_pool/pcie/p096.c b/test_pool/pcie/p096.c index 5e049cc1..5085b5c8 100644 --- a/test_pool/pcie/p096.c +++ b/test_pool/pcie/p096.c @@ -58,7 +58,7 @@ payload (void) irq_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!irq_map) { - val_print(ACS_PRINT_ERR, "\n Memory allocation error", 0); + val_print(ERROR, "\n Memory allocation error"); val_set_status(index, RESULT_FAIL (TEST_NUM, 1)); return; } @@ -70,8 +70,8 @@ payload (void) dev_bdf = val_peripheral_get_info (ANY_BDF, count); if (dev_bdf == 0) { - val_print(ACS_PRINT_INFO, - "\n Skipping legacy IRQ check for peripheral without BDF", 0); + val_print(TRACE, + "\n Skipping legacy IRQ check for peripheral without BDF"); continue; } @@ -81,34 +81,34 @@ payload (void) case 0: break; case 1: - val_print(ACS_PRINT_WARN, "\n Unable to access PCI bridge device", 0); + val_print(WARN, "\n Unable to access PCI bridge device"); break; case 2: - val_print(ACS_PRINT_WARN, "\n Unable to fetch _PRT ACPI handle", 0); + val_print(WARN, "\n Unable to fetch _PRT ACPI handle"); /* Not a fatal error, just skip this device */ status = 0; continue; case 3: - val_print(ACS_PRINT_WARN, "\n Unable to access _PRT ACPI object", 0); + val_print(WARN, "\n Unable to access _PRT ACPI object"); /* Not a fatal error, just skip this device */ status = 0; continue; case 4: - val_print(ACS_PRINT_WARN, "\n Interrupt hard-wire error", 0); + val_print(WARN, "\n Interrupt hard-wire error"); /* Not a fatal error, just skip this device */ status = 0; continue; case 5: - val_print(ACS_PRINT_ERR, "\n Legacy interrupt out of range", 0); + val_print(ERROR, "\n Legacy interrupt out of range"); break; case 6: - val_print(ACS_PRINT_ERR, "\n Maximum number of interrupts has been reached", 0); + val_print(ERROR, "\n Maximum number of interrupts has been reached"); break; default: if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) warn_cnt++; else - val_print (ACS_PRINT_ERR, "\n Unknown error", 0); + val_print (ERROR, "\n Unknown error"); break; } @@ -125,14 +125,14 @@ payload (void) if (irq_map->legacy_irq_map[current_irq_pin].irq_list[ccnt] == irq_map->legacy_irq_map[next_irq_pin].irq_list[ncnt]) { status = 7; - val_print(ACS_PRINT_ERR, "\n BDF : %x", dev_bdf); - val_print(ACS_PRINT_ERR, " Legacy interrupt %c", + val_print(ERROR, "\n BDF : %x", dev_bdf); + val_print(ERROR, " Legacy interrupt %c", pin_name(current_irq_pin)); - val_print(ACS_PRINT_ERR, "(%d) routing", current_irq_pin); + val_print(ERROR, "(%d) routing", current_irq_pin); - val_print(ACS_PRINT_ERR, "\n is same as the %c", + val_print(ERROR, "\n is same as the %c", pin_name(next_irq_pin)); - val_print(ACS_PRINT_ERR, "(%d) routing", next_irq_pin); + val_print(ERROR, "(%d) routing", next_irq_pin); } } } diff --git a/test_pool/pcie/p097.c b/test_pool/pcie/p097.c index a610a482..9eb78489 100644 --- a/test_pool/pcie/p097.c +++ b/test_pool/pcie/p097.c @@ -39,7 +39,7 @@ static uint32_t check_msi_status(uint32_t bdf) if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) || (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &msi_cap_offset))) { - val_print(ACS_PRINT_DEBUG, "\n No MSI/MSI-X Capability for bdf 0x%x", bdf); + val_print(DEBUG, "\n No MSI/MSI-X Capability for bdf 0x%x", bdf); return 0; } @@ -138,8 +138,8 @@ payload (void) tbl_index_next = tbl_index + 1; val_pcie_read_cfg(bdf, TYPE01_RIDR, &class_code); - val_print(ACS_PRINT_DEBUG, "\n Primary BDF is 0x%x", bdf); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", class_code); + val_print(DEBUG, "\n Primary BDF is 0x%x", bdf); + val_print(DEBUG, "\n Class code is 0x%x", class_code); base_cc = class_code >> TYPE01_BCC_SHIFT; @@ -153,14 +153,14 @@ payload (void) || (base_cc > RES_CC)) { tbl_index++; - val_print(ACS_PRINT_DEBUG, "\n Skipping DP/NIC/MAS/RES device.", 0); + val_print(DEBUG, "\n Skipping DP/NIC/MAS/RES device."); continue; } dp_type = val_pcie_device_port_type(bdf); /* Check entry is EP. Else move to next BDF. */ if (dp_type == EP) { - val_print(ACS_PRINT_DEBUG, "\n Continuing... device is EP", 0); + val_print(DEBUG, "\n Continuing... device is EP"); current_dev_bdf = bdf; if (!check_msi_status(current_dev_bdf)) { @@ -183,8 +183,8 @@ payload (void) val_pcie_read_cfg(bdf, TYPE01_RIDR, &class_code); - val_print(ACS_PRINT_DEBUG, "\n Secondary BDF is 0x%x", bdf); - val_print(ACS_PRINT_DEBUG, "\n Class code is 0x%x", class_code); + val_print(DEBUG, "\n Secondary BDF is 0x%x", bdf); + val_print(DEBUG, "\n Class code is 0x%x", class_code); base_cc = class_code >> TYPE01_BCC_SHIFT; @@ -197,7 +197,7 @@ payload (void) || (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) || (base_cc > RES_CC)) { - val_print(ACS_PRINT_DEBUG, "\n Skipping DP/NIC/MAS/RES device.", 0); + val_print(DEBUG, "\n Skipping DP/NIC/MAS/RES device."); tbl_index_next++; continue; } @@ -206,7 +206,7 @@ payload (void) /* Check entry is EP. Else move to next BDF. */ if (dp_type == EP) { - val_print(ACS_PRINT_DEBUG, "\n Continuing...device is EP", 0); + val_print(DEBUG, "\n Continuing...device is EP"); next_dev_bdf = bdf; if (!check_msi_status(next_dev_bdf)) { @@ -242,13 +242,13 @@ payload (void) } } else { - val_print (ACS_PRINT_DEBUG, "\n BDF is not EP 0x%x", bdf); + val_print (DEBUG, "\n BDF is not EP 0x%x", bdf); } tbl_index++; } if (test_skip) { - val_print(ACS_PRINT_ERR, "\n No MSI vectors found ", 0);; + val_print(ERROR, "\n No MSI vectors found ");; val_set_status (index, RESULT_SKIP(TEST_NUM, 01)); } else if (!status) { val_set_status (index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/pcie/p100.c b/test_pool/pcie/p100.c index 3ead126f..152f18fc 100644 --- a/test_pool/pcie/p100.c +++ b/test_pool/pcie/p100.c @@ -54,15 +54,15 @@ payload(void) /* Check entry is Rootport */ if (dp_type == RP) { - val_print(ACS_PRINT_DEBUG, "\n BDF 0x%x", bdf); + val_print(DEBUG, "\n BDF 0x%x", bdf); val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value); frs_cap_sup = (reg_value >> DCAP2R_FRS_SHIFT) & DCAP2R_FRS_MASK; if (!frs_cap_sup) { - val_print(ACS_PRINT_DEBUG, "\n FRS not supported for RP", 0); - val_print(ACS_PRINT_DEBUG, "\n Skipping for BDF 0x%x", bdf); + val_print(DEBUG, "\n FRS not supported for RP"); + val_print(DEBUG, "\n Skipping for BDF 0x%x", bdf); continue; } @@ -73,7 +73,7 @@ payload(void) if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) && (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND)) { - val_print(ACS_PRINT_ERR, "\n MSI/MSI-X not supported for BDF 0x%x", bdf); + val_print(ERROR, "\n MSI/MSI-X not supported for BDF 0x%x", bdf); test_fails++; } } diff --git a/test_pool/pcie/p105.c b/test_pool/pcie/p105.c index f6865fb2..6a10b000 100644 --- a/test_pool/pcie/p105.c +++ b/test_pool/pcie/p105.c @@ -42,7 +42,7 @@ payload(void) target_dev_index = val_dma_get_info(DMA_NUM_CTRL, 0); if (!target_dev_index) { - val_print(ACS_PRINT_DEBUG, "\n No DMA controllers detected... ", 0); + val_print(DEBUG, "\n No DMA controllers detected... "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -64,9 +64,9 @@ payload(void) if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { goto test_warn_unimplemented; } - val_print(ACS_PRINT_ERR, "\n The DMA addr allocated to device %d ", + val_print(ERROR, "\n The DMA addr allocated to device %d ", target_dev_index); - val_print(ACS_PRINT_ERR, "\n is not present in the SMMU IOVA table\n", 0); + val_print(ERROR, "\n is not present in the SMMU IOVA table\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index)); return; } diff --git a/test_pool/pe/pe001.c b/test_pool/pe/pe001.c index f6ba5c66..98ab5f8a 100644 --- a/test_pool/pe/pe001.c +++ b/test_pool/pe/pe001.c @@ -161,7 +161,7 @@ return_reg_value(uint32_t reg, uint8_t dependency) break; default: - val_print(ACS_PRINT_ERR, "\n Unknown dependency = %d ", dependency); + val_print(ERROR, "\n Unknown dependency = %d ", dependency); return 0x0; } @@ -242,7 +242,7 @@ payload(uint32_t num_pe) volatile pe_reg_info *pe_buffer; if (num_pe == 1) { - val_print(ACS_PRINT_DEBUG, "\n Skipping as num of PE is 1 ", 0); + val_print(DEBUG, "\n Skipping as num of PE is 1 "); val_set_status(my_index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -258,22 +258,22 @@ payload(uint32_t num_pe) val_pe_reg_write(CSSELR_EL1, i << 1); cache_list[i] = return_reg_value(reg_list[0].reg_name, reg_list[0].dependency); val_data_cache_ops_by_va((addr_t)(cache_list + i), CLEAN_AND_INVALIDATE); - val_print(ACS_PRINT_INFO, "\n Primary PE Index %d", my_index); - val_print(ACS_PRINT_INFO, ", cache index %d", i); - val_print(ACS_PRINT_INFO, ", size read 0x%016llx", cache_list[i]); + val_print(TRACE, "\n Primary PE Index %d", my_index); + val_print(TRACE, ", cache index %d", i); + val_print(TRACE, ", size read 0x%016llx", cache_list[i]); } i++; } for (i = 1; i < NUM_OF_REGISTERS; i++) { rd_data_array[i] = return_reg_value(reg_list[i].reg_name, reg_list[i].dependency); - val_print(ACS_PRINT_INFO, "\n Primary PE Index %d, ", my_index); - val_print(ACS_PRINT_INFO, reg_list[i].reg_desc, 0); + val_print(TRACE, "\n Primary PE Index %d, ", my_index); + val_print(TRACE, reg_list[i].reg_desc); if (reg_list[i].dependency == AA32) - val_print(ACS_PRINT_INFO, " 0x%08llx ", rd_data_array[i]); + val_print(TRACE, " 0x%08llx ", rd_data_array[i]); else - val_print(ACS_PRINT_INFO, " 0x%016llx ", rd_data_array[i]); + val_print(TRACE, " 0x%016llx ", rd_data_array[i]); val_data_cache_ops_by_va((addr_t)(rd_data_array + i), CLEAN_AND_INVALIDATE); } @@ -283,7 +283,7 @@ payload(uint32_t num_pe) g_pe_reg_info = (pe_reg_info *) val_memory_calloc(num_pe, sizeof(pe_reg_info)); if (g_pe_reg_info == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for secondary PE Registers Failed \n", 0); + val_print(ERROR, "\n Allocation for secondary PE Registers Failed \n"); val_set_status(my_index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -295,15 +295,15 @@ payload(uint32_t num_pe) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if(timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); return; } } } - val_print(ACS_PRINT_TEST, "\n Primary PE Index %d", my_index); - val_print(ACS_PRINT_TEST, "\n Primary PE MIDR_EL1 0x%08llx", rd_data_array[1]); + val_print(INFO, "\n Primary PE Index %d", my_index); + val_print(INFO, "\n Primary PE MIDR_EL1 0x%08llx", rd_data_array[1]); for (i = 0; i < num_pe; i++) { uint32_t unique = 1; @@ -318,11 +318,11 @@ payload(uint32_t num_pe) } if (unique == 1 && rd_data_array[1] != pe_buffer->reg_data[1]) { if (t == 0) { - val_print(ACS_PRINT_TEST, "\n Other Cores 0x%08llx ", + val_print(INFO, "\n Other Cores 0x%08llx ", pe_buffer->reg_data[1]); t = 1; } else { - val_print(ACS_PRINT_TEST, "\n 0x%08llx ", + val_print(INFO, "\n 0x%08llx ", pe_buffer->reg_data[1]); } } @@ -330,7 +330,7 @@ payload(uint32_t num_pe) } if (t == 0) { - val_print(ACS_PRINT_TEST, "\n Other Cores Identical ", 0); + val_print(INFO, "\n Other Cores Identical "); } pe_buffer = NULL; @@ -343,20 +343,20 @@ payload(uint32_t num_pe) if (!(pe_buffer->cache_status[cache_index]) && (pe_buffer->pe_cache[cache_index] != 0)) { - val_print(ACS_PRINT_INFO, "\n PE Index %d", i); - val_print(ACS_PRINT_INFO, ", cache index %d", cache_index); - val_print(ACS_PRINT_INFO, ", size read 0x%016llx", + val_print(TRACE, "\n PE Index %d", i); + val_print(TRACE, ", cache index %d", cache_index); + val_print(TRACE, ", size read 0x%016llx", pe_buffer->pe_cache[cache_index]); } else if (pe_buffer->pe_cache[cache_index] != 0) { - val_print(ACS_PRINT_ERR, "\n PE Index %d", i); - val_print(ACS_PRINT_ERR, ", cache index %d", cache_index); - val_print(ACS_PRINT_ERR, ", size read 0x%016llx FAIL\n", + val_print(ERROR, "\n PE Index %d", i); + val_print(ERROR, ", cache index %d", cache_index); + val_print(ERROR, ", size read 0x%016llx FAIL\n", pe_buffer->pe_cache[cache_index]); - val_print(ACS_PRINT_ERR, " Masked Primary PE Value 0x%016llx \n", + val_print(ERROR, " Masked Primary PE Value 0x%016llx \n", cache_list[cache_index] & (~reg_list[0].reg_mask)); - val_print(ACS_PRINT_ERR, " Masked Current PE Value 0x%016llx ", + val_print(ERROR, " Masked Current PE Value 0x%016llx ", pe_buffer->pe_cache[cache_index] & (~reg_list[0].reg_mask)); cache_fail = cache_fail + 1; } @@ -364,28 +364,28 @@ payload(uint32_t num_pe) for (int reg_index = 1; reg_index < NUM_OF_REGISTERS; reg_index++) { if (!(pe_buffer->reg_status[reg_index])) { - val_print(ACS_PRINT_INFO, "\n PE Index %d, ", i); - val_print(ACS_PRINT_INFO, reg_list[reg_index].reg_desc, 0); + val_print(TRACE, "\n PE Index %d, ", i); + val_print(TRACE, reg_list[reg_index].reg_desc); if (reg_list[reg_index].dependency == AA32) - val_print(ACS_PRINT_INFO, " 0x%08llx", pe_buffer->reg_data[reg_index]); + val_print(TRACE, " 0x%08llx", pe_buffer->reg_data[reg_index]); else - val_print(ACS_PRINT_INFO, " 0x%016llx", pe_buffer->reg_data[reg_index]); + val_print(TRACE, " 0x%016llx", pe_buffer->reg_data[reg_index]); } else { - val_print(ACS_PRINT_ERR, "\n PE Index %d, ", i); - val_print(ACS_PRINT_ERR, reg_list[reg_index].reg_desc, 0); + val_print(ERROR, "\n PE Index %d, ", i); + val_print(ERROR, reg_list[reg_index].reg_desc); if (reg_list[reg_index].dependency == AA32) { - val_print(ACS_PRINT_ERR, " 0x%08llx FAIL\n", + val_print(ERROR, " 0x%08llx FAIL\n", pe_buffer->reg_data[reg_index]); - val_print(ACS_PRINT_ERR, " Masked Primary PE Value 0x%08llx \n", + val_print(ERROR, " Masked Primary PE Value 0x%08llx \n", rd_data_array[reg_index] & (~reg_list[reg_index].reg_mask)); - val_print(ACS_PRINT_ERR, " Masked Current PE Value 0x%08llx ", + val_print(ERROR, " Masked Current PE Value 0x%08llx ", pe_buffer->reg_data[reg_index] & (~reg_list[reg_index].reg_mask)); } else { - val_print(ACS_PRINT_ERR, " 0x%016llx FAIL\n", + val_print(ERROR, " 0x%016llx FAIL\n", pe_buffer->reg_data[reg_index]); - val_print(ACS_PRINT_ERR, " Masked Primary PE Value 0x%016llx \n", + val_print(ERROR, " Masked Primary PE Value 0x%016llx \n", rd_data_array[reg_index] & (~reg_list[reg_index].reg_mask)); - val_print(ACS_PRINT_ERR, " Masked Current PE Value 0x%016llx ", + val_print(ERROR, " Masked Current PE Value 0x%016llx ", pe_buffer->reg_data[reg_index] & (~reg_list[reg_index].reg_mask)); } reg_fail = reg_fail + 1; @@ -398,7 +398,7 @@ payload(uint32_t num_pe) } if (total_fail) { - val_print(ACS_PRINT_ERR, "\n\n Total Register and cache fail for all PE %d \n", + val_print(ERROR, "\n\n Total Register and cache fail for all PE %d \n", total_fail); val_set_status(my_index, RESULT_FAIL(TEST_NUM, 4)); } diff --git a/test_pool/pe/pe002.c b/test_pool/pe/pe002.c index 17d567bb..be5eb5c5 100644 --- a/test_pool/pe/pe002.c +++ b/test_pool/pe/pe002.c @@ -40,8 +40,8 @@ payload() return; } - val_print(ACS_PRINT_DEBUG, "\n Number of PE is %d", num_of_pe); - val_print(ACS_PRINT_DEBUG, "\n Gic version is %d", gic_version); + val_print(DEBUG, "\n Number of PE is %d", num_of_pe); + val_print(DEBUG, "\n Gic version is %d", gic_version); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); diff --git a/test_pool/pe/pe006.c b/test_pool/pe/pe006.c index e11800f2..7028e7e0 100644 --- a/test_pool/pe/pe006.c +++ b/test_pool/pe/pe006.c @@ -30,7 +30,7 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (!g_crypto_support) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Crypto extension not supported", + val_print_primary_pe(DEBUG, "\n Crypto extension not supported", 0, index); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; diff --git a/test_pool/pe/pe009.c b/test_pool/pe/pe009.c index e6c88fa3..1b0d54bf 100644 --- a/test_pool/pe/pe009.c +++ b/test_pool/pe/pe009.c @@ -55,7 +55,7 @@ payload() val_set_status(index, RESULT_PASS(TEST_NUM, 1)); else { if (index == primary_pe_idx) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Number of PMU counters reported: %d, expected >= 4", data); } val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); @@ -80,7 +80,7 @@ payload_check_for_pmuv3() data = fetch_pmu_version(); if (data == 0x0 || data == 0xF) { val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print_primary_pe(ACS_PRINT_ERR, + val_print_primary_pe(ERROR, "\n PMUv3 not implemented, ID_AA64DFR0_EL1 PMUVer: 0x%lx", data, primary_pe_idx); return; } diff --git a/test_pool/pe/pe010.c b/test_pool/pe/pe010.c index a40c3d10..e8f5a649 100644 --- a/test_pool/pe/pe010.c +++ b/test_pool/pe/pe010.c @@ -35,7 +35,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Error : Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Error : Received Exception of type %d", interrupt_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); } @@ -66,7 +66,7 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ val_pe_reg_write(PMOVSCLR_EL0, 0x1); - val_print(ACS_PRINT_INFO, "\n Received PMUIRQ ", 0); + val_print(TRACE, "\n Received PMUIRQ "); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(int_id); @@ -99,7 +99,7 @@ payload() } if (val_gic_install_isr(int_id, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -117,7 +117,7 @@ payload() val_pe_reg_write(PMCR_EL0, pmcr_value); exception_taken: if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Interrupt not recieved within timeout", 0); + val_print(ERROR, "\n Interrupt not recieved within timeout"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); } } diff --git a/test_pool/pe/pe011.c b/test_pool/pe/pe011.c index 16ad30ba..13b7f167 100644 --- a/test_pool/pe/pe011.c +++ b/test_pool/pe/pe011.c @@ -38,7 +38,7 @@ payload() breakpointcount = VAL_EXTRACT_BITS(data, 12, 15) + 1; if (breakpointcount < 6) { if (pe_index == primary_pe_idx) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Number of PE breakpoints reported: %d, expected >= 6", breakpointcount); } val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); @@ -51,7 +51,7 @@ payload() val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); else { if (pe_index == primary_pe_idx) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Number of PE context-aware breakpoints reported: %d, expected > 1", context_aware_breakpoints); } diff --git a/test_pool/pe/pe012.c b/test_pool/pe/pe012.c index 52cd7bf8..88d9e1ec 100644 --- a/test_pool/pe/pe012.c +++ b/test_pool/pe/pe012.c @@ -38,7 +38,7 @@ payload() val_set_status(index, RESULT_PASS(TEST_NUM, 1)); else { if (index == primary_pe_idx) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Number of synchronous watchpoints reported: %d, expected > 3", data); } val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); diff --git a/test_pool/pe/pe014.c b/test_pool/pe/pe014.c index df0960d0..2deb3c2d 100644 --- a/test_pool/pe/pe014.c +++ b/test_pool/pe/pe014.c @@ -50,8 +50,8 @@ payload() uint64_t data2 = val_pe_reg_read(ID_AA64ISAR2_EL1); if (index == primary_pe_idx) { - val_print(ACS_PRINT_DEBUG, "\n ID_AA64ISAR1_EL1 = %llx", data1); - val_print(ACS_PRINT_DEBUG, "\n ID_AA64ISAR2_EL1 = %llx", data2); + val_print(DEBUG, "\n ID_AA64ISAR1_EL1 = %llx", data1); + val_print(DEBUG, "\n ID_AA64ISAR2_EL1 = %llx", data2); } /* PAuth is optional, For PAuth authentication support atleast one of generic or address * authentication of any one of the standard algorithm is needed diff --git a/test_pool/pe/pe016.c b/test_pool/pe/pe016.c index 020ce558..0fd7cbff 100644 --- a/test_pool/pe/pe016.c +++ b/test_pool/pe/pe016.c @@ -93,7 +93,7 @@ pe016_entry(uint32_t num_pe) smbios_slots = val_get_num_smbios_slots(); if (smbios_slots == 0) { - val_print(ACS_PRINT_WARN, "\n SMBIOS Table Not Found, Skipping the test\n", 0); + val_print(WARN, "\n SMBIOS Table Not Found, Skipping the test\n"); status = ACS_STATUS_SKIP; val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); @@ -105,7 +105,7 @@ pe016_entry(uint32_t num_pe) if (status != TEST_SKIP_VAL) { g_sve_reg_info = (sve_reg_details *) val_memory_calloc(num_pe, sizeof(sve_reg_details)); if (g_sve_reg_info == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory Allocation for SVE Register data Failed", 0); + val_print(ERROR, "\n Memory Allocation for SVE Register data Failed"); return ACS_STATUS_FAIL; } @@ -114,17 +114,17 @@ pe016_entry(uint32_t num_pe) for (i = 0; i < num_pe; i++) { reg_buffer = g_sve_reg_info + i; - val_print(ACS_PRINT_DEBUG, "\n PE Index = %d", i); + val_print(DEBUG, "\n PE Index = %d", i); if (reg_buffer->status == ACS_STATUS_SKIP) - val_print(ACS_PRINT_DEBUG, "\n Processor is not v9, Skipping the test", 0); + val_print(DEBUG, "\n Processor is not v9, Skipping the test"); else if (reg_buffer->status == ACS_STATUS_ERR) - val_print(ACS_PRINT_DEBUG, "\n Processor Family Not Found in SMBIOS Table", 0); + val_print(DEBUG, "\n Processor Family Not Found in SMBIOS Table"); else if (reg_buffer->status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_DEBUG, "\n Processor is v9 and FEAT_SVE2 is not implemented.", 0); - val_print(ACS_PRINT_DEBUG, " ID_AA64ZFR0_EL1.SVEver 0x%llx FAIL", reg_buffer->data); + val_print(DEBUG, "\n Processor is v9 and FEAT_SVE2 is not implemented."); + val_print(DEBUG, " ID_AA64ZFR0_EL1.SVEver 0x%llx FAIL", reg_buffer->data); } else - val_print(ACS_PRINT_DEBUG, "\n ID_AA64ZFR0_EL1.SVEver 0x%llx PASS", reg_buffer->data); + val_print(DEBUG, "\n ID_AA64ZFR0_EL1.SVEver 0x%llx PASS", reg_buffer->data); } val_memory_free((void *) g_sve_reg_info); diff --git a/test_pool/pe/pe020.c b/test_pool/pe/pe020.c index 81a6c2c9..f52ab656 100644 --- a/test_pool/pe/pe020.c +++ b/test_pool/pe/pe020.c @@ -40,7 +40,7 @@ payload() val_set_status(index, RESULT_PASS(TEST_NUM, 1)); else { if (index == primary_pe_idx) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Number of PMU counters reported: %d, expected > 1", data); } val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); diff --git a/test_pool/pe/pe026.c b/test_pool/pe/pe026.c index 6996d2b5..2c5ea92a 100644 --- a/test_pool/pe/pe026.c +++ b/test_pool/pe/pe026.c @@ -54,7 +54,7 @@ static void payload(void) if (VAL_EXTRACT_BITS(data2, 20, 23) == 0x2 || VAL_EXTRACT_BITS(data2, 28, 31) == 0x1) { - val_print(ACS_PRINT_INFO, "\n System supports both FEAT_LPA & FEAT_LPA2 ", 0); + val_print(TRACE, "\n System supports both FEAT_LPA & FEAT_LPA2 "); val_set_status(index, RESULT_PASS(TEST_NUM, 01)); return; } diff --git a/test_pool/pe/pe032.c b/test_pool/pe/pe032.c index 2f7e45ad..e1010e4b 100644 --- a/test_pool/pe/pe032.c +++ b/test_pool/pe/pe032.c @@ -30,9 +30,9 @@ static void payload(void) uint64_t data1 = val_pe_reg_read(ID_AA64ISAR1_EL1); uint64_t data2 = val_pe_reg_read(ID_AA64ISAR2_EL1); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR1_EL1.APA[7:4] = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.APA[7:4] = %llx", VAL_EXTRACT_BITS(data1, 4, 7), index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR2_EL1.APA3[15:12] = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR2_EL1.APA3[15:12] = %llx", VAL_EXTRACT_BITS(data2, 12, 15), index); /* Pointer signing is mandatory, Check for pointer signing using standard arm algorithm. diff --git a/test_pool/pe/pe033.c b/test_pool/pe/pe033.c index cdb021d8..99b909ff 100644 --- a/test_pool/pe/pe033.c +++ b/test_pool/pe/pe033.c @@ -31,7 +31,7 @@ static void payload(void) /* Read ID_AA64PFR0_EL1[47:44] for Activity monitors extension */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 44, 47); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.AMU[47:44] = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64PFR0_EL1.AMU[47:44] = %llx", data, index); if (data != 0) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/pe/pe034.c b/test_pool/pe/pe034.c index cc7d4b6f..874b681f 100644 --- a/test_pool/pe/pe034.c +++ b/test_pool/pe/pe034.c @@ -29,7 +29,7 @@ static void payload(void) if (!g_crypto_support) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Crypto extension not supported", + val_print_primary_pe(DEBUG, "\n Crypto extension not supported", 0, index); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; diff --git a/test_pool/pe/pe036.c b/test_pool/pe/pe036.c index 36a2aa09..a0077168 100644 --- a/test_pool/pe/pe036.c +++ b/test_pool/pe/pe036.c @@ -32,7 +32,7 @@ static void payload(void) /* Read ID_AA64MMFR2_EL1[27:24] for enhanced Nested Virtualization support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 24, 27); if (index == primary_pe_idx) { - val_print(ACS_PRINT_DEBUG, "\n ID_AA64MMFR2_EL1.NV = %llx", data); + val_print(DEBUG, "\n ID_AA64MMFR2_EL1.NV = %llx", data); } /* Read ID_AA64MMFR2_EL1.NV[27:24] == 2 indicates FEAT_NV2 support diff --git a/test_pool/pe/pe037.c b/test_pool/pe/pe037.c index 46984c90..4035aa5a 100644 --- a/test_pool/pe/pe037.c +++ b/test_pool/pe/pe037.c @@ -34,7 +34,7 @@ void payload(void) /* Read ID_AA64PFR0_EL1.SVE[35:32] = 0b0001 for SVE */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 32, 35); if (index == primary_pe_idx) - val_print(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.SVE = %llx", data); + val_print(DEBUG, "\n ID_AA64PFR0_EL1.SVE = %llx", data); if (data == 0) { /* SVE Not Implemented Skip the test */ @@ -45,7 +45,7 @@ void payload(void) /* Read ID_AA64DFR0_EL1.PMSVer[35:32] = 0b0010 for v8.3-SPE */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 32, 35); if (index == primary_pe_idx) - val_print(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.PMSVer = %llx", data); + val_print(DEBUG, "\n ID_AA64DFR0_EL1.PMSVer = %llx", data); if (data == 0) /* SPE Not Implemented Skip the test */ diff --git a/test_pool/pe/pe040.c b/test_pool/pe/pe040.c index efdeef02..2d004754 100644 --- a/test_pool/pe/pe040.c +++ b/test_pool/pe/pe040.c @@ -35,7 +35,7 @@ static void payload_check_if_pmuv3_5(void) /* Read ID_AA64DFR0_EL1.PMUVer[11:8] >= 0b0110 and != 0xF for PMU v3.5 or higher support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.PMUVer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.PMUVer = %llx", data, index); @@ -52,7 +52,7 @@ static void payload_check_if_pmuv3_7(void) uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.PMUVer = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.PMUVer = %llx", data, index); /* Read ID_AA64DFR0_EL1.PMUVer[11:8] >= 0b0111 and != 0xF for PMU v3.7 or higher support */ diff --git a/test_pool/pe/pe043.c b/test_pool/pe/pe043.c index b67a53a7..95f7ecef 100644 --- a/test_pool/pe/pe043.c +++ b/test_pool/pe/pe043.c @@ -36,8 +36,8 @@ static void payload(void) data_csv2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 56, 59); data_csv3 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 60, 63); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.CSV2 = %llx", data_csv2, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.CSV3 = %llx", data_csv3, index); + val_print_primary_pe(DEBUG, "\n ID_AA64PFR0_EL1.CSV2 = %llx", data_csv2, index); + val_print_primary_pe(DEBUG, "\n ID_AA64PFR0_EL1.CSV3 = %llx", data_csv3, index); if (((data_csv2 == 2) || (data_csv2 == 3)) && (data_csv3 == 1)) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/pe/pe047.c b/test_pool/pe/pe047.c index 789297e0..8cdce498 100644 --- a/test_pool/pe/pe047.c +++ b/test_pool/pe/pe047.c @@ -31,7 +31,7 @@ static void payload(void) /* Read ID_AA64ISAR1_EL1.SPECRES[43:40] = 0b0001 For CFP, DVP, CPP RCTX Instructions */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 40, 43); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR1_EL1.SPECRES = %llx", data, index); + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.SPECRES = %llx", data, index); if (data != 1 && data != 2) val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); diff --git a/test_pool/pe/pe053.c b/test_pool/pe/pe053.c index 4b3887e0..66f8c94b 100644 --- a/test_pool/pe/pe053.c +++ b/test_pool/pe/pe053.c @@ -30,9 +30,9 @@ static void payload(void) uint32_t data2 = val_pe_reg_read(ID_AA64ISAR2_EL1); uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR1_EL1.APA[7:4] = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.APA[7:4] = %llx", VAL_EXTRACT_BITS(data1, 4, 7), index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR2_EL1.APA3[15:12] = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR2_EL1.APA3[15:12] = %llx", VAL_EXTRACT_BITS(data2, 12, 15), index); /* Read ID_AA64ISAR1_EL1.APA[7:4] and ID_AA64ISAR2_EL1.APA3[15:12] == 0b0101 or 0b0110 diff --git a/test_pool/pe/pe056.c b/test_pool/pe/pe056.c index 89c35935..dced153c 100644 --- a/test_pool/pe/pe056.c +++ b/test_pool/pe/pe056.c @@ -34,14 +34,14 @@ static void payload(void) trapping for WFE instruction */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 32, 35); if (index == primary_pe_idx) - val_print(ACS_PRINT_DEBUG, "\n ID_AA64MMFR1_EL1.TWED = %llx", data); + val_print(DEBUG, "\n ID_AA64MMFR1_EL1.TWED = %llx", data); if (data == 1) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); else { if (index == primary_pe_idx) - val_print(ACS_PRINT_WARN, - "\n Recommended WFE fine-tuning delay feature not implemented", 0); + val_print(WARN, + "\n Recommended WFE fine-tuning delay feature not implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); } } diff --git a/test_pool/pe/pe060.c b/test_pool/pe/pe060.c index 82632548..ae8c4460 100644 --- a/test_pool/pe/pe060.c +++ b/test_pool/pe/pe060.c @@ -31,7 +31,7 @@ static void payload(void) /* ID_AA64ISAR1_EL1.LS64[63:60] >= 0b0001 indicates FEAT_LS64 support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 60, 63); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64ISAR1_EL1.LS64 = %llx", data, index); + val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.LS64 = %llx", data, index); if (data >= 1) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/pe/pe061.c b/test_pool/pe/pe061.c index df637212..020c704a 100644 --- a/test_pool/pe/pe061.c +++ b/test_pool/pe/pe061.c @@ -31,7 +31,7 @@ static void payload(void) /* ID_AA64DFR0_EL1.BRBE, bits [55:52] non-zero value indicate FEAT_BRBE support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 52, 55); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64DFR0_EL1.BRBE = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64DFR0_EL1.BRBE = %llx", data, index); if (data == 0) { @@ -41,7 +41,7 @@ static void payload(void) /* BRBIDR0_EL1.NUMREC[7:0] = 0x20 or 0x40 indicates atleast 32 branch record buffer support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(BRBIDR0_EL1), 0, 7); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n BRBIDR0_EL1.NUMREC = %llx", + val_print_primary_pe(DEBUG, "\n BRBIDR0_EL1.NUMREC = %llx", data, index); if (data == 0x20 || data == 0x40) diff --git a/test_pool/pe/pe062.c b/test_pool/pe/pe062.c index 5f61b555..d3fa4cf4 100644 --- a/test_pool/pe/pe062.c +++ b/test_pool/pe/pe062.c @@ -34,7 +34,7 @@ static void payload(void) * bits[62:59] can individually enabled as PBHA bits for both Stage-1 and Stage-2 */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 12, 15); - val_print_primary_pe(ACS_PRINT_INFO, "\n ID_AA64MMFR1_EL1.HPDS = %llx", + val_print_primary_pe(TRACE, "\n ID_AA64MMFR1_EL1.HPDS = %llx", data, index); /* If FEAT_HPDS2 is not supported then PBHA bits cannot be enabled */ @@ -47,7 +47,7 @@ static void payload(void) if (el != AARCH64_EL1 && el != AARCH64_EL2) { val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Current EL = %llx", el, index); + val_print_primary_pe(DEBUG, "\n Current EL = %llx", el, index); return; } @@ -58,7 +58,7 @@ static void payload(void) if (el == AARCH64_EL2) { e2h = VAL_EXTRACT_BITS(val_pe_reg_read(HCR_EL2), 34, 34); - val_print_primary_pe(ACS_PRINT_INFO, "\n HCR_EL2.E2H = %llx", + val_print_primary_pe(TRACE, "\n HCR_EL2.E2H = %llx", e2h, index); } @@ -79,9 +79,9 @@ static void payload(void) if (VAL_EXTRACT_BITS(data, 41, 41) != 0) { if (VAL_EXTRACT_BITS(data, 43, 46) != 0) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_ELx.HPD0 = %llx", + val_print_primary_pe(DEBUG, "\n TCR_ELx.HPD0 = %llx", VAL_EXTRACT_BITS(data, 41, 41), index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_ELx.HWU0nn = %llx", + val_print_primary_pe(DEBUG, "\n TCR_ELx.HWU0nn = %llx", VAL_EXTRACT_BITS(data, 43, 46), index); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; @@ -93,9 +93,9 @@ static void payload(void) if (VAL_EXTRACT_BITS(data, 42, 42) != 0) { if (VAL_EXTRACT_BITS(data, 47, 50) != 0) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_ELx.HPD1 = %llx", + val_print_primary_pe(DEBUG, "\n TCR_ELx.HPD1 = %llx", VAL_EXTRACT_BITS(data, 42, 42), index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_ELx.HWU1nn = %llx", + val_print_primary_pe(DEBUG, "\n TCR_ELx.HWU1nn = %llx", VAL_EXTRACT_BITS(data, 47, 50), index); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; @@ -109,9 +109,9 @@ static void payload(void) if (VAL_EXTRACT_BITS(data, 24, 24) != 0) { if (VAL_EXTRACT_BITS(data, 25, 28) != 0) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_EL2.HPD = %llx", + val_print_primary_pe(DEBUG, "\n TCR_EL2.HPD = %llx", VAL_EXTRACT_BITS(data, 24, 24), index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n TCR_EL2.HWUnn = %llx", + val_print_primary_pe(DEBUG, "\n TCR_EL2.HWUnn = %llx", VAL_EXTRACT_BITS(data, 25, 28), index); val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); return; @@ -120,7 +120,7 @@ static void payload(void) } if (el != AARCH64_EL2) { - val_print_primary_pe(ACS_PRINT_WARN, "\n Current EL needs to be in EL2", + val_print_primary_pe(WARN, "\n Current EL needs to be in EL2", 0, index); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; @@ -129,7 +129,7 @@ static void payload(void) /* VTCR_EL2.HWUnn[28:25] !=0 indicates corresponding PBHA bit can be enabled in Stage-2 */ data = val_pe_reg_read(VTCR_EL2); if (VAL_EXTRACT_BITS(data, 25, 28) != 0) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n VTCR_EL2.HWUnn = %llx", + val_print_primary_pe(DEBUG, "\n VTCR_EL2.HWUnn = %llx", VAL_EXTRACT_BITS(data, 25, 28), index); val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); } else diff --git a/test_pool/pe/pe065.c b/test_pool/pe/pe065.c index eef686d8..406245de 100644 --- a/test_pool/pe/pe065.c +++ b/test_pool/pe/pe065.c @@ -31,7 +31,7 @@ static void payload(void) /* ID_AA64PFR1_EL1.PFAR, bits [63:60] value one indicate FEAT_PFAR support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 60, 63); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ID_AA64PFR1_EL1.PFAR = %llx", + val_print_primary_pe(DEBUG, "\n ID_AA64PFR1_EL1.PFAR = %llx", data, index); if (data == 1) diff --git a/test_pool/pe/pe066.c b/test_pool/pe/pe066.c index 32ead140..4eebf824 100644 --- a/test_pool/pe/pe066.c +++ b/test_pool/pe/pe066.c @@ -52,7 +52,7 @@ payload() if (breakpointcount < 6) { - val_print_primary_pe(ACS_PRINT_ERR, + val_print_primary_pe(ERROR, "\n Number of PE breakpoints reported: %d, expected >= 6", breakpointcount, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); @@ -74,14 +74,14 @@ payload() else context_aware_breakpoints = (dfr1_ctx == 0) ? 16 : (dfr1_ctx + 1); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Total Breakpoints : %u", + val_print_primary_pe(DEBUG, "\n Total Breakpoints : %u", breakpointcount, pe_index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Context-Aware Breakpoints : %u", + val_print_primary_pe(DEBUG, "\n Context-Aware Breakpoints : %u", context_aware_breakpoints, pe_index); if (context_aware_breakpoints < 2) { - val_print_primary_pe(ACS_PRINT_ERR, + val_print_primary_pe(ERROR, "\n Context-aware breakpoints reported: %u, expected >= 2", context_aware_breakpoints, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); @@ -102,9 +102,9 @@ payload() ctx_end = context_aware_breakpoints - 1; } - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Context-Aware BP range st : BP[%u]", + val_print_primary_pe(DEBUG, "\n Context-Aware BP range st : BP[%u]", ctx_start, pe_index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Context-Aware BP range end : BP[%u]", + val_print_primary_pe(DEBUG, "\n Context-Aware BP range end : BP[%u]", ctx_end, pe_index); /* Breakpoints 4 and 5 must be context-aware */ @@ -112,7 +112,7 @@ payload() val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); else { - val_print_primary_pe(ACS_PRINT_ERR, + val_print_primary_pe(ERROR, "\n Breakpoints 4 and 5 are not context-aware as required", 0, pe_index); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); } diff --git a/test_pool/peripherals/d001.c b/test_pool/peripherals/d001.c index ce19ac15..7a7b501a 100644 --- a/test_pool/peripherals/d001.c +++ b/test_pool/peripherals/d001.c @@ -41,7 +41,7 @@ test_status_t check_for_usb_intrf (uint32_t usb_type) uint32_t usb_pref, usb_alt, progif_pref, progif_alt; uint64_t count = val_peripheral_get_info(NUM_USB, 0); - val_print(ACS_PRINT_DEBUG, "\n Num of USB CTRL %d detected", count); + val_print(DEBUG, "\n Num of USB CTRL %d detected", count); /* If USB peripheral count is zero, skip the test */ if (count == 0) { return TEST_SKIP; @@ -63,48 +63,47 @@ test_status_t check_for_usb_intrf (uint32_t usb_type) while (count != 0) { /* If DT system */ if (val_peripheral_get_info(USB_PLATFORM_TYPE, count - 1) == PLATFORM_TYPE_DT) { - val_print(ACS_PRINT_INFO, "\n USB %d info from DT table", count - 1); + val_print(TRACE, "\n USB %d info from DT table", count - 1); interface = val_peripheral_get_info(USB_INTERFACE_TYPE, count - 1); - val_print(ACS_PRINT_DEBUG, "\n USB interface is %d", interface); + val_print(DEBUG, "\n USB interface is %d", interface); if (interface != usb_pref) { /* Continue if USB implements allowed alternative else fail */ if (interface == usb_alt) { count--; continue; } else { - val_print(ACS_PRINT_WARN, "\n Detected USB CTRL %d supports", count - 1); - val_print(ACS_PRINT_WARN, " %x interface and not EHCI/XHCI", interface); + val_print(WARN, "\n Detected USB CTRL %d supports", count - 1); + val_print(WARN, " %x interface and not EHCI/XHCI", interface); fail_cnt++; } } /* For non-DT system */ } else { bdf = val_peripheral_get_info(USB_BDF, count - 1); - val_print(ACS_PRINT_DEBUG, "\n USB bdf %lx info from non DT table", bdf); - val_print(ACS_PRINT_DEBUG, "\n USB %d info from non DT", count - 1); + val_print(DEBUG, "\n USB bdf %lx info from non DT table", bdf); + val_print(DEBUG, "\n USB %d info from non DT", count - 1); ret = val_pcie_read_cfg(bdf, TYPE01_CCR_SHIFT, &interface); /* Extract programming interface field as per PCI Code and ID Assignment Specification */ interface = (interface >> TYPE01_CCR_SHIFT) & 0xFF; - val_print(ACS_PRINT_DEBUG, "\n USB interface value is %lx", interface); + val_print(DEBUG, "\n USB interface value is %lx", interface); if (ret == PCIE_NO_MAPPING || (interface < PCIE_PROGIF_EHCI) || (interface == 0xFF)) { - val_print(ACS_PRINT_INFO, "\n WARN: USB CTRL ECAM access failed 0x%x ", + val_print(TRACE, "\n WARN: USB CTRL ECAM access failed 0x%x ", interface); - val_print(ACS_PRINT_INFO, "\n Re-checking using PCIIO protocol", - 0); + val_print(TRACE, "\n Re-checking using PCIIO protocol"); ret = val_pcie_io_read_cfg(bdf, TYPE01_CCR_SHIFT, &interface); if (ret == PCIE_NO_MAPPING) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Reading device class code using PciIo protocol failed " - , 0); + ); fail_cnt++; } interface = (interface >> TYPE01_CCR_SHIFT) & 0xFF; - val_print(ACS_PRINT_DEBUG, "\n (PCIIO) USB interface value is %lx", + val_print(DEBUG, "\n (PCIIO) USB interface value is %lx", interface); if (interface != progif_pref) { @@ -113,9 +112,9 @@ test_status_t check_for_usb_intrf (uint32_t usb_type) count--; continue; } else { - val_print(ACS_PRINT_WARN, "\n Detected USB CTRL %d supports", + val_print(WARN, "\n Detected USB CTRL %d supports", count - 1); - val_print(ACS_PRINT_WARN, " %x interface and not EHCI/XHCI", interface); + val_print(WARN, " %x interface and not EHCI/XHCI", interface); fail_cnt++; } } diff --git a/test_pool/peripherals/d002.c b/test_pool/peripherals/d002.c index 7156175d..46f94639 100644 --- a/test_pool/peripherals/d002.c +++ b/test_pool/peripherals/d002.c @@ -43,7 +43,7 @@ payload() if (val_peripheral_get_info(SATA_PLATFORM_TYPE, count - 1) == PLATFORM_TYPE_DT) { interface = val_peripheral_get_info(SATA_INTERFACE_TYPE, count - 1); if (interface != SATA_TYPE_AHCI) { - val_print(ACS_PRINT_DEBUG, "\n Detected SATA CTRL not AHCI 0x%x ", + val_print(DEBUG, "\n Detected SATA CTRL not AHCI 0x%x ", interface); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -54,19 +54,19 @@ payload() ret = val_pcie_read_cfg(bdf, 0x8, &interface); interface = (interface >> 8) & 0xFF; if (ret == PCIE_NO_MAPPING || interface != 0x01) { - val_print(ACS_PRINT_INFO, " WARN: SATA CTRL ECAM access failed %x\n", + val_print(TRACE, " WARN: SATA CTRL ECAM access failed %x\n", interface); - val_print(ACS_PRINT_INFO, " Re-checking SATA CTRL using PciIo protocol\n", 0); + val_print(TRACE, " Re-checking SATA CTRL using PciIo protocol\n"); ret = val_pcie_io_read_cfg(bdf, 0x8, &interface); if (ret == PCIE_NO_MAPPING) { - val_print(ACS_PRINT_DEBUG, " Reading device class code using PciIo" - " protocol failed\n", 0); + val_print(DEBUG, " Reading device class code using PciIo" + " protocol failed\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } interface = (interface >> 8) & 0xFF; if (interface != 0x01) { - val_print(ACS_PRINT_DEBUG, " Detected SATA CTRL not AHCI\n", 0); + val_print(DEBUG, " Detected SATA CTRL not AHCI\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/peripherals/d003.c b/test_pool/peripherals/d003.c index a92dc065..f13a272c 100644 --- a/test_pool/peripherals/d003.c +++ b/test_pool/peripherals/d003.c @@ -46,7 +46,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Error : Received Exception of type %d", interrupt_type); + val_print(ERROR, "\n Error : Received Exception of type %d", interrupt_type); val_set_status(index, TEST_FAIL); } @@ -161,7 +161,7 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uart_disable_txintr(); - val_print(ACS_PRINT_DEBUG, "\n Received interrupt on %d ", int_id); + val_print(DEBUG, "\n Received interrupt on %d ", int_id); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(int_id); } @@ -181,7 +181,7 @@ check_arm_generic_uart() branch_to_test = &&exception_taken; if (count == 0) { - val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); + val_print(ERROR, "\n No UART defined by Platform "); if (g_build_sbsa) return TEST_FAIL; else @@ -243,7 +243,7 @@ check_uart_16550() uint32_t test_fail = 0; if (count == 0) { - val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); + val_print(ERROR, "\n No UART defined by Platform "); if (g_build_sbsa) return TEST_FAIL; else @@ -257,7 +257,7 @@ check_uart_16550() || interface_type == COMPATIBLE_GENERIC_16550) { test_skip = 0; - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n UART 16550 found with instance: %x", count - 1); @@ -265,7 +265,7 @@ check_uart_16550() uart_base = val_peripheral_get_info(UART_BASE0, count - 1); if (uart_base == 0) { - val_print(ACS_PRINT_ERR, "\n UART base must be specified" + val_print(ERROR, "\n UART base must be specified" " for instance: %x", count - 1); return TEST_FAIL; } @@ -286,7 +286,7 @@ check_uart_16550() width_mask = WIDTH_BIT32; break; default: - val_print(ACS_PRINT_ERR, "\n UART access width must be specified" + val_print(ERROR, "\n UART access width must be specified" " for instance: %x", count - 1); return TEST_FAIL; } @@ -297,15 +297,15 @@ check_uart_16550() { if (baud_rate != 0) { - val_print(ACS_PRINT_ERR, "\n Baud rate %d outside" + val_print(ERROR, "\n Baud rate %d outside" " supported range", baud_rate); - val_print(ACS_PRINT_ERR, " for instance %x", count - 1); + val_print(ERROR, " for instance %x", count - 1); test_fail = 1; } } - val_print(ACS_PRINT_ERR, "\nDEBUG: uart_base %llx", uart_base); - val_print(ACS_PRINT_ERR, "\nDEBUG: access_width %d", access_width); + val_print(ERROR, "\nDEBUG: uart_base %llx", uart_base); + val_print(ERROR, "\nDEBUG: access_width %d", access_width); /* Check the read/write property of Line Control Register */ @@ -317,7 +317,7 @@ check_uart_16550() uart_16550_reg_write(uart_base, LCR, reg_shift, width_mask, lcr_reg); if ((lcr_scratch2 != 0) || (lcr_scratch3 != 0xFF)) { - val_print(ACS_PRINT_ERR, "\n LCR register are not read/write" + val_print(ERROR, "\n LCR register are not read/write" " for instance: %x", count - 1); test_fail = 1; } @@ -331,7 +331,7 @@ check_uart_16550() uart_16550_reg_write(uart_base, IER, reg_shift, width_mask, ier_reg); if ((ier_scratch2 != 0) || (ier_scratch3 != 0xF)) { - val_print(ACS_PRINT_ERR, "\n IER register[0:3] are not read/write" + val_print(ERROR, "\n IER register[0:3] are not read/write" " for instance: %x", count - 1); test_fail = 1; } @@ -343,7 +343,7 @@ check_uart_16550() uart_16550_reg_write(uart_base, MCR, reg_shift, width_mask, mcr_reg); if ((msr_status & 0xF0) != CTS_DCD_EN) { - val_print(ACS_PRINT_ERR, "\n Loopback test mode failed" + val_print(ERROR, "\n Loopback test mode failed" " for instance: %x", count - 1); test_fail = 1; } @@ -395,7 +395,7 @@ payload_check_arm_generic_uart_interrupt() uint32_t interface_type; if (count == 0) { - val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); + val_print(ERROR, "\n No UART defined by Platform "); val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); return; } @@ -416,7 +416,7 @@ payload_check_arm_generic_uart_interrupt() /* Check int_id is SPI or ESPI */ if (!(IsSpi(int_id)) && !(val_gic_is_valid_espi(int_id))) { - val_print(ACS_PRINT_ERR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); + val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); val_set_status(index, RESULT_FAIL(TEST_NUM1, 2)); return; } @@ -431,7 +431,7 @@ payload_check_arm_generic_uart_interrupt() /* Install ISR */ if (val_gic_install_isr(int_id, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM1, 3)); return; } @@ -444,7 +444,7 @@ payload_check_arm_generic_uart_interrupt() }; if (timeout == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Did not receive UART interrupt on %d ", int_id); test_fail++; diff --git a/test_pool/peripherals/d004.c b/test_pool/peripherals/d004.c index 6620d1a9..d23366a9 100644 --- a/test_pool/peripherals/d004.c +++ b/test_pool/peripherals/d004.c @@ -51,7 +51,7 @@ payload_check_dma_mem_attribute(void) if (!target_dev_index) { - val_print(ACS_PRINT_TEST, "\n No DMA controllers detected... ", 0); + val_print(INFO, "\n No DMA controllers detected... "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -79,7 +79,7 @@ payload_check_dma_mem_attribute(void) if (ret == ACS_STATUS_PAL_NOT_IMPLEMENTED) { goto test_warn_unimplemented; } - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DMA controller %d: Failed to get" " memory attributes\n", target_dev_index); @@ -93,7 +93,7 @@ payload_check_dma_mem_attribute(void) MEM_NORMAL_NC_IN_OUT(attr) || /* Check Inner Non-Cacheable, Outer Non-Cacheable*/ MEM_DEVICE(attr))) /* Check Device type */ { - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n DMA controller %d: DMA memory must be inner/outer writeback inner " "shareable, inner/outer non-cacheable, or device type\n", target_dev_index); @@ -130,7 +130,7 @@ payload_check_io_coherent_dma_mem_attribute(void) if (!target_dev_index) { - val_print(ACS_PRINT_TEST, "\n No DMA controllers detected... ", 0); + val_print(INFO, "\n No DMA controllers detected... "); val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); return; } @@ -149,7 +149,7 @@ payload_check_io_coherent_dma_mem_attribute(void) if (ret == ACS_STATUS_PAL_NOT_IMPLEMENTED) { goto test_warn_unimplemented; } else if (ret) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DMA controller %d: Failed to get memory attributes\n", target_dev_index); val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); @@ -159,11 +159,11 @@ payload_check_io_coherent_dma_mem_attribute(void) /* Check Inner Write-Back, Outer Write-Back, Inner Shareable */ if (!(MEM_NORMAL_WB_IN_OUT(attr) && MEM_SH_INNER(sh))) { - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n DMA controller %d: I/O Coherent DMA memory must\n", target_dev_index); - val_print(ACS_PRINT_INFO, - " be inner/outer writeback, inner shareable\n", 0); + val_print(TRACE, + " be inner/outer writeback, inner shareable\n"); val_set_status(index, RESULT_FAIL(TEST_NUM1, 2)); flag_fail = 1; } diff --git a/test_pool/pfdi/pfdi001.c b/test_pool/pfdi/pfdi001.c index 6106883c..093ed816 100644 --- a/test_pool/pfdi/pfdi001.c +++ b/test_pool/pfdi/pfdi001.c @@ -32,7 +32,7 @@ static void payload_version_check(void *arg) pfdi_version.x0 = val_pfdi_version(&pfdi_version.x1, &pfdi_version.x2, &pfdi_version.x3, &pfdi_version.x4); if (pfdi_version.x0 >> 31) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI get version failed err = %ld", pfdi_version.x0); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -41,32 +41,32 @@ static void payload_version_check(void *arg) /* Return status Bits[63:31] must be zero */ if (val_pfdi_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(pfdi_version.x0, 31, 63)) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", index); + val_print(ERROR, "\n Failed on PE = %d", index); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } major = PFDI_VERSION_GET_MAJOR(pfdi_version.x0); if (major != PFDI_MAJOR_VERSION) { - val_print(ACS_PRINT_ERR, "\n Major Version not as expected, Current version = %d", major); + val_print(ERROR, "\n Major Version not as expected, Current version = %d", major); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } minor = PFDI_VERSION_GET_MINOR(pfdi_version.x0); if (minor != PFDI_MINOR_VERSION) { - val_print(ACS_PRINT_ERR, "\n Minor Version not as expected, Current version = %d", minor); + val_print(ERROR, "\n Minor Version not as expected, Current version = %d", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } if ((pfdi_version.x1 != 0) || (pfdi_version.x2 != 0) || (pfdi_version.x3 != 0) || (pfdi_version.x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_version.x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_version.x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_version.x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_version.x4); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_version.x1); + val_print(ERROR, " x2=0x%llx", pfdi_version.x2); + val_print(ERROR, " x3=0x%llx", pfdi_version.x3); + val_print(ERROR, " x4=0x%llx", pfdi_version.x4); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; } diff --git a/test_pool/pfdi/pfdi002.c b/test_pool/pfdi/pfdi002.c index 8aeb33ca..663ff0db 100644 --- a/test_pool/pfdi/pfdi002.c +++ b/test_pool/pfdi/pfdi002.c @@ -55,7 +55,7 @@ static void payload_all_pe_version_check(void *arg) /* Allocate memory to save all PFDI Versions or status for all PE's */ g_pfdi_version_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_version_details == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Version Details Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Version Details Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -77,7 +77,7 @@ static void payload_all_pe_version_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -93,42 +93,42 @@ static void payload_all_pe_version_check(void *arg) version = pfdi_buffer->x0; if (version >> 31) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI get version failed %ld, ", version); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "on PE = %d", i); test_fail++; } if (val_pfdi_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(pfdi_buffer->x0, 31, 63)) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } major = PFDI_VERSION_GET_MAJOR(version); if (major != PFDI_MAJOR_VERSION) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Major Version not as expected, Current version = %d", major); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } minor = PFDI_VERSION_GET_MINOR(version); if (minor != PFDI_MINOR_VERSION) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Minor Version not as expected, Current version =%d", minor); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi003.c b/test_pool/pfdi/pfdi003.c index 0316526d..7f3e78ea 100644 --- a/test_pool/pfdi/pfdi003.c +++ b/test_pool/pfdi/pfdi003.c @@ -59,7 +59,7 @@ static void payload_functions_check(void *arg) /* Allocate memory to save all PFDI features status for all PE's */ g_pfdi_feature_details = (feature_details *) val_memory_calloc(num_pe, sizeof(feature_details)); if (g_pfdi_feature_details == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Feature Details Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Feature Details Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -83,7 +83,7 @@ static void payload_functions_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -102,10 +102,10 @@ static void payload_functions_check(void *arg) fn_status = 0; for (f_id = PFDI_FN_PFDI_VERSION; f_id <= PFDI_FN_PFDI_FORCE_ERROR; f_id++) { if (pfdi_buffer->status[fn_status] != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI mandatory function 0x%x ", f_id); - val_print(ACS_PRINT_ERR, "failed on PE %d, ", i); - val_print(ACS_PRINT_ERR, "status = %d", pfdi_buffer->status[fn_status]); + val_print(ERROR, "failed on PE %d, ", i); + val_print(ERROR, "status = %d", pfdi_buffer->status[fn_status]); test_fail++; } fn_status++; diff --git a/test_pool/pfdi/pfdi004.c b/test_pool/pfdi/pfdi004.c index 4469dbc4..a3439716 100644 --- a/test_pool/pfdi/pfdi004.c +++ b/test_pool/pfdi/pfdi004.c @@ -57,8 +57,8 @@ static void payload_feature_check(void *arg) g_pfdi_feature_check_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_feature_check_details == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Feature Check Function Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Feature Check Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -80,7 +80,7 @@ static void payload_feature_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -95,20 +95,20 @@ static void payload_feature_check(void *arg) run_fail = 0; if (status_buffer->x0 < PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI Feature Check function failed err = %ld", + val_print(ERROR, "\n PFDI Feature Check function failed err = %ld", status_buffer->x0); - val_print(ACS_PRINT_ERR, " on PE index = %d", i); + val_print(ERROR, " on PE index = %d", i); run_fail++; } if ((status_buffer->x1 != 0) || (status_buffer->x2 != 0) || (status_buffer->x3 != 0) || (status_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", status_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", status_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", status_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", status_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", status_buffer->x1); + val_print(ERROR, " x2=0x%llx", status_buffer->x2); + val_print(ERROR, " x3=0x%llx", status_buffer->x3); + val_print(ERROR, " x4=0x%llx", status_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); run_fail++; } diff --git a/test_pool/pfdi/pfdi005.c b/test_pool/pfdi/pfdi005.c index 551f248c..f540569f 100644 --- a/test_pool/pfdi/pfdi005.c +++ b/test_pool/pfdi/pfdi005.c @@ -56,8 +56,8 @@ static void payload_pe_test_id_check(void *arg) g_pfdi_st_version_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_st_version_details == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Self Test Version Details Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Self Test Version Details Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } @@ -79,7 +79,7 @@ static void payload_pe_test_id_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 5)); goto free_pfdi_details; } @@ -88,7 +88,7 @@ static void payload_pe_test_id_check(void *arg) val_time_delay_ms(ONE_MILLISECOND); for (i = 0; i < num_pe; i++) { - val_print(ACS_PRINT_DEBUG, "\n PFDI Self Test version details for PE index = %d", i); + val_print(DEBUG, "\n PFDI Self Test version details for PE index = %d", i); pfdi_buffer = g_pfdi_st_version_details + i; test_fail = 0; @@ -101,44 +101,44 @@ static void payload_pe_test_id_check(void *arg) /* Return status Bits[63:32] must be zero */ if (val_pfdi_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(version, 32, 63)) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } /* Return status Bits[23:20] must be zero */ if (val_pfdi_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(version, 20, 23)) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } major = VAL_EXTRACT_BITS(version, 8, 15); - val_print(ACS_PRINT_DEBUG, "\n PFDI Self Test Major Version = %d", major); + val_print(DEBUG, "\n PFDI Self Test Major Version = %d", major); minor = VAL_EXTRACT_BITS(version, 0, 7); - val_print(ACS_PRINT_DEBUG, "\n PFDI Self Test Minor Version = %d", minor); + val_print(DEBUG, "\n PFDI Self Test Minor Version = %d", minor); vendor_id = VAL_EXTRACT_BITS(version, 24, 31); - val_print(ACS_PRINT_DEBUG, "\n PFDI Self Test Vendor ID = %d", vendor_id); + val_print(DEBUG, "\n PFDI Self Test Vendor ID = %d", vendor_id); } else if (temp_status == PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n PFDI Self test metadata not available on PE %d ", i); + val_print(ERROR, "\n PFDI Self test metadata not available on PE %d ", i); if (pfdi_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n Registers X1 is not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, "\n Registers X1 is not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); test_fail++; } } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI PE Test ID failed err = %lld", temp_status); test_fail++; } if ((pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X2-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X2-X4 are not zero:"); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi006.c b/test_pool/pfdi/pfdi006.c index ac186e57..3e28d048 100644 --- a/test_pool/pfdi/pfdi006.c +++ b/test_pool/pfdi/pfdi006.c @@ -53,7 +53,7 @@ static void payload_pe_test_info_check(void *arg) g_pfdi_pe_test_support_info = (PFDI_RET_PARAMS *)val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_pe_test_support_info == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI PE Test Support Info Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI PE Test Support Info Failed \n"); return; } @@ -74,7 +74,7 @@ static void payload_pe_test_info_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -90,24 +90,24 @@ static void payload_pe_test_info_check(void *arg) val_pfdi_invalidate_ret_params(test_buffer); if (test_buffer->x0 < PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI query Test part count failed %lld", + val_print(ERROR, "\n PFDI query Test part count failed %lld", test_buffer->x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "on PE = %d", i); test_fail++; } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Test Part Count = 0x%llx", test_buffer->x0); - val_print(ACS_PRINT_DEBUG, "on PE %d", i); + val_print(DEBUG, "on PE %d", i); } if ((test_buffer->x1 != 0) || (test_buffer->x2 != 0) || (test_buffer->x3 != 0) || (test_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", test_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", test_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", test_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", test_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", test_buffer->x1); + val_print(ERROR, " x2=0x%llx", test_buffer->x2); + val_print(ERROR, " x3=0x%llx", test_buffer->x3); + val_print(ERROR, " x4=0x%llx", test_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi007.c b/test_pool/pfdi/pfdi007.c index 54964aca..7533c4aa 100644 --- a/test_pool/pfdi/pfdi007.c +++ b/test_pool/pfdi/pfdi007.c @@ -74,7 +74,7 @@ static void payload_run(void *arg) g_pfdi_range_status = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_range_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for g_pfdi_range_status Failed", 0); + val_print(ERROR, "\n Allocation for g_pfdi_range_status Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -82,7 +82,7 @@ static void payload_run(void *arg) g_pfdi_all_parts_status = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_all_parts_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for g_pfdi_all_parts_status Failed", 0); + val_print(ERROR, "\n Allocation for g_pfdi_all_parts_status Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details_range; } @@ -102,7 +102,7 @@ static void payload_run(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); goto free_pfdi_details_both; } @@ -120,50 +120,50 @@ static void payload_run(void *arg) /* All-parts validation */ if (pfdi_all_parts_buffer->x0 == PFDI_ACS_SUCCESS) { if (pfdi_all_parts_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n X1 not zero for SUCCESS (all-parts): x1=0x%llx", + val_print(ERROR, "\n X1 not zero for SUCCESS (all-parts): x1=0x%llx", pfdi_all_parts_buffer->x1); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, " on PE %d", i); test_fail++; } } else if (pfdi_all_parts_buffer->x0 == PFDI_ACS_FAULT_FOUND) { /* FAULT_FOUND: x1 contains the faulty test part index (zero is valid) */ if (pfdi_all_parts_buffer->x1 == PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n Fault in test part (all-parts) on PE %d ", i); - val_print(ACS_PRINT_ERR, "cannot be identified", 0); + val_print(ERROR, "\n Fault in test part (all-parts) on PE %d ", i); + val_print(ERROR, "cannot be identified"); } else { - val_print(ACS_PRINT_ERR, "\n Test part %lld (all-parts) ", pfdi_all_parts_buffer->x1); - val_print(ACS_PRINT_ERR, "triggered the fault on PE %d", i); + val_print(ERROR, "\n Test part %lld (all-parts) ", pfdi_all_parts_buffer->x1); + val_print(ERROR, "triggered the fault on PE %d", i); } } else if (pfdi_all_parts_buffer->x0 == PFDI_ACS_ERROR) { if (pfdi_all_parts_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n X1 not zero for ERROR (all-parts): x1=0x%llx", + val_print(ERROR, "\n X1 not zero for ERROR (all-parts): x1=0x%llx", pfdi_all_parts_buffer->x1); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, " on PE %d", i); test_fail++; } - val_print(ACS_PRINT_ERR, "\n All-parts execution failed on PE index %d", i); + val_print(ERROR, "\n All-parts execution failed on PE index %d", i); } else { - val_print(ACS_PRINT_ERR, "\n All-parts run returned unexpected x0 on PE index %d", i); + val_print(ERROR, "\n All-parts run returned unexpected x0 on PE index %d", i); test_fail++; } /* Check X2-X4 are zero for all-parts execution */ if (pfdi_all_parts_buffer->x2 || pfdi_all_parts_buffer->x3 || pfdi_all_parts_buffer->x4) { - val_print(ACS_PRINT_ERR, "\n X2-X4 not zero (all-parts):", 0); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_all_parts_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_all_parts_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_all_parts_buffer->x4); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, "\n X2-X4 not zero (all-parts):"); + val_print(ERROR, " x2=0x%llx", pfdi_all_parts_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_all_parts_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_all_parts_buffer->x4); + val_print(ERROR, " on PE %d", i); test_fail++; } /* Check if test part count acquisition failed on this PE */ if (IS_TEST_FAIL(val_get_status(i))) { - val_print(ACS_PRINT_ERR, "\n Failed to get Test Part count on PE %d ", i); + val_print(ERROR, "\n Failed to get Test Part count on PE %d ", i); test_fail++; continue; } @@ -171,44 +171,44 @@ static void payload_run(void *arg) /* Range validation */ if (pfdi_range_buffer->x0 == PFDI_ACS_SUCCESS) { if (pfdi_range_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n X1 not zero for SUCCESS (range): x1=0x%llx", + val_print(ERROR, "\n X1 not zero for SUCCESS (range): x1=0x%llx", pfdi_range_buffer->x1); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, " on PE %d", i); test_fail++; } } else if (pfdi_range_buffer->x0 == PFDI_ACS_FAULT_FOUND) { /* FAULT_FOUND: x1 contains the faulty test part index (zero is valid) */ if (pfdi_range_buffer->x1 == PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n Fault in test part (range) on PE %d ", i); - val_print(ACS_PRINT_ERR, "cannot be identified", 0); + val_print(ERROR, "\n Fault in test part (range) on PE %d ", i); + val_print(ERROR, "cannot be identified"); } else { - val_print(ACS_PRINT_ERR, "\n Test part %lld (range) ", pfdi_range_buffer->x1); - val_print(ACS_PRINT_ERR, "triggered the fault on PE %d", i); + val_print(ERROR, "\n Test part %lld (range) ", pfdi_range_buffer->x1); + val_print(ERROR, "triggered the fault on PE %d", i); } } else if (pfdi_range_buffer->x0 == PFDI_ACS_ERROR) { if (pfdi_range_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n X1 not zero for ERROR (range): x1=0x%llx", + val_print(ERROR, "\n X1 not zero for ERROR (range): x1=0x%llx", pfdi_range_buffer->x1); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, " on PE %d", i); test_fail++; } - val_print(ACS_PRINT_ERR, "\n Range execution failed to complete on PE %d", i); + val_print(ERROR, "\n Range execution failed to complete on PE %d", i); } else { - val_print(ACS_PRINT_ERR, "\n Range run returned unexpected x0 on PE %d", i); + val_print(ERROR, "\n Range run returned unexpected x0 on PE %d", i); test_fail++; } /* Check X2-X4 are zero for range execution */ if (pfdi_range_buffer->x2 || pfdi_range_buffer->x3 || pfdi_range_buffer->x4) { - val_print(ACS_PRINT_ERR, "\n X2-X4 not zero (range):", 0); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_range_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_range_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_range_buffer->x4); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, "\n X2-X4 not zero (range):"); + val_print(ERROR, " x2=0x%llx", pfdi_range_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_range_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_range_buffer->x4); + val_print(ERROR, " on PE %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi008.c b/test_pool/pfdi/pfdi008.c index f62c368c..e81504a8 100644 --- a/test_pool/pfdi/pfdi008.c +++ b/test_pool/pfdi/pfdi008.c @@ -54,8 +54,8 @@ static void payload_test_results(void *arg) g_pfdi_results_status_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_results_status_details == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Results Function Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Results Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -77,7 +77,7 @@ static void payload_test_results(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -95,49 +95,49 @@ static void payload_test_results(void *arg) if (pfdi_buffer->x0 < PFDI_ACS_SUCCESS) { if (pfdi_buffer->x0 == PFDI_ACS_FAULT_FOUND) { if (pfdi_buffer->x1 == PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n Fault in PFDI test part on PE %d ", i); - val_print(ACS_PRINT_ERR, "cannot be identified", 0); + val_print(ERROR, "\n Fault in PFDI test part on PE %d ", i); + val_print(ERROR, "cannot be identified"); } else { - val_print(ACS_PRINT_ERR, "\n PFDI test part %lld ", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, "triggered the fault on PE %d", i); + val_print(ERROR, "\n PFDI test part %lld ", pfdi_buffer->x1); + val_print(ERROR, "triggered the fault on PE %d", i); } } else if (pfdi_buffer->x0 == PFDI_ACS_ERROR) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI Test parts have executed but failed to complete on PE %d", i); } else if (pfdi_buffer->x0 == PFDI_ACS_NOT_RAN) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI Test parts have not executed power-on tests on PE %d", i); } else { - val_print(ACS_PRINT_ERR, "\n PFDI PE Results function failed err = %lld", + val_print(ERROR, "\n PFDI PE Results function failed err = %lld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, "on PE %d", i); + val_print(ERROR, "on PE %d", i); test_fail++; } } else if (pfdi_buffer->x0 == PFDI_ACS_SUCCESS) { check_x1++; } else { - val_print(ACS_PRINT_ERR, "\n PFDI PE Results function failed err = %lld", + val_print(ERROR, "\n PFDI PE Results function failed err = %lld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, "on PE %d", i); + val_print(ERROR, "on PE %d", i); check_x1++; test_fail++; } if (check_x1) { if (pfdi_buffer->x1 != 0) { - val_print(ACS_PRINT_ERR, "\n Register X1 is not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Register X1 is not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } if ((pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X2-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X2-X4 are not zero:"); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi009.c b/test_pool/pfdi/pfdi009.c index 18d9a80b..4c29ad0c 100644 --- a/test_pool/pfdi/pfdi009.c +++ b/test_pool/pfdi/pfdi009.c @@ -54,8 +54,8 @@ static void payload_fw_check(void *arg) g_pfdi_fw_check_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_fw_check_details == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI FW Check Function Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI FW Check Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -77,7 +77,7 @@ static void payload_fw_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); goto free_pfdi_details; } @@ -92,24 +92,24 @@ static void payload_fw_check(void *arg) test_fail = 0; if (pfdi_buffer->x0 == PFDI_ACS_FAULT_FOUND) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI FW Check fault found status %lld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, "on PE %d", i); + val_print(ERROR, "on PE %d", i); } else if (pfdi_buffer->x0 < PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI FW Check function failed %lld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, "on PE %d", i); + val_print(ERROR, "on PE %d", i); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi010.c b/test_pool/pfdi/pfdi010.c index 242e120e..2bd64d5c 100644 --- a/test_pool/pfdi/pfdi010.c +++ b/test_pool/pfdi/pfdi010.c @@ -54,8 +54,8 @@ static void payload_invalid_fn_check(void *arg) g_pfdi_invalid_fn_check_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_invalid_fn_check_details == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Reserved Function Support Check Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Reserved Function Support Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -77,7 +77,7 @@ static void payload_invalid_fn_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -92,20 +92,20 @@ static void payload_invalid_fn_check(void *arg) run_fail = 0; if (pfdi_buffer->x0 != PFDI_ACS_NOT_SUPPORTED) { - val_print(ACS_PRINT_ERR, "\n PFDI Reserved function support check failed err = %ld", + val_print(ERROR, "\n PFDI Reserved function support check failed err = %ld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, " on PE index = %d", i); + val_print(ERROR, " on PE index = %d", i); run_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); run_fail++; } diff --git a/test_pool/pfdi/pfdi011.c b/test_pool/pfdi/pfdi011.c index 50973090..38a6d553 100644 --- a/test_pool/pfdi/pfdi011.c +++ b/test_pool/pfdi/pfdi011.c @@ -45,9 +45,9 @@ static void payload_regs_preserve_check(void *arg) for (i = 0; i < REG_COUNT_X5_X17; i++) { if (pre_smc_regs[i] != post_smc_regs[i]) { reg_verify_fail++; - val_print(ACS_PRINT_ERR, "\n Reg Verify fail for version X%d ", i + 5); - val_print(ACS_PRINT_ERR, "before 0x%llx ", pre_smc_regs[i]); - val_print(ACS_PRINT_ERR, "after 0x%llx ", post_smc_regs[i]); + val_print(ERROR, "\n Reg Verify fail for version X%d ", i + 5); + val_print(ERROR, "before 0x%llx ", pre_smc_regs[i]); + val_print(ERROR, "after 0x%llx ", post_smc_regs[i]); } } @@ -64,9 +64,9 @@ static void payload_regs_preserve_check(void *arg) for (i = 0; i < REG_COUNT_X5_X17; i++) { if (pre_smc_regs[i] != post_smc_regs[i]) { reg_verify_fail++; - val_print(ACS_PRINT_ERR, "\n Reg Verify fail for PE test ID X%d ", i + 5); - val_print(ACS_PRINT_ERR, "before 0x%llx ", pre_smc_regs[i]); - val_print(ACS_PRINT_ERR, "after 0x%llx ", post_smc_regs[i]); + val_print(ERROR, "\n Reg Verify fail for PE test ID X%d ", i + 5); + val_print(ERROR, "before 0x%llx ", pre_smc_regs[i]); + val_print(ERROR, "after 0x%llx ", post_smc_regs[i]); } } @@ -83,9 +83,9 @@ static void payload_regs_preserve_check(void *arg) for (i = 0; i < REG_COUNT_X5_X17; i++) { if (pre_smc_regs[i] != post_smc_regs[i]) { reg_verify_fail++; - val_print(ACS_PRINT_ERR, "\n Reg Verify fail for Test result X%d ", i + 5); - val_print(ACS_PRINT_ERR, "before 0x%llx ", pre_smc_regs[i]); - val_print(ACS_PRINT_ERR, "after 0x%llx ", post_smc_regs[i]); + val_print(ERROR, "\n Reg Verify fail for Test result X%d ", i + 5); + val_print(ERROR, "before 0x%llx ", pre_smc_regs[i]); + val_print(ERROR, "after 0x%llx ", post_smc_regs[i]); } } diff --git a/test_pool/pfdi/pfdi012.c b/test_pool/pfdi/pfdi012.c index bfba0796..b5c02a4c 100644 --- a/test_pool/pfdi/pfdi012.c +++ b/test_pool/pfdi/pfdi012.c @@ -293,8 +293,8 @@ static void payload_pfdi_error_injection(void *arg) g_pfdi_force_error_check = (pfdi_force_error_check *) val_memory_calloc(num_pe, sizeof(pfdi_force_error_check)); if (g_pfdi_force_error_check == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Force Error Check Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Force Error Check Failed"); val_set_status(index, RESULT_FAIL(test_num, 1)); return; } @@ -318,7 +318,7 @@ static void payload_pfdi_error_injection(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(test_num, 2)); goto free_pfdi_details; } @@ -335,27 +335,27 @@ static void payload_pfdi_error_injection(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->force_err[j]); if (pfdi_buffer->force_err[j].x0 == PFDI_ACS_ERROR) { - val_print(ACS_PRINT_ERR, "\n PFDI Force Error can not be scheduled for %a", + val_print(ERROR, "\n PFDI Force Error can not be scheduled for %a", (uint64_t)pfdi_test_names[j]); - val_print(ACS_PRINT_ERR, " status %ld", pfdi_buffer->force_err[j].x0); - val_print(ACS_PRINT_ERR, " on PE index %d", i); + val_print(ERROR, " status %ld", pfdi_buffer->force_err[j].x0); + val_print(ERROR, " on PE index %d", i); } else if (pfdi_buffer->force_err[j].x0 != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI Force Error failed for %a", + val_print(ERROR, "\n PFDI Force Error failed for %a", (uint64_t)pfdi_test_names[j]); - val_print(ACS_PRINT_ERR, " err %ld", pfdi_buffer->force_err[j].x0); - val_print(ACS_PRINT_ERR, " on PE index %d", i); + val_print(ERROR, " err %ld", pfdi_buffer->force_err[j].x0); + val_print(ERROR, " on PE index %d", i); run_fail++; } if ((pfdi_buffer->force_err[j].x1 != 0) || (pfdi_buffer->force_err[j].x2 != 0) || (pfdi_buffer->force_err[j].x3 != 0) || (pfdi_buffer->force_err[j].x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->force_err[j].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->force_err[j].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->force_err[j].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->force_err[j].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); - val_print(ACS_PRINT_ERR, " for %a", (uint64_t)pfdi_test_names[j]); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->force_err[j].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->force_err[j].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->force_err[j].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->force_err[j].x4); + val_print(ERROR, "\n Failed on PE = %d", i); + val_print(ERROR, " for %a", (uint64_t)pfdi_test_names[j]); run_fail++; } } @@ -383,8 +383,8 @@ static void payload_pfdi_error_recovery_check(void *arg) g_pfdi_err_recovery_check = (pfdi_err_recovery_check *) val_memory_calloc(num_pe, sizeof(pfdi_err_recovery_check)); if (g_pfdi_err_recovery_check == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Error Recovery Check Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Error Recovery Check Failed"); val_set_status(index, RESULT_FAIL(test_num, 2)); return; } @@ -411,7 +411,7 @@ static void payload_pfdi_error_recovery_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(test_num, 2)); goto free_pfdi_error_recovery; } @@ -432,44 +432,44 @@ static void payload_pfdi_error_recovery_check(void *arg) val_data_cache_ops_by_va((addr_t)&rec_buffer->norm_mode_status[j], CLEAN_AND_INVALIDATE); if (rec_buffer->force_err_status[j] != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI Force Error failed for %a", + val_print(ERROR, "\n PFDI Force Error failed for %a", (uint64_t)pfdi_test_names[j]); - val_print(ACS_PRINT_ERR, " err %ld", rec_buffer->force_err_status[j]); - val_print(ACS_PRINT_ERR, " on PE index %d, Skipping the test", i); + val_print(ERROR, " err %ld", rec_buffer->force_err_status[j]); + val_print(ERROR, " on PE index %d, Skipping the test", i); run_skip++; } if (rec_buffer->alt_status[j] == fail_status[j]) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI Scheduled error affected unrelated function, return status %ld", rec_buffer->alt_status[j]); run_fail++; } if (rec_buffer->rec_status[j].x0 != fail_status[j]) { - val_print(ACS_PRINT_ERR, "\n PFDI return %a", (uint64_t)pfdi_test_names[j]); - val_print(ACS_PRINT_ERR, " check failed err %ld", rec_buffer->rec_status[j].x0); - val_print(ACS_PRINT_ERR, " on PE index %d", i); + val_print(ERROR, "\n PFDI return %a", (uint64_t)pfdi_test_names[j]); + val_print(ERROR, " check failed err %ld", rec_buffer->rec_status[j].x0); + val_print(ERROR, " on PE index %d", i); run_fail++; } if (rec_buffer->norm_mode_status[j] == fail_status[j]) { - val_print(ACS_PRINT_ERR, "\n PFDI Error recovery failed for %a", + val_print(ERROR, "\n PFDI Error recovery failed for %a", (uint64_t)pfdi_test_names[j]); - val_print(ACS_PRINT_ERR, " failed err %ld", rec_buffer->norm_mode_status[j]); - val_print(ACS_PRINT_ERR, " on PE index %d", i); + val_print(ERROR, " failed err %ld", rec_buffer->norm_mode_status[j]); + val_print(ERROR, " on PE index %d", i); run_fail++; } if ((rec_buffer->rec_status[j].x1 != 0) || (rec_buffer->rec_status[j].x2 != 0) || (rec_buffer->rec_status[j].x3 != 0) || (rec_buffer->rec_status[j].x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", rec_buffer->rec_status[j].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", rec_buffer->rec_status[j].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", rec_buffer->rec_status[j].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", rec_buffer->rec_status[j].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); - val_print(ACS_PRINT_ERR, " for %a", (uint64_t)pfdi_test_names[j]); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", rec_buffer->rec_status[j].x1); + val_print(ERROR, " x2=0x%llx", rec_buffer->rec_status[j].x2); + val_print(ERROR, " x3=0x%llx", rec_buffer->rec_status[j].x3); + val_print(ERROR, " x4=0x%llx", rec_buffer->rec_status[j].x4); + val_print(ERROR, "\n Failed on PE = %d", i); + val_print(ERROR, " for %a", (uint64_t)pfdi_test_names[j]); run_fail++; } diff --git a/test_pool/pfdi/pfdi013.c b/test_pool/pfdi/pfdi013.c index 193e65e5..76b49878 100644 --- a/test_pool/pfdi/pfdi013.c +++ b/test_pool/pfdi/pfdi013.c @@ -59,7 +59,7 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) g_pfdi_status = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Run Function Failed", 0); + val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -74,7 +74,7 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -92,19 +92,19 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) test_fail = 0; if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Invalid parameter test failed on PE %d", i); - val_print(ACS_PRINT_ERR, " (expected -3, got %ld)", pfdi_buffer->x0); + val_print(ERROR, "\n Invalid parameter test failed on PE %d", i); + val_print(ERROR, " (expected -3, got %ld)", pfdi_buffer->x0); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi014.c b/test_pool/pfdi/pfdi014.c index 353a9dd0..c4d7d1be 100644 --- a/test_pool/pfdi/pfdi014.c +++ b/test_pool/pfdi/pfdi014.c @@ -68,7 +68,7 @@ payload_check_pe_test_run_start_beyond_max(void *arg) g_pfdi_status = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Run Function Failed", 0); + val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -83,7 +83,7 @@ payload_check_pe_test_run_start_beyond_max(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -101,26 +101,26 @@ payload_check_pe_test_run_start_beyond_max(void *arg) test_fail = 0; if (IS_TEST_FAIL(val_get_status(i))) { - val_print(ACS_PRINT_ERR, "\n Failed to get Test Part count on PE %d", i); + val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); val_set_status(i, RESULT_SKIP(TEST_NUM, 1)); continue; } /* Expected result: x0 = -3, x1-x4 = 0 */ if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Invalid parameter response on PE %d", i); - val_print(ACS_PRINT_ERR, " (expected -3, got %ld)", pfdi_buffer->x0); + val_print(ERROR, "\n Invalid parameter response on PE %d", i); + val_print(ERROR, " (expected -3, got %ld)", pfdi_buffer->x0); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi016.c b/test_pool/pfdi/pfdi016.c index cd0565f7..6c71af9f 100644 --- a/test_pool/pfdi/pfdi016.c +++ b/test_pool/pfdi/pfdi016.c @@ -54,8 +54,8 @@ static void payload_invalid_feature_check(void *arg) g_pfdi_invalid_feature_check = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_invalid_feature_check == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Invalid Feature Support Check Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Invalid Feature Support Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -77,7 +77,7 @@ static void payload_invalid_feature_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -92,20 +92,20 @@ static void payload_invalid_feature_check(void *arg) run_fail = 0; if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI Invalid feature support check failed err = %ld", + val_print(ERROR, "\n PFDI Invalid feature support check failed err = %ld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, " on PE index = %d", i); + val_print(ERROR, " on PE index = %d", i); run_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); run_fail++; } diff --git a/test_pool/pfdi/pfdi017.c b/test_pool/pfdi/pfdi017.c index 06d65c91..4f954b3a 100644 --- a/test_pool/pfdi/pfdi017.c +++ b/test_pool/pfdi/pfdi017.c @@ -55,8 +55,8 @@ static void payload_unsupp_fn_check(void *arg) g_pfdi_unsupp_function_check = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_unsupp_function_check == NULL) { - val_print(ACS_PRINT_ERR, - "\n Allocation for PFDI Invalid Feature Support Check Failed", 0); + val_print(ERROR, + "\n Allocation for PFDI Invalid Feature Support Check Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -78,7 +78,7 @@ static void payload_unsupp_fn_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -93,20 +93,20 @@ static void payload_unsupp_fn_check(void *arg) run_fail = 0; if (pfdi_buffer->x0 != PFDI_ACS_NOT_SUPPORTED) { - val_print(ACS_PRINT_ERR, "\n PFDI Unsupported function check failed err = %ld", + val_print(ERROR, "\n PFDI Unsupported function check failed err = %ld", pfdi_buffer->x0); - val_print(ACS_PRINT_ERR, " on PE index = %d", i); + val_print(ERROR, " on PE index = %d", i); run_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, "\n Failed on PE = %d", i); run_fail++; } diff --git a/test_pool/pfdi/pfdi018.c b/test_pool/pfdi/pfdi018.c index 43a4afda..3dec196f 100644 --- a/test_pool/pfdi/pfdi018.c +++ b/test_pool/pfdi/pfdi018.c @@ -68,7 +68,7 @@ payload_check_pe_test_run_end_beyond_max(void *arg) g_pfdi_status = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Run Function Failed", 0); + val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -83,7 +83,7 @@ payload_check_pe_test_run_end_beyond_max(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -101,26 +101,26 @@ payload_check_pe_test_run_end_beyond_max(void *arg) test_fail = 0; if (IS_TEST_FAIL(val_get_status(i))) { - val_print(ACS_PRINT_ERR, "\n Failed to get Test Part count on PE %d", i); + val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); val_set_status(i, RESULT_SKIP(TEST_NUM, 1)); continue; } /* Expected result: x0 = -3, x1-x4 = 0 */ if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Invalid parameter test failed on PE %d", i); - val_print(ACS_PRINT_ERR, " (expected -3, got %ld)", pfdi_buffer->x0); + val_print(ERROR, "\n Invalid parameter test failed on PE %d", i); + val_print(ERROR, " (expected -3, got %ld)", pfdi_buffer->x0); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, " on PE %d", i); + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, " on PE %d", i); test_fail++; } diff --git a/test_pool/pfdi/pfdi019.c b/test_pool/pfdi/pfdi019.c index 07577040..a0c6dc83 100644 --- a/test_pool/pfdi/pfdi019.c +++ b/test_pool/pfdi/pfdi019.c @@ -67,7 +67,7 @@ payload_check_pe_test_run_either_minus_one(void *arg) g_pfdi_status = (PFDI_RET_PARAMS *) val_memory_calloc(2 * num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Run Function Failed", 0); + val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -82,7 +82,7 @@ payload_check_pe_test_run_either_minus_one(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -100,23 +100,23 @@ payload_check_pe_test_run_either_minus_one(void *arg) val_pfdi_invalidate_ret_params(pfdi_buffer); if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Invalid param test failed on PE: %d", i); - val_print(ACS_PRINT_ERR, " when %a", + val_print(ERROR, "\n Invalid param test failed on PE: %d", i); + val_print(ERROR, " when %a", (uint64_t)(j == 0 ? "Start is -1 but End is not -1" : "End is -1 but Start is not -1")); - val_print(ACS_PRINT_ERR, " (expected -3, got %ld)", pfdi_buffer->x0); + val_print(ERROR, " (expected -3, got %ld)", pfdi_buffer->x0); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, " on PE %d", i); - val_print(ACS_PRINT_ERR, " when %a", + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, " on PE %d", i); + val_print(ERROR, " when %a", (uint64_t)(j == 0 ? "Start is -1 but End is not -1" : "End is -1 but Start is not -1")); test_fail++; diff --git a/test_pool/pfdi/pfdi020.c b/test_pool/pfdi/pfdi020.c index d32fc4a9..7c0a29f8 100644 --- a/test_pool/pfdi/pfdi020.c +++ b/test_pool/pfdi/pfdi020.c @@ -78,7 +78,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) g_pfdi_status = (PFDI_RET_PARAMS *) val_memory_calloc(2 * num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Run Function Failed", 0); + val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -93,7 +93,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -107,7 +107,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) test_fail = 0; if (IS_TEST_FAIL(val_get_status(i))) { - val_print(ACS_PRINT_ERR, "\n Failed to get Test Part count on PE %d", i); + val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); continue; } @@ -118,23 +118,23 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) val_pfdi_invalidate_ret_params(pfdi_buffer); if (pfdi_buffer->x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n Invalid param test failed on PE: %d", i); - val_print(ACS_PRINT_ERR, " when %a", + val_print(ERROR, "\n Invalid param test failed on PE: %d", i); + val_print(ERROR, " when %a", (uint64_t)(j == 0 ? "Start is less than -1" : "End is less than -1")); - val_print(ACS_PRINT_ERR, " (expected -3, got %ld)", pfdi_buffer->x0); + val_print(ERROR, " (expected -3, got %ld)", pfdi_buffer->x0); test_fail++; } if ((pfdi_buffer->x1 != 0) || (pfdi_buffer->x2 != 0) || (pfdi_buffer->x3 != 0) || (pfdi_buffer->x4 != 0)) { - val_print(ACS_PRINT_ERR, "\n Registers X1-X4 are not zero:", 0); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->x4); - val_print(ACS_PRINT_ERR, " on PE %d", i); - val_print(ACS_PRINT_ERR, " when %a", + val_print(ERROR, "\n Registers X1-X4 are not zero:"); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->x4); + val_print(ERROR, " on PE %d", i); + val_print(ERROR, " when %a", (uint64_t)(j == 0 ? "Start is less than -1" : "End is less than -1")); test_fail++; diff --git a/test_pool/pfdi/pfdi021.c b/test_pool/pfdi/pfdi021.c index d28bd927..6048c2fa 100644 --- a/test_pool/pfdi/pfdi021.c +++ b/test_pool/pfdi/pfdi021.c @@ -84,7 +84,7 @@ static void payload_invalid_pe_version_check(void *arg) g_pfdi_invalid_version = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_version == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Version Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Version Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -108,7 +108,7 @@ static void payload_invalid_pe_version_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -126,22 +126,22 @@ static void payload_invalid_pe_version_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI version with invalid x%d", inval_case + 1); - val_print(ACS_PRINT_ERR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 1); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi022.c b/test_pool/pfdi/pfdi022.c index be859396..904ec569 100644 --- a/test_pool/pfdi/pfdi022.c +++ b/test_pool/pfdi/pfdi022.c @@ -78,7 +78,7 @@ static void payload_invalid_pe_feature_check(void *arg) g_pfdi_invalid_feature = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_feature == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Feature Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Feature Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -102,7 +102,7 @@ static void payload_invalid_pe_feature_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -120,21 +120,21 @@ static void payload_invalid_pe_feature_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI feature with invalid x%d", inval_case + 2); - val_print(ACS_PRINT_ERR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "\n PFDI feature with invalid x%d", inval_case + 2); + val_print(ERROR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 2); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi023.c b/test_pool/pfdi/pfdi023.c index d66ac66e..7665f4f7 100644 --- a/test_pool/pfdi/pfdi023.c +++ b/test_pool/pfdi/pfdi023.c @@ -84,7 +84,7 @@ static void payload_invalid_pe_test_id_check(void *arg) g_pfdi_invalid_pe_test_id = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_pe_test_id == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid PE Test ID Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid PE Test ID Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -108,7 +108,7 @@ static void payload_invalid_pe_test_id_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -126,22 +126,22 @@ static void payload_invalid_pe_test_id_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI PE Test ID with invalid x%d", inval_case + 1); - val_print(ACS_PRINT_ERR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 1); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi024.c b/test_pool/pfdi/pfdi024.c index 14d168c8..f3878c54 100644 --- a/test_pool/pfdi/pfdi024.c +++ b/test_pool/pfdi/pfdi024.c @@ -84,7 +84,7 @@ static void payload_invalid_pe_test_part_count_check(void *arg) g_pfdi_invalid_test_part_count = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_test_part_count == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Test Part Count Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Test Part Count Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -108,7 +108,7 @@ static void payload_invalid_pe_test_part_count_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -126,22 +126,22 @@ static void payload_invalid_pe_test_part_count_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI Test Part Count with invalid x%d", inval_case + 1); - val_print(ACS_PRINT_ERR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 1); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi025.c b/test_pool/pfdi/pfdi025.c index 3313d00d..123be870 100644 --- a/test_pool/pfdi/pfdi025.c +++ b/test_pool/pfdi/pfdi025.c @@ -84,7 +84,7 @@ static void payload_invalid_pe_test_result_check(void *arg) g_pfdi_invalid_test_result = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_test_result == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Test Result Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Test Result Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -108,7 +108,7 @@ static void payload_invalid_pe_test_result_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -126,22 +126,22 @@ static void payload_invalid_pe_test_result_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI test_result with invalid x%d", inval_case + 1); - val_print(ACS_PRINT_ERR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 1); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi026.c b/test_pool/pfdi/pfdi026.c index 46dcdd07..170bc81a 100644 --- a/test_pool/pfdi/pfdi026.c +++ b/test_pool/pfdi/pfdi026.c @@ -84,7 +84,7 @@ static void payload_invalid_pe_fw_check(void *arg) g_pfdi_invalid_fw_check = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_fw_check == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Firmware Check Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Firmware Check Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -108,7 +108,7 @@ static void payload_invalid_pe_fw_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -126,22 +126,22 @@ static void payload_invalid_pe_fw_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n PFDI fw_check with invalid x%d", inval_case + 1); - val_print(ACS_PRINT_ERR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, " param failed %ld, ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 1); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi027.c b/test_pool/pfdi/pfdi027.c index 3cf57632..43e19501 100644 --- a/test_pool/pfdi/pfdi027.c +++ b/test_pool/pfdi/pfdi027.c @@ -153,7 +153,7 @@ payload_check_error_overwrite(void *arg) g_results = (pfdi_error_injection_results *) val_memory_calloc(num_pe * PFDI_FN_MAX_IDX, sizeof(pfdi_error_injection_results)); if (g_results == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for results Failed", 0); + val_print(ERROR, "\n Allocation for results Failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -170,7 +170,7 @@ payload_check_error_overwrite(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_results; } @@ -190,45 +190,45 @@ payload_check_error_overwrite(void *arg) /* Validate first FORCE_ERROR call status */ if (result->first_error_x0 == PFDI_ACS_ERROR) { - val_print(ACS_PRINT_WARN, "\n FORCE_ERROR first %a error; skipping checks", + val_print(WARN, "\n FORCE_ERROR first %a error; skipping checks", (uint64_t)pfdi_fn_names[j]); - val_print(ACS_PRINT_WARN, " on PE index %d", i); + val_print(WARN, " on PE index %d", i); test_skip++; continue; } if (result->first_error_x0 != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI force_error %a ", (uint64_t)pfdi_fn_names[j]); - val_print(ACS_PRINT_ERR, "first injection failed err %ld ", + val_print(ERROR, "\n PFDI force_error %a ", (uint64_t)pfdi_fn_names[j]); + val_print(ERROR, "first injection failed err %ld ", (int64_t)result->first_error_x0); - val_print(ACS_PRINT_ERR, "on PE index %d", i); + val_print(ERROR, "on PE index %d", i); test_fail++; } /* Validate second FORCE_ERROR call status */ if (result->second_error_x0 == PFDI_ACS_ERROR) { - val_print(ACS_PRINT_WARN, "\n FORCE_ERROR second %a error; skipping checks", + val_print(WARN, "\n FORCE_ERROR second %a error; skipping checks", (uint64_t)pfdi_fn_names[j]); - val_print(ACS_PRINT_WARN, " on PE index %d", i); + val_print(WARN, " on PE index %d", i); test_skip++; continue; } if (result->second_error_x0 != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI force_error %a ", (uint64_t)pfdi_fn_names[j]); - val_print(ACS_PRINT_ERR, "second injection failed err %ld ", + val_print(ERROR, "\n PFDI force_error %a ", (uint64_t)pfdi_fn_names[j]); + val_print(ERROR, "second injection failed err %ld ", (int64_t)result->second_error_x0); - val_print(ACS_PRINT_ERR, "on PE index %d", i); + val_print(ERROR, "on PE index %d", i); test_fail++; } /* Validate first call returns second injected error (overwrite behavior) */ if (result->first_call_x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI return %a ", (uint64_t)pfdi_fn_names[j]); - val_print(ACS_PRINT_ERR, "overwrite check failed err %ld ", + val_print(ERROR, "\n PFDI return %a ", (uint64_t)pfdi_fn_names[j]); + val_print(ERROR, "overwrite check failed err %ld ", (int64_t)result->first_call_x0); - val_print(ACS_PRINT_ERR, "expected %ld ", (int64_t)PFDI_ACS_INVALID_PARAMETERS); - val_print(ACS_PRINT_ERR, "on PE index %d", i); + val_print(ERROR, "expected %ld ", (int64_t)PFDI_ACS_INVALID_PARAMETERS); + val_print(ERROR, "on PE index %d", i); if (result->first_call_x0 == PFDI_ACS_NOT_SUPPORTED) - val_print(ACS_PRINT_ERR, " (second error did not overwrite first)", 0); + val_print(ERROR, " (second error did not overwrite first)"); test_fail++; } } diff --git a/test_pool/pfdi/pfdi028.c b/test_pool/pfdi/pfdi028.c index 1e6e164e..f112e14d 100644 --- a/test_pool/pfdi/pfdi028.c +++ b/test_pool/pfdi/pfdi028.c @@ -149,7 +149,7 @@ payload_check_pe_locality(void *arg) pfdi_fun_status *same_first; if (num_pe < 2) { - val_print(ACS_PRINT_WARN, "\n Test requires minimum 2 PEs, skipping", 0); + val_print(WARN, "\n Test requires minimum 2 PEs, skipping"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -159,7 +159,7 @@ payload_check_pe_locality(void *arg) g_pfdi_pe_locality_check = (pfdi_pe_locality_check *) val_memory_calloc(1, sizeof(pfdi_pe_locality_check)); if (g_pfdi_pe_locality_check == NULL) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed", 0); + val_print(ERROR, "\n Memory allocation failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -186,7 +186,7 @@ payload_check_pe_locality(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(other_pe_index)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** waiting for other PE index = %d", + val_print(ERROR, "\n **Timed out** waiting for other PE index = %d", other_pe_index); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); goto free_locality_buffer; @@ -208,35 +208,35 @@ payload_check_pe_locality(void *arg) idx = i; if (err->x0[idx] == PFDI_ACS_ERROR) { - val_print(ACS_PRINT_WARN, "\n FORCE_ERROR %a error; skipping checks", + val_print(WARN, "\n FORCE_ERROR %a error; skipping checks", (uint64_t)pfdi_fn_names[idx]); - val_print(ACS_PRINT_WARN, " on PE index %d", index); + val_print(WARN, " on PE index %d", index); test_skip++; continue; } if (err->x0[idx] != PFDI_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PFDI Force Error failed for %a", + val_print(ERROR, "\n PFDI Force Error failed for %a", (uint64_t)pfdi_fn_names[idx]); - val_print(ACS_PRINT_ERR, " x0=%ld", err->x0[idx]); - val_print(ACS_PRINT_ERR, " on PE index %d", index); + val_print(ERROR, " x0=%ld", err->x0[idx]); + val_print(ERROR, " on PE index %d", index); test_fail++; continue; } if (cross_pe->x0[idx] == PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n Other PE saw injected error for %a", + val_print(ERROR, "\n Other PE saw injected error for %a", (uint64_t)pfdi_fn_names[idx]); - val_print(ACS_PRINT_ERR, " x0=%ld", cross_pe->x0[idx]); - val_print(ACS_PRINT_ERR, " on PE index %d", other_pe_index); + val_print(ERROR, " x0=%ld", cross_pe->x0[idx]); + val_print(ERROR, " on PE index %d", other_pe_index); test_fail++; } if (same_first->x0[idx] != PFDI_ACS_UNKNOWN) { - val_print(ACS_PRINT_ERR, "\n Calling PE did not see injected error for %a", + val_print(ERROR, "\n Calling PE did not see injected error for %a", (uint64_t)pfdi_fn_names[idx]); - val_print(ACS_PRINT_ERR, " x0=%ld", same_first->x0[idx]); - val_print(ACS_PRINT_ERR, " on PE index %d", index); + val_print(ERROR, " x0=%ld", same_first->x0[idx]); + val_print(ERROR, " on PE index %d", index); test_fail++; } diff --git a/test_pool/pfdi/pfdi029.c b/test_pool/pfdi/pfdi029.c index 8d61e8bd..bbddb520 100644 --- a/test_pool/pfdi/pfdi029.c +++ b/test_pool/pfdi/pfdi029.c @@ -74,7 +74,7 @@ static void payload_invalid_run_check(void *arg) g_pfdi_invalid_run = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_run == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Test Run Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Test Run Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -98,7 +98,7 @@ static void payload_invalid_run_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -116,21 +116,21 @@ static void payload_invalid_run_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI test run with invalid x%d", inval_case + 2); - val_print(ACS_PRINT_ERR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "\n PFDI test run with invalid x%d", inval_case + 2); + val_print(ERROR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 2); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi030.c b/test_pool/pfdi/pfdi030.c index 1708e3ff..350b9951 100644 --- a/test_pool/pfdi/pfdi030.c +++ b/test_pool/pfdi/pfdi030.c @@ -74,7 +74,7 @@ static void payload_invalid_force_error_check(void *arg) g_pfdi_invalid_force_error = (PFDI_INVAL_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_force_error == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Force Error Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Force Error Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -98,7 +98,7 @@ static void payload_invalid_force_error_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -116,21 +116,21 @@ static void payload_invalid_force_error_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI force_error with invalid x%d", inval_case + 2); - val_print(ACS_PRINT_ERR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "\n PFDI force_error with invalid x%d", inval_case + 2); + val_print(ERROR, " param failed %ld ", pfdi_buffer->inval[inval_case].x0); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for x%d invalid case:", inval_case + 2); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pfdi/pfdi031.c b/test_pool/pfdi/pfdi031.c index 4e9c47d7..05c457ed 100644 --- a/test_pool/pfdi/pfdi031.c +++ b/test_pool/pfdi/pfdi031.c @@ -70,7 +70,7 @@ static void payload_force_error_invalid_fn_check(void *arg) g_pfdi_force_error_invalid_fn = (PFDI_INVAL_FUNC_RETURNS *) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_FUNC_RETURNS)); if (g_pfdi_force_error_invalid_fn == NULL) { - val_print(ACS_PRINT_ERR, "\n Allocation for PFDI Invalid Force Error Failed \n", 0); + val_print(ERROR, "\n Allocation for PFDI Invalid Force Error Failed \n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -94,7 +94,7 @@ static void payload_force_error_invalid_fn_check(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); + val_print(ERROR, "\n **Timed out** for PE index = %d", i); val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); goto free_pfdi_details; } @@ -112,24 +112,24 @@ static void payload_force_error_invalid_fn_check(void *arg) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[inval_case]); if (pfdi_buffer->inval[inval_case].x0 != PFDI_ACS_INVALID_PARAMETERS) { - val_print(ACS_PRINT_ERR, "\n PFDI force_error with invalid %a", + val_print(ERROR, "\n PFDI force_error with invalid %a", (inval_case == 0) ? (uint64_t)"RESERVED" : (uint64_t)"INVALID"); - val_print(ACS_PRINT_ERR, " function ID failed status %ld ", + val_print(ERROR, " function ID failed status %ld ", pfdi_buffer->inval[inval_case].x0); - val_print(ACS_PRINT_ERR, "on PE = %d", i); + val_print(ERROR, "on PE = %d", i); test_fail++; } if ((pfdi_buffer->inval[inval_case].x1 != 0) || (pfdi_buffer->inval[inval_case].x2 != 0) || (pfdi_buffer->inval[inval_case].x3 != 0) || (pfdi_buffer->inval[inval_case].x4 != 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Registers X1-X4 are not zero for %a function ID:", (inval_case == 0) ? (uint64_t)"RESERVED" : (uint64_t)"INVALID"); - val_print(ACS_PRINT_ERR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); - val_print(ACS_PRINT_ERR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); - val_print(ACS_PRINT_ERR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); - val_print(ACS_PRINT_ERR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); - val_print(ACS_PRINT_ERR, "\n Failed on PE = %d", i); + val_print(ERROR, " x1=0x%llx", pfdi_buffer->inval[inval_case].x1); + val_print(ERROR, " x2=0x%llx", pfdi_buffer->inval[inval_case].x2); + val_print(ERROR, " x3=0x%llx", pfdi_buffer->inval[inval_case].x3); + val_print(ERROR, " x4=0x%llx", pfdi_buffer->inval[inval_case].x4); + val_print(ERROR, "\n Failed on PE = %d", i); test_fail++; } } diff --git a/test_pool/pmu/pmu001.c b/test_pool/pmu/pmu001.c index 5b5715c4..5fb1a841 100644 --- a/test_pool/pmu/pmu001.c +++ b/test_pool/pmu/pmu001.c @@ -50,7 +50,7 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ val_pe_reg_write(PMOVSCLR_EL0, 0x1); - val_print(ACS_PRINT_INFO, "\n Received PMUIRQ ", 0); + val_print(TRACE, "\n Received PMUIRQ "); val_set_status(index, RESULT_PASS(TEST_NUM, 01)); val_gic_end_of_interrupt(int_id); @@ -70,7 +70,7 @@ payload() if (int_id != 23) { timeout = 0; - val_print(ACS_PRINT_ERR, "\n Incorrect PPI value %d ", int_id); + val_print(ERROR, "\n Incorrect PPI value %d ", int_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } diff --git a/test_pool/pmu/pmu004.c b/test_pool/pmu/pmu004.c index 79a9ccca..ccc88694 100644 --- a/test_pool/pmu/pmu004.c +++ b/test_pool/pmu/pmu004.c @@ -172,24 +172,22 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE min_monitor_cnt = PMU_SYS_2_MON_COUNT; event_ptr = scenario_2_events; } else { - val_print(ACS_PRINT_ERR, "\n Undefined scenario passed to sys_pmu_test_scenario ()", - 0); + val_print(ERROR, "\n Undefined scenario passed to sys_pmu_test_scenario ()"); return TEST_FAIL; } /* Validate node_type passed */ if (node_type != PMU_NODE_MEM_CNTR && node_type != PMU_NODE_PCIE_RC) { - val_print(ACS_PRINT_ERR, "\n Invalid node_type passed to sys_pmu_test_scenario ()", - 0); + val_print(ERROR, "\n Invalid node_type passed to sys_pmu_test_scenario ()"); return TEST_FAIL; } /* Get PMU node index corresponding to the node instance primary */ node_index = val_pmu_get_node_index(node_primary_instance, node_type); if (node_index == PMU_INVALID_INDEX) { - val_print(ACS_PRINT_ERR, "\n Node primary instance : 0x%lx ", + val_print(ERROR, "\n Node primary instance : 0x%lx ", node_primary_instance); - val_print(ACS_PRINT_ERR, "\n Node type : 0x%x has no PMU associated with it", + val_print(ERROR, "\n Node type : 0x%x has no PMU associated with it", (uint32_t)node_type); return TEST_FAIL; } @@ -197,7 +195,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE /* Based on scenario to run check if minimum event counters are met*/ data = val_pmu_get_monitor_count(node_index); if (data < min_monitor_cnt) { - val_print(ACS_PRINT_ERR, "\n PMU node must support atleast %d counter for " + val_print(ERROR, "\n PMU node must support atleast %d counter for " "\n measuring current scenario ", min_monitor_cnt); return TEST_FAIL; } @@ -209,7 +207,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE addr_len = val_srat_get_info(SRAT_MEM_ADDR_LEN, node_primary_instance); if ((base_addr == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * BUFFER_SIZE)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid base address for proximity domain : 0x%lx", node_primary_instance); return TEST_FAIL; @@ -220,7 +218,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE if (num_ecam == 0) { /* If APMT has PCIE RC entry we shouldn't have entered this if(), if we did, something's wrong with system information */ - val_print(ACS_PRINT_ERR, "\n No ECAMs reported by system", 0); + val_print(ERROR, "\n No ECAMs reported by system"); return TEST_FAIL; } } @@ -230,9 +228,9 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE for (i = 0; i < min_monitor_cnt; i++) { status = val_pmu_configure_monitor(node_index, event_ptr[i], i); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Required PMU Event 0x%x not supported", event_ptr[i]); - val_print(ACS_PRINT_ERR, " at node %d", node_index); + val_print(ERROR, " at node %d", node_index); return TEST_FAIL; } } @@ -245,7 +243,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE if (node_type == PMU_NODE_MEM_CNTR) { status = generate_mem_traffic(base_addr, BUFFER_SIZE / 2); if (status) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed", node_index); + val_print(ERROR, "\n Memory allocation failed", node_index); val_pmu_disable_all_monitors(node_index); return TEST_FAIL; } @@ -268,7 +266,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE if (node_type == PMU_NODE_MEM_CNTR) { status = generate_mem_traffic(base_addr, BUFFER_SIZE); if (status) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed", node_index); + val_print(ERROR, "\n Memory allocation failed", node_index); val_pmu_disable_all_monitors(node_index); return TEST_FAIL; } @@ -286,7 +284,7 @@ test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE for (i = 0; i < min_monitor_cnt ; i++) { /* Check for FAIL */ if (monitor_data[i].t1_value > monitor_data[i].t2_value) { - val_print(ACS_PRINT_ERR, "\n Monitors didn't move in expected proportions" + val_print(ERROR, "\n Monitors didn't move in expected proportions" " for PMU node index: 0x%x", node_index); /* Disable PMU monitors */ @@ -328,7 +326,7 @@ static void payload_check_sys_pmu_scenario(void *arg) /* Get number of memory ranges from SRAT table */ num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_print(ERROR, "\n No Proximity domains in the system"); val_set_status(index, RESULT_FAIL(test_data->test_num, 02)); return; } @@ -339,7 +337,7 @@ static void payload_check_sys_pmu_scenario(void *arg) /* Get proximity domain mapped to the memory range */ mc_prox_domain = val_srat_get_prox_domain(mem_range_index); if (mc_prox_domain == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n Proximity domain not found", 0); + val_print(ERROR, "\n Proximity domain not found"); fail_cnt++; continue; } @@ -368,7 +366,7 @@ static void payload_check_sys_pmu_scenario(void *arg) } if (!run_flag) { - val_print(ACS_PRINT_ERR, "\n No PMU associated with PCIe interface", 0); + val_print(ERROR, "\n No PMU associated with PCIe interface"); val_set_status(index, RESULT_FAIL(test_data->test_num, 03)); return; } diff --git a/test_pool/pmu/pmu005.c b/test_pool/pmu/pmu005.c index 9675ede5..ed70fb20 100644 --- a/test_pool/pmu/pmu005.c +++ b/test_pool/pmu/pmu005.c @@ -77,8 +77,8 @@ test_status_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_eve /* Get PMU node index corresponding to the node instance primary */ node_index = val_pmu_get_node_index(node_primary_instance, node_type); if (node_index == PMU_INVALID_INDEX) { - val_print(ACS_PRINT_ERR, "\n Node primary instance : 0x%lx ", node_primary_instance); - val_print(ACS_PRINT_ERR, "\n Node type : 0x%x has no PMU associated with it", + val_print(ERROR, "\n Node primary instance : 0x%lx ", node_primary_instance); + val_print(ERROR, "\n Node type : 0x%x has no PMU associated with it", (uint32_t)node_type); return TEST_FAIL; } @@ -86,8 +86,8 @@ test_status_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_eve /* Based on scenario to run check if minimum event counters are met*/ num_counters = val_pmu_get_monitor_count(node_index); if (num_counters <= 0) { - val_print(ACS_PRINT_ERR, "\n PMU node must support atleast one counter." - , 0); + val_print(ERROR, "\n PMU node must support atleast one counter." + ); return TEST_FAIL; } @@ -103,15 +103,15 @@ test_status_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_eve if (val_pmu_configure_monitor(node_index, event_list[event_idx], counter) == 0) { event_supported[event_idx] = 1; - val_print(ACS_PRINT_DEBUG, "\n Counter : %d ", counter); - val_print(ACS_PRINT_DEBUG, "Supports event ID :%d", event_list[event_idx]); + val_print(DEBUG, "\n Counter : %d ", counter); + val_print(DEBUG, "Supports event ID :%d", event_list[event_idx]); } } } for (event_idx = 0; event_idx < num_events; event_idx++) { if (!event_supported[event_idx]) { - val_print(ACS_PRINT_DEBUG, "\n Missing support for event ID %d", + val_print(DEBUG, "\n Missing support for event ID %d", event_list[event_idx]); return TEST_FAIL; } @@ -142,7 +142,7 @@ static void payload_check_pmu_monitors(void *arg) /* Get number of memory ranges from SRAT table */ num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_print(ERROR, "\n No Proximity domains in the system"); val_set_status(index, RESULT_FAIL(test_data->test_num, 02)); return; } @@ -181,13 +181,13 @@ static void payload_check_pmu_monitors(void *arg) } } } else { - val_print(ACS_PRINT_ERR, "\n Invalid interface type passed to check_monitors()", 0); + val_print(ERROR, "\n Invalid interface type passed to check_monitors()"); val_set_status(index, RESULT_FAIL(test_data->test_num, 03)); return; } if (!run_flag) { - val_print(ACS_PRINT_ERR, "\n No PMU associated with PCIe interface", 0); + val_print(ERROR, "\n No PMU associated with PCIe interface"); val_set_status(index, RESULT_FAIL(test_data->test_num, 04)); return; } diff --git a/test_pool/pmu/pmu008.c b/test_pool/pmu/pmu008.c index 89a4b225..29202713 100644 --- a/test_pool/pmu/pmu008.c +++ b/test_pool/pmu/pmu008.c @@ -64,7 +64,7 @@ static uint32_t generate_traffic(uint64_t prox_domain, uint32_t size, void (*rem addr_len = val_srat_get_info(SRAT_MEM_ADDR_LEN, prox_domain); if ((prox_base_addr == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * BUFFER_SIZE)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid base address for proximity domain : 0x%lx", prox_domain); return 1; @@ -114,15 +114,15 @@ static void payload(void) node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); - val_print(ACS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + val_print(DEBUG, "\n PMU NODES = %d", node_count); if (node_count == 0) { val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); - val_print(ACS_PRINT_TEST, "\n No PMU nodes found in APMT table", 0); - val_print(ACS_PRINT_TEST, "\n The test must be considered fail" - " if system has CoreSight PMU", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); + val_print(INFO, "\n No PMU nodes found in APMT table"); + val_print(INFO, "\n The test must be considered fail" + " if system has CoreSight PMU"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); return; } @@ -132,16 +132,16 @@ static void payload(void) } if (cs_com != 0x1) { val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); - val_print(ACS_PRINT_TEST, "\n No CoreSight PMU nodes found", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); + val_print(INFO, "\n No CoreSight PMU nodes found"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); return; } /*Get number of memory ranges from SRAT table */ num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_print(ERROR, "\n No Proximity domains in the system"); val_set_status(index, RESULT_WARN(TEST_NUM, 2)); return; } @@ -150,14 +150,14 @@ static void payload(void) pe_uid = val_pe_get_uid(index); pe_prox_domain = val_srat_get_info(SRAT_GICC_PROX_DOMAIN, pe_uid); if (pe_prox_domain == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n Could not get proximity domain info for given PE", 0); + val_print(ERROR, "\n Could not get proximity domain info for given PE"); val_set_status(index, RESULT_WARN(TEST_NUM, 3)); return; } /* Get memory controller local to the primary PE */ mc_node_index = val_pmu_get_node_index(pe_prox_domain, PMU_NODE_MEM_CNTR); if (mc_node_index == PMU_INVALID_INDEX) { - val_print(ACS_PRINT_ERR, "\n PMU node not found", 0); + val_print(ERROR, "\n PMU node not found"); val_set_status(index, RESULT_WARN(TEST_NUM, 4)); return; } @@ -165,7 +165,7 @@ static void payload(void) /* Check if the PMU supports atleast 3 counters */ data = val_pmu_get_monitor_count(mc_node_index); if (data < 3) { - val_print(ACS_PRINT_ERR, "\n PMU node must support atleast 3 counter", 0); + val_print(ERROR, "\n PMU node must support atleast 3 counter"); val_set_status(index, RESULT_WARN(TEST_NUM, 5)); return; } @@ -174,9 +174,9 @@ static void payload(void) for (i = 0; i < NUM_PMU_MON; i++) { status = val_pmu_configure_monitor(mc_node_index, config_events[i], i); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Required PMU Event 0x%x not supported", config_events[i]); - val_print(ACS_PRINT_ERR, " at node %d", mc_node_index); + val_print(ERROR, " at node %d", mc_node_index); val_set_status(index, RESULT_WARN(TEST_NUM, 6)); return; } @@ -189,7 +189,7 @@ static void payload(void) /* Get remote PE details */ remote_pe_prox_domain = val_srat_get_info(SRAT_GICC_REMOTE_PROX_DOMAIN, pe_prox_domain); if (remote_pe_prox_domain == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n Could not get remote PE proximity domain", 0); + val_print(ERROR, "\n Could not get remote PE proximity domain"); val_set_status(index, RESULT_WARN(TEST_NUM, 7)); return; } @@ -202,7 +202,7 @@ static void payload(void) /* Generate remote and local traffic for 2 MB */ status = generate_traffic(pe_prox_domain, BUFFER_SIZE / 2, payload1); if (status) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed", 0); + val_print(ERROR, "\n Memory allocation failed"); val_set_status(index, RESULT_WARN(TEST_NUM, 8)); return; } @@ -221,7 +221,7 @@ static void payload(void) status = generate_traffic(pe_prox_domain, BUFFER_SIZE, payload2); if (status) { - val_print(ACS_PRINT_ERR, "\n Memory allocation failed", 0); + val_print(ERROR, "\n Memory allocation failed"); val_set_status(index, RESULT_WARN(TEST_NUM, 9)); return; } diff --git a/test_pool/pmu/pmu009.c b/test_pool/pmu/pmu009.c index 32975a49..c0cceccc 100644 --- a/test_pool/pmu/pmu009.c +++ b/test_pool/pmu/pmu009.c @@ -45,15 +45,15 @@ static void payload(void) pmu_node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); - val_print(ACS_PRINT_DEBUG, "\n PMU NODES = %d", pmu_node_count); + val_print(DEBUG, "\n PMU NODES = %d", pmu_node_count); if (pmu_node_count == 0) { val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); - val_print(ACS_PRINT_TEST, "\n No PMU nodes found in APMT table", 0); - val_print(ACS_PRINT_TEST, "\n The test must be considered fail" - " if system has CoreSight PMU", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); + val_print(INFO, "\n No PMU nodes found in APMT table"); + val_print(INFO, "\n The test must be considered fail" + " if system has CoreSight PMU"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); return; } @@ -63,9 +63,9 @@ static void payload(void) } if (cs_com != 0x1) { val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); - val_print(ACS_PRINT_TEST, "\n No CoreSight PMU nodes found", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); + val_print(INFO, "\n No CoreSight PMU nodes found"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); return; } @@ -88,7 +88,7 @@ static void payload(void) /* Get number of monitor to the interface pmu node */ num_mon = val_pmu_get_monitor_count(pmu_node_index); if (num_mon == 0) { - val_print(ACS_PRINT_ERR, "\n PMU node must support atleast 1 counter", 0); + val_print(ERROR, "\n PMU node must support atleast 1 counter"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; } @@ -101,9 +101,9 @@ static void payload(void) status = val_pmu_configure_monitor(pmu_node_index, config_events[i], mon_index); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Required PMU Event 0x%x not supported", config_events[i]); - val_print(ACS_PRINT_ERR, " at node %d", pmu_node_index); + val_print(ERROR, " at node %d", pmu_node_index); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); return; } @@ -116,7 +116,7 @@ static void payload(void) val_set_status(index, RESULT_WARN(TEST_NUM, 2)); return; } else if (ret_status) { - val_print(ACS_PRINT_ERR, "\n workload generate function failed", 0); + val_print(ERROR, "\n workload generate function failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); return; } @@ -129,7 +129,7 @@ static void payload(void) val_set_status(index, RESULT_WARN(TEST_NUM, 3)); return; } else if (ret_status) { - val_print(ACS_PRINT_ERR, "\n count value not as expected", 0); + val_print(ERROR, "\n count value not as expected"); val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); return; } diff --git a/test_pool/power_wakeup/u001.c b/test_pool/power_wakeup/u001.c index 7cd426b5..8647e4ab 100644 --- a/test_pool/power_wakeup/u001.c +++ b/test_pool/power_wakeup/u001.c @@ -35,7 +35,7 @@ isr1() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_INFO, " Received EL1 PHY interrupt\n", 0); + val_print(TRACE, " Received EL1 PHY interrupt\n"); g_el1phy_int_received = 1; val_set_status(index, RESULT_PASS(TEST_NUM, 1)); intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); @@ -53,7 +53,7 @@ payload1() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); if (val_gic_install_isr(intid, isr1)) { - val_print(ACS_PRINT_WARN, "\n GIC Install Handler Failed...", 0); + val_print(WARN, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -82,10 +82,10 @@ payload1() val_timer_set_phy_el1(0); intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); - val_print(ACS_PRINT_DEBUG, "\n PE wakeup by some other events/int", 0); + val_print(DEBUG, "\n PE wakeup by some other events/int"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); } - val_print(ACS_PRINT_INFO, "\n delay loop remainig value %d", delay_loop); + val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; } diff --git a/test_pool/power_wakeup/u002.c b/test_pool/power_wakeup/u002.c index bf13e540..3841563a 100644 --- a/test_pool/power_wakeup/u002.c +++ b/test_pool/power_wakeup/u002.c @@ -37,7 +37,7 @@ isr_failsafe() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_ERR, " Received Failsafe interrupt\n", 0); + val_print(ERROR, " Received Failsafe interrupt\n"); g_failsafe_int_rcvd = 1; /* On some system the failsafe is rcvd just after test interrupt and resulting @@ -78,13 +78,13 @@ isr2() /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_vir_el1(0); - val_print(ACS_PRINT_INFO, " Received EL1 VIRT interrupt\n", 0); + val_print(TRACE, " Received EL1 VIRT interrupt\n"); g_el1vir_int_received = 1; val_set_status(index, RESULT_PASS(TEST_NUM, 1)); intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_DEBUG, " Clear Failsafe interrupt\n", 0); + val_print(DEBUG, " Clear Failsafe interrupt\n"); } static @@ -98,7 +98,7 @@ payload2() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); if (val_gic_install_isr(intid, isr2)) { - val_print(ACS_PRINT_WARN, "\n GIC Install Handler Failed...", 0); + val_print(WARN, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -134,10 +134,10 @@ payload2() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_end_of_interrupt(intid); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); - val_print(ACS_PRINT_DEBUG, - "\n PE wakeup by some other events/int or didn't enter WFI", 0); + val_print(DEBUG, + "\n PE wakeup by some other events/int or didn't enter WFI"); } - val_print(ACS_PRINT_INFO, "\n delay loop remainig value %d", delay_loop); + val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; } diff --git a/test_pool/power_wakeup/u003.c b/test_pool/power_wakeup/u003.c index 677a68ac..611a7bd9 100644 --- a/test_pool/power_wakeup/u003.c +++ b/test_pool/power_wakeup/u003.c @@ -37,7 +37,7 @@ isr_failsafe() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_ERR, " Received Failsafe interrupt\n", 0); + val_print(ERROR, " Received Failsafe interrupt\n"); g_failsafe_int_rcvd = 1; /* On some system the failsafe is rcvd just after test interrupt and resulting in incorrect fail, to avoid this ensure set test as fail only when failsafe @@ -59,13 +59,13 @@ isr3() /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_phy_el2(0); - val_print(ACS_PRINT_INFO, " Received EL2 Physical interrupt\n", 0); + val_print(TRACE, " Received EL2 Physical interrupt\n"); g_el2phy_int_rcvd = 1; val_set_status(index, RESULT_PASS(TEST_NUM, 1)); intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_DEBUG, " Clear Failsafe interrupt\n", 0); + val_print(DEBUG, " Clear Failsafe interrupt\n"); } static @@ -98,7 +98,7 @@ payload3() intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); if (val_gic_install_isr(intid, isr3)) { - val_print(ACS_PRINT_WARN, "\n GIC Install Handler Failed...", 0); + val_print(WARN, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -133,10 +133,10 @@ payload3() intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_end_of_interrupt(intid); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); - val_print(ACS_PRINT_DEBUG, - "\n PE wakeup by some other events/int or didn't enter WFI", 0); + val_print(DEBUG, + "\n PE wakeup by some other events/int or didn't enter WFI"); } - val_print(ACS_PRINT_INFO, "\n delay loop remainig value %d", delay_loop); + val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; } diff --git a/test_pool/power_wakeup/u004.c b/test_pool/power_wakeup/u004.c index be39d93d..a1f49a48 100644 --- a/test_pool/power_wakeup/u004.c +++ b/test_pool/power_wakeup/u004.c @@ -38,7 +38,7 @@ isr_failsafe() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_ERR, " Received Failsafe interrupt\n", 0); + val_print(ERROR, " Received Failsafe interrupt\n"); g_failsafe_int_received = 1; /* On some system the failsafe is rcvd just after test interrupt and resulting in incorrect fail, to avoid this ensure set test as fail only when failsafe @@ -58,12 +58,12 @@ isr4() uint32_t intid; val_wd_set_ws0(wd_num, 0); - val_print(ACS_PRINT_INFO, " Received WS0 interrupt\n", 0); + val_print(TRACE, " Received WS0 interrupt\n"); g_wd_int_received = 1; intid = val_wd_get_info(wd_num, WD_INFO_GSIV); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_DEBUG, " Clear Failsafe interrupt\n", 0); + val_print(DEBUG, " Clear Failsafe interrupt\n"); } static @@ -102,7 +102,7 @@ payload4() val_set_status(index, RESULT_PASS(TEST_NUM, 1)); if (!wd_num) { - val_print(ACS_PRINT_DEBUG, "\n No watchdog implemented ", 0); + val_print(DEBUG, "\n No watchdog implemented "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -129,7 +129,7 @@ payload4() status = val_wd_set_ws0(wd_num, timer_expire_val); if (status) { wakeup_clear_failsafe(); - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -158,12 +158,12 @@ payload4() intid = val_wd_get_info(wd_num, WD_INFO_GSIV); val_gic_clear_interrupt(intid); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); - val_print(ACS_PRINT_DEBUG, - "\n PE wakeup by some other events/int or didn't enter WFI", 0); + val_print(DEBUG, + "\n PE wakeup by some other events/int or didn't enter WFI"); } - val_print(ACS_PRINT_DEBUG, "\n delay loop remainig value %d", delay_loop); + val_print(DEBUG, "\n delay loop remainig value %d", delay_loop); } else { - val_print(ACS_PRINT_WARN, "\n GIC Install Handler Failed...", 0); + val_print(WARN, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); } @@ -172,7 +172,7 @@ payload4() } if (!ns_wdg) { - val_print(ACS_PRINT_DEBUG, " No non-secure watchdog implemented\n", 0); + val_print(DEBUG, " No non-secure watchdog implemented\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } diff --git a/test_pool/power_wakeup/u005.c b/test_pool/power_wakeup/u005.c index 4ca50e47..b20c4fa2 100644 --- a/test_pool/power_wakeup/u005.c +++ b/test_pool/power_wakeup/u005.c @@ -38,7 +38,7 @@ isr_failsafe() uint32_t intid; val_timer_set_phy_el1(0); - val_print(ACS_PRINT_ERR, " Received Failsafe interrupt\n", 0); + val_print(ERROR, " Received Failsafe interrupt\n"); g_failsafe_int_rcvd = 1; /* On some system the failsafe is rcvd just after test interrupt and resulting in incorrect fail, to avoid this ensure set test as fail only when failsafe @@ -61,13 +61,13 @@ isr5() uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); val_timer_disable_system_timer((addr_t)cnt_base_n); - val_print(ACS_PRINT_INFO, " Received Sys timer interrupt\n", 0); + val_print(TRACE, " Received Sys timer interrupt\n"); g_timer_int_rcvd = 1; val_set_status(index, RESULT_PASS(TEST_NUM, 1)); intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_DEBUG, " Clear Failsafe interrupt\n", 0); + val_print(DEBUG, " Clear Failsafe interrupt\n"); } static @@ -103,7 +103,7 @@ payload5() timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); if (!timer_num) { - val_print(ACS_PRINT_DEBUG, "\n No system timers implemented", 0); + val_print(DEBUG, "\n No system timers implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -116,14 +116,14 @@ payload5() //Read CNTACR to determine whether access permission from NS state is permitted status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); if (status == ACS_STATUS_SKIP) { - val_print(ACS_PRINT_DEBUG, " Timer cntbase can't accessed\n", 0); + val_print(DEBUG, " Timer cntbase can't accessed\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { - val_print(ACS_PRINT_DEBUG, " Timer cntbase is invalid\n", 0); + val_print(DEBUG, " Timer cntbase is invalid\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -159,21 +159,21 @@ payload5() intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); val_gic_clear_interrupt(intid); val_set_status(index, RESULT_SKIP(TEST_NUM, 4)); - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n PE wakeup by some other events/int or didn't enter WFI", 0); } - val_print(ACS_PRINT_INFO, "\n delay loop remainig value %d", delay_loop); + val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; } else{ - val_print(ACS_PRINT_WARN, "\n GIC Install Handler Failed...", 0); + val_print(WARN, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } } if (!ns_timer) { - val_print(ACS_PRINT_WARN, " No non-secure systimer implemented\n", 0); + val_print(WARN, " No non-secure systimer implemented\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); return; } diff --git a/test_pool/power_wakeup/u006.c b/test_pool/power_wakeup/u006.c index b4dedd1a..eaadea27 100644 --- a/test_pool/power_wakeup/u006.c +++ b/test_pool/power_wakeup/u006.c @@ -39,13 +39,13 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t status; - val_print(ACS_PRINT_DEBUG, "\n Received interrupt ", 0); + val_print(DEBUG, "\n Received interrupt "); if (wakeup_event == SYSTIMER_SEMF) val_timer_disable_system_timer((addr_t)cnt_base_n); else if (wakeup_event == WATCHDOG_SEMF) { status = val_wd_set_ws0(wd_num, 0); if (status) - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); } val_set_status(index, RESULT_PASS(TEST_NUM, 1)); @@ -100,7 +100,7 @@ payload_target_pe() { uint64_t data1, data2; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); -// val_print(ACS_PRINT_DEBUG, "\n Print from target PE :%X", index); +// val_print(DEBUG, "\n Print from target PE :%X", index); val_get_test_data(index, &data1, &data2); val_pe_reg_write(VBAR_EL2, data2); @@ -141,7 +141,7 @@ payload() // if none of these are present in a platform, skip the test wakeup_event = wakeup_event_for_semantic_f(); if (wakeup_event == 0) { - val_print(ACS_PRINT_DEBUG, "\n No Watchdogs and system timers present", 0); + val_print(DEBUG, "\n No Watchdogs and system timers present"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -149,7 +149,7 @@ payload() // Step3: Route the interrupt to target PE and install ISR val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); if (val_gic_install_isr(intid, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); val_gic_route_interrupt_to_pe(intid, index); return; @@ -171,7 +171,7 @@ payload() else if (wakeup_event == WATCHDOG_SEMF) { status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -183,18 +183,18 @@ payload() ; if (timeout == 0) - val_print(ACS_PRINT_ERR, "\n Target PE was not able to wake up successfully " - "from sleep \n due to watchdog/sytimer interrupt", 0); + val_print(ERROR, "\n Target PE was not able to wake up successfully " + "from sleep \n due to watchdog/sytimer interrupt"); // Step7: Clear the pending/active interrupt if any if (1 == val_gic_get_interrupt_state(intid)) { - val_print(ACS_PRINT_ERR, "\n Pending interrupt was seen for the 1st interrupt", 0); + val_print(ERROR, "\n Pending interrupt was seen for the 1st interrupt"); if (wakeup_event == SYSTIMER_SEMF) val_timer_disable_system_timer((addr_t)cnt_base_n); else if (wakeup_event == WATCHDOG_SEMF) { status = val_wd_set_ws0(wd_num, 0); if (status) { - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -213,7 +213,7 @@ payload() // Step9: Generate timer interrupt again, when target PE is off and make sure it doesn't wakeup val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); if (val_gic_install_isr(intid, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); val_gic_route_interrupt_to_pe(intid, index); return; @@ -225,13 +225,13 @@ payload() else if (wakeup_event == WATCHDOG_SEMF) { status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } } - val_print(ACS_PRINT_ERR, "\n Interrupt generating sequence triggered", 0); + val_print(ERROR, "\n Interrupt generating sequence triggered"); // Step10: wait for interrupt to become active or pending for a timeout duration timeout = TIMEOUT_MEDIUM; @@ -239,16 +239,16 @@ payload() ; if (timeout == 0) - val_print(ACS_PRINT_ERR, "\n No pending interrupt was seen for the 2nd interrupt", 0); + val_print(ERROR, "\n No pending interrupt was seen for the 2nd interrupt"); if (1 == val_gic_get_interrupt_state(intid)) { - val_print(ACS_PRINT_ERR, "\n Pending interrupt was seen for the 2nd interrupt", 0); + val_print(ERROR, "\n Pending interrupt was seen for the 2nd interrupt"); if (wakeup_event == SYSTIMER_SEMF) val_timer_disable_system_timer((addr_t)cnt_base_n); else if (wakeup_event == WATCHDOG_SEMF) { status = val_wd_set_ws0(wd_num, 0); if (status) { - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; } diff --git a/test_pool/ras/ras001.c b/test_pool/ras/ras001.c index 25c12585..2ec6c4d8 100644 --- a/test_pool/ras/ras001.c +++ b/test_pool/ras/ras001.c @@ -43,9 +43,9 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -55,7 +55,7 @@ payload() /* Get Current Node Type */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + val_print(DEBUG, "\n Node Type not found index %d", node_index); fail_cnt++; break; } @@ -68,7 +68,7 @@ payload() if (value == NODE_TYPE_PE) { status = val_ras_get_info(RAS_INFO_PE_RES_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n PE Resource type not found index %d", node_index); + val_print(DEBUG, "\n PE Resource type not found index %d", node_index); fail_cnt++; break; } @@ -80,7 +80,7 @@ payload() /* Get Error Record number for Current Node */ status = val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); if (status || num_err_recs == 0) { - val_print(ACS_PRINT_ERR, "\n RAS Node %d has no error records implemented ", + val_print(ERROR, "\n RAS Node %d has no error records implemented ", node_index); continue; } @@ -90,15 +90,15 @@ payload() /* Read FR register of the current error record */ value = val_ras_reg_read(node_index, RAS_ERR_FR, err_rec_idx); if (value == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, "\n Couldn't read ERR<%d>FR register", err_rec_idx); - val_print(ACS_PRINT_ERR, "\n RAS node index: %d", node_index); + val_print(ERROR, "\n Couldn't read ERR<%d>FR register", err_rec_idx); + val_print(ERROR, "\n RAS node index: %d", node_index); fail_cnt++; continue; } /* Check only if ERR_FR.CE != 0 - Check ERR_FR.CEC[14:12] != 0 for CEC to be implemented */ if ((value & ERR_FR_CE_MASK) && !(value & ERR_FR_CEC_MASK)) { - val_print(ACS_PRINT_ERR, "\n CEC not implemented for node_index %d", node_index); + val_print(ERROR, "\n CEC not implemented for node_index %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras002.c b/test_pool/ras/ras002.c index ccd6e3fd..d24bb76b 100644 --- a/test_pool/ras/ras002.c +++ b/test_pool/ras/ras002.c @@ -43,9 +43,9 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -55,7 +55,7 @@ payload() /* Get Current Node Type */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + val_print(DEBUG, "\n Node Type not found index %d", node_index); fail_cnt++; break; } @@ -68,7 +68,7 @@ payload() if (value == NODE_TYPE_PE) { status = val_ras_get_info(RAS_INFO_PE_RES_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n PE Resource type not found index %d", node_index); + val_print(DEBUG, "\n PE Resource type not found index %d", node_index); fail_cnt++; break; } @@ -80,7 +80,7 @@ payload() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); if (status || num_err_recs == 0) { - val_print(ACS_PRINT_ERR, "\n RAS Node %d has no error records implemented ", + val_print(ERROR, "\n RAS Node %d has no error records implemented ", node_index); continue; } @@ -90,29 +90,29 @@ payload() /* Read FR register of the current error record */ value = val_ras_reg_read(node_index, RAS_ERR_FR, err_rec_idx); if (value == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, "\n Couldn't read ERR<%d>FR register", err_rec_idx); - val_print(ACS_PRINT_ERR, "\n RAS node index: %d", node_index); + val_print(ERROR, "\n Couldn't read ERR<%d>FR register", err_rec_idx); + val_print(ERROR, "\n RAS node index: %d", node_index); fail_cnt++; continue; } /* Check only if DE[52] != 0 then DUI[17:16] != 0 of FR Register For DUI Control */ if ((value & ERR_FR_DE_MASK) && !(value & ERR_FR_DUI_MASK)) { - val_print(ACS_PRINT_ERR, "\n DUI not implemented for node_index %d", node_index); + val_print(ERROR, "\n DUI not implemented for node_index %d", node_index); fail_cnt++; continue; } /* Check only if ERR_FR.CE != 0 -> Check CFI[11:10] != 0 of FR Register For CFI Control */ if ((value & ERR_FR_CE_MASK) && !(value & ERR_FR_CFI_MASK)) { - val_print(ACS_PRINT_ERR, "\n CFI not implemented for node_index %d", node_index); + val_print(ERROR, "\n CFI not implemented for node_index %d", node_index); fail_cnt++; continue; } /* Check UI[5:4] != 0 of FR Register For UI Control */ if (!(value & ERR_FR_UI_MASK)) { - val_print(ACS_PRINT_ERR, "\n UI not implemented for node_index %d", node_index); + val_print(ERROR, "\n UI not implemented for node_index %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras003.c b/test_pool/ras/ras003.c index 03ed3a79..2a1ed724 100644 --- a/test_pool/ras/ras003.c +++ b/test_pool/ras/ras003.c @@ -42,14 +42,14 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } if (num_node < 2) { - val_print(ACS_PRINT_DEBUG, "\n RAS Nodes should be more than 1. Skipping...", 0); + val_print(DEBUG, "\n RAS Nodes should be more than 1. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -60,14 +60,14 @@ payload() status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &base_addr); if (status) { /* Interface is System Register based, Skipping this node */ - val_print(ACS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + val_print(DEBUG, "\n Interface is SR, Skipping node %d", node_index); continue; } /* Get FHI number for this Node, If Not Skip the Node */ status = val_ras_get_info(RAS_INFO_FHI_ID, node_index, &fhi_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n FHI not supported for index %d", node_index); + val_print(DEBUG, "\n FHI not supported for index %d", node_index); continue; } @@ -80,7 +80,7 @@ payload() status = val_ras_get_info(RAS_INFO_BASE_ADDR, sec_node, &base_addr_sec); if (status) { /* Interface is System Register based, Skipping this node */ - val_print(ACS_PRINT_DEBUG, "\n Interface is SR, Skipping sec_node %d", node_index); + val_print(DEBUG, "\n Interface is SR, Skipping sec_node %d", node_index); continue; } @@ -91,14 +91,14 @@ payload() /* Get FHI number for this Node */ status = val_ras_get_info(RAS_INFO_FHI_ID, sec_node, &fhi_id_sec); if (status) { - val_print(ACS_PRINT_DEBUG, "\n FHI not supported for index %d", sec_node); + val_print(DEBUG, "\n FHI not supported for index %d", sec_node); continue; } /* Check if FHI is same otherwise fail the test */ if (fhi_id != fhi_id_sec) { - val_print(ACS_PRINT_ERR, "\n FHI different for Same Group index %d", node_index); - val_print(ACS_PRINT_ERR, " : %d", sec_node); + val_print(ERROR, "\n FHI different for Same Group index %d", node_index); + val_print(ERROR, " : %d", sec_node); fail_cnt++; continue; } diff --git a/test_pool/ras/ras004.c b/test_pool/ras/ras004.c index f6d953bf..dd065ba5 100644 --- a/test_pool/ras/ras004.c +++ b/test_pool/ras/ras004.c @@ -42,15 +42,15 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } if (num_node < 2) { - val_print(ACS_PRINT_DEBUG, "\n RAS Nodes should be more than 1. Skipping...", 0); + val_print(DEBUG, "\n RAS Nodes should be more than 1. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -61,14 +61,14 @@ payload() status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &base_addr); if (status) { /* Interface is System Register based, Skipping this node */ - val_print(ACS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + val_print(DEBUG, "\n Interface is SR, Skipping node %d", node_index); continue; } /* Get ERI number for Node, If Not Skip the Node */ status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &eri_id); if (status) { - val_print(ACS_PRINT_DEBUG, "\n ERI Not supported for index %d", node_index); + val_print(DEBUG, "\n ERI Not supported for index %d", node_index); continue; } @@ -81,7 +81,7 @@ payload() status = val_ras_get_info(RAS_INFO_BASE_ADDR, sec_node, &base_addr_sec); if (status) { /* Interface is System Register based, Skipping this node */ - val_print(ACS_PRINT_DEBUG, "\n Interface is SR, Skipping sec_node %d", sec_node); + val_print(DEBUG, "\n Interface is SR, Skipping sec_node %d", sec_node); continue; } @@ -92,14 +92,14 @@ payload() /* Get ERI number for this Node */ status = val_ras_get_info(RAS_INFO_ERI_ID, sec_node, &eri_id_sec); if (status) { - val_print(ACS_PRINT_DEBUG, "\n ERI Not supported for index %d", sec_node); + val_print(DEBUG, "\n ERI Not supported for index %d", sec_node); continue; } /* Check if ERI is same otherwise fail the test */ if (eri_id != eri_id_sec) { - val_print(ACS_PRINT_ERR, "\n ERI Diff for Same Group Nodes. Index %d", node_index); - val_print(ACS_PRINT_ERR, " : %d", sec_node); + val_print(ERROR, "\n ERI Diff for Same Group Nodes. Index %d", node_index); + val_print(ERROR, " : %d", sec_node); fail_cnt++; continue; } @@ -110,7 +110,7 @@ payload() val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } else if (test_skip) { - val_print(ACS_PRINT_ERR, "\n No ERI found in RAS nodes ", 0); + val_print(ERROR, "\n No ERI found in RAS nodes "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } diff --git a/test_pool/ras/ras005.c b/test_pool/ras/ras005.c index 523bc793..cd5fb58e 100644 --- a/test_pool/ras/ras005.c +++ b/test_pool/ras/ras005.c @@ -39,7 +39,7 @@ intr_handler(void) /* Clear the interrupt pending state */ - val_print(ACS_PRINT_INFO, "\n Received interrupt %x ", 0); + val_print(TRACE, "\n Received interrupt %x "); val_gic_end_of_interrupt(int_id); return; } @@ -62,9 +62,9 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -77,12 +77,12 @@ payload() status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &eri_id); if (status) { /* No ERI Support for this node */ - val_print(ACS_PRINT_DEBUG, "\n ERI Not supported for node %d", node_index); + val_print(DEBUG, "\n ERI Not supported for node %d", node_index); } else { test_skip = 0; /* ERI Support, Check for SPI/PPI */ if (IS_NOT_SPI_PPI(eri_id)) { - val_print(ACS_PRINT_ERR, "\n ERI Not SPI/PPI for node %d", node_index); + val_print(ERROR, "\n ERI Not SPI/PPI for node %d", node_index); fail_cnt++; continue; } @@ -92,12 +92,12 @@ payload() status = val_ras_get_info(RAS_INFO_FHI_ID, node_index, &fhi_id); if (status) { /* No FHI Support for this node */ - val_print(ACS_PRINT_DEBUG, "\n FHI Not supported for node %d", node_index); + val_print(DEBUG, "\n FHI Not supported for node %d", node_index); } else { test_skip = 0; /* FHI Support, Check for SPI/PPI */ if (IS_NOT_SPI_PPI(fhi_id)) { - val_print(ACS_PRINT_ERR, "\n FHI Not SPI/PPI for node %d", node_index); + val_print(ERROR, "\n FHI Not SPI/PPI for node %d", node_index); fail_cnt++; continue; } @@ -112,7 +112,7 @@ payload() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; } @@ -131,7 +131,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -142,7 +142,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -151,7 +151,7 @@ payload() val_ras_wait_timeout(1); if (intr_pending) { - val_print(ACS_PRINT_ERR, "\n Not Connected to GIC for node %d", node_index); + val_print(ERROR, "\n Not Connected to GIC for node %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras006.c b/test_pool/ras/ras006.c index 66304d09..1f64d8f4 100644 --- a/test_pool/ras/ras006.c +++ b/test_pool/ras/ras006.c @@ -60,9 +60,9 @@ payload() /* get number of nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -70,7 +70,7 @@ payload() /* get number of MC nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS MC nodes not found. Skipping...", 0); + val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -79,7 +79,7 @@ payload() /* check whether current node is memory controller node */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &node_type); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't get node type for RAS node index: 0x%lx", node_index); fail_cnt++; @@ -91,7 +91,7 @@ payload() (both implemented and unimplemented) */ status = val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't get number of error records for RAS node index: 0x%lx", node_index); fail_cnt++; @@ -99,7 +99,7 @@ payload() } /* skip if num of error records in zero */ if (num_err_recs == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Number of error records for RAS node index: 0x%lx is zero", node_index); test_skip++; @@ -109,7 +109,7 @@ payload() /* get proximity domain of RAS memory controller node */ status = val_ras_get_info(RAS_INFO_MC_RES_PROX_DOMAIN, node_index, &mc_prox_domain); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't get MC proximity domain for RAS node index: 0x%lx", node_index); fail_cnt++; @@ -120,7 +120,7 @@ payload() defined method */ prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); if (prox_base_addr == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid base address for proximity domain : 0x%lx", mc_prox_domain); fail_cnt++; @@ -131,7 +131,7 @@ payload() err_inj_addr = (uint64_t)val_mem_alloc_at_address(prox_base_addr, ONE_BYTE_BUFFER); if (err_inj_addr == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Unable to allocate address in proximity domain : 0x%lx failed.", mc_prox_domain); /* test not applicable if memory isn't accessible by PE */ @@ -153,7 +153,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -164,7 +164,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -173,7 +173,7 @@ payload() val_ras_wait_timeout(1); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory error injection for RAS node index: 0x%lx failed.", node_index); fail_cnt++; @@ -183,8 +183,8 @@ payload() /* perform a read to error-injected address, which will cause system to record the error with address syndrome in one of the error records present for the current RAS node */ err_inj_addr_data = val_mmio_read(err_inj_addr); - val_print(ACS_PRINT_DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); - val_print(ACS_PRINT_DEBUG, " Data read: 0x%lx", err_inj_addr_data); + val_print(DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); + val_print(DEBUG, " Data read: 0x%lx", err_inj_addr_data); /* wait loop to allow system to update RAS error records */ val_ras_wait_timeout(1); @@ -192,7 +192,7 @@ payload() /* get error record implemented bitmap from RAS info table */ status = val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_impl_bitmap); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't get implemented rec bitmap for RAS node index: 0x%lx", node_index); fail_cnt++; @@ -203,7 +203,7 @@ payload() ERRADDR field of error records */ status = val_ras_get_info(RAS_INFO_ADDR_MODE, node_index, &err_rec_addrmode_bitmap); if (status) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't get implemented addr mode bitmap for RAS node index: 0x%lx", node_index); fail_cnt++; @@ -228,10 +228,10 @@ payload() error record */ data = val_ras_reg_read(node_index, RAS_ERR_STATUS, err_rec_index); if (data == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>STATUS register for ", err_rec_index); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "RAS node index: 0x%lx", node_index); fail_cnt++; @@ -252,10 +252,10 @@ payload() /* read ERRADDR.AI bit */ data = val_ras_reg_read(node_index, RAS_ERR_ADDR, err_rec_index); if (data == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>STATUS register for ", err_rec_index); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "RAS node index: 0x%lx", node_index); fail_cnt++; @@ -264,7 +264,7 @@ payload() err_rec_addr_ai = (data >> ERR_ADDR_AI_SHIFT) & 0x1; if (err_rec_addrmode == 0 && err_rec_addr_ai == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n RAS node index: 0x%lx PASSED", node_index); /* error record comply with RAS_07 requirements */ @@ -278,7 +278,7 @@ payload() /* check if system RAS recorded the error in memory with address syndrome if no, rule is not applicable for the node */ if (!err_recorded) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Memory error not recorded for RAS node index: 0x%lx", node_index); test_skip++; diff --git a/test_pool/ras/ras007.c b/test_pool/ras/ras007.c index 58b706b6..7f7c1045 100644 --- a/test_pool/ras/ras007.c +++ b/test_pool/ras/ras007.c @@ -43,9 +43,9 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if system \ - components supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if system \ + components supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -56,7 +56,7 @@ payload() status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &value); if (status) { /* Interface is System Register based, Skipping this node */ - val_print(ACS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + val_print(DEBUG, "\n Interface is SR, Skipping node %d", node_index); continue; } @@ -65,7 +65,7 @@ payload() /* Get Start error index number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &start_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; } @@ -73,7 +73,7 @@ payload() /* Check which error records are implemented in this node */ status = val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_implement); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get err rec info for index %d", node_index); + val_print(DEBUG, "\n Could not get err rec info for index %d", node_index); fail_cnt++; continue; } @@ -81,7 +81,7 @@ payload() /* Get error status reporting value for this node */ status = val_ras_get_info(RAS_INFO_STATUS_REPORT, node_index, &err_status); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get status for index %d", node_index); + val_print(DEBUG, "\n Could not get status for index %d", node_index); fail_cnt++; continue; } @@ -91,7 +91,7 @@ payload() if (err_status & record_imp_bits) { /* Fail the test as one of the implemented ER has error reporting not supported */ - val_print(ACS_PRINT_ERR, "\n ERRGSR not supported for index %d", node_index); + val_print(ERROR, "\n ERRGSR not supported for index %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras008.c b/test_pool/ras/ras008.c index abb61932..f53a4258 100644 --- a/test_pool/ras/ras008.c +++ b/test_pool/ras/ras008.c @@ -51,7 +51,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to point to next instrcution */ val_pe_update_elr(context, branch_to_test); - val_print(ACS_PRINT_ERR, "\n Error : Received Sync Exception type %d", interrupt_type); + val_print(ERROR, "\n Error : Received Sync Exception type %d", interrupt_type); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); } @@ -70,7 +70,7 @@ payload(void) branch_to_test = (uint64_t)&&exception_taken; if (count == 0) { - val_print(ACS_PRINT_WARN, "\n No UART defined by Platform ", 0); + val_print(WARN, "\n No UART defined by Platform "); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -84,7 +84,7 @@ payload(void) /*Make sure access to Reserved doesn't cause any exceptions*/ value = *((volatile uint32_t *)(l_uart_base + UART_RES)); - val_print(ACS_PRINT_DEBUG, "\n Value from UART Reserved Space 0x%llx", value); + val_print(DEBUG, "\n Value from UART Reserved Space 0x%llx", value); *((volatile uint32_t *)(l_uart_base + UART_RES)) = (uint32_t)(0xDEAD); diff --git a/test_pool/ras/ras009.c b/test_pool/ras/ras009.c index d67cc6bf..348cf021 100644 --- a/test_pool/ras/ras009.c +++ b/test_pool/ras/ras009.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); } static @@ -69,23 +69,22 @@ payload() /* Read ID_AA64MMFR3_EL1.ANERR[47:44] == 0b0010 or 0b0011 indicate FEAT_ANERR support */ anerr = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR3_EL1), 44, 47); - val_print(ACS_PRINT_INFO, "\n ID_AA64MMFR3_EL1.ANERR field = 0x%llx", anerr); + val_print(TRACE, "\n ID_AA64MMFR3_EL1.ANERR field = 0x%llx", anerr); if (anerr == FEAT_ANERR_VAL2 || anerr == FEAT_ANERR_VAL3) { - val_print(ACS_PRINT_INFO, "\n FEAT_ANERR implemented.", 0); + val_print(TRACE, "\n FEAT_ANERR implemented."); val_set_status(index, RESULT_PASS(TEST_NUM, 01)); return; } - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n FEAT_ANERR not implemented." - " Proceeding to synchronous Data Abort test.\n", - 0); + " Proceeding to synchronous Data Abort test.\n"); /* get number of nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS nodes not found.", 0); + val_print(ERROR, "\n RAS nodes not found."); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -93,7 +92,7 @@ payload() /* get number of MC nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS MC nodes not found.", 0); + val_print(ERROR, "\n RAS MC nodes not found."); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -103,7 +102,7 @@ payload() /* check whether current node is memory controller node */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &node_type); if (status) { - val_print(ACS_PRINT_ERR, "\n Couldn't get node type for node : 0x%lx", node_index); + val_print(ERROR, "\n Couldn't get node type for node : 0x%lx", node_index); fail_cnt++; continue; } @@ -114,7 +113,7 @@ payload() /* Get proximity domain of RAS memory controller node */ status = val_ras_get_info(RAS_INFO_MC_RES_PROX_DOMAIN, node_index, &mc_prox_domain); if (status) { - val_print(ACS_PRINT_ERR, "\n Couldn't get MC prox domain for node : 0x%lx", node_index); + val_print(ERROR, "\n Couldn't get MC prox domain for node : 0x%lx", node_index); fail_cnt++; continue; } @@ -122,16 +121,16 @@ payload() /* Get base addr for proximity domain to inject error in platform defined method */ prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); if (prox_base_addr == SRAT_INVALID_INFO) { - val_print(ACS_PRINT_ERR, "\n Invalid base for prox domain : 0x%lx", mc_prox_domain); + val_print(ERROR, "\n Invalid base for prox domain : 0x%lx", mc_prox_domain); fail_cnt++; continue; } /* check if the address accessible to PE by trying to allocate the address */ err_inj_addr = (uint64_t)val_mem_alloc_at_address(prox_base_addr, ONE_BYTE_BUFFER); - val_print(ACS_PRINT_ERR, "\n err_inj_addr : 0x%lx", err_inj_addr); + val_print(ERROR, "\n err_inj_addr : 0x%lx", err_inj_addr); if (err_inj_addr == 0) { - val_print(ACS_PRINT_ERR, "\n Unable to allocate address in prox domain : 0x%lx", + val_print(ERROR, "\n Unable to allocate address in prox domain : 0x%lx", mc_prox_domain); /* test not applicable if memory isn't accessible by PE */ test_skip++; @@ -143,7 +142,7 @@ payload() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -163,7 +162,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -177,7 +176,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -189,15 +188,15 @@ payload() * system to record the error with address syndrome in one of * the error records present for the current RAS node */ err_inj_addr_data = (*(volatile addr_t *)err_inj_addr); - val_print(ACS_PRINT_DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); - val_print(ACS_PRINT_DEBUG, " Data read: 0x%lx", err_inj_addr_data); + val_print(DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); + val_print(DEBUG, " Data read: 0x%lx", err_inj_addr_data); exception_return: - val_print(ACS_PRINT_INFO, "\n value esr_pending, %d", esr_pending); + val_print(TRACE, "\n value esr_pending, %d", esr_pending); /* Check for External Abort */ if (esr_pending) { - val_print(ACS_PRINT_DEBUG, "\n Data abort Check Fail, for node %d", node_index); + val_print(DEBUG, "\n Data abort Check Fail, for node %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras010.c b/test_pool/ras/ras010.c index fa398a6c..3b02b802 100644 --- a/test_pool/ras/ras010.c +++ b/test_pool/ras/ras010.c @@ -40,7 +40,7 @@ payload() /* get total number of RAS2 memory info blocks */ num_of_mem_blocks = val_ras2_get_mem_info(RAS2_NUM_MEM_BLOCK, 0); if (num_of_mem_blocks == 0) { - val_print(ACS_PRINT_DEBUG, "\n No nodes in RAS2 table or RAS2 table not present", 0); + val_print(DEBUG, "\n No nodes in RAS2 table or RAS2 table not present"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -49,7 +49,7 @@ payload() /* check whether current NUMA node (proximity domain) support patrol scrubbing */ scrub_support = val_ras2_get_mem_info(RAS2_SCRUB_SUPPORT, i); if (scrub_support == 0) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Patrol scrubbing not supported by proximity domain: 0x%x", val_ras2_get_mem_info(RAS2_PROX_DOMAIN, i)); fail_cnt++; diff --git a/test_pool/ras/ras011.c b/test_pool/ras/ras011.c index 186d0348..80d18c62 100644 --- a/test_pool/ras/ras011.c +++ b/test_pool/ras/ras011.c @@ -39,7 +39,7 @@ intr_handler(void) { /* Clear the interrupt pending state */ - val_print(ACS_PRINT_INFO, "\n Received interrupt %x ", 0); + val_print(TRACE, "\n Received interrupt %x "); val_gic_end_of_interrupt(int_id); return; } @@ -55,7 +55,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); } /* @@ -88,7 +88,7 @@ payload_poison_supported() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -97,7 +97,7 @@ payload_poison_supported() /* Get number of MC nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS MC nodes not found. Skipping...", 0); + val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -106,7 +106,7 @@ payload_poison_supported() /* Check current PE RAS Support with mpidr */ status = val_ras_get_info(RAS_INFO_NODE_INDEX_FOR_AFF, mpidr, &pe_node_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n RAS Node not found for PE", 0); + val_print(DEBUG, "\n RAS Node not found for PE"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -114,7 +114,7 @@ payload_poison_supported() /* Check if Platform Supports Poison Storage & Forwarding else skip */ poison_check = val_ras_check_plat_poison_support(); if (!poison_check) { - val_print(ACS_PRINT_ERR, "\n Poison storage & forward not supported. Skipping...", 0); + val_print(ERROR, "\n Poison storage & forward not supported. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -124,7 +124,7 @@ payload_poison_supported() /* Get Current Node Type */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + val_print(DEBUG, "\n Node Type not found index %d", node_index); fail_cnt++; break; } @@ -137,7 +137,7 @@ payload_poison_supported() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; } @@ -151,7 +151,7 @@ payload_poison_supported() status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &int_id); if (status) { /* Interrupt details not found, Failing for this node */ - val_print(ACS_PRINT_DEBUG, "\n No Intr found, Failed for node %d", node_index); + val_print(DEBUG, "\n No Intr found, Failed for node %d", node_index); fail_cnt++; continue; } @@ -163,7 +163,7 @@ payload_poison_supported() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -175,11 +175,11 @@ payload_poison_supported() /* Setup an error in an implementation defined way */ status = val_ras_setup_error(err_in_params, &err_out_params); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_print(ACS_PRINT_DEBUG, "\n ras_setup_error unimplemented, node %d", node_index); + val_print(DEBUG, "\n ras_setup_error unimplemented, node %d", node_index); warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -190,7 +190,7 @@ payload_poison_supported() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -199,7 +199,7 @@ payload_poison_supported() /* Read Status Register for Memory Controller RAS Node */ status = val_ras_check_err_record(node_index, err_in_params.ras_error_type); if (status) { - val_print(ACS_PRINT_ERR, "\n MC Err Status Check Failed, for node %d", node_index); + val_print(ERROR, "\n MC Err Status Check Failed, for node %d", node_index); fail_cnt++; continue; } @@ -207,7 +207,7 @@ payload_poison_supported() /* Read Status Register for PE RAS Node */ status = val_ras_check_err_record(pe_node_index, err_in_params.ras_error_type); if (status) { - val_print(ACS_PRINT_ERR, "\n PE Err Status Check Failed, for node %d", node_index); + val_print(ERROR, "\n PE Err Status Check Failed, for node %d", node_index); fail_cnt++; continue; } @@ -216,10 +216,10 @@ payload_poison_supported() /* Read Status Register for RAS Nodes */ mc_status = val_ras_reg_read(node_index, RAS_ERR_STATUS, rec_index); if (mc_status == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>STATUS register for ", rec_index); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "RAS node index: 0x%lx", node_index); fail_cnt++; @@ -227,10 +227,10 @@ payload_poison_supported() } pe_status = val_ras_reg_read(pe_node_index, RAS_ERR_STATUS, rec_index); if (pe_status == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>STATUS register for ", rec_index); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "RAS node index: 0x%lx", pe_node_index); fail_cnt++; @@ -239,12 +239,12 @@ payload_poison_supported() /* Check Poison Information Storage/Forwarding in MC/PE Ras Node */ if (!(mc_status & ERR_STATUS_PN_MASK)) { - val_print(ACS_PRINT_DEBUG, "\n Poison Storage Fail, for node %d", node_index); + val_print(DEBUG, "\n Poison Storage Fail, for node %d", node_index); fail_cnt++; continue; } if (!(pe_status & ERR_STATUS_PN_MASK)) { - val_print(ACS_PRINT_DEBUG, "\n Poison Frwding Fail, for node %d", pe_node_index); + val_print(DEBUG, "\n Poison Frwding Fail, for node %d", pe_node_index); fail_cnt++; continue; } @@ -289,7 +289,7 @@ payload_poison_unsupported() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); return; } @@ -298,7 +298,7 @@ payload_poison_unsupported() /* Get number of MC nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS MC nodes not found. Skipping...", 0); + val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM1, 01)); return; } @@ -307,7 +307,7 @@ payload_poison_unsupported() /* Check current PE RAS Support with mpidr */ status = val_ras_get_info(RAS_INFO_NODE_INDEX_FOR_AFF, mpidr, &pe_node_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n RAS Node not found for PE", 0); + val_print(DEBUG, "\n RAS Node not found for PE"); val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); return; } @@ -315,7 +315,7 @@ payload_poison_unsupported() /* Check if Platform Supports Poison Storage & Forwarding */ poison_check = val_ras_check_plat_poison_support(); if (poison_check) { - val_print(ACS_PRINT_ERR, "\n Poison storage & forward supported. Skipping...", 0); + val_print(ERROR, "\n Poison storage & forward supported. Skipping..."); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } @@ -325,7 +325,7 @@ payload_poison_unsupported() /* Get Current Node Type */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + val_print(DEBUG, "\n Node Type not found index %d", node_index); fail_cnt++; break; } @@ -338,7 +338,7 @@ payload_poison_unsupported() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; } @@ -352,7 +352,7 @@ payload_poison_unsupported() status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &int_id); if (status) { /* Interrupt details not found, Failing for this node */ - val_print(ACS_PRINT_DEBUG, "\n No Intr found, Failed for node %d", node_index); + val_print(DEBUG, "\n No Intr found, Failed for node %d", node_index); fail_cnt++; continue; } @@ -364,7 +364,7 @@ payload_poison_unsupported() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM1, 03)); return; } @@ -376,11 +376,11 @@ payload_poison_unsupported() /* Setup an error in an implementation defined way */ status = val_ras_setup_error(err_in_params, &err_out_params); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_print(ACS_PRINT_DEBUG, "\n ras_setup_error unimplemented, node %d", node_index); + val_print(DEBUG, "\n ras_setup_error unimplemented, node %d", node_index); warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -391,7 +391,7 @@ payload_poison_unsupported() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -400,7 +400,7 @@ payload_poison_unsupported() /* Read Status Register for Memory Controller RAS Node */ status = val_ras_check_err_record(node_index, err_in_params.ras_error_type); if (status) { - val_print(ACS_PRINT_ERR, "\n MC Err Status Check Failed, for node %d", node_index); + val_print(ERROR, "\n MC Err Status Check Failed, for node %d", node_index); fail_cnt++; continue; } @@ -408,14 +408,14 @@ payload_poison_unsupported() /* Read Status Register for PE RAS Node */ status = val_ras_check_err_record(pe_node_index, err_in_params.ras_error_type); if (status) { - val_print(ACS_PRINT_ERR, "\n PE Err Status Check Failed, for node %d", node_index); + val_print(ERROR, "\n PE Err Status Check Failed, for node %d", node_index); fail_cnt++; continue; } /* Check for abort if poison forwarding is not supported */ if (esr_pending) { - val_print(ACS_PRINT_DEBUG, "\n EA Check Fail, for node %d", pe_node_index); + val_print(DEBUG, "\n EA Check Fail, for node %d", pe_node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras012.c b/test_pool/ras/ras012.c index e1ef3ae2..ac3eab58 100644 --- a/test_pool/ras/ras012.c +++ b/test_pool/ras/ras012.c @@ -35,7 +35,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); + val_print(ERROR, "\n Received exception of type: %d", interrupt_type); } static @@ -55,7 +55,7 @@ payload() /* Get Number of nodes with RAS Functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -66,7 +66,7 @@ payload() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; } @@ -83,7 +83,7 @@ payload() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -102,7 +102,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -111,7 +111,7 @@ payload() /* Read Status Register for RAS Nodes */ status = val_ras_check_err_record(node_index, err_in_params.ras_error_type); if (status) { - val_print(ACS_PRINT_ERR, "\n Err Status Check Failed, for node %d", node_index); + val_print(ERROR, "\n Err Status Check Failed, for node %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras013.c b/test_pool/ras/ras013.c index 8a980a96..a6aa7cd4 100644 --- a/test_pool/ras/ras013.c +++ b/test_pool/ras/ras013.c @@ -44,9 +44,9 @@ static void payload(void) /* get number of PE nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_PE, 0, &num_pc_node); if (status || (num_pc_node == 0)) { - val_print(ACS_PRINT_DEBUG, "\n No RAS Nodes found in AEST table.", 0); - val_print(ACS_PRINT_DEBUG, "\n The test must be considered fail if PE \ - supports RAS nodes", 0); + val_print(DEBUG, "\n No RAS Nodes found in AEST table."); + val_print(DEBUG, "\n The test must be considered fail if PE \ + supports RAS nodes"); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -64,7 +64,7 @@ static void payload(void) /* Check for Resource Shared in case of Processor Node */ status = val_ras_get_info(RAS_INFO_PE_FLAG, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n PE Resource flag not found index %d", node_index); + val_print(DEBUG, "\n PE Resource flag not found index %d", node_index); fail_cnt++; break; } @@ -81,12 +81,12 @@ static void payload(void) /* Check for interface type is memory-mapped */ status = val_ras_get_info(RAS_INFO_INTF_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Interface Type not found index %d", node_index); + val_print(DEBUG, "\n Interface Type not found index %d", node_index); fail_cnt++; break; } if (value != 1) { - val_print(ACS_PRINT_ERR, "\n Interface Type must be MMIO for index %d", node_index); + val_print(ERROR, "\n Interface Type must be MMIO for index %d", node_index); fail_cnt++; continue; } @@ -98,7 +98,7 @@ static void payload(void) val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } else if (test_skip) { - val_print(ACS_PRINT_ERR, "\n No Resource are Shared between two or more PE. " + val_print(ERROR, "\n No Resource are Shared between two or more PE. " "Skipping... ", 0); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; diff --git a/test_pool/ras/ras014.c b/test_pool/ras/ras014.c index ba4f8657..f4235ae1 100644 --- a/test_pool/ras/ras014.c +++ b/test_pool/ras/ras014.c @@ -48,7 +48,7 @@ static void payload(void) /* Check for interface type is System Register Based */ status = val_ras_get_info(RAS_INFO_INTF_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Interface Type not found index %d", node_index); + val_print(DEBUG, "\n Interface Type not found index %d", node_index); fail_cnt++; break; } @@ -59,12 +59,12 @@ static void payload(void) status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &eri_id); if (status) { /* No ERI Support for this node */ - val_print(ACS_PRINT_DEBUG, "\n ERI Not supported for node %d", node_index); + val_print(DEBUG, "\n ERI Not supported for node %d", node_index); } else { test_skip = 0; /* ERI Support, Check for PPI */ if ((eri_id < 16) || (eri_id > 31)) { - val_print(ACS_PRINT_ERR, "\n ERI Not PPI for node %d", node_index); + val_print(ERROR, "\n ERI Not PPI for node %d", node_index); fail_cnt++; continue; } @@ -74,12 +74,12 @@ static void payload(void) status = val_ras_get_info(RAS_INFO_FHI_ID, node_index, &fhi_id); if (status) { /* No FHI Support for this node */ - val_print(ACS_PRINT_DEBUG, "\n FHI Not supported for node %d", node_index); + val_print(DEBUG, "\n FHI Not supported for node %d", node_index); } else { test_skip = 0; /* FHI Support, Check for PPI */ if ((fhi_id < 16) || (fhi_id > 31)) { - val_print(ACS_PRINT_ERR, "\n FHI Not PPI for node %d", node_index); + val_print(ERROR, "\n FHI Not PPI for node %d", node_index); fail_cnt++; continue; } diff --git a/test_pool/ras/ras016.c b/test_pool/ras/ras016.c index e367c3e3..b244a9a6 100644 --- a/test_pool/ras/ras016.c +++ b/test_pool/ras/ras016.c @@ -41,11 +41,11 @@ payload() /* Check that the PE implements RAS System Architecture v2 */ ras_field = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 28, 31); - val_print(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.RAS : %x", ras_field); + val_print(DEBUG, "\n ID_AA64PFR0_EL1.RAS : %x", ras_field); if (ras_field < RAS_VERSION_2) { - val_print(ACS_PRINT_ERR, "\n RASv2 not implemented (ID_AA64PFR0_EL1.RAS = 0x%x).", + val_print(ERROR, "\n RASv2 not implemented (ID_AA64PFR0_EL1.RAS = 0x%x).", ras_field); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; @@ -55,7 +55,7 @@ payload() status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_nodes); if (status || (num_nodes == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS Nodes not found. ", 0); + val_print(ERROR, "\n RAS Nodes not found. "); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -66,7 +66,7 @@ payload() /* Get Error Record number for this Node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index : %d", node_index); + val_print(DEBUG, "\n Could not get Start Index : %d", node_index); fail_cnt++; continue; } @@ -75,7 +75,7 @@ payload() regval = val_ras_reg_read(node_index, RAS_ERR_FR, rec_index); if (regval == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Node %d: couldn't read ERR<0>FR register.", node_index); fail_cnt++; @@ -85,15 +85,15 @@ payload() /* RV field [28] must be nonzero */ if (!(regval & ERR_FR_RV_MASK)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Node %d: FEAT_RASSA_RV not implemented.", node_index); fail_cnt++; continue; } - val_print(ACS_PRINT_INFO, "\n Node %d: ", node_index); - val_print(ACS_PRINT_INFO, "\n FEAT_RASSA_RV implemented (ERR_FR = 0x%llx).", regval); + val_print(TRACE, "\n Node %d: ", node_index); + val_print(TRACE, "\n FEAT_RASSA_RV implemented (ERR_FR = 0x%llx).", regval); } if (fail_cnt) diff --git a/test_pool/ras/ras017.c b/test_pool/ras/ras017.c index 4327329d..04b21267 100644 --- a/test_pool/ras/ras017.c +++ b/test_pool/ras/ras017.c @@ -41,10 +41,10 @@ payload(void) /* Check that the PE implements RAS System Architecture v2 */ ras_field = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 28, 31); - val_print(ACS_PRINT_DEBUG, "\n ID_AA64PFR0_EL1.RAS : %x", ras_field); + val_print(DEBUG, "\n ID_AA64PFR0_EL1.RAS : %x", ras_field); if (ras_field < RAS_VERSION_2) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RASv2 not implemented (ID_AA64PFR0_EL1.RAS = 0x%x).", ras_field); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); @@ -54,7 +54,7 @@ payload(void) /* Get number of RAS nodes */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_nodes); if (status || (num_nodes == 0)) { - val_print(ACS_PRINT_ERR, "\n RAS Nodes not found. ", 0); + val_print(ERROR, "\n RAS Nodes not found. "); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -64,7 +64,7 @@ payload(void) /* Get Node Type */ status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + val_print(DEBUG, "\n Node Type not found index %d", node_index); fail_cnt++; break; } @@ -76,7 +76,7 @@ payload(void) if (value == NODE_TYPE_PE) { status = val_ras_get_info(RAS_INFO_PE_RES_TYPE, node_index, &value); if (status) { - val_print(ACS_PRINT_DEBUG, "\n PE Resource type not found index %d", + val_print(DEBUG, "\n PE Resource type not found index %d", node_index); fail_cnt++; break; @@ -88,7 +88,7 @@ payload(void) /* Get first record index for this node */ status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Could not get Start Index for index %d", + val_print(DEBUG, "\n Could not get Start Index for index %d", node_index); fail_cnt++; continue; @@ -97,7 +97,7 @@ payload(void) /* Read ERRFR */ regval = val_ras_reg_read(node_index, RAS_ERR_FR, rec_index); if (regval == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>FR register.", rec_index); fail_cnt++; continue; @@ -107,7 +107,7 @@ payload(void) if ((regval & ERR_FR_CEC_MASK) != 0) { /* CED field [30] must be nonzero */ if ((regval & ERR_FR_CED_MASK) == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Node %d: FEAT_RASSA_CED not implemented.", node_index); fail_cnt++; @@ -120,7 +120,7 @@ payload(void) if (fi_field == 2 || fi_field == 3) { /* DFI field [27:26] must be nonzero */ if ((regval & ERR_FR_DFI_MASK) == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Node %d: FEAT_RASSA_DFI not implemented (FR bits[27:26] == 0).", node_index); fail_cnt++; diff --git a/test_pool/ras/ras018.c b/test_pool/ras/ras018.c index fcabb39c..4453ccef 100644 --- a/test_pool/ras/ras018.c +++ b/test_pool/ras/ras018.c @@ -39,7 +39,7 @@ esr(uint64_t interrupt_type, void *context) /* Update the ELR to return to test specified address */ val_pe_update_elr(context, (uint64_t)branch_to_test); - val_print(ACS_PRINT_ERR, "\n Received exception of type: 0x%llx", interrupt_type); + val_print(ERROR, "\n Received exception of type: 0x%llx", interrupt_type); } static @@ -68,26 +68,24 @@ payload() /* Read ID_AA64MMFR3_EL1.ADERR[59:56] == 0b0010 or 0b0011 indicate FEAT_ADERR support */ aderr = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR3_EL1), 56, 59); - val_print(ACS_PRINT_INFO, "\n ID_AA64MMFR3_EL1.ADERR field = 0x%llx", aderr); + val_print(TRACE, "\n ID_AA64MMFR3_EL1.ADERR field = 0x%llx", aderr); if (aderr == FEAT_ADERR_VAL2 || aderr == FEAT_ADERR_VAL3) { - val_print(ACS_PRINT_INFO, "\n FEAT_ADERR implemented.", 0); + val_print(TRACE, "\n FEAT_ADERR implemented."); val_set_status(index, RESULT_PASS(TEST_NUM, 01)); return; } - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n FEAT_ADERR not implemented. " - "Proceeding to synchronous Data Abort test.", - 0); + "Proceeding to synchronous Data Abort test."); /* get number of nodes with RAS functionality */ status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS nodes not found. " - "Firmware interface is missing. Please conduct a paper-based analysis.", - 0); + "Firmware interface is missing. Please conduct a paper-based analysis."); val_set_status(index, RESULT_WARN(TEST_NUM, 01)); return; } @@ -101,8 +99,8 @@ payload() status |= val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err); if (status || (intf_type != RAS_INTERFACE_MMIO) || (num_err == 0)) { - val_print(ACS_PRINT_DEBUG, "\n intf_type: 0x%llx", intf_type); - val_print(ACS_PRINT_DEBUG, "\n num_err: 0x%llx", num_err); + val_print(DEBUG, "\n intf_type: 0x%llx", intf_type); + val_print(DEBUG, "\n num_err: 0x%llx", num_err); continue; } @@ -111,20 +109,20 @@ payload() dev_addr = val_memory_get_addr(MEM_TYPE_DEVICE, 0, &attr); if (!dev_addr) { - val_print(ACS_PRINT_ERR, - "\n Failed to obtain Device memory address.\n", 0); + val_print(ERROR, + "\n Failed to obtain Device memory address.\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } - val_print(ACS_PRINT_INFO, + val_print(TRACE, "\n Using Device memory address: 0x%llx\n", dev_addr); /* Install sync and async handlers to handle exceptions.*/ status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_print(ERROR, "\n Failed in installing the exception handler"); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -144,7 +142,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_setup_error failed, node %d", node_index); fail_cnt++; break; } @@ -158,7 +156,7 @@ payload() warn_cnt++; break; } else if (status) { - val_print(ACS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + val_print(ERROR, "\n val_ras_inject_error failed, node %d", node_index); fail_cnt++; break; } @@ -170,22 +168,22 @@ payload() * system to record the error with address syndrome in one of * the error records present for the current RAS node */ read_data = val_mmio_read(dev_addr); - val_print(ACS_PRINT_DEBUG, "\n Error injected address: 0x%llx", dev_addr); - val_print(ACS_PRINT_DEBUG, "\n Data read: 0x%lx", read_data); + val_print(DEBUG, "\n Error injected address: 0x%llx", dev_addr); + val_print(DEBUG, "\n Data read: 0x%lx", read_data); exception_return: - val_print(ACS_PRINT_INFO, "\n value esr_pending, %d", esr_pending); + val_print(TRACE, "\n value esr_pending, %d", esr_pending); /* Check that a synchronous Data Abort was received */ if (esr_pending) { - val_print(ACS_PRINT_DEBUG, "\n Data abort Check Fail, for node %d", node_index); + val_print(DEBUG, "\n Data abort Check Fail, for node %d", node_index); fail_cnt++; continue; } } if (usable_node_cnt == 0) { - val_print(ACS_PRINT_INFO, - "\n No usable MMIO RAS nodes -- skipping test.\n", 0); + val_print(TRACE, + "\n No usable MMIO RAS nodes -- skipping test.\n"); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } diff --git a/test_pool/smmu/i001.c b/test_pool/smmu/i001.c index 5cb8056d..1270a9f0 100644 --- a/test_pool/smmu/i001.c +++ b/test_pool/smmu/i001.c @@ -35,7 +35,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -49,7 +49,7 @@ payload() } } if ((smmuv2_flag) && (smmuv3_flag)) { - val_print(ACS_PRINT_ERR, "\n ALL SMMUs are not of the same Architecture version\n", 0); + val_print(ERROR, "\n ALL SMMUs are not of the same Architecture version\n"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/smmu/i002.c b/test_pool/smmu/i002.c index 47151cc5..8e793154 100644 --- a/test_pool/smmu/i002.c +++ b/test_pool/smmu/i002.c @@ -39,7 +39,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -69,7 +69,7 @@ payload() * addressing. i.e data_oas == 0x6*/ if ((is_smmu_4k != 1) && (data_oas != 0x6)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print(ACS_PRINT_ERR, "\n PE supports 4kB granule and FEAT_LPA2 is " + val_print(ERROR, "\n PE supports 4kB granule and FEAT_LPA2 is " "implemented, but SMMU %x does not support 52 bit " "addressing", num_smmu); return; @@ -84,7 +84,7 @@ payload() * addressing. i.e data_oas == 0x6*/ if ((is_smmu_16k != 1) && (data_oas != 0x6)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); - val_print(ACS_PRINT_ERR, "\n PE supports 16kB granule and FEAT_LPA2 is " + val_print(ERROR, "\n PE supports 16kB granule and FEAT_LPA2 is " "implemented, but SMMU %x does not support 52 bit " " addressing", num_smmu); return; @@ -96,7 +96,7 @@ payload() (VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x2)) { if (is_smmu_4k != 1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); - val_print(ACS_PRINT_ERR, "\n PE supports 4kB granules, " + val_print(ERROR, "\n PE supports 4kB granules, " "but SMMU %x does not", num_smmu); return; } @@ -107,7 +107,7 @@ payload() (VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x2)) { if (is_smmu_16k != 1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); - val_print(ACS_PRINT_ERR, "\n PE supports 16kB granules, " + val_print(ERROR, "\n PE supports 16kB granules, " "but SMMU %x does not", num_smmu); return; } @@ -118,7 +118,7 @@ payload() (VAL_EXTRACT_BITS(data_pe_mmfr0, 36, 39) == 0x2)) { if (is_smmu_64k != 1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); - val_print(ACS_PRINT_ERR, "\n PE supports 64kB granules, " + val_print(ERROR, "\n PE supports 64kB granules, " "but SMMU %x does not", num_smmu); return; } diff --git a/test_pool/smmu/i003.c b/test_pool/smmu/i003.c index 79c44866..acfa9900 100644 --- a/test_pool/smmu/i003.c +++ b/test_pool/smmu/i003.c @@ -38,17 +38,17 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } /* Check if uefi memory map has any 52 bit addr */ memmap_addr_52bit = val_memory_region_has_52bit_addr(); - val_print(ACS_PRINT_DEBUG, "\n uefi mem map has 52 bit addr: %d", memmap_addr_52bit); + val_print(DEBUG, "\n uefi mem map has 52 bit addr: %d", memmap_addr_52bit); data_pa_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 0, 3); - val_print(ACS_PRINT_DEBUG, "\n PE pa range value: %d", data_pa_range); + val_print(DEBUG, "\n PE pa range value: %d", data_pa_range); while (num_smmu--) { /* SMMUv2 does not support 52 bit OAS */ @@ -57,8 +57,8 @@ payload() if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { data_oas = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, num_smmu), 0, 2); - val_print(ACS_PRINT_DEBUG, "\n SMMU %d OAS value:", num_smmu); - val_print(ACS_PRINT_DEBUG, " %d", data_oas); + val_print(DEBUG, "\n SMMU %d OAS value:", num_smmu); + val_print(DEBUG, " %d", data_oas); /* check if smmuv3 supporting 52 bit oas */ if (data_oas != 0x6) smmu_52bit = smmu_52bit & 0; @@ -71,8 +71,8 @@ payload() } if (((smmu_52bit == 0) || (data_pa_range != 0x6)) && memmap_addr_52bit) { - val_print(ACS_PRINT_ERR, "\n PE or SMMU doesn't support 52-bit, \ - but uefi mem map has 52-bit addr", 0); + val_print(ERROR, "\n PE or SMMU doesn't support 52-bit, \ + but uefi mem map has 52-bit addr"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } diff --git a/test_pool/smmu/i004.c b/test_pool/smmu/i004.c index 9e1015a4..8e592e35 100644 --- a/test_pool/smmu/i004.c +++ b/test_pool/smmu/i004.c @@ -50,7 +50,7 @@ payload(void *arg) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(test_data->test_num, 1)); return; } @@ -66,8 +66,8 @@ payload(void *arg) s1ts = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv2_IDR0, num_smmu), 30, 30); // Stage 1 translation functionality cannot be provided by SMMU v2 revision if (!s1ts) { - val_print(ACS_PRINT_ERR, - "\n SMMUv2 not providing Stage1 functionality ", 0); + val_print(ERROR, + "\n SMMUv2 not providing Stage1 functionality "); val_set_status(index, RESULT_FAIL(test_data->test_num, 1)); return; } @@ -80,21 +80,21 @@ payload(void *arg) s1p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 1, 1); // Stage 1 translation functionality cannot be provided by SMMU v3.0/3.1 revisions if (!s1p) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3.%d not providing Stage1 functionality ", minor); val_set_status(index, RESULT_FAIL(test_data->test_num, 2)); return; } } else { /* If both PE & SMMU Implement S_EL2, Skip this test */ - val_print(ACS_PRINT_DEBUG, "\n S-EL2 implemented...Skipping", 0); + val_print(DEBUG, "\n S-EL2 implemented...Skipping"); val_set_status(index, RESULT_SKIP(test_data->test_num, 2)); return; } } if (smmu_rev < 2) { - val_print(ACS_PRINT_ERR, - "\n SMMU revision must be at least v2 ", 0); + val_print(ERROR, + "\n SMMU revision must be at least v2 "); val_set_status(index, RESULT_FAIL(test_data->test_num, 3)); return; } diff --git a/test_pool/smmu/i005.c b/test_pool/smmu/i005.c index 87d70022..283410ba 100644 --- a/test_pool/smmu/i005.c +++ b/test_pool/smmu/i005.c @@ -41,7 +41,7 @@ test_status_t check_smmu_stg2_support (void) /* Get total number of SMMUs present in the system */ num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); return TEST_FAIL; } @@ -52,7 +52,7 @@ test_status_t check_smmu_stg2_support (void) /* Check for SMMUv2 stage 2 support by reading SMMUv2_IDR0 29th bit*/ s2ts = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv2_IDR0, i), 29, 29); if (!s2ts) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv2 index: 0x%x not providing Stage2 functionality", i); fail_cnt++; } @@ -60,12 +60,12 @@ test_status_t check_smmu_stg2_support (void) /* Read SMMUv3_IDR0 bit 0 for stage 2 translation support */ s2p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, i), 0, 0); if (!s2p) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3 index: 0x%x not providing Stage2 functionality", i); fail_cnt++; } } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv%d register read is not supported", smmu_rev); fail_cnt++; } @@ -110,7 +110,7 @@ payload_check_sel2_and_smmu_stg2_support() /* Skip the test if Secure EL2 is implemented */ if (pe_s_el2 == 0x1) { - val_print(ACS_PRINT_DEBUG, "\n Secure EL2 is supported, skipping the test.", 0); + val_print(DEBUG, "\n Secure EL2 is supported, skipping the test."); val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); return; } diff --git a/test_pool/smmu/i006.c b/test_pool/smmu/i006.c index 1885d22b..d57557db 100644 --- a/test_pool/smmu/i006.c +++ b/test_pool/smmu/i006.c @@ -33,22 +33,22 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered ", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { - val_print(ACS_PRINT_DEBUG, "\n Not valid for SMMU v3 ", 0); + val_print(DEBUG, "\n Not valid for SMMU v3 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } if (!val_iovirt_check_unique_ctx_intid(num_smmu)) { val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print(ACS_PRINT_ERR, "\n Unique interrupt ID per context bank check " - "failed for SMMU %x", 0); + val_print(ERROR, "\n Unique interrupt ID per context bank check " + "failed for SMMU %x"); return; } } diff --git a/test_pool/smmu/i007.c b/test_pool/smmu/i007.c index 3d84bbad..9822087a 100644 --- a/test_pool/smmu/i007.c +++ b/test_pool/smmu/i007.c @@ -36,7 +36,7 @@ payload() data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (data == 0) { - val_print(ACS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_print(WARN, "\n PCIe Subsystem not discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -44,14 +44,14 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -59,7 +59,7 @@ payload() data = val_smmu_read_cfg(SMMUv3_IDR0, num_smmu); // Check I/O coherent access if (VAL_EXTRACT_BITS(data, 4, 4) == 0) { - val_print(ACS_PRINT_ERR, "\n\t IO-Coherent access not supported ", 0); + val_print(ERROR, "\n\t IO-Coherent access not supported "); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/smmu/i008.c b/test_pool/smmu/i008.c index 04419455..167090b7 100644 --- a/test_pool/smmu/i008.c +++ b/test_pool/smmu/i008.c @@ -43,7 +43,7 @@ payload_check_smmu_stg1_support(void) num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered.", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered."); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -51,16 +51,16 @@ payload_check_smmu_stg1_support(void) while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMUv3, or higher must be supported.", 0); + val_print(ERROR, + "\n SMMUv3, or higher must be supported."); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } else { - val_print(ACS_PRINT_INFO, "\n Detected SMMUv3, or higher implementation ", 0); + val_print(TRACE, "\n Detected SMMUv3, or higher implementation "); data = val_smmu_read_cfg(SMMUv3_IDR0, num_smmu); /* Check Stage 1 translation support */ if ((data & BIT1) == 0) { - val_print(ACS_PRINT_ERR, "\n Stage 1 translation not supported ", 0); + val_print(ERROR, "\n Stage 1 translation not supported "); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -80,7 +80,7 @@ payload_check_smmu_stg2_support(void) num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered.", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered."); val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); return; } @@ -88,16 +88,16 @@ payload_check_smmu_stg2_support(void) while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMUv3, or higher must be supported.", 0); + val_print(ERROR, + "\n SMMUv3, or higher must be supported."); val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); return; } else { - val_print(ACS_PRINT_INFO, "\n Detected SMMUv3, or higher implementation ", 0); + val_print(TRACE, "\n Detected SMMUv3, or higher implementation "); data = val_smmu_read_cfg(SMMUv3_IDR0, num_smmu); /* Check Stage 2 translation support */ if ((data & BIT0) == 0) { - val_print(ACS_PRINT_ERR, "\n Stage 2 translation not supported ", 0); + val_print(ERROR, "\n Stage 2 translation not supported "); val_set_status(index, RESULT_FAIL(TEST_NUM1, 03)); return; } diff --git a/test_pool/smmu/i009.c b/test_pool/smmu/i009.c index a729d349..f25acecd 100644 --- a/test_pool/smmu/i009.c +++ b/test_pool/smmu/i009.c @@ -43,7 +43,7 @@ check_smmuv3_2_or_higher(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); return; } @@ -51,15 +51,15 @@ check_smmuv3_2_or_higher(void) while (num_smmu--) { /* Read SMMU major version */ if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMU implementation must be SMMUv3.2 or higher required.", 0); + val_print(ERROR, + "\n SMMU implementation must be SMMUv3.2 or higher required."); fail_cnt++; } else { /* Read SMMU minor version */ data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 7); if (data < 0x2) { /* SMMUv3.2 or higher not implemented */ - val_print(ACS_PRINT_ERR, - "\n SMMU implementation must be SMMUv3.2 or higher required.", 0); + val_print(ERROR, + "\n SMMU implementation must be SMMUv3.2 or higher required."); fail_cnt++; } } @@ -86,7 +86,7 @@ payload_check_l1_l2_table_resizing(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM1, 01)); return; } @@ -98,16 +98,16 @@ payload_check_l1_l2_table_resizing(void) data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR3, num_smmu), 11, 12); /* Non zero value indicates either level or level 2 is supported */ if (data == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMU index = 0x%x doesn't provide level 1 or level 2 support." , num_smmu); fail_cnt++; } } else { /* SMMU_IDR3.BBML is SMMUv3 register check */ - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv2 implementations cannot provide level 1 or level 2 support." - , 0); + ); fail_cnt++; } } @@ -131,7 +131,7 @@ payload_check_smmuv3_3_or_higher(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM2, 01)); return; } @@ -139,15 +139,15 @@ payload_check_smmuv3_3_or_higher(void) while (num_smmu--) { /* Read SMMU major version */ if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMU implementation must be SMMUv3.3 or higher required.", 0); + val_print(ERROR, + "\n SMMU implementation must be SMMUv3.3 or higher required."); fail_cnt++; } else { /* Read SMMU minor version */ data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 7); if (data < 0x3) { /* SMMUv3.3 or higher not implemented */ - val_print(ACS_PRINT_ERR, - "\n SMMU implementation must be SMMUv3.3 or higher required.", 0); + val_print(ERROR, + "\n SMMU implementation must be SMMUv3.3 or higher required."); fail_cnt++; } diff --git a/test_pool/smmu/i010.c b/test_pool/smmu/i010.c index 655a2e73..3c971490 100644 --- a/test_pool/smmu/i010.c +++ b/test_pool/smmu/i010.c @@ -41,14 +41,14 @@ payload() s_el2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 36, 39); if (!s_el2) { - val_print(ACS_PRINT_ERR, "\n Secure EL2 not implemented", 0); + val_print(ERROR, "\n Secure EL2 not implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -57,21 +57,21 @@ payload() smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); if (smmu_rev < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMUv2 or lower detected: revision must be v3.2 or higher ", 0); + val_print(ERROR, + "\n SMMUv2 or lower detected: revision must be v3.2 or higher "); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } else { minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); if (minor < 2) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } s1p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 1, 1); if (!s1p) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3.%d detected: but " "Stage 1 translation not supported ", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); diff --git a/test_pool/smmu/i011.c b/test_pool/smmu/i011.c index 23020db9..1a75df75 100644 --- a/test_pool/smmu/i011.c +++ b/test_pool/smmu/i011.c @@ -41,14 +41,14 @@ payload() s_el2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 36, 39); if (!s_el2) { - val_print(ACS_PRINT_ERR, "\n Secure EL2 not implemented", 0); + val_print(ERROR, "\n Secure EL2 not implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -57,21 +57,21 @@ payload() smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); if (smmu_rev < 3) { - val_print(ACS_PRINT_ERR, - "\n SMMUv2 or lower detected: revision must be v3.2 or higher ", 0); + val_print(ERROR, + "\n SMMUv2 or lower detected: revision must be v3.2 or higher "); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } else { minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); if (minor < 2) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } s2p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 0, 0); if (!s2p) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n SMMUv3.%d detected: but Stage 2 " "translation not supported ", minor); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); diff --git a/test_pool/smmu/i012.c b/test_pool/smmu/i012.c index 2145c853..4bab05bb 100644 --- a/test_pool/smmu/i012.c +++ b/test_pool/smmu/i012.c @@ -46,13 +46,13 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered ", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } if (!(pe_mpam || frac)) { - val_print(ACS_PRINT_DEBUG, "\n No MPAM controlled resources present ", 0); + val_print(DEBUG, "\n No MPAM controlled resources present "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -61,7 +61,7 @@ payload() smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); if (smmu_rev < 3) { /* MPAM support not required for SMMUv2 and below */ - val_print(ACS_PRINT_DEBUG, "\n SMMU revision v2 or lower detected ", 0); + val_print(DEBUG, "\n SMMU revision v2 or lower detected "); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -76,16 +76,16 @@ payload() max_id = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_MPAMIDR, num_smmu), 0, 15); if (!(mpam && max_id)) { - val_print(ACS_PRINT_ERR, - "\n SMMU without MPAM support detected ", 0); + val_print(ERROR, + "\n SMMU without MPAM support detected "); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } } else { /* MPAM support not required for SMMUv3.0/3.1 */ - val_print(ACS_PRINT_WARN, - "\n SMMU revision v3.0/3.1 detected ", 0); + val_print(WARN, + "\n SMMU revision v3.0/3.1 detected "); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } diff --git a/test_pool/smmu/i013.c b/test_pool/smmu/i013.c index 1b6cfd80..c29317dd 100644 --- a/test_pool/smmu/i013.c +++ b/test_pool/smmu/i013.c @@ -37,14 +37,14 @@ payload(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; } diff --git a/test_pool/smmu/i014.c b/test_pool/smmu/i014.c index 7028504b..b03d0568 100644 --- a/test_pool/smmu/i014.c +++ b/test_pool/smmu/i014.c @@ -37,14 +37,14 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; } diff --git a/test_pool/smmu/i015.c b/test_pool/smmu/i015.c index c58c73c9..bdb7e77d 100644 --- a/test_pool/smmu/i015.c +++ b/test_pool/smmu/i015.c @@ -40,14 +40,14 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -56,7 +56,7 @@ payload() if (!data && pe_vmid) { val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print(ACS_PRINT_ERR, "\n 16 bit VMID not " + val_print(ERROR, "\n 16 bit VMID not " "supported for SMMU %x", num_smmu); return; } diff --git a/test_pool/smmu/i016.c b/test_pool/smmu/i016.c index 7068b48a..20a63f79 100644 --- a/test_pool/smmu/i016.c +++ b/test_pool/smmu/i016.c @@ -37,21 +37,21 @@ payload() data_va_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 16, 19); if (data_va_range == 0) { - val_print(ACS_PRINT_DEBUG, "\n Large VA Not Supported by PE ", 0); + val_print(DEBUG, "\n Large VA Not Supported by PE "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Large VA Not Supported in SMMUv2", 0); + val_print(WARN, "\n Large VA Not Supported in SMMUv2"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } @@ -61,7 +61,7 @@ payload() /* If PE Supports Large VA Range then SMMU_IDR5.VAX = 0b01 */ if (data_va_range == 1) { if (data_vax != 1) { - val_print(ACS_PRINT_ERR, "\n Large VA Not Supported in SMMU %x", num_smmu); + val_print(ERROR, "\n Large VA Not Supported in SMMU %x", num_smmu); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } diff --git a/test_pool/smmu/i017.c b/test_pool/smmu/i017.c index 99e99259..2cc008dd 100644 --- a/test_pool/smmu/i017.c +++ b/test_pool/smmu/i017.c @@ -37,24 +37,24 @@ payload() data_pe_tlb = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 56, 59); if (data_pe_tlb != 0x2) { - val_print(ACS_PRINT_DEBUG, "\n TLB Range Invalid Not " - "Supported For PE ", 0); + val_print(DEBUG, "\n TLB Range Invalid Not " + "Supported For PE "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered" - " ", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered" + " "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_DEBUG, "\n Not valid for SMMUv2 or older" - "version ", 0); + val_print(DEBUG, "\n Not valid for SMMUv2 or older" + "version "); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -64,7 +64,7 @@ payload() /* If PE TLB Range Invalidation then SMMU_IDR3.RIL = 0b1 */ if (data_pe_tlb == 0x2) { if (data_ril != 0x1) { - val_print(ACS_PRINT_ERR, "\n Range Invalidation unsupported " + val_print(ERROR, "\n Range Invalidation unsupported " "for SMMU %x", num_smmu); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/smmu/i018.c b/test_pool/smmu/i018.c index 4c6ef03e..60884567 100644 --- a/test_pool/smmu/i018.c +++ b/test_pool/smmu/i018.c @@ -41,14 +41,14 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -60,7 +60,7 @@ payload() if (s1p && !asid && pe_asid) { val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print(ACS_PRINT_ERR, "\n 16 bit ASID unsupported " + val_print(ERROR, "\n 16 bit ASID unsupported " "for SMMU %x", num_smmu); return; } diff --git a/test_pool/smmu/i019.c b/test_pool/smmu/i019.c index 6e257ceb..f901ae01 100644 --- a/test_pool/smmu/i019.c +++ b/test_pool/smmu/i019.c @@ -40,7 +40,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -54,7 +54,7 @@ payload() while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -64,13 +64,13 @@ payload() if ((data_pe_endian == 1) && ((data == 1) || (data == 2))) { /* If PE supports big endian */ val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); - val_print(ACS_PRINT_ERR, "\n PE supports big endian, " + val_print(ERROR, "\n PE supports big endian, " "but SMMU %x does not", num_smmu); return; } else if ((data_pe_endian == 0) && ((data == 1) || (data == 3))) { /* If PE supports little endian */ val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); - val_print(ACS_PRINT_ERR, "\n PE supports little endian, " + val_print(ERROR, "\n PE supports little endian, " "but SMMU %x does not", num_smmu); return; } diff --git a/test_pool/smmu/i020.c b/test_pool/smmu/i020.c index a25e21b3..01c86cbf 100644 --- a/test_pool/smmu/i020.c +++ b/test_pool/smmu/i020.c @@ -40,14 +40,14 @@ payload(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; } diff --git a/test_pool/smmu/i021.c b/test_pool/smmu/i021.c index c3e7f6d6..7fe6e0d3 100644 --- a/test_pool/smmu/i021.c +++ b/test_pool/smmu/i021.c @@ -51,19 +51,19 @@ check_smmu_pmcg(uint32_t check_counter) num_pmcg = val_iovirt_get_pmcg_info(PMCG_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered ", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered "); return ACS_STATUS_SKIP; } else if (num_pmcg == 0) { /* If SMMUs are present in system and no PMCGs detected, report test as FAIL*/ - val_print(ACS_PRINT_ERR, "\n SMMUs in the system don't implement SMMUv3" - " Performance Monitors Extension ", 0); + val_print(ERROR, "\n SMMUs in the system don't implement SMMUv3" + " Performance Monitors Extension "); return ACS_STATUS_FAIL; } while (num_smmu--) { smmu_version = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); if (smmu_version != 3) { - val_print(ACS_PRINT_DEBUG, "\n Valid for only SMMU v3, smmu version %d", + val_print(DEBUG, "\n Valid for only SMMU v3, smmu version %d", smmu_version); continue; } @@ -81,7 +81,7 @@ check_smmu_pmcg(uint32_t check_counter) /* Check if PMCG node memory is mapped. If not, map it */ status = val_mmu_update_entry(pmcg_base, SIZE_4KB, DEVICE_nGnRnE); if (status) { - val_print(ACS_PRINT_ERR, "\n Could not map PMCG node memory", 0); + val_print(ERROR, "\n Could not map PMCG node memory"); return ACS_STATUS_FAIL; } @@ -90,9 +90,9 @@ check_smmu_pmcg(uint32_t check_counter) /* If checking counter count, ensure there are at least 4 */ if (check_counter && num_pmcg_count < 4) { - val_print(ACS_PRINT_ERR, "\n PMCG has less than 4 counters for SMMU" + val_print(ERROR, "\n PMCG has less than 4 counters for SMMU" "index : %d", num_smmu); - val_print(ACS_PRINT_ERR, "\n Number of PMCG counters : %d", + val_print(ERROR, "\n Number of PMCG counters : %d", num_pmcg_count); test_fail++; } @@ -102,7 +102,7 @@ check_smmu_pmcg(uint32_t check_counter) } if (num_pmcg_found == 0) { - val_print(ACS_PRINT_ERR, "\n PMU Extension not implemented for SMMU index : %d", + val_print(ERROR, "\n PMU Extension not implemented for SMMU index : %d", num_smmu); test_fail++; } diff --git a/test_pool/smmu/i022.c b/test_pool/smmu/i022.c index 8e5ebeba..502b936c 100644 --- a/test_pool/smmu/i022.c +++ b/test_pool/smmu/i022.c @@ -44,16 +44,16 @@ payload() num_dma_req = num_pcie_rc; for (i = 0; i < num_pcie_rc; i++) { /* print info fields */ - val_print(ACS_PRINT_DEBUG, "\n RC segment no : 0x%llx", + val_print(DEBUG, "\n RC segment no : 0x%llx", val_iovirt_get_pcie_rc_info(RC_SEGMENT_NUM, i)); - val_print(ACS_PRINT_DEBUG, "\n CCA attribute : 0x%x", + val_print(DEBUG, "\n CCA attribute : 0x%x", val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, i)); - val_print(ACS_PRINT_DEBUG, "\n SMMU base addr : 0x%llx\n", + val_print(DEBUG, "\n SMMU base addr : 0x%llx\n", val_iovirt_get_pcie_rc_info(RC_SMMU_BASE, i)); if (val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, i) == 0x1 && val_iovirt_get_pcie_rc_info(RC_SMMU_BASE, i) == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DMA capable PCIe root port with segment no: %llx not behind a SMMU.", val_iovirt_get_pcie_rc_info(RC_SEGMENT_NUM, i)); test_fails++; @@ -65,20 +65,20 @@ payload() num_dma_req += num_named_comp; for (i = 0; i < num_named_comp; i++) { /* print info fields */ - val_print(ACS_PRINT_DEBUG, "\n Named component :", 0); - val_print(ACS_PRINT_DEBUG, - (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i), 0); - val_print(ACS_PRINT_DEBUG, "\n CCA attribute : 0x%x", + val_print(DEBUG, "\n Named component :"); + val_print(DEBUG, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i)); + val_print(DEBUG, "\n CCA attribute : 0x%x", val_iovirt_get_named_comp_info(NAMED_COMP_CCA_ATTR, i)); - val_print(ACS_PRINT_DEBUG, "\n SMMU base addr : 0x%llx\n", + val_print(DEBUG, "\n SMMU base addr : 0x%llx\n", val_iovirt_get_named_comp_info(NAMED_COMP_SMMU_BASE, i)); if (val_iovirt_get_named_comp_info(NAMED_COMP_CCA_ATTR, i) == 0x1 && val_iovirt_get_named_comp_info(NAMED_COMP_SMMU_BASE, i) == 0) { - val_print(ACS_PRINT_ERR, - "\n DMA capable named component with namespace path: ", 0); - val_print(ACS_PRINT_ERR, - (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i), 0); - val_print(ACS_PRINT_ERR, " not behind a SMMU.", 0); + val_print(ERROR, + "\n DMA capable named component with namespace path: "); + val_print(ERROR, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i)); + val_print(ERROR, " not behind a SMMU."); test_fails++; } } @@ -86,7 +86,7 @@ payload() if (test_fails) val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); else if (!num_dma_req) { - val_print(ACS_PRINT_DEBUG, "\n No DMA requestors present", 0); + val_print(DEBUG, "\n No DMA requestors present"); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); } else { val_set_status(index, RESULT_PASS(TEST_NUM, 01)); diff --git a/test_pool/smmu/i023.c b/test_pool/smmu/i023.c index 42ab1792..9e1f5c8a 100644 --- a/test_pool/smmu/i023.c +++ b/test_pool/smmu/i023.c @@ -46,13 +46,13 @@ payload(void) /*Check for ETR devices using ETR using unique HID (ARMHC97C)*/ status = val_get_device_path("ARMHC97C", etr_path); if (status != 0) { - val_print(ACS_PRINT_ERR, "\n Unable to get ETR device info from ACPI namespace", 0); + val_print(ERROR, "\n Unable to get ETR device info from ACPI namespace"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } if ((char)etr_path[0][0] == '\0') { - val_print(ACS_PRINT_ERR, "\n No ETR devices are discovered ", 0); + val_print(ERROR, "\n No ETR devices are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } else { @@ -62,19 +62,19 @@ payload(void) etr_count++; } } - val_print(ACS_PRINT_DEBUG, "\n Num of ETR devices found etr_count: %d ", etr_count); + val_print(DEBUG, "\n Num of ETR devices found etr_count: %d ", etr_count); num_named_comp = val_iovirt_get_named_comp_info(NUM_NAMED_COMP, 0); - val_print(ACS_PRINT_DEBUG, "\n NUM Named component : %d", num_named_comp); + val_print(DEBUG, "\n NUM Named component : %d", num_named_comp); /*ETR device must be behind SMMU or CATU*/ for (i = 0; i < etr_count; i++) { for (j = 0; j < num_named_comp; j++) { smmu_found = 0; /* print info fields */ - val_print(ACS_PRINT_DEBUG, "\n Named component :", 0); - val_print(ACS_PRINT_DEBUG, - (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, j), 0); + val_print(DEBUG, "\n Named component :"); + val_print(DEBUG, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, j)); /*Check the ETR and Named Componnet paths are matching*/ if (!val_strncmp((char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, j), @@ -91,17 +91,17 @@ payload(void) /*SMMU not found in ETR path, check for CATU*/ if (!smmu_found) { /*Check for CATU in the path of ETR device*/ - val_print(ACS_PRINT_DEBUG, "\n SMMU not found in ETR Path at index %d", i); + val_print(DEBUG, "\n SMMU not found in ETR Path at index %d", i); /*Check the CATU in ETR path*/ status = val_smmu_is_etr_behind_catu((char8_t *)etr_path[i]); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_print(ACS_PRINT_DEBUG, - "\n val_smmu_is_etr_behind_catu API not implemented", 0); + val_print(DEBUG, + "\n val_smmu_is_etr_behind_catu API not implemented"); val_set_status(index, RESULT_WARN(TEST_NUM, 1)); return; } else if (status) { - val_print(ACS_PRINT_DEBUG, "\n No CATU found in ETR path at index %d", i); + val_print(DEBUG, "\n No CATU found in ETR path at index %d", i); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } diff --git a/test_pool/smmu/i024.c b/test_pool/smmu/i024.c index d68e8439..bc93136a 100644 --- a/test_pool/smmu/i024.c +++ b/test_pool/smmu/i024.c @@ -35,14 +35,14 @@ static void payload(void) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_print(ERROR, "\n No SMMU Controllers are discovered "); val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(ACS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_print(WARN, "\n Not valid for SMMU v2 "); val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); return; } @@ -51,7 +51,7 @@ static void payload(void) * if SMMU_IDR0.ATS[10:10] == 0b1 */ data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 10, 10); if (data != 1) { - val_print(ACS_PRINT_ERR, "\n ATS is not supported for Smmu Index : %d ", num_smmu); + val_print(ERROR, "\n ATS is not supported for Smmu Index : %d ", num_smmu); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } diff --git a/test_pool/smmu/i025.c b/test_pool/smmu/i025.c index 8c3c008a..3deda853 100644 --- a/test_pool/smmu/i025.c +++ b/test_pool/smmu/i025.c @@ -39,29 +39,29 @@ payload() /* Get cache maintenance instruction support */ data_pe_cmow = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 56, 59); if (data_pe_cmow != 0x1) { - val_print(ACS_PRINT_DEBUG, "\n Instruction Cache Invalidation Not " - "Supported For PE", 0); + val_print(DEBUG, "\n Instruction Cache Invalidation Not " + "Supported For PE"); } /* Get prediction invalidation instructions support */ data_pe_specres = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 40, 43); if (data_pe_specres == 0x0) { - val_print(ACS_PRINT_DEBUG, "\n Branch Prediction Invalidation Not " - "Supported For PE", 0); + val_print(DEBUG, "\n Branch Prediction Invalidation Not " + "Supported For PE"); } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_DEBUG, "\n No SMMU Controllers are discovered" - " ", 0); + val_print(DEBUG, "\n No SMMU Controllers are discovered" + " "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { - val_print(ACS_PRINT_DEBUG, "\n Not valid for SMMUv2 or older" - "version ", 0); + val_print(DEBUG, "\n Not valid for SMMUv2 or older" + "version "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -71,7 +71,7 @@ payload() /* Broadcast TLB Invalidation supported if SMMU_IDR0.BTM, bit[5] = 0b1 */ if (data_pe_specres || data_pe_cmow) { if (data_btm != 0x1) { - val_print(ACS_PRINT_ERR, "\n Broadcast TLB Maintenance unsupported " + val_print(ERROR, "\n Broadcast TLB Maintenance unsupported " "for SMMU %x", num_smmu); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; diff --git a/test_pool/timer/t001.c b/test_pool/timer/t001.c index 45a2f5ab..47d108e2 100644 --- a/test_pool/timer/t001.c +++ b/test_pool/timer/t001.c @@ -39,8 +39,8 @@ payload_check_system_counter_presence() counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0); if (counter_freq == 0) { - val_print(ACS_PRINT_DEBUG, "\n Generic system counter not implemented," - " CNTFRQ_EL0 = 0", 0); + val_print(DEBUG, "\n Generic system counter not implemented," + " CNTFRQ_EL0 = 0"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } else { @@ -72,9 +72,9 @@ payload_check_system_timer_freq() /* Print counter frequency in DEBUG verbosity */ if (print_mhz) - val_print(ACS_PRINT_DEBUG, "\n Counter frequency is %ld MHz", print_freq); + val_print(DEBUG, "\n Counter frequency is %ld MHz", print_freq); else - val_print(ACS_PRINT_DEBUG, "\n Counter frequency is %ld KHz", print_freq); + val_print(DEBUG, "\n Counter frequency is %ld KHz", print_freq); /* Check if Generic system counter frequency is greater than 10MHz */ if (counter_freq > 10*1000*1000) { @@ -84,9 +84,9 @@ payload_check_system_timer_freq() /* If 10Mhz check fails, print frequency in ERROR verbosity */ if (print_mhz) - val_print(ACS_PRINT_ERR, "\n Counter frequency is %ld MHz", print_freq); + val_print(ERROR, "\n Counter frequency is %ld MHz", print_freq); else - val_print(ACS_PRINT_ERR, "\n Counter frequency is %ld KHz", print_freq); + val_print(ERROR, "\n Counter frequency is %ld KHz", print_freq); val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); } diff --git a/test_pool/timer/t002.c b/test_pool/timer/t002.c index 61c6da89..2267e050 100644 --- a/test_pool/timer/t002.c +++ b/test_pool/timer/t002.c @@ -31,11 +31,11 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0) == 0) { - val_print(ACS_PRINT_INFO, "\n Physical EL1 timer flag = %x", + val_print(TRACE, "\n Physical EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0)); - val_print(ACS_PRINT_INFO, "\n Physical EL2 timer flag = %x", + val_print(TRACE, "\n Physical EL2 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0)); - val_print(ACS_PRINT_INFO, "\n Virtual EL1 timer flag = %x", + val_print(TRACE, "\n Virtual EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0)); if ((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON) && @@ -43,8 +43,8 @@ payload() (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON)) { val_set_status(index, RESULT_PASS(TEST_NUM, 1)); } else { - val_print(ACS_PRINT_ERR, "\n PE Timers are not always-on\n" - " And no system wake up timer", 0); + val_print(ERROR, "\n PE Timers are not always-on\n" + " And no system wake up timer"); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); } } else { diff --git a/test_pool/timer/t003.c b/test_pool/timer/t003.c index ab56679e..e2948913 100644 --- a/test_pool/timer/t003.c +++ b/test_pool/timer/t003.c @@ -36,7 +36,7 @@ payload() uint64_t data1; if (!timer_num) { - val_print(ACS_PRINT_DEBUG, "\n No System timers are defined ", 0); + val_print(DEBUG, "\n No System timers are defined "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -52,15 +52,15 @@ payload() cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_ctl_base == 0) { - val_print(ACS_PRINT_DEBUG, "\n CNTCTL BASE is zero ", 0); + val_print(DEBUG, "\n CNTCTL BASE is zero "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } //Read CNTACR to determine whether access permission from NS state is permitted status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); if (status == ACS_STATUS_SKIP) { - val_print(ACS_PRINT_DEBUG, - "\n Security doesn't allow access to timer registers ", 0); + val_print(DEBUG, + "\n Security doesn't allow access to timer registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -69,47 +69,47 @@ payload() data = val_mmio_read(cnt_ctl_base + CNTTIDR); val_mmio_write(cnt_ctl_base + CNTTIDR, 0xFFFFFFFF); if (data != val_mmio_read(cnt_ctl_base + CNTTIDR)) { - val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for" + val_print(DEBUG, "\n Read-write check failed for" " CNTCTLBase.CNTTIDR, expected value %x ", data); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } if (cnt_base_n == 0) { - val_print(ACS_PRINT_DEBUG, "\n CNT_BASE_N is zero ", 0); + val_print(DEBUG, "\n CNT_BASE_N is zero "); val_set_status(index, RESULT_SKIP(TEST_NUM, 4)); return; } // Read CNTPCT register data1 = val_mmio_read64(cnt_base_n + CNTPCT_LOWER); - val_print(ACS_PRINT_DEBUG, "\n CNTPCT Read value = 0x%llx ", data1); + val_print(DEBUG, "\n CNTPCT Read value = 0x%llx ", data1); // Writes to Read-Only registers must be ignored val_mmio_write64(cnt_base_n + CNTPCT_LOWER, (data1 - ARBIT_VALUE)); if (val_mmio_read64(cnt_base_n + CNTPCT_LOWER) < data1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); - val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTPCT reg must be read-only ", 0); + val_print(DEBUG, "\n CNTBaseN: CNTPCT reg must be read-only "); return; } // Read CNTVCT register data1 = val_mmio_read64(cnt_base_n + CNTVCT_LOWER); - val_print(ACS_PRINT_DEBUG, "\n CNTVCT Read value = 0x%llx ", data1); + val_print(DEBUG, "\n CNTVCT Read value = 0x%llx ", data1); // Writes to Read-Only registers must be ignored val_mmio_write64(cnt_base_n + CNTVCT_LOWER, (data1 - ARBIT_VALUE)); if (val_mmio_read64(cnt_base_n + CNTVCT_LOWER) < data1) { val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); - val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTVCT reg must be read-only ", 0); + val_print(DEBUG, "\n CNTBaseN: CNTVCT reg must be read-only "); return; } // Read CNTFRQ register data = val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ); - val_print(ACS_PRINT_DEBUG, "\n CNTFRQ Read value = 0x%x ", + val_print(DEBUG, "\n CNTFRQ Read value = 0x%x ", data); // Writes to Read-Only registers must be ignored @@ -117,7 +117,7 @@ payload() if (val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ) != data) { val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); - val_print(ACS_PRINT_DEBUG, "\n CNTBaseN: CNTFRQ reg must be read-only ", 0); + val_print(DEBUG, "\n CNTBaseN: CNTFRQ reg must be read-only "); return; } @@ -125,9 +125,9 @@ payload() data = 0x3; val_mmio_write(cnt_base_n + CNTP_CTL, data); if (data != (val_mmio_read(cnt_base_n + CNTP_CTL) & 0x3)) { - val_print(ACS_PRINT_ERR, "\n Read-write check failed for " + val_print(ERROR, "\n Read-write check failed for " "CNTBaseN.CNTP_CTL, expected value %x ", data); - val_print(ACS_PRINT_DEBUG, "\n Read value %x ", + val_print(DEBUG, "\n Read value %x ", val_mmio_read(cnt_base_n + CNTP_CTL)); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); val_mmio_write(cnt_base_n + CNTP_CTL, 0x0); // Disable the timer before return @@ -142,7 +142,7 @@ payload() val_mmio_write(cnt_base_n + CNTP_CVAL_HIGHER, data); if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER)) { - val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for " + val_print(DEBUG, "\n Read-write check failed for " "CNTBaseN.CNTP_CVAL[31:0], read value %x ", val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER)); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); @@ -150,7 +150,7 @@ payload() } if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER)) { - val_print(ACS_PRINT_DEBUG, "\n Read-write check failed for" + val_print(DEBUG, "\n Read-write check failed for" " CNTBaseN.CNTP_CVAL[63:32], read value %x ", val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER)); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); @@ -161,7 +161,7 @@ payload() } if (!ns_timer) { - val_print(ACS_PRINT_DEBUG, "\n No non-secure systimer implemented", 0); + val_print(DEBUG, "\n No non-secure systimer implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); return; } diff --git a/test_pool/timer/t004.c b/test_pool/timer/t004.c index 48c0023b..06b6cc77 100644 --- a/test_pool/timer/t004.c +++ b/test_pool/timer/t004.c @@ -34,7 +34,7 @@ isr() { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_INFO, "\n Received sys timer interrupt ", 0); + val_print(TRACE, "\n Received sys timer interrupt "); val_timer_disable_system_timer((addr_t)cnt_base_n); val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_gic_end_of_interrupt(intid); @@ -53,7 +53,7 @@ payload() uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); if (!timer_num) { - val_print(ACS_PRINT_DEBUG, "\n No System timers are defined ", 0); + val_print(DEBUG, "\n No System timers are defined "); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -71,15 +71,15 @@ payload() //Read CNTACR to determine whether access permission from NS state is permitted status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); if (status == ACS_STATUS_SKIP) { - val_print(ACS_PRINT_WARN, - "\n Security doesn't allow access to timer registers ", 0); + val_print(WARN, + "\n Security doesn't allow access to timer registers "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { - val_print(ACS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); + val_print(WARN, "\n CNT_BASE_N is zero "); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -88,14 +88,14 @@ payload() /* Check intid is SPI or ESPI */ if (!(IsSpi(intid)) && !(val_gic_is_valid_espi(intid))) { - val_print(ACS_PRINT_ERR, "\n Interrupt-%d is neither SPI nor ESPI", intid); + val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } /* Install ISR */ if (val_gic_install_isr(intid, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } @@ -107,14 +107,14 @@ payload() ; if (timeout == 0) { - val_print(ACS_PRINT_ERR, "\n Sys timer interrupt not received on %d ", intid); + val_print(ERROR, "\n Sys timer interrupt not received on %d ", intid); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } } if (!ns_timer) { - val_print(ACS_PRINT_WARN, "\n No non-secure systimer implemented", 0); + val_print(WARN, "\n No non-secure systimer implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); return; } diff --git a/test_pool/timer/t005.c b/test_pool/timer/t005.c index b2724750..5d51dde9 100644 --- a/test_pool/timer/t005.c +++ b/test_pool/timer/t005.c @@ -35,7 +35,7 @@ isr_sys_timer() val_timer_disable_system_timer((addr_t)cnt_base_n); val_gic_end_of_interrupt(intid); irq_received = 1; - val_print(ACS_PRINT_INFO, "\n System timer interrupt received", 0); + val_print(TRACE, "\n System timer interrupt received"); } static @@ -43,7 +43,7 @@ void isr_phy_el1() { val_timer_set_phy_el1(0); - val_print(ACS_PRINT_INFO, "\n Received el1_phy interrupt ", 0); + val_print(TRACE, "\n Received el1_phy interrupt "); val_gic_end_of_interrupt(intid_phy); } @@ -85,7 +85,7 @@ payload() } if (!ns_timer) { - val_print(ACS_PRINT_DEBUG, "\n No non-secure systimer implemented", 0); + val_print(DEBUG, "\n No non-secure systimer implemented"); val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -93,7 +93,7 @@ payload() /* Start Sys timer*/ cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { - val_print(ACS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); + val_print(WARN, "\n CNT_BASE_N is zero "); val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); return; } @@ -114,7 +114,7 @@ payload() /* Put current PE in to low power mode*/ status = val_suspend_pe(0, 0); if (status) { - val_print(ACS_PRINT_DEBUG, "\n Not able to suspend the PE : %d", status); + val_print(DEBUG, "\n Not able to suspend the PE : %d", status); val_timer_disable_system_timer((addr_t)cnt_base_n); val_gic_clear_interrupt(intid); val_timer_set_phy_el1(0); @@ -123,7 +123,7 @@ payload() } if (irq_received == 0) { - val_print(ACS_PRINT_ERR, "\n System timer interrupt not generated", 0); + val_print(ERROR, "\n System timer interrupt not generated"); val_timer_disable_system_timer((addr_t)cnt_base_n); val_gic_clear_interrupt(intid); val_timer_set_phy_el1(0); @@ -138,7 +138,7 @@ payload() /*Disable PE timer*/ val_timer_set_phy_el1(0); - val_print(ACS_PRINT_INFO, "\n Read back PE timer count :%d", timer_cnt); + val_print(TRACE, "\n Read back PE timer count :%d", timer_cnt); /* Check whether count is moved or not*/ if ((timer_cnt < ((pe_timer_ticks - sys_timer_ticks) + (sys_timer_ticks/100))) diff --git a/test_pool/timer/t006.c b/test_pool/timer/t006.c index fdc3e560..f9fdfbda 100644 --- a/test_pool/timer/t006.c +++ b/test_pool/timer/t006.c @@ -43,9 +43,9 @@ payload() } if (print_mhz) - val_print(ACS_PRINT_ERR, "\n Counter frequency is %ld MHz", print_freq); + val_print(ERROR, "\n Counter frequency is %ld MHz", print_freq); else - val_print(ACS_PRINT_ERR, "\n Counter frequency is %ld KHz", print_freq); + val_print(ERROR, "\n Counter frequency is %ld KHz", print_freq); if (counter_freq >= 50*1000*1000) { val_set_status(index, RESULT_PASS(TEST_NUM, 1)); diff --git a/test_pool/timer/t008.c b/test_pool/timer/t008.c index 6564eda6..052a82dc 100644 --- a/test_pool/timer/t008.c +++ b/test_pool/timer/t008.c @@ -42,7 +42,7 @@ void payload(void) feat_ecv_impl = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 60, 63); if (feat_ecv_impl) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n FEAT_ECV is Implemented, Reading CntPctSS", + val_print_primary_pe(DEBUG, "\n FEAT_ECV is Implemented, Reading CntPctSS", 0, index); if (g_el1skiptrap_mask & EL1SKIPTRAP_CNTPCT) @@ -51,11 +51,11 @@ void payload(void) while (iter) { curr_value = read_cntpctss_el0(); if (curr_value < prev_value) { - val_print_primary_pe(ACS_PRINT_ERR, "\n CNTPCTSS_EL0 did not increment", + val_print_primary_pe(ERROR, "\n CNTPCTSS_EL0 did not increment", 0, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n CNTPCTSS_EL0 Value: %lx", + val_print_primary_pe(DEBUG, "\n CNTPCTSS_EL0 Value: %lx", curr_value, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Previous Value: %lx", + val_print_primary_pe(DEBUG, "\n Previous Value: %lx", prev_value, index); test_fail = 1; } @@ -65,7 +65,7 @@ void payload(void) } read_virt_ss_timer: - val_print_primary_pe(ACS_PRINT_DEBUG, "\n FEAT_ECV is Implemented, Reading CntVctSS", + val_print_primary_pe(DEBUG, "\n FEAT_ECV is Implemented, Reading CntVctSS", 0, index); prev_value = 0; iter = NUM_ITERATIONS; @@ -73,11 +73,11 @@ void payload(void) while (iter) { curr_value = read_cntvctss_el0(); if (curr_value < prev_value) { - val_print_primary_pe(ACS_PRINT_ERR, "\n CNTVCTSS_EL0 did not increment", + val_print_primary_pe(ERROR, "\n CNTVCTSS_EL0 did not increment", 0, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n CNTVCTSS_EL0 Value: %lx", + val_print_primary_pe(DEBUG, "\n CNTVCTSS_EL0 Value: %lx", curr_value, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Previous Value: %lx", + val_print_primary_pe(DEBUG, "\n Previous Value: %lx", prev_value, index); test_fail = 1; } @@ -92,17 +92,17 @@ void payload(void) if (g_el1skiptrap_mask & EL1SKIPTRAP_CNTPCT) goto read_virt_timer; - val_print_primary_pe(ACS_PRINT_DEBUG, "\n FEAT_ECV isn't Implemented, Reading CntPct", + val_print_primary_pe(DEBUG, "\n FEAT_ECV isn't Implemented, Reading CntPct", 0, index); while (iter) { isb(); curr_value = read_cntpct_el0(); if (curr_value < prev_value) { - val_print_primary_pe(ACS_PRINT_ERR, "\n CNTPCT_EL0 did not increment", + val_print_primary_pe(ERROR, "\n CNTPCT_EL0 did not increment", 0, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n CNTPCT_EL0 Value: %lx", + val_print_primary_pe(DEBUG, "\n CNTPCT_EL0 Value: %lx", curr_value, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Previous Value: %lx", + val_print_primary_pe(DEBUG, "\n Previous Value: %lx", prev_value, index); test_fail = 1; } @@ -112,7 +112,7 @@ void payload(void) } read_virt_timer: - val_print_primary_pe(ACS_PRINT_DEBUG, "\n FEAT_ECV isn't Implemented, Reading CntVct", + val_print_primary_pe(DEBUG, "\n FEAT_ECV isn't Implemented, Reading CntVct", 0, index); prev_value = 0; iter = NUM_ITERATIONS; @@ -121,11 +121,11 @@ void payload(void) isb(); curr_value = read_cntvct_el0(); if (curr_value < prev_value) { - val_print_primary_pe(ACS_PRINT_ERR, "\n CNTVCT_EL0 did not increment", + val_print_primary_pe(ERROR, "\n CNTVCT_EL0 did not increment", 0, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n CNTVCT_EL0 Value: %lx", + val_print_primary_pe(DEBUG, "\n CNTVCT_EL0 Value: %lx", curr_value, index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Previous Value: %lx", + val_print_primary_pe(DEBUG, "\n Previous Value: %lx", prev_value, index); test_fail = 1; } diff --git a/test_pool/tpm/tpm001.c b/test_pool/tpm/tpm001.c index c65d8e1e..cae023b4 100644 --- a/test_pool/tpm/tpm001.c +++ b/test_pool/tpm/tpm001.c @@ -36,7 +36,7 @@ payload() /* Check if TPM is present */ tpm_is_present = val_tpm2_get_info(TPM2_INFO_IS_PRESENT); if (tpm_is_present == 0) { - val_print(ACS_PRINT_ERR, "\n TPM not present", 0); + val_print(ERROR, "\n TPM not present"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -44,7 +44,7 @@ payload() /* Retrieve TPM version via family identifier (e.g., "2.0", "1.2") */ tpm_family_version = val_tpm2_get_version(); if (tpm_family_version != 2) { - val_print(ACS_PRINT_ERR, "\n TPM version is not 2.0", 0); + val_print(ERROR, "\n TPM version is not 2.0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); return; } diff --git a/test_pool/tpm/tpm002.c b/test_pool/tpm/tpm002.c index 88608fdc..cccc7ea4 100644 --- a/test_pool/tpm/tpm002.c +++ b/test_pool/tpm/tpm002.c @@ -42,29 +42,29 @@ payload() /* Step 1: Check TPM presence */ tpm_present = val_tpm2_get_info(TPM2_INFO_IS_PRESENT); if (tpm_present == 0) { - val_print(ACS_PRINT_ERR, "\n TPM not present", 0); + val_print(ERROR, "\n TPM not present"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); return; } /* Step 2: Get TPM interface type from ACPI TPM2 table */ tpm_start_method = val_tpm2_get_info(TPM2_INFO_INTERFACE_TYPE); - val_print(ACS_PRINT_INFO, "\n TPM interface type: 0x%llx", tpm_start_method); + val_print(TRACE, "\n TPM interface type: 0x%llx", tpm_start_method); /* Step 3: Reject interfaces that are known to support only locality 0 */ if (tpm_start_method == TPM_IF_START_METHOD_ACPI || tpm_start_method == TPM_IF_START_METHOD_CRB_SMC || tpm_start_method == TPM_IF_START_METHOD_CRB_FFA) { - val_print(ACS_PRINT_INFO, - "\n Skipping test: TPM locality not accessible at current privilege level", 0); + val_print(TRACE, + "\n Skipping test: TPM locality not accessible at current privilege level"); val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); return; } /* Step 4: Get TPM base address from ACPI TPM2 table */ tpm_base_addr = val_tpm2_get_info(TPM2_INFO_BASE_ADDR); - val_print(ACS_PRINT_INFO, "\n TPM Base Address: 0x%llx", tpm_base_addr); + val_print(TRACE, "\n TPM Base Address: 0x%llx", tpm_base_addr); /* Step 5: Handle FIFO (TIS) interface */ if (tpm_start_method == TPM_IF_START_METHOD_TIS) { @@ -78,21 +78,21 @@ payload() */ tpm_base_addr = TPM_FIFO_BASE_ADDRESS; val_mmu_update_entry(tpm_base_addr, TPM_MMIO_MAP_SIZE, DEVICE_nGnRnE); - val_print(ACS_PRINT_WARN, "\n ACPI base address is 0, " + val_print(WARN, "\n ACPI base address is 0, " "Using default FIFO base: 0x%llx", tpm_base_addr); } interface_id_addr = tpm_base_addr + TPM_FIFO_INTERFACE_ID_OFFSET; - val_print(ACS_PRINT_INFO, "\n Tpm_fifo_interface_id_0 address: 0x%llx", + val_print(TRACE, "\n Tpm_fifo_interface_id_0 address: 0x%llx", interface_id_addr); interface_id_val = val_mmio_read64(interface_id_addr); - val_print(ACS_PRINT_INFO, "\n Tpm_fifo_interface_id_0 Value : 0x%llx", + val_print(TRACE, "\n Tpm_fifo_interface_id_0 Value : 0x%llx", interface_id_val); cap_locality = VAL_EXTRACT_BITS(interface_id_val, 8, 8); /* CapLocality is bit[8] */ if (cap_locality == 0) { - val_print(ACS_PRINT_ERR, "\n TPM FIFO interface supports only locality 0", 0); + val_print(ERROR, "\n TPM FIFO interface supports only locality 0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); return; } @@ -107,16 +107,16 @@ payload() TPM_MMIO_MAP_SIZE, DEVICE_nGnRnE); interface_id_addr = (tpm_base_addr - TPM_CRB_CONTROL_AREA_OFFSET) + TPM_CRB_INTERFACE_ID_OFFSET; - val_print(ACS_PRINT_INFO, "\n Tpm_fifo_interface_id_0 address: 0x%llx", + val_print(TRACE, "\n Tpm_fifo_interface_id_0 address: 0x%llx", interface_id_addr); interface_id_val = val_mmio_read64(interface_id_addr); - val_print(ACS_PRINT_INFO, "\n Tpm_fifo_interface_id_0 Value : 0x%llx", + val_print(TRACE, "\n Tpm_fifo_interface_id_0 Value : 0x%llx", interface_id_val); cap_locality = VAL_EXTRACT_BITS(interface_id_val, 8, 8); /* CapLocality is bit[8] */ if (cap_locality == 0) { - val_print(ACS_PRINT_ERR, "\n TPM CRB interface supports only locality 0", 0); + val_print(ERROR, "\n TPM CRB interface supports only locality 0"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); return; } @@ -124,7 +124,7 @@ payload() /* Step 7: Catch any unknown/unhandled interface types */ else { - val_print(ACS_PRINT_ERR, "\n Invalid TPM interface type per TPM2 spec", 0); + val_print(ERROR, "\n Invalid TPM interface type per TPM2 spec"); val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 05)); return; } diff --git a/test_pool/watchdog/w001.c b/test_pool/watchdog/w001.c index 3ffd1f30..7dee9cd3 100644 --- a/test_pool/watchdog/w001.c +++ b/test_pool/watchdog/w001.c @@ -37,7 +37,7 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t data, ns_wdg = 0; - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n Found %d watchdogs in table ", wd_num); @@ -58,9 +58,9 @@ payload() ns_wdg++; refresh_base = val_wd_get_info(wd_num, WD_INFO_REFRESH_BASE); - val_print(ACS_PRINT_INFO, "\n Watchdog Refresh base is %llx ", refresh_base); + val_print(TRACE, "\n Watchdog Refresh base is %llx ", refresh_base); ctrl_base = val_wd_get_info(wd_num, WD_INFO_CTRL_BASE); - val_print(ACS_PRINT_INFO, "\n Watchdog CTRL base is %llx ", ctrl_base); + val_print(TRACE, "\n Watchdog CTRL base is %llx ", ctrl_base); data = val_mmio_read(ctrl_base); /*Control register bits 31:3 are reserved 0*/ @@ -86,10 +86,10 @@ payload() if (!ns_wdg) { if (g_build_sbsa || g_build_pcbsa) { - val_print(ACS_PRINT_ERR, "\n No non-secure Watchdogs reported", 0); + val_print(ERROR, "\n No non-secure Watchdogs reported"); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); } else { - val_print(ACS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); + val_print(WARN, "\n No non-secure Watchdogs reported"); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); } return; diff --git a/test_pool/watchdog/w002.c b/test_pool/watchdog/w002.c index 79d1b93f..2123551e 100644 --- a/test_pool/watchdog/w002.c +++ b/test_pool/watchdog/w002.c @@ -43,11 +43,11 @@ isr() { val_wd_set_ws0(wd_num, 0); g_wd_int_received = 1; - val_print(ACS_PRINT_DEBUG, "\n Received WS0 interrupt ", 0); + val_print(DEBUG, "\n Received WS0 interrupt "); val_gic_end_of_interrupt(int_id); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_DEBUG, " Clear Failsafe interrupt\n", 0); + val_print(DEBUG, " Clear Failsafe interrupt\n"); } static @@ -58,7 +58,7 @@ isr_failsafe() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_timer_set_phy_el1(0); - val_print(ACS_PRINT_ERR, " Received Failsafe interrupt\n", 0); + val_print(ERROR, " Received Failsafe interrupt\n"); g_failsafe_int_received = 1; /* On some system the failsafe is rcvd just after test interrupt and resulting @@ -103,7 +103,7 @@ payload() wd_num = val_wd_get_info(0, WD_INFO_COUNT); if (wd_num == 0) { - val_print(ACS_PRINT_DEBUG, "\n No Watchdogs reported %d ", wd_num); + val_print(DEBUG, "\n No Watchdogs reported %d ", wd_num); if (g_build_sbsa || g_build_pcbsa) val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); else @@ -123,18 +123,18 @@ payload() ns_wdg++; int_id = val_wd_get_info(wd_num, WD_INFO_GSIV); - val_print(ACS_PRINT_DEBUG, "\n WS0 Interrupt id %d ", int_id); + val_print(DEBUG, "\n WS0 Interrupt id %d ", int_id); /* Check intid is SPI or ESPI */ if (!(IsSpi(int_id)) && !(val_gic_is_valid_espi(int_id))) { - val_print(ACS_PRINT_ERR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); + val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } /* Install ISR */ if (val_gic_install_isr(int_id, isr)) { - val_print(ACS_PRINT_ERR, "\n GIC Install Handler Failed...", 0); + val_print(ERROR, "\n GIC Install Handler Failed..."); val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } @@ -148,7 +148,7 @@ payload() g_wd_int_received = 0; status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { - val_print(ACS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); + val_print(ERROR, "\n Setting watchdog timeout failed"); val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); return; } @@ -165,13 +165,13 @@ payload() val_wd_set_ws0(wd_num, 0); if (g_failsafe_int_received && (g_wd_int_received == 0)) { - val_print(ACS_PRINT_ERR, "\n Failsafe interrupt received, no WS0 interrupt", 0); + val_print(ERROR, "\n Failsafe interrupt received, no WS0 interrupt"); val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); return; } if ((timeout == 0) && (g_wd_int_received == 0)) { - val_print(ACS_PRINT_ERR, "\n WS0 Interrupt not rcvd within timeout %d", int_id); + val_print(ERROR, "\n WS0 Interrupt not rcvd within timeout %d", int_id); val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); return; } @@ -180,10 +180,10 @@ payload() if (!ns_wdg) { if (g_build_sbsa || g_build_pcbsa) { - val_print(ACS_PRINT_ERR, "\n No non-secure Watchdogs reported", 0); + val_print(ERROR, "\n No non-secure Watchdogs reported"); val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); } else { - val_print(ACS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); + val_print(WARN, "\n No non-secure Watchdogs reported"); val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); } return; diff --git a/test_pool/watchdog/w003.c b/test_pool/watchdog/w003.c index 11b8b97d..29980018 100644 --- a/test_pool/watchdog/w003.c +++ b/test_pool/watchdog/w003.c @@ -34,10 +34,10 @@ payload(void) uint32_t data, ns_wdg = 0; - val_print(ACS_PRINT_DEBUG, "\n Found %d watchdogs in ACPI table ", wd_num); + val_print(DEBUG, "\n Found %d watchdogs in ACPI table ", wd_num); if (wd_num == 0) { - val_print(ACS_PRINT_WARN, "\n No Watchdogs reported %d ", wd_num); + val_print(WARN, "\n No Watchdogs reported %d ", wd_num); val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); return; } @@ -50,14 +50,14 @@ payload(void) ns_wdg++; ctrl_base = val_wd_get_info(wd_num, WD_INFO_CTRL_BASE); - val_print(ACS_PRINT_INFO, "\n Watchdog CTRL base is %llx ", ctrl_base); + val_print(TRACE, "\n Watchdog CTRL base is %llx ", ctrl_base); /* W_IIDR.Architecture Revision [19:16] = 0x1 for Watchdog Rev 1 */ data = VAL_EXTRACT_BITS(val_mmio_read(ctrl_base + WD_IIDR_OFFSET), 16, 19); if (data != 1) { - val_print(ACS_PRINT_ERR, "\n Watchdog Architecture version is %x", data); + val_print(ERROR, "\n Watchdog Architecture version is %x", data); val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); return; } @@ -65,7 +65,7 @@ payload(void) } while(wd_num); if(!ns_wdg) { - val_print(ACS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); + val_print(WARN, "\n No non-secure Watchdogs reported"); val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); return; } diff --git a/val/ValLib.inf b/val/ValLib.inf index bdd09090..18e66488 100644 --- a/val/ValLib.inf +++ b/val/ValLib.inf @@ -77,6 +77,7 @@ src/mpam_execute_test.c src/drtm_execute_test.c src/pc_bsa_execute_test.c + src/val_logger.c [Packages] MdePkg/MdePkg.dec diff --git a/val/ValLibRB.inf b/val/ValLibRB.inf index 99b53148..4866a764 100644 --- a/val/ValLibRB.inf +++ b/val/ValLibRB.inf @@ -82,6 +82,7 @@ src/rule_enum_string_map.c src/rule_lookup.c src/test_wrappers.c + src/val_logger.c [Packages] MdePkg/MdePkg.dec diff --git a/val/driver/gic/acs_exception.c b/val/driver/gic/acs_exception.c index 1f179a4d..e7382a78 100644 --- a/val/driver/gic/acs_exception.c +++ b/val/driver/gic/acs_exception.c @@ -42,7 +42,7 @@ static void default_irq_handler(uint64_t exception_type, void *context) if (g_intr_handler[ack_interrupt]) { g_intr_handler[ack_interrupt](); } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n GIC_INIT: Unregistered Handler for the interrupt_id : 0x%x", ack_interrupt); } @@ -55,7 +55,7 @@ static void default_irq_handler(uint64_t exception_type, void *context) void bsa_gic_vector_table_init(void) { - val_print(ACS_PRINT_DEBUG, " GIC_INIT: Setting Up Vector Table...\n", 0); + val_print(DEBUG, " GIC_INIT: Setting Up Vector Table...\n"); /* Setting Up Vector Table */ bsa_gic_set_el2_vector_table(); @@ -86,15 +86,15 @@ uint32_t val_acs_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void uint32_t common_exception_handler(uint32_t exception_type) { - val_print(ACS_PRINT_INFO, "\n GIC_INIT: In Exception Handler Type : %x", exception_type); + val_print(TRACE, "\n GIC_INIT: In Exception Handler Type : %x", exception_type); /* Call Handler for exception, Handler would have * already been installed using install_esr call */ g_esr_handler[exception_type](exception_type, NULL); - val_print(ACS_PRINT_INFO, "\n GIC_INIT: Common Handler, FAR = %llx", bsa_gic_get_far()); - val_print(ACS_PRINT_INFO, "\n GIC_INIT: Common Handler, ESR = %llx", bsa_gic_get_esr()); + val_print(TRACE, "\n GIC_INIT: Common Handler, FAR = %llx", bsa_gic_get_far()); + val_print(TRACE, "\n GIC_INIT: Common Handler, ESR = %llx", bsa_gic_get_esr()); /* If ELR is updated inside the handler then skip the elr update in assembly handler * Return 1 else return 0 diff --git a/val/driver/gic/gic.c b/val/driver/gic/gic.c index c58067fa..24bbf8d2 100644 --- a/val/driver/gic/gic.c +++ b/val/driver/gic/gic.c @@ -141,11 +141,11 @@ val_gic_max_espi_val(void) GICD_TYPER_ESPI_RANGE_MASK; max_espi_val = (32 * (espi_range + 1) + 4095); - val_print(ACS_PRINT_INFO, "\n max ESPI value %d ", max_espi_val); + val_print(TRACE, "\n max ESPI value %d ", max_espi_val); return max_espi_val; } else { - val_print(ACS_PRINT_INFO, "\n max ESPI value %d ", max_espi_val); + val_print(TRACE, "\n max ESPI value %d ", max_espi_val); return 0; } } diff --git a/val/driver/gic/its/acs_gic_its.c b/val/driver/gic/its/acs_gic_its.c index 811efc41..9f638797 100644 --- a/val/driver/gic/its/acs_gic_its.c +++ b/val/driver/gic/its/acs_gic_its.c @@ -110,7 +110,7 @@ ArmGicSetItsCommandQueueBase( Address = (uint64_t)val_aligned_alloc(SIZE_64KB, (NUM_PAGES_8 * SIZE_4KB)); if (!Address) { - val_print(ACS_PRINT_ERR, "ITS : Could Not Allocate Memory CmdQ. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not Allocate Memory CmdQ. Test may not pass.\n"); return 1; } @@ -227,14 +227,14 @@ static uint32_t ArmGicSetItsTables(uint32_t its_index) // level 1 needs 64 bits i.e 8 bytes TableSize = (1 << (lvl1_bits))*ARM_GITS_BASER_INDIRECT_LVL1_ENTRY_SIZE; if (TableSize > max_page_size*ARM_GITS_BASER_MAX_PAGES) { - val_print(ACS_PRINT_WARN, "ITS : Level 1 table size exceeded limit", 0); - val_print(ACS_PRINT_WARN, "max did size will not be supported..\n", 0); + val_print(WARN, "ITS : Level 1 table size exceeded limit"); + val_print(WARN, "max did size will not be supported..\n"); TableSize = max_page_size*ARM_GITS_BASER_MAX_PAGES; } } else { - val_print(ACS_PRINT_WARN, "ITS : Multilevel table not supported and single level table\n", 0); - val_print(ACS_PRINT_WARN, "size exceeded limit settings support only upto 24 bit \n", 0); - val_print(ACS_PRINT_WARN, "(if entry_size is 8 bytes)", 0); + val_print(WARN, "ITS : Multilevel table not supported and single level table\n"); + val_print(WARN, "size exceeded limit settings support only upto 24 bit \n"); + val_print(WARN, "(if entry_size is 8 bytes)"); TableSize = max_page_size*ARM_GITS_BASER_MAX_PAGES; } } @@ -250,7 +250,7 @@ static uint32_t ArmGicSetItsTables(uint32_t its_index) Address = (uint64_t)val_aligned_alloc(max_page_size, TableSize); if (!Address) { - val_print(ACS_PRINT_ERR, "ITS : Could Not Allocate Memory DT/CT. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not Allocate Memory DT/CT. Test may not pass.\n"); return 1; } @@ -284,7 +284,7 @@ static uint32_t ArmGicSetItsTables(uint32_t its_index) Address = (uint64_t)val_aligned_alloc(SIZE_64KB, (NUM_PAGES_8 * SIZE_4KB)); if (!Address) { - val_print(ACS_PRINT_ERR, "ITS : Could Not Allocate Memory For ITT. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not Allocate Memory For ITT. Test may not pass.\n"); return 1; } @@ -436,8 +436,8 @@ static void PollTillCommandQueueDone(uint32_t its_index) count++; if (count > WAIT_ITS_COMMAND_DONE) { - val_print(ACS_PRINT_ERR, - "\n ITS : Command Queue READR not moving, Test may not pass", 0); + val_print(ERROR, + "\n ITS : Command Queue READR not moving, Test may not pass"); break; } @@ -631,7 +631,7 @@ uint32_t val_its_init(void) sizeof(uint32_t) * (g_gic_its_info->GicNumIts)); if (g_cwriter_ptr == NULL) { - val_print(ACS_PRINT_ERR, "ITS : Could Not Allocate Memory CWriteR. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not Allocate Memory CWriteR. Test may not pass.\n"); return 0; } @@ -666,12 +666,12 @@ uint32_t val_its_init(void) g_its_setup_done = 1; - val_print(ACS_PRINT_INFO, " ITS : Info Block\n", 0); + val_print(TRACE, " ITS : Info Block\n"); for (index = 0; index < g_gic_its_info->GicNumIts; index++) { - val_print(ACS_PRINT_INFO, " GIC ITS Index: %x", g_gic_its_info->GicIts[index].its_index); - val_print(ACS_PRINT_INFO, " ID: %x", g_gic_its_info->GicIts[index].ID); - val_print(ACS_PRINT_INFO, " Base: %x\n", g_gic_its_info->GicIts[index].Base); + val_print(TRACE, " GIC ITS Index: %x", g_gic_its_info->GicIts[index].its_index); + val_print(TRACE, " ID: %x", g_gic_its_info->GicIts[index].ID); + val_print(TRACE, " Base: %x\n", g_gic_its_info->GicIts[index].Base); } return 0; diff --git a/val/driver/gic/its/acs_gic_redistributor.c b/val/driver/gic/its/acs_gic_redistributor.c index ec7176bc..6a07caff 100644 --- a/val/driver/gic/its/acs_gic_redistributor.c +++ b/val/driver/gic/its/acs_gic_redistributor.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2021,2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2021,2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,7 +43,7 @@ ArmGicSetItsConfigTableBase( Address = (uint64_t)val_aligned_alloc(SIZE_4KB, PAGES_TO_SIZE(Pages)); if (!Address) { - val_print(ACS_PRINT_ERR, "ITS : Could Not get Mem Config Table. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not get Mem Config Table. Test may not pass.\n"); return 1; } @@ -89,7 +89,7 @@ ArmGicSetItsPendingTableBase( Address = (uint64_t)val_aligned_alloc(SIZE_64KB, PAGES_TO_SIZE(Pages)); if (!Address) { - val_print(ACS_PRINT_ERR, "ITS : Could Not get Memory Pending Table. Test may not pass.\n", 0); + val_print(ERROR, "ITS : Could Not get Memory Pending Table. Test may not pass.\n"); return 1; } diff --git a/val/driver/gic/v2/gic_v2.c b/val/driver/gic/v2/gic_v2.c index 5ef96a64..d64b894f 100644 --- a/val/driver/gic/v2/gic_v2.c +++ b/val/driver/gic/v2/gic_v2.c @@ -107,9 +107,9 @@ v2_Init(void) /* Get the max interrupt */ max_num_interrupts = val_get_max_intid(); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: D base %x\n", gicd_base); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: CPU IF base %x\n", cpuif_base); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: Interrupts %d\n", max_num_interrupts); + val_print(DEBUG, " GIC_INIT: D base %x\n", gicd_base); + val_print(DEBUG, " GIC_INIT: CPU IF base %x\n", cpuif_base); + val_print(DEBUG, " GIC_INIT: Interrupts %d\n", max_num_interrupts); /* Disable all interrupt */ for (index = 0; index < max_num_interrupts; index++) { diff --git a/val/driver/gic/v3/gic_v3.c b/val/driver/gic/v3/gic_v3.c index 25f5cd7e..df377fe7 100644 --- a/val/driver/gic/v3/gic_v3.c +++ b/val/driver/gic/v3/gic_v3.c @@ -377,8 +377,8 @@ v3_Init(void) /* Get the max interrupt */ max_num_interrupts = val_get_max_intid(); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: D base %x\n", gicd_base); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: Interrupts %d\n", max_num_interrupts); + val_print(DEBUG, " GIC_INIT: D base %x\n", gicd_base); + val_print(DEBUG, " GIC_INIT: Interrupts %d\n", max_num_interrupts); #if defined(TARGET_SIMULATION) /* Fast-sim: disable in register chunks (32 IRQs per write) */ @@ -406,7 +406,7 @@ v3_Init(void) /* Set ARI bits for v3 mode */ val_mmio_write(gicd_base + GICD_CTLR, val_mmio_read(gicd_base + GICD_CTLR) | GIC_ARE_ENABLE); val_mmio_write(gicd_base + GICD_CTLR, val_mmio_read(gicd_base + GICD_CTLR) | 0x2); - val_print(ACS_PRINT_DEBUG, " GIC_INIT: GICD_CTLR value 0x%08x\n", + val_print(DEBUG, " GIC_INIT: GICD_CTLR value 0x%08x\n", val_mmio_read(gicd_base + GICD_CTLR)); #if defined(TARGET_SIMULATION) diff --git a/val/driver/gic/v3/gic_v3_extended.c b/val/driver/gic/v3/gic_v3_extended.c index 8226db10..a96420cd 100644 --- a/val/driver/gic/v3/gic_v3_extended.c +++ b/val/driver/gic/v3/gic_v3_extended.c @@ -287,8 +287,8 @@ v3_extended_init(void) max_num_espi_interrupts = val_gic_max_espi_val(); max_num_eppi_interrupts = val_gic_max_eppi_val(); - val_print(ACS_PRINT_DEBUG, "\n GIC_INIT: Extended SPI Interrupts %d\n", max_num_espi_interrupts); - val_print(ACS_PRINT_DEBUG, "\n GIC_INIT: Extended PPI Interrupts %d\n", max_num_eppi_interrupts); + val_print(DEBUG, "\n GIC_INIT: Extended SPI Interrupts %d\n", max_num_espi_interrupts); + val_print(DEBUG, "\n GIC_INIT: Extended PPI Interrupts %d\n", max_num_eppi_interrupts); #if defined(TARGET_SIMULATION) /* Fast-sim: bulk disable in 32-interrupt chunks */ diff --git a/val/driver/pcie/pcie.c b/val/driver/pcie/pcie.c index 92bbd031..06f0434a 100644 --- a/val/driver/pcie/pcie.c +++ b/val/driver/pcie/pcie.c @@ -50,7 +50,7 @@ uint32_t pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) val_pcie_read_cfg(bdf, HEADER_OFFSET, &header_value); if (PCIE_HEADER_TYPE(header_value) == TYPE1_HEADER) { - val_print(ACS_PRINT_INFO, " TYPE1 HEADER found\n", 0); + val_print(TRACE, " TYPE1 HEADER found\n"); val_pcie_write_cfg(bdf, BUS_NUM_REG_OFFSET, BUS_NUM_REG_CFG(0xFF, sec_bus, bus)); sub_bus = pcie_enumerate_device(sec_bus, (sec_bus+1)); val_pcie_write_cfg(bdf, BUS_NUM_REG_OFFSET, BUS_NUM_REG_CFG(sub_bus, sec_bus, bus)); @@ -59,7 +59,7 @@ uint32_t pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) if (PCIE_HEADER_TYPE(header_value) == TYPE0_HEADER) { - val_print(ACS_PRINT_INFO, " END POINT found\n", 0); + val_print(TRACE, " END POINT found\n"); sub_bus = sec_bus - 1; } @@ -77,6 +77,6 @@ uint32_t pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) **/ void val_bsa_pcie_enumerate(void) { - val_print(ACS_PRINT_INFO, "\n Starting Enumeration\n", 0); + val_print(TRACE, "\n Starting Enumeration\n"); pcie_enumerate_device(PRI_BUS, SEC_BUS); } diff --git a/val/driver/smmu_v3/smmu_v3.c b/val/driver/smmu_v3/smmu_v3.c index f388c80e..a4a02575 100644 --- a/val/driver/smmu_v3/smmu_v3.c +++ b/val/driver/smmu_v3/smmu_v3.c @@ -70,7 +70,7 @@ static int smmu_cmdq_build_cmd(uint64_t *cmd, uint8_t opcode) cmd[1] |= BITFIELD_SET(CMDQ_CFGI_1_RANGE, CMDQ_CFGI_1_ALL_STES); break; default: - val_print(ACS_PRINT_ERR, "\n Unsupported SMMU command 0x%x ", opcode); + val_print(ERROR, "\n Unsupported SMMU command 0x%x ", opcode); return -1; } @@ -94,7 +94,7 @@ static int smmu_cmdq_write_cmd(smmu_dev_t *smmu, uint64_t *cmd) } if (!timeout) { - val_print(ACS_PRINT_ERR, "\n SMMU CMD queue is full ", 0); + val_print(ERROR, "\n SMMU CMD queue is full "); return -1; } @@ -142,12 +142,12 @@ static void smmu_cmdq_poll_until_consumed(smmu_dev_t *smmu) } if (!timeout) { - val_print(ACS_PRINT_ERR, "\n CMDQ poll timeout at 0x%08x", queue.prod); - val_print(ACS_PRINT_ERR, "\n prod_reg = 0x%08x,", + val_print(ERROR, "\n CMDQ poll timeout at 0x%08x", queue.prod); + val_print(ERROR, "\n prod_reg = 0x%08x,", val_mmio_read((uint64_t)smmu->cmdq.prod_reg)); - val_print(ACS_PRINT_ERR, "\n cons_reg = 0x%08x", + val_print(ERROR, "\n cons_reg = 0x%08x", val_mmio_read((uint64_t)smmu->cmdq.cons_reg)); - val_print(ACS_PRINT_ERR, "\n gerror = 0x%08x ", + val_print(ERROR, "\n gerror = 0x%08x ", val_mmio_read(smmu->base + SMMU_GERROR_OFFSET)); } } @@ -221,7 +221,7 @@ static uint32_t smmu_strtab_init_linear(smmu_dev_t *smmu) size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); cfg->strtab_ptr = val_memory_calloc(2, size); if (!cfg->strtab_ptr) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate linear stream table. ", 0); + val_print(ERROR, "\n Failed to allocate linear stream table. "); return 0; } @@ -244,7 +244,7 @@ static uint32_t smmu_cmd_queue_init(smmu_dev_t *smmu) cmdq_size = (cmdq_size < 32)?32:cmdq_size; cmdq->base_ptr = val_memory_calloc (2, cmdq_size); if (!cmdq->base_ptr) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate Command queue struct. ", 0); + val_print(ERROR, "\n Failed to allocate Command queue struct. "); return 0; } @@ -270,7 +270,7 @@ static uint32_t smmu_evnt_queue_init(smmu_dev_t *smmu) evntq_size = (evntq_size < 64)?64:evntq_size; evntq->base_ptr = val_memory_calloc (1, evntq_size); if (!evntq->base_ptr) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate Event queue struct. ", 0); + val_print(ERROR, "\n Failed to allocate Event queue struct. "); return 0; } @@ -341,7 +341,7 @@ static int smmu_strtab_init_level2(smmu_dev_t *smmu, uint32_t sid) desc->span = STRTAB_SPLIT + 1; desc->l2ptr = val_memory_calloc(2, size); if (!desc->l2ptr) { - val_print(ACS_PRINT_ERR, "\n failed to allocate l2 stream table for SID %u ", + val_print(ERROR, "\n failed to allocate l2 stream table for SID %u ", sid); return 0; } @@ -361,7 +361,7 @@ static int smmu_strtab_init_level1(smmu_dev_t *smmu) cfg->l1_desc = val_memory_calloc(cfg->l1_ent_count, sizeof(*cfg->l1_desc)); if (!cfg->l1_desc) { - val_print(ACS_PRINT_ERR, "\n failed to allocate l1 stream table desc ", 0); + val_print(ERROR, "\n failed to allocate l1 stream table desc "); return 0; } @@ -382,7 +382,7 @@ static int smmu_strtab_init_2level(smmu_dev_t *smmu) l1_tbl_size = cfg->l1_ent_count * STRTAB_L1_DESC_SIZE; cfg->strtab_ptr = val_memory_alloc(2 * l1_tbl_size); if (!cfg->strtab_ptr) { - val_print(ACS_PRINT_ERR, "\n failed to allocate l1 stream table ", 0); + val_print(ERROR, "\n failed to allocate l1 stream table "); return 0; } @@ -412,7 +412,7 @@ static uint32_t smmu_strtab_init(smmu_dev_t *smmu) ret = smmu_strtab_init_linear(smmu); if (!ret) { - val_print(ACS_PRINT_ERR, "\n Stream table init failed ", 0); + val_print(ERROR, "\n Stream table init failed "); return ret; } @@ -475,64 +475,64 @@ static int smmu_handle_evt(uint64_t *event) { switch (BITFIELD_GET(EVTQ_0_ID, event[0])) { case EVT_ID_UUT: - val_print(ACS_PRINT_TEST, "\n\n Unsupported Upstream Transaction ", 0); + val_print(INFO, "\n\n Unsupported Upstream Transaction "); break; case EVT_ID_TRANSID_FAULT: - val_print(ACS_PRINT_TEST, "\n\n Transaction StreamID out of range ", 0); + val_print(INFO, "\n\n Transaction StreamID out of range "); break; case EVT_ID_STE_FETCH_FAULT: - val_print(ACS_PRINT_TEST, "\n\n Fetch of STE caused external abort ", 0); + val_print(INFO, "\n\n Fetch of STE caused external abort "); break; case EVT_ID_BAD_STE: - val_print(ACS_PRINT_TEST, "\n\n Used STE invalid ", 0); + val_print(INFO, "\n\n Used STE invalid "); break; case EVT_ID_BAD_ATS_TREQ: - val_print(ACS_PRINT_TEST, "\n\n Address Translation Request disallowed ", 0); + val_print(INFO, "\n\n Address Translation Request disallowed "); break; case EVT_ID_STREAM_DISABLED: - val_print(ACS_PRINT_TEST, "\n\n Non-substream transactions disabled ", 0); + val_print(INFO, "\n\n Non-substream transactions disabled "); break; case EVT_ID_TRANSL_FORBIDDEN: - val_print(ACS_PRINT_TEST, "\n\n Forbidden translation ", 0); + val_print(INFO, "\n\n Forbidden translation "); break; case EVT_ID_BAD_SSID: - val_print(ACS_PRINT_TEST, "\n\n Bad Substream ID ", 0); + val_print(INFO, "\n\n Bad Substream ID "); break; case EVT_ID_CD_FETCH_FAULT: - val_print(ACS_PRINT_TEST, "\n\n Fetch of CD caused external abort ", 0); + val_print(INFO, "\n\n Fetch of CD caused external abort "); break; case EVT_ID_BAD_CD: - val_print(ACS_PRINT_TEST, "\n\n Fetched CD invalid ", 0); + val_print(INFO, "\n\n Fetched CD invalid "); break; case EVT_ID_WALK_EABT: - val_print(ACS_PRINT_TEST, "\n\n Fetch of TTD caused external abort", 0); + val_print(INFO, "\n\n Fetch of TTD caused external abort"); break; case EVT_ID_TRANSLATION_FAULT: - val_print(ACS_PRINT_TEST, "\n\n SMMU_FAULT_REASON_PTE_FETCH ", 0); + val_print(INFO, "\n\n SMMU_FAULT_REASON_PTE_FETCH "); break; case EVT_ID_ADDR_SIZE_FAULT: - val_print(ACS_PRINT_TEST, "\n\n SMMU_FAULT_REASON_OOR_ADDRESS ", 0); + val_print(INFO, "\n\n SMMU_FAULT_REASON_OOR_ADDRESS "); break; case EVT_ID_ACCESS_FAULT: - val_print(ACS_PRINT_TEST, "\n\n SMMU_FAULT_REASON_ACCESS ", 0); + val_print(INFO, "\n\n SMMU_FAULT_REASON_ACCESS "); break; case EVT_ID_PERMISSION_FAULT: - val_print(ACS_PRINT_TEST, "\n\n SMMU_FAULT_REASON_PERMISSION ", 0); + val_print(INFO, "\n\n SMMU_FAULT_REASON_PERMISSION "); break; case EVT_ID_TLB_CONFLICT: - val_print(ACS_PRINT_TEST, "\n\n TLB conflict occurred ", 0); + val_print(INFO, "\n\n TLB conflict occurred "); break; case EVT_ID_CFG_CONFLICT: - val_print(ACS_PRINT_TEST, "\n\n Configuration cache conflict occurred ", 0); + val_print(INFO, "\n\n Configuration cache conflict occurred "); break; case EVT_ID_PAGE_REQUEST: - val_print(ACS_PRINT_TEST, "\n\n Speculation Page Req hint ", 0); + val_print(INFO, "\n\n Speculation Page Req hint "); break; case EVT_ID_VMS_FETCH: - val_print(ACS_PRINT_TEST, "\n\n Fetch of VMS caused external abort ", 0); + val_print(INFO, "\n\n Fetch of VMS caused external abort "); break; default: - val_print(ACS_PRINT_TEST, "\n\n INVALID FAULT ", 0); + val_print(INFO, "\n\n INVALID FAULT "); return 1; } @@ -585,13 +585,13 @@ static uint32_t smmu_gerror_check(smmu_dev_t *smmu) active = gerror ^ gerrorn; if (active & SMMU_GERROR_MSI_EVTQ_ABT_ERR) { - val_print(ACS_PRINT_DEBUG, "\n EVTQ MSI write aborted ", 0); + val_print(DEBUG, "\n EVTQ MSI write aborted "); return 1; } if (active & SMMU_GERROR_EVTQ_ABT_ERR) { - val_print(ACS_PRINT_DEBUG, "\n EVTQ write aborted -- events may have been lost", 0); + val_print(DEBUG, "\n EVTQ write aborted -- events may have been lost"); return 1; } @@ -609,7 +609,7 @@ static void smmu_evtq_thread(void) ret = smmu_gerror_check(smmu); if (ret) { - val_print(ACS_PRINT_WARN, "\n GERROR occurred. Eventq is not writable. ", 0); + val_print(WARN, "\n GERROR occurred. Eventq is not writable. "); return; } @@ -617,23 +617,23 @@ static void smmu_evtq_thread(void) while (!smmu_queue_remove_raw(evntq, event)) { uint8_t id = BITFIELD_GET(EVTQ_0_ID, event[0]); ret = smmu_handle_evt(event); - val_print(ACS_PRINT_TEST, "\n event 0x%02x received: %d ", id); + val_print(INFO, "\n event 0x%02x received: %d ", id); for (i = 0; i < ARRAY_SIZE(event); ++i) { - val_print(ACS_PRINT_TEST, "\n 0x%016llx ", (unsigned long long)event[i]); + val_print(INFO, "\n 0x%016llx ", (unsigned long long)event[i]); } - val_print(ACS_PRINT_INFO, "\n prod is: %x", val_mmio_read((uint64_t)evntq->prod_reg)); - val_print(ACS_PRINT_INFO, "\n cons is: %x", val_mmio_read((uint64_t)evntq->cons_reg)); + val_print(TRACE, "\n prod is: %x", val_mmio_read((uint64_t)evntq->prod_reg)); + val_print(TRACE, "\n cons is: %x", val_mmio_read((uint64_t)evntq->cons_reg)); } if (queue_sync_prod_in(evntq)) - val_print(ACS_PRINT_WARN, "\n EVTQ overflow detected -- events lost ", 0); + val_print(WARN, "\n EVTQ overflow detected -- events lost "); } while (!smmu_queue_empty(&evntq->queue)); if (val_mmio_read((uint64_t)evntq->prod_reg) == val_mmio_read((uint64_t)evntq->cons_reg)) { - val_print(ACS_PRINT_TEST, "\n No outstanding events in the queue. Queue Empty.\n", 0); + val_print(INFO, "\n No outstanding events in the queue. Queue Empty.\n"); } evntq->queue.cons = ((queue->prod) & (1 << 31)) | @@ -648,7 +648,7 @@ static int smmu_dev_disable(smmu_dev_t *smmu) ret = smmu_reg_write_sync(smmu, 0, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); if (ret) - val_print(ACS_PRINT_ERR, "\n failed to clear cr0 ", 0); + val_print(ERROR, "\n failed to clear cr0 "); return ret; } @@ -675,7 +675,7 @@ static int smmu_reset(smmu_dev_t *smmu) ret = smmu_reg_write_sync(smmu, 0, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); if (ret) { - val_print(ACS_PRINT_ERR, "\n failed to clear SMMU_CR0 ", 0); + val_print(ERROR, "\n failed to clear SMMU_CR0 "); return ret; } @@ -698,7 +698,7 @@ static int smmu_reset(smmu_dev_t *smmu) ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); if (ret) { - val_print(ACS_PRINT_ERR, "\n failed to enable command queue ", 0); + val_print(ERROR, "\n failed to enable command queue "); return ret; } @@ -712,7 +712,7 @@ static int smmu_reset(smmu_dev_t *smmu) ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); if (ret) { - val_print(ACS_PRINT_ERR, "\n failed to enable event queue ", 0); + val_print(ERROR, "\n failed to enable event queue "); return ret; } @@ -720,7 +720,7 @@ static int smmu_reset(smmu_dev_t *smmu) ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); if (ret) { - val_print(ACS_PRINT_ERR, "\n failed to enable SMMU ", 0); + val_print(ERROR, "\n failed to enable SMMU "); return ret; } @@ -776,14 +776,14 @@ static uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en) if (smmu_index >= g_num_smmus) { - val_print(ACS_PRINT_ERR, " smmu_set_state: invalid smmu index\n", 0); + val_print(ERROR, " smmu_set_state: invalid smmu index\n"); return 1; } smmu = &g_smmu[smmu_index]; if (smmu->base == 0) { - val_print(ACS_PRINT_ERR, " smmu_set_state: smmu unsupported\n", 0); + val_print(ERROR, " smmu_set_state: smmu unsupported\n"); return 1; } @@ -798,7 +798,7 @@ static uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en) SMMU_CR0ACK_OFFSET); if (ret) { - val_print(ACS_PRINT_ERR, " smmu_set_state: failed to set SMMU state\n", + val_print(ERROR, " smmu_set_state: failed to set SMMU state\n", 0); return ret; } @@ -811,7 +811,7 @@ static uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en) gbpa &= ~SMMU_GBPA_ABORT; if (smmu_gbpa_write_sync(smmu, gbpa)) { - val_print(ACS_PRINT_ERR, "\n GBPA update sync failed", 0); + val_print(ERROR, "\n GBPA update sync failed"); return 1; } } @@ -862,7 +862,7 @@ static uint32_t smmu_probe(smmu_dev_t *smmu) smmu->supported.s2p = 1; if (!(data & (IDR0_S1P | IDR0_S2P))) { - val_print(ACS_PRINT_ERR, " no translation support!\n ", 0); + val_print(ERROR, " no translation support!\n "); return 0; } @@ -872,13 +872,13 @@ static uint32_t smmu_probe(smmu_dev_t *smmu) case IDR0_TTF_AARCH64: break; default: - val_print(ACS_PRINT_ERR, " AArch64 table format not supported!\n", 0); + val_print(ERROR, " AArch64 table format not supported!\n"); return 0; } data = val_mmio_read(smmu->base + SMMU_IDR1_OFFSET); if (data & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET)) { - val_print(ACS_PRINT_ERR, " fixed table base addr not supported\n", 0); + val_print(ERROR, " fixed table base addr not supported\n"); return 0; } @@ -890,8 +890,8 @@ static uint32_t smmu_probe(smmu_dev_t *smmu) (BITFIELD_GET(IDR1_SIDSIZE, data)) : MAX_SID; smmu->ssid_bits = BITFIELD_GET(IDR1_SSIDSIZE, data); - val_print(ACS_PRINT_INFO, " ssid_bits = %d", smmu->ssid_bits); - val_print(ACS_PRINT_INFO, " sid_bits = %d\n", smmu->sid_bits); + val_print(TRACE, " ssid_bits = %d", smmu->ssid_bits); + val_print(TRACE, " sid_bits = %d\n", smmu->sid_bits); if (smmu->sid_bits <= STRTAB_SPLIT) smmu->supported.st_level_2lvl = 0; @@ -900,15 +900,15 @@ static uint32_t smmu_probe(smmu_dev_t *smmu) data = val_mmio_read(smmu->base + SMMU_IDR5_OFFSET); if (BITFIELD_GET(IDR5_OAS, data) >= SMMU_OAS_MAX_IDX) { - val_print(ACS_PRINT_ERR, " Unknown output address size\n", 0); + val_print(ERROR, " Unknown output address size\n"); return 0; } smmu->oas = smmu_oas[BITFIELD_GET(IDR5_OAS, data)]; smmu->ias = get_max(smmu->ias, smmu->oas); - val_print(ACS_PRINT_INFO, " ias %d-bit", smmu->ias); - val_print(ACS_PRINT_INFO, " oas %d-bit\n", smmu->oas); + val_print(TRACE, " ias %d-bit", smmu->ias); + val_print(TRACE, " oas %d-bit\n", smmu->oas); return 1; } @@ -930,8 +930,8 @@ static void dump_strtab(uint64_t *ste) int i; for (i = 0; i < 8; i++) { - val_print(ACS_PRINT_INFO, "ste[%d] = ", i); - val_print(ACS_PRINT_INFO, "%p\n", ste[i]); + val_print(TRACE, "ste[%d] = ", i); + val_print(TRACE, "%p\n", ste[i]); } } @@ -940,8 +940,8 @@ static void dump_cdtab(uint64_t *ctx_desc) int i; for (i = 0; i < 8; i++) { - val_print(ACS_PRINT_INFO, "ctx_desc[%d] = ", i); - val_print(ACS_PRINT_INFO, "%llx\n", ctx_desc[i]); + val_print(TRACE, "ctx_desc[%d] = ", i); + val_print(TRACE, "%llx\n", ctx_desc[i]); } } @@ -960,7 +960,7 @@ static int smmu_cdtab_alloc_leaf_table(smmu_cdtab_l1_ctx_desc_t *l1_desc) l1_desc->l2ptr = val_memory_alloc(size*2); if (!l1_desc->l2ptr) { - val_print(ACS_PRINT_ERR, "\n failed to allocate context descriptor table ", 0); + val_print(ERROR, "\n failed to allocate context descriptor table "); return 1; } @@ -1001,14 +1001,14 @@ static int smmu_cdtab_write_ctx_desc(smmu_master_t *master, if (ssid >= (1 << master->stage1_config.s1cdmax)) { - val_print(ACS_PRINT_ERR, "\n smmu_cdtab_write_ctx_desc: ssid out of range ", 0); + val_print(ERROR, "\n smmu_cdtab_write_ctx_desc: ssid out of range "); return 0; } cdptr = smmu_cdtab_get_ctx_desc(master); if (!cdptr) { - val_print(ACS_PRINT_ERR, "\n smmu_cdtab_write_ctx_desc: cdptr is NULL ", 0); + val_print(ERROR, "\n smmu_cdtab_write_ctx_desc: cdptr is NULL "); return 0; } @@ -1024,7 +1024,7 @@ static int smmu_cdtab_write_ctx_desc(smmu_master_t *master, cdptr[0] = val; - if (g_print_level <= ACS_PRINT_INFO) + if (g_print_level <= TRACE) dump_cdtab(cdptr); return 1; @@ -1084,7 +1084,7 @@ static int smmu_cdtab_alloc(smmu_master_t *master) cdcfg->cdtab_ptr = val_memory_calloc(2, l1_tbl_size); if (!cdcfg->cdtab_ptr) { - val_print(ACS_PRINT_ERR, "\n smmu_cdtab_alloc: alloc failed ", 0); + val_print(ERROR, "\n smmu_cdtab_alloc: alloc failed "); return 0; } @@ -1117,14 +1117,14 @@ uint64_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt if (master_attr.smmu_index >= g_num_smmus) { - val_print(ACS_PRINT_ERR, "\n val_smmu_map: invalid smmu index ", 0); + val_print(ERROR, "\n val_smmu_map: invalid smmu index "); return 1; } smmu = &g_smmu[master_attr.smmu_index]; if (smmu->base == 0) { - val_print(ACS_PRINT_ERR, "\n val_smmu_map: smmu unsupported ", 0); + val_print(ERROR, "\n val_smmu_map: smmu unsupported "); return 1; } @@ -1157,7 +1157,7 @@ uint64_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt if (master_attr.streamid >= (0x1ul << smmu->sid_bits)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n val_smmu_map: sid %d out of range ", master_attr.streamid); return 1; @@ -1166,7 +1166,7 @@ uint64_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt if (smmu->supported.st_level_2lvl) { if(!smmu_strtab_init_level2(smmu, master->sid)) { - val_print(ACS_PRINT_ERR, "\n val_smmu_map: l2 stream table init failed ", 0); + val_print(ERROR, "\n val_smmu_map: l2 stream table init failed "); return 1; } } @@ -1212,7 +1212,7 @@ uint64_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt ste = smmu_strtab_get_ste_for_sid(smmu, master->sid); smmu_strtab_write_ste(master, ste); - if (g_print_level <= ACS_PRINT_INFO) + if (g_print_level <= TRACE) dump_strtab(ste); smmu_tlbi_cfgi(smmu); @@ -1240,9 +1240,9 @@ uint32_t val_smmu_config_ste_dcp(smmu_master_attributes_t master_attr, uint32_t else ste[1] = ste[1] & BITFIELD_SET(STRTAB_STE_1_DCP, value); - if (g_print_level <= ACS_PRINT_INFO) + if (g_print_level <= TRACE) { - val_print(ACS_PRINT_INFO, "\n Dump STE values", 0); + val_print(TRACE, "\n Dump STE values"); dump_strtab(ste); } @@ -1346,16 +1346,16 @@ uint32_t val_smmu_init(void) g_smmu = val_memory_calloc(g_num_smmus, sizeof(smmu_dev_t)); if (!g_smmu) { - val_print(ACS_PRINT_ERR, "\n smmu_init memory allocation failure", 0); + val_print(ERROR, "\n smmu_init memory allocation failure"); return ACS_STATUS_ERR; } for (g_smmu_index = 0; g_smmu_index < g_num_smmus; ++g_smmu_index) { smmu_version = val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, g_smmu_index); if (smmu_version != 3) { - val_print(ACS_PRINT_ERR, " Only SMMUv3.x init supported\n", 0); - val_print(ACS_PRINT_ERR, " smmu %d version is", g_smmu_index); - val_print(ACS_PRINT_ERR, " %d\n", smmu_version); + val_print(ERROR, " Only SMMUv3.x init supported\n"); + val_print(ERROR, " smmu %d version is", g_smmu_index); + val_print(ERROR, " %d\n", smmu_version); continue; } @@ -1363,7 +1363,7 @@ uint32_t val_smmu_init(void) g_smmu[g_smmu_index].page1_base = g_smmu[g_smmu_index].base + SMMU_PAGE1_BASE_OFFSET; if (smmu_init(&g_smmu[g_smmu_index])) { - val_print(ACS_PRINT_ERR, " smmu_init: smmu %d init failed\n", g_smmu_index); + val_print(ERROR, " smmu_init: smmu %d init failed\n", g_smmu_index); g_smmu[g_smmu_index].base = 0; return ACS_STATUS_ERR; } @@ -1384,7 +1384,7 @@ val_smmu_get_info(SMMU_INFO_e type, uint32_t smmu_index) smmu_dev_t *smmu; if (smmu_index >= g_num_smmus) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n val_smmu_get_info: invalid smmu index(%d) ", smmu_index); return 0; @@ -1407,18 +1407,18 @@ val_smmu_get_info(SMMU_INFO_e type, uint32_t smmu_index) // This API checks if there are any outstanding events in the event queue. void val_smmu_dump_eventq(void) { - val_print(ACS_PRINT_TEST, "\n Eventq dump starting... ", 0); + val_print(INFO, "\n Eventq dump starting... "); for (g_smmu_index = 0; g_smmu_index < g_num_smmus; g_smmu_index++) { if (val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, g_smmu_index) != 3) { - val_print(ACS_PRINT_ERR, "\n only SMMUv3.x supported, skipping smmu %d", g_smmu_index); + val_print(ERROR, "\n only SMMUv3.x supported, skipping smmu %d", g_smmu_index); continue; } - val_print(ACS_PRINT_TEST, "\n Eventq of SMMU index %x ", g_smmu_index); + val_print(INFO, "\n Eventq of SMMU index %x ", g_smmu_index); smmu_evtq_thread(); } - val_print(ACS_PRINT_TEST, "\n Eventq dump finished... ", 0); + val_print(INFO, "\n Eventq dump finished... "); return; } diff --git a/val/include/acs_common.h b/val/include/acs_common.h index c38ceb60..a083da29 100644 --- a/val/include/acs_common.h +++ b/val/include/acs_common.h @@ -17,6 +17,7 @@ /** This file is common to all test cases and Val layer of the Suite */ +#include "val_logger.h" #ifndef __ACS_COMMON_H__ diff --git a/val/include/acs_drtm.h b/val/include/acs_drtm.h index bebcf200..7ebe1eec 100644 --- a/val/include/acs_drtm.h +++ b/val/include/acs_drtm.h @@ -28,10 +28,10 @@ #define ACS_ACPI_SIGNATURE(A, B, C, D) ((D << 24) | (C << 16) | (B << 8) | (A)) #define PRINT_ACPI_NAME_FROM_SIGNATURE(sig) \ do { \ - val_print(ACS_PRINT_DEBUG, "\n Table : %c", (char)((sig) & 0xFF)); \ - val_print(ACS_PRINT_DEBUG, "%c", (char)(((sig) >> 8) & 0xFF)); \ - val_print(ACS_PRINT_DEBUG, "%c", (char)(((sig) >> 16) & 0xFF)); \ - val_print(ACS_PRINT_DEBUG, "%c", (char)(((sig) >> 24) & 0xFF)); \ + val_print(DEBUG, "\n Table : %c", (char)((sig) & 0xFF)); \ + val_print(DEBUG, "%c", (char)(((sig) >> 8) & 0xFF)); \ + val_print(DEBUG, "%c", (char)(((sig) >> 16) & 0xFF)); \ + val_print(DEBUG, "%c", (char)(((sig) >> 24) & 0xFF)); \ } while (0) #define DRTM_1_0_FN_BASE 0xC4000110 diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 7cd8b08d..6bfb21ed 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -93,6 +93,7 @@ #include #include "platform_override.h" typedef INT8 int8_t; + typedef INT16 int16_t; typedef INT32 int32_t; typedef INT64 int64_t; typedef CHAR8 char8_t; @@ -108,7 +109,6 @@ typedef INT64 intmax_t; typedef UINT64 uintmax_t; - #if defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L /* bool is a keyword */ #else diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 23ebf2e9..c643e911 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -23,13 +23,8 @@ #include "acs_pfdi.h" #include "acs_cxl.h" -/* set G_PRINT_LEVEL to one of the below values in your application entry - to control the verbosity of the prints */ -#define ACS_PRINT_ERR 5 /* Only Errors. use this to de-clutter the terminal and focus only on specifics */ -#define ACS_PRINT_WARN 4 /* Only warnings & errors. use this to de-clutter the terminal and focus only on specifics */ -#define ACS_PRINT_TEST 3 /* Test description and result descriptions. THIS is DEFAULT */ -#define ACS_PRINT_DEBUG 2 /* For Debug statements. contains register dumps etc */ -#define ACS_PRINT_INFO 1 /* Print all statements. Do not use unless really needed */ +extern uint32_t g_print_level; + #define ACS_STATUS_FAIL 0x90000000 #define ACS_STATUS_ERR 0xEDCB1234 //some impropable value? @@ -39,6 +34,12 @@ #define ACS_INVALID_INDEX 0xFFFFFFFF #define ACS_STATUS_UNKNOWN 0xFFFFFFFF +#define val_print(level, ...) \ + do { \ + if ((level) >= g_print_level) \ + val_printf((level), __VA_ARGS__); \ + } while (0) + #define ACS_STATUS_PAL_NOT_IMPLEMENTED 0x4B1D /* PAL reports feature/API not implemented */ #ifndef NOT_IMPLEMENTED #define NOT_IMPLEMENTED ACS_STATUS_PAL_NOT_IMPLEMENTED @@ -101,7 +102,7 @@ typedef char char8_t; /* GENERIC VAL APIs */ void val_allocate_shared_mem(void); void val_free_shared_mem(void); -void val_print(uint32_t level, char8_t *string, uint64_t data); +//void val_print(uint32_t level, char8_t *string, uint64_t data); void val_print_raw(uint64_t uart_addr, uint32_t level, char8_t *string, uint64_t data); void val_print_primary_pe(uint32_t level, char8_t *string, uint64_t data, uint32_t index); void val_print_test_start(char8_t *string); diff --git a/val/include/val_logger.h b/val/include/val_logger.h index 021cdb71..223c90f4 100644 --- a/val/include/val_logger.h +++ b/val/include/val_logger.h @@ -13,7 +13,6 @@ #endif #include "pal_interface.h" -#include #include #include diff --git a/val/src/AArch64/Drtm.S b/val/src/AArch64/Drtm.S index c5a25f3c..46fb09d1 100644 --- a/val/src/AArch64/Drtm.S +++ b/val/src/AArch64/Drtm.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/AArch64/SystemReg.S b/val/src/AArch64/SystemReg.S index fab6bb80..00b12355 100644 --- a/val/src/AArch64/SystemReg.S +++ b/val/src/AArch64/SystemReg.S @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/AArch64/VecTable.S b/val/src/AArch64/VecTable.S index b9d28378..ba6998e8 100644 --- a/val/src/AArch64/VecTable.S +++ b/val/src/AArch64/VecTable.S @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/acs_cxl.c b/val/src/acs_cxl.c index e0478f7a..101ab3d1 100644 --- a/val/src/acs_cxl.c +++ b/val/src/acs_cxl.c @@ -51,12 +51,12 @@ CXL_COMPONENT_ENTRY * val_cxl_get_component_entry(uint32_t component_index) { if (g_cxl_component_table == NULL) { - val_print(ACS_PRINT_ERR, " CXL: component table not initialised", 0); + val_print(ERROR, " CXL: component table not initialised"); return NULL; } if (component_index >= g_cxl_component_table->num_entries) { - val_print(ACS_PRINT_ERR, " CXL: invalid component index %u", component_index); + val_print(ERROR, " CXL: invalid component index %u", component_index); return NULL; } @@ -91,12 +91,12 @@ val_cxl_find_comp_capability(uint32_t index, uint32_t cap_id) for (idx = 0; idx <= entries; ++idx) { cap_hdr = val_mmio_read(base + (uint64_t)idx * CXL_CAP_HDR_SIZE); - val_print(ACS_PRINT_INFO, "\n cap_hdr %llx", cap_hdr); + val_print(TRACE, "\n cap_hdr %llx", cap_hdr); if ((cap_hdr == 0u) || (cap_hdr == PCIE_UNKNOWN_RESPONSE)) continue; found_id = CXL_CAP_HDR_CAPID(cap_hdr); - val_print(ACS_PRINT_INFO, "\n Found id %llx", found_id); + val_print(TRACE, "\n Found id %llx", found_id); if (found_id == cap_id) return 0; @@ -159,7 +159,7 @@ val_cxl_print_component_summary(void) uint32_t idx; if (g_cxl_component_table == NULL) { - val_print(ACS_PRINT_INFO, " CXL_COMPONENT: Discovered 0 components", 0); + val_print(TRACE, " CXL_COMPONENT: Discovered 0 components"); return; } @@ -195,40 +195,40 @@ val_cxl_print_component_summary(void) } } - val_print(ACS_PRINT_TEST, " CXL_INFO: Number of host bridges : %u\n", + val_print(INFO, " CXL_INFO: Number of host bridges : %u\n", g_cxl_info_table->num_entries); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Number of components : %4u\n", (uint64_t)total); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Root Ports : %4u\n", (uint64_t)role_root_port); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Devices (Endpoints) : %4u\n", (uint64_t)role_endpoint); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Type1 Devices : %4u\n", (uint64_t)type1_devices); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Type2 Devices : %4u\n", (uint64_t)type2_devices); - val_print(ACS_PRINT_TEST, + val_print(INFO, " CXL_INFO: Type3 Devices : %4u\n", (uint64_t)type3_devices); - val_print(ACS_PRINT_INFO, " CXL_COMPONENT: Discovered %u components", (uint64_t)total); + val_print(TRACE, " CXL_COMPONENT: Discovered %u components", (uint64_t)total); for (idx = 0; idx < g_cxl_component_table->num_entries; idx++) { const CXL_COMPONENT_ENTRY *entry = &g_cxl_component_table->component[idx]; const char *role_str = val_cxl_role_name(entry->role); const char *dtype_str = val_cxl_device_type_name(entry->device_type); - val_print(ACS_PRINT_INFO, "\n Component Index : %u", (uint64_t)idx); - val_print(ACS_PRINT_INFO, " BDF : 0x%x", (uint64_t)entry->bdf); - val_print(ACS_PRINT_INFO, " Role : %a", (uint64_t)role_str); - val_print(ACS_PRINT_INFO, " Device Type : %a", (uint64_t)dtype_str); + val_print(TRACE, "\n Component Index : %u", (uint64_t)idx); + val_print(TRACE, " BDF : 0x%x", (uint64_t)entry->bdf); + val_print(TRACE, " Role : %a", (uint64_t)role_str); + val_print(TRACE, " Device Type : %a", (uint64_t)dtype_str); if (entry->component_reg_base) { - val_print(ACS_PRINT_INFO, " CompReg Base : 0x%llx", entry->component_reg_base); - val_print(ACS_PRINT_INFO, " CompReg Len : 0x%llx", entry->component_reg_length); + val_print(TRACE, " CompReg Base : 0x%llx", entry->component_reg_base); + val_print(TRACE, " CompReg Len : 0x%llx", entry->component_reg_length); } - val_print(ACS_PRINT_INFO, " HDM Decoder Count : %u", entry->hdm_decoder_count); + val_print(TRACE, " HDM Decoder Count : %u", entry->hdm_decoder_count); } } @@ -255,7 +255,7 @@ val_cxl_find_capability(uint32_t bdf, uint32_t cid, uint32_t *cid_offset) dvsec_id = hdr2 & CXL_DVSEC_HDR2_ID_MASK; if (dvsec_id == cid) { - val_print(ACS_PRINT_INFO, " \nFound CXL DVSEC 0x%lx", dvsec_id); + val_print(TRACE, " \nFound CXL DVSEC 0x%lx", dvsec_id); *cid_offset = next_cap_offset; return 0; } @@ -350,8 +350,8 @@ val_cxl_free_component_table(void) g_cxl_component_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_cxl_component_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_cxl_component_table pointer is already NULL"); } } @@ -376,7 +376,7 @@ val_cxl_get_component_info(CXL_COMPONENT_INFO_e type, uint32_t index) { if (g_cxl_component_table == NULL) { - val_print(ACS_PRINT_ERR, " GET_CXL_COMPONENT_INFO: component table not created", 0); + val_print(ERROR, " GET_CXL_COMPONENT_INFO: component table not created"); return 0; } @@ -384,7 +384,7 @@ val_cxl_get_component_info(CXL_COMPONENT_INFO_e type, uint32_t index) return g_cxl_component_table->num_entries; if (index >= g_cxl_component_table->num_entries) { - val_print(ACS_PRINT_ERR, " GET_CXL_COMPONENT_INFO: Invalid index %u", index); + val_print(ERROR, " GET_CXL_COMPONENT_INFO: Invalid index %u", index); return 0; } @@ -405,7 +405,7 @@ val_cxl_get_component_info(CXL_COMPONENT_INFO_e type, uint32_t index) case CXL_COMPONENT_INFO_HDM_COUNT: return entry->hdm_decoder_count; default: - val_print(ACS_PRINT_ERR, " GET_CXL_COMPONENT_INFO: Unsupported type %u", type); + val_print(ERROR, " GET_CXL_COMPONENT_INFO: Unsupported type %u", type); break; } @@ -645,10 +645,10 @@ void val_cxl_dump_reg_block(uint64_t base_pa, hdr_fmt = " \n[CXL Device Registers] base=0x%lx"; else hdr_fmt = " \n[CXL Register Block] base=0x%lx"; - val_print(ACS_PRINT_INFO, (char8_t *)hdr_fmt, base_pa); + val_print(TRACE, (char8_t *)hdr_fmt, base_pa); if (block_len && block_len < CXL_CAP_HDR_SIZE) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: Block length too small\n", 0); + val_print(TRACE, " ERROR in CXL Summary :: Block length too small\n"); return; } @@ -665,19 +665,19 @@ void val_cxl_dump_reg_block(uint64_t base_pa, hdr_cnt = max_cnt_by_len; } - val_print(ACS_PRINT_INFO, " \nDevCap Array count=%ld", (uint64_t)hdr_cnt); + val_print(TRACE, " \nDevCap Array count=%ld", (uint64_t)hdr_cnt); for (i = 0; i < hdr_cnt; ++i) { if (val_cxl_dev_cap_hdr_read(hdr_base, i, &id_local, &ver_local, &cap_off)) break; id = id_local; ver = ver_local; - val_print(ACS_PRINT_INFO, " \nDevCap[%ld]: ", (uint64_t)i); - val_print(ACS_PRINT_INFO, " ID=0x%x ", (uint64_t)id); - val_print(ACS_PRINT_INFO, " (%a) ", (uint64_t)val_cxl_dev_cap_name(id)); - val_print(ACS_PRINT_INFO, " Ver=%d ", (uint64_t)ver); - val_print(ACS_PRINT_INFO, " Off=0x%x", (uint64_t)cap_off); + val_print(TRACE, " \nDevCap[%ld]: ", (uint64_t)i); + val_print(TRACE, " ID=0x%x ", (uint64_t)id); + val_print(TRACE, " (%a) ", (uint64_t)val_cxl_dev_cap_name(id)); + val_print(TRACE, " Ver=%d ", (uint64_t)ver); + val_print(TRACE, " Off=0x%x", (uint64_t)cap_off); /* Bounds check for capability structure */ if (block_len && cap_off >= block_len) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary:: -> Cap offset out of range", 0); + val_print(TRACE, " ERROR in CXL Summary:: -> Cap offset out of range"); } } return; @@ -688,11 +688,11 @@ void val_cxl_dump_reg_block(uint64_t base_pa, cap_ver = CXL_CAP_HDR_VER(arr_hdr); cachemem_ver = CXL_CAP_HDR_CACHEMEM_VER(arr_hdr); arr_sz = CXL_CAP_ARRAY_ENTRIES(arr_hdr); - val_print(ACS_PRINT_INFO, " \nCXL_Capability_Header: ID=0x%x", cap_id); - val_print(ACS_PRINT_INFO, " \nPrimary Array: CXL.cachemem v%ld", + val_print(TRACE, " \nCXL_Capability_Header: ID=0x%x", cap_id); + val_print(TRACE, " \nPrimary Array: CXL.cachemem v%ld", (uint64_t)cachemem_ver); - val_print(ACS_PRINT_INFO, " CXL Cap v%ld", cap_ver); - val_print(ACS_PRINT_INFO, " entries=%ld", arr_sz); + val_print(TRACE, " CXL Cap v%ld", cap_ver); + val_print(TRACE, " entries=%ld", arr_sz); for (idx = 0; idx <= arr_sz; ++idx) { cap_hdr = val_mmio_read(base_pa + (uint64_t)idx * CXL_CAP_HDR_SIZE); if (cap_hdr == PCIE_UNKNOWN_RESPONSE || cap_hdr == 0x00000000) @@ -701,10 +701,10 @@ void val_cxl_dump_reg_block(uint64_t base_pa, ver = CXL_CAP_HDR_VER(cap_hdr); cap_ptr = CXL_CAP_HDR_POINTER(cap_hdr); cap_base = base_pa + cap_ptr; - val_print(ACS_PRINT_INFO, " \nCapID=0x%x ", id); - val_print(ACS_PRINT_INFO, " (%a) ", (uint64_t)val_cxl_cap_name(id)); - val_print(ACS_PRINT_INFO, " Ver=%d ", ver); - val_print(ACS_PRINT_INFO, " @+0x%llx", (idx * CXL_CAP_HDR_SIZE)); + val_print(TRACE, " \nCapID=0x%x ", id); + val_print(TRACE, " (%a) ", (uint64_t)val_cxl_cap_name(id)); + val_print(TRACE, " Ver=%d ", ver); + val_print(TRACE, " @+0x%llx", (idx * CXL_CAP_HDR_SIZE)); if ((component != NULL) && (block_id == CXL_REG_BLOCK_COMPONENT) && (id == CXL_CAPID_HDM_DECODER)) val_cxl_parse_hdm_capability(component, cap_base); @@ -777,7 +777,7 @@ static void val_cxl_parse_register_locator(uint32_t bdf, val_cxl_assign_component_role(component, dp_type); if (val_pcie_read_cfg(bdf, ecap_off + CXL_DVSEC_HDR1_OFFSET, &dvsec_hdr1)) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: DVSEC Header1 read failed", 0); + val_print(TRACE, " ERROR in CXL Summary :: DVSEC Header1 read failed"); return; } @@ -785,26 +785,26 @@ static void val_cxl_parse_register_locator(uint32_t bdf, dvsec_rev = (dvsec_hdr1 >> CXL_DVSEC_HDR1_REV_SHIFT) & CXL_DVSEC_HDR1_REV_MASK; dvsec_len = (dvsec_hdr1 >> CXL_DVSEC_HDR1_LEN_SHIFT) & CXL_DVSEC_HDR1_LEN_MASK; - val_print(ACS_PRINT_INFO, " \nDVSEC Header 1 : 0x%lx", dvsec_hdr1); - val_print(ACS_PRINT_INFO, " \nVendor ID : 0x%lx", dvsec_vendor); - val_print(ACS_PRINT_INFO, " Revision : 0x%lx", dvsec_rev); - val_print(ACS_PRINT_INFO, " Length (B) : 0x%lx", dvsec_len); + val_print(TRACE, " \nDVSEC Header 1 : 0x%lx", dvsec_hdr1); + val_print(TRACE, " \nVendor ID : 0x%lx", dvsec_vendor); + val_print(TRACE, " Revision : 0x%lx", dvsec_rev); + val_print(TRACE, " Length (B) : 0x%lx", dvsec_len); if (dvsec_len < CXL_RL_REG_BLK_ENTRIES || ((dvsec_len - CXL_RL_REG_BLK_ENTRIES) % CXL_RL_ENTRY_SIZE) != 0) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: RL: Bad DVSEC Length 0x%lx", + val_print(TRACE, " ERROR in CXL Summary :: RL: Bad DVSEC Length 0x%lx", (uint64_t)dvsec_len); return; } num_entries = (dvsec_len - CXL_RL_REG_BLK_ENTRIES) / CXL_RL_ENTRY_SIZE; - val_print(ACS_PRINT_INFO, " \nRegister Locator: %ld entries", num_entries); + val_print(TRACE, " \nRegister Locator: %ld entries", num_entries); ent_off_cfg = ecap_off + CXL_RL_REG_BLK_ENTRIES; for (i = 0; i < num_entries; i++, ent_off_cfg += CXL_RL_ENTRY_SIZE) { if (val_pcie_read_cfg(bdf, ent_off_cfg + CXL_RL_REG_OFF_LOW, ®0) || val_pcie_read_cfg(bdf, ent_off_cfg + CXL_RL_REG_OFF_HIGH, &off)) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: RL[%ld]: entry read failed", i); + val_print(TRACE, " ERROR in CXL Summary :: RL[%ld]: entry read failed", i); continue; } @@ -816,21 +816,21 @@ static void val_cxl_parse_register_locator(uint32_t bdf, { bar_st = val_cxl_get_mmio_bar_host_pa(bdf, bar_num, &bar_base, &bar_is64); if (bar_st != PCIE_SUCCESS) { - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: RL[%ld]: ", i); - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: BAR%ld not usable ", + val_print(TRACE, " ERROR in CXL Summary :: RL[%ld]: ", i); + val_print(TRACE, " ERROR in CXL Summary :: BAR%ld not usable ", (uint64_t)bar_num); switch (bar_st) { case VAL_CXL_BAR_ERR_INVALID_INDEX: - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: Invalid BAR index", 0); + val_print(TRACE, " ERROR in CXL Summary :: Invalid BAR index"); break; case VAL_CXL_BAR_ERR_CFG_READ: - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: CFG read failed", 0); + val_print(TRACE, " ERROR in CXL Summary :: CFG read failed"); break; case VAL_CXL_BAR_ERR_NOT_MMIO: - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: BAR not MMIO type", 0); + val_print(TRACE, " ERROR in CXL Summary :: BAR not MMIO type"); break; case VAL_CXL_BAR_ERR_ZERO: - val_print(ACS_PRINT_INFO, " ERROR in CXL Summary :: BAR is zero", 0); + val_print(TRACE, " ERROR in CXL Summary :: BAR is zero"); break; default: break; @@ -839,10 +839,10 @@ static void val_cxl_parse_register_locator(uint32_t bdf, } } block_pa = bar_base + reg_off; - val_print(ACS_PRINT_INFO, " \nRL reg0=0x%lx ", reg0); - val_print(ACS_PRINT_INFO, " off=0x%lx", off); - val_print(ACS_PRINT_INFO, " BlockID=0x%x ", block_id); - val_print(ACS_PRINT_INFO, " BIR=%d", CXL_RL_BAR_NUM(bir)); + val_print(TRACE, " \nRL reg0=0x%lx ", reg0); + val_print(TRACE, " off=0x%lx", off); + val_print(TRACE, " BlockID=0x%x ", block_id); + val_print(TRACE, " BIR=%d", CXL_RL_BAR_NUM(bir)); blkname = (block_id == CXL_REG_BLOCK_COMPONENT) ? "\nCXL Component Registers" : @@ -850,11 +850,11 @@ static void val_cxl_parse_register_locator(uint32_t bdf, (block_id == CXL_REG_BLOCK_VENDOR_SPECIFIC) ? "Vendor-Specific Reg Block" : "CXL Register Block"; - val_print(ACS_PRINT_INFO, " \nRL[%ld]: ", i); - val_print(ACS_PRINT_INFO, " BlockID=0x%x ", block_id); - val_print(ACS_PRINT_INFO, " (%a) ", (uint64_t)blkname); - val_print(ACS_PRINT_INFO, " BIR=%ld ", CXL_RL_BAR_NUM(bir)); - val_print(ACS_PRINT_INFO, " off=0x%lx ", reg_off); + val_print(TRACE, " \nRL[%ld]: ", i); + val_print(TRACE, " BlockID=0x%x ", block_id); + val_print(TRACE, " (%a) ", (uint64_t)blkname); + val_print(TRACE, " BIR=%ld ", CXL_RL_BAR_NUM(bir)); + val_print(TRACE, " off=0x%lx ", reg_off); if (component && block_id == CXL_REG_BLOCK_COMPONENT) { component->component_reg_base = block_pa + CXL_CACHEMEM_PRIMARY_OFFSET; @@ -961,7 +961,7 @@ val_cxl_assign_host_bridge_indices(void) } entry->host_bridge_index = host_index; - val_print(ACS_PRINT_INFO, " \n host_index:%llx ", host_index); + val_print(TRACE, " \n host_index:%llx ", host_index); } } @@ -1042,7 +1042,7 @@ val_cxl_create_table() if (val_cxl_device_is_cxl(bdf) != ACS_STATUS_PASS) continue; - val_print(ACS_PRINT_INFO, "\n CXL device is: 0x%lx ", bdf); + val_print(TRACE, "\n CXL device is: 0x%lx ", bdf); status = val_cxl_create_default_component_table(); if (status != ACS_STATUS_PASS) return ACS_STATUS_ERR; @@ -1090,9 +1090,9 @@ val_cxl_create_table() if (val_cxl_get_or_create_component(bdf) == NULL) return ACS_STATUS_ERR; - val_print(ACS_PRINT_INFO, "\n BDF: 0x%lx :: ", bdf); - val_print(ACS_PRINT_INFO, " Device type : 0x%lx", dp_type); - val_print(ACS_PRINT_INFO, " Found CXL DVSEC (ID=0x%x)", dvsec_id); + val_print(TRACE, "\n BDF: 0x%lx :: ", bdf); + val_print(TRACE, " Device type : 0x%lx", dp_type); + val_print(TRACE, " Found CXL DVSEC (ID=0x%x)", dvsec_id); switch (dvsec_id) { case CXL_DVSEC_ID_DEVICE: @@ -1150,7 +1150,7 @@ val_cxl_create_info_table(uint64_t *cxl_info_table) uint32_t window; if (cxl_info_table == NULL) { - val_print(ACS_PRINT_ERR, " CXL_INFO: Input table pointer is NULL ", 0); + val_print(ERROR, " CXL_INFO: Input table pointer is NULL "); return; } g_cxl_info_table = (CXL_INFO_TABLE *)cxl_info_table; @@ -1159,7 +1159,7 @@ val_cxl_create_info_table(uint64_t *cxl_info_table) /* Print parsed informationi*/ num_cxl_hb = g_cxl_info_table->num_entries; - val_print(ACS_PRINT_INFO, "\n CXL_INFO: Number of host bridges : %u\n", num_cxl_hb); + val_print(TRACE, "\n CXL_INFO: Number of host bridges : %u\n", num_cxl_hb); if (num_cxl_hb == 0) return; @@ -1168,25 +1168,25 @@ val_cxl_create_info_table(uint64_t *cxl_info_table) CXL_INFO_BLOCK *entry = &g_cxl_info_table->device[index]; if (val_cxl_host_discover_capabilities(entry) != ACS_STATUS_PASS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, " CXL_INFO: Failed to map host bridge component window (UID 0x%x)", entry->uid); } - val_print(ACS_PRINT_INFO, " \nCXL_INFO: Host Bridge[%u]\n", index); - val_print(ACS_PRINT_INFO, " UID : 0x%x\n", entry->uid); - val_print(ACS_PRINT_INFO, " Structure Type : 0x%x\n", entry->cxl_struct_type); - val_print(ACS_PRINT_INFO, " Component Type : 0x%x\n", entry->component_reg_type); - val_print(ACS_PRINT_INFO, " Component Base : 0x%llx\n", entry->component_reg_base); - val_print(ACS_PRINT_INFO, " Component Length : 0x%llx\n", entry->component_reg_length); - val_print(ACS_PRINT_INFO, " Revision : 0x%x\n", entry->cxl_version); + val_print(TRACE, " \nCXL_INFO: Host Bridge[%u]\n", index); + val_print(TRACE, " UID : 0x%x\n", entry->uid); + val_print(TRACE, " Structure Type : 0x%x\n", entry->cxl_struct_type); + val_print(TRACE, " Component Type : 0x%x\n", entry->component_reg_type); + val_print(TRACE, " Component Base : 0x%llx\n", entry->component_reg_base); + val_print(TRACE, " Component Length : 0x%llx\n", entry->component_reg_length); + val_print(TRACE, " Revision : 0x%x\n", entry->cxl_version); - val_print(ACS_PRINT_INFO, " CFMWS Count : %u", entry->cfmws_count); + val_print(TRACE, " CFMWS Count : %u", entry->cfmws_count); for (window = 0; window < entry->cfmws_count && window < CXL_MAX_CFMWS_WINDOWS; window++) { - val_print(ACS_PRINT_INFO, " CFMWS Index : %u\n", window); - val_print(ACS_PRINT_INFO, " Base : 0x%llx\n", entry->cfmws_base[window]); - val_print(ACS_PRINT_INFO, " Length : 0x%llx\n", entry->cfmws_length[window]); + val_print(TRACE, " CFMWS Index : %u\n", window); + val_print(TRACE, " Base : 0x%llx\n", entry->cfmws_base[window]); + val_print(TRACE, " Length : 0x%llx\n", entry->cfmws_length[window]); } } @@ -1215,12 +1215,12 @@ val_cxl_get_info(CXL_INFO_e type, uint32_t index) { if (g_cxl_info_table == NULL) { - val_print(ACS_PRINT_ERR, " GET_CXL_INFO: CXL info table is not created ", 0); + val_print(ERROR, " GET_CXL_INFO: CXL info table is not created "); return 0; } if ((type != CXL_INFO_NUM_DEVICES) && (index >= g_cxl_info_table->num_entries)) { - val_print(ACS_PRINT_ERR, " GET_CXL_INFO: Invalid index %d ", index); + val_print(ERROR, " GET_CXL_INFO: Invalid index %d ", index); return 0; } @@ -1242,7 +1242,7 @@ val_cxl_get_info(CXL_INFO_e type, uint32_t index) case CXL_INFO_VERSION: return g_cxl_info_table->device[index].cxl_version; default: - val_print(ACS_PRINT_ERR, " GET_CXL_INFO: Unsupported info type %d ", type); + val_print(ERROR, " GET_CXL_INFO: Unsupported info type %d ", type); break; } @@ -1330,8 +1330,8 @@ val_cxl_get_cfmws_window(uint32_t host_index, uint64_t *base, uint64_t *size) if (((candidate_base | candidate_size) & CXL_HDM_ALIGNMENT_MASK) != 0u) continue; - val_print(ACS_PRINT_INFO, "\n CFMWS Base address is : 0x%llx", candidate_base); - val_print(ACS_PRINT_INFO, "\n CFMWS address size is : 0x%llx", candidate_size); + val_print(TRACE, "\n CFMWS Base address is : 0x%llx", candidate_base); + val_print(TRACE, "\n CFMWS address size is : 0x%llx", candidate_size); *base = candidate_base; *size = candidate_size; return ACS_STATUS_PASS; @@ -1356,7 +1356,7 @@ val_cxl_device_cache_capable(uint32_t bdf) uint32_t cxl_caps; if (val_cxl_find_capability(bdf, CXL_DVSEC_ID_DEVICE, &dvsec_off)) { - val_print(ACS_PRINT_DEBUG, "DVSEC Capability not found for bdf 0x%x", bdf); + val_print(DEBUG, "DVSEC Capability not found for bdf 0x%x", bdf); return 0; } diff --git a/val/src/acs_dma.c b/val/src/acs_dma.c index 0b1f52ef..9a1521bb 100644 --- a/val/src/acs_dma.c +++ b/val/src/acs_dma.c @@ -39,9 +39,8 @@ val_dma_free_info_table(void) g_dma_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_dma_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_dma_info_table pointer is already NULL"); } } @@ -57,16 +56,16 @@ val_dma_create_info_table(uint64_t *dma_info_ptr) { if (dma_info_ptr == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating DMA INFO table\n", 0); + val_print(TRACE, " Creating DMA INFO table\n"); g_dma_info_table = (DMA_INFO_TABLE *)dma_info_ptr; pal_dma_create_info_table(g_dma_info_table); - val_print(ACS_PRINT_TEST, " DMA_INFO: Number of DMA CTRL in PCIe : %x\n", + val_print(INFO, " DMA_INFO: Number of DMA CTRL in PCIe : %x\n", val_dma_get_info(DMA_NUM_CTRL, 0)); } @@ -86,12 +85,12 @@ val_dma_get_info(DMA_INFO_e type, uint32_t index) if (g_dma_info_table == NULL) { - val_print(ACS_PRINT_DEBUG, "GET_DMA_INFO: DMA info table is not created\n", 0); + val_print(DEBUG, "GET_DMA_INFO: DMA info table is not created\n"); return 0; } if (index > g_dma_info_table->num_dma_ctrls) { - val_print(ACS_PRINT_ERR, "GET_DMA_INFO: Index (%d) is greater than num of DMA\n", index); + val_print(ERROR, "GET_DMA_INFO: Index (%d) is greater than num of DMA\n", index); return 0; } @@ -119,7 +118,7 @@ val_dma_get_info(DMA_INFO_e type, uint32_t index) return ((uint64_t)g_dma_info_table->info[index].flags & (PCI_EP_MASK)); default: - val_print(ACS_PRINT_ERR, "This DMA info option not supported %d\n", type); + val_print(ERROR, "This DMA info option not supported %d\n", type); break; } diff --git a/val/src/acs_ete.c b/val/src/acs_ete.c index 3d5f4650..a927a9d2 100644 --- a/val/src/acs_ete.c +++ b/val/src/acs_ete.c @@ -69,13 +69,13 @@ uint64_t parse_tracestream(uint8_t *trace_bytes, uint64_t trace_size) uint64_t trcidr0_read = val_pe_reg_read(TRCIDR0); uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Trace Size: %d ", trace_size, pe_index); + val_print_primary_pe(DEBUG, "\n Trace Size: %d ", trace_size, pe_index); /* Iterate through trace stream bytes until all are parsed */ while (byte_index < trace_size) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n byte_value: %d ", + val_print_primary_pe(DEBUG, "\n byte_value: %d ", trace_bytes[byte_index], pe_index); - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Trace index of the byte value: %d ", + val_print_primary_pe(DEBUG, "\n Trace index of the byte value: %d ", byte_index, pe_index); /* Identify and handle packet type based on current header packet byte */ @@ -301,7 +301,7 @@ uint64_t parse_tracestream(uint8_t *trace_bytes, uint64_t trace_size) ((header & Q_EXACT_MATCH_PKT_MASK) == Q_EXACT_MATCH_PKT_VAL)) pkt_len = 1 + trace_cbit_len(trace_bytes, byte_index, 1, 5); else { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Reserved or Invalid Trace Packet", + val_print_primary_pe(DEBUG, "\n Reserved or Invalid Trace Packet", 0, pe_index); return TRACE_PKT_INVALID; } @@ -328,7 +328,7 @@ uint64_t val_ete_get_trace_timestamp(uint64_t buffer_address) val_memcpy(trace_bytes, (void *)buffer_address, 100); ts_start_byte = parse_tracestream(trace_bytes, sizeof(trace_bytes)); if (ts_start_byte == TRACE_PKT_INVALID) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n ETE Parsing failed", 0, index); + val_print_primary_pe(DEBUG, "\n ETE Parsing failed", 0, index); return 0; } @@ -346,11 +346,11 @@ uint64_t val_ete_get_trace_timestamp(uint64_t buffer_address) } if (timestamp == 0) { - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Timestamp Parsing failed", 0, index); + val_print_primary_pe(DEBUG, "\n Timestamp Parsing failed", 0, index); return 0; } else - val_print_primary_pe(ACS_PRINT_DEBUG, "\n Timestamp Value: 0x%llx", timestamp, index); + val_print_primary_pe(DEBUG, "\n Timestamp Value: 0x%llx", timestamp, index); return timestamp; } diff --git a/val/src/acs_exerciser.c b/val/src/acs_exerciser.c index fbea0b7b..7a628824 100644 --- a/val/src/acs_exerciser.c +++ b/val/src/acs_exerciser.c @@ -67,7 +67,7 @@ uint32_t val_exerciser_create_info_table(void) num_ecam = (uint32_t)val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_ERR, " No ECAMs discovered\n ", 0); + val_print(ERROR, " No ECAMs discovered\n "); return 1; } @@ -75,7 +75,7 @@ uint32_t val_exerciser_create_info_table(void) /* if no bdf table ptr return error */ if (bdf_table->num_entries == 0) { - val_print(ACS_PRINT_DEBUG, "\n No BDFs discovered ", 0); + val_print(DEBUG, "\n No BDFs discovered "); return 1; } @@ -88,7 +88,7 @@ uint32_t val_exerciser_create_info_table(void) if (val_pcie_read_cfg(Bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) { /* Return if there is a bdf mapping issue */ - val_print(ACS_PRINT_ERR, "\n BDF 0x%x mapping issue", Bdf); + val_print(ERROR, "\n BDF 0x%x mapping issue", Bdf); return 1; } @@ -101,15 +101,15 @@ uint32_t val_exerciser_create_info_table(void) g_exerciser_info_table.e_info[num_exerciser_info++].initialized = 0; vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK; vendor_name = lookup_vendor_name(vendor_id); - val_print(ACS_PRINT_DEBUG, " exerciser Bdf %x\n", Bdf); - val_print(ACS_PRINT_DEBUG, " Vendor ID: 0x%04x, ", vendor_id); - val_print(ACS_PRINT_DEBUG, "Vendor Name: ", 0); - val_print(ACS_PRINT_DEBUG, vendor_name, 0); - val_print(ACS_PRINT_DEBUG, "\n\n", 0); + val_print(DEBUG, " exerciser Bdf %x\n", Bdf); + val_print(DEBUG, " Vendor ID: 0x%04x, ", vendor_id); + val_print(DEBUG, "Vendor Name: "); + val_print(DEBUG, vendor_name); + val_print(DEBUG, "\n\n"); } } g_exerciser_info_table.num_exerciser = num_exerciser_info; - val_print(ACS_PRINT_TEST, "\n PCIE_INFO: Number of exerciser cards %4d \n", + val_print(INFO, "\n PCIE_INFO: Number of exerciser cards %4d \n", g_exerciser_info_table.num_exerciser); return 0; } @@ -219,7 +219,7 @@ uint32_t val_exerciser_init(uint32_t instance) { Bdf = g_exerciser_info_table.e_info[instance].bdf; if (val_exerciser_get_state(&state, instance) || (state != EXERCISER_ON)) { - val_print(ACS_PRINT_ERR, "\n Exerciser Bdf %lx not ready", Bdf); + val_print(ERROR, "\n Exerciser Bdf %lx not ready", Bdf); return 1; } @@ -237,7 +237,7 @@ uint32_t val_exerciser_init(uint32_t instance) g_exerciser_info_table.e_info[instance].initialized = 1; } else - val_print(ACS_PRINT_INFO, "\n Already initialized %2d", + val_print(TRACE, "\n Already initialized %2d", instance); return 0; } @@ -326,7 +326,7 @@ uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type) case UNCORR_PTLP_EGR_BLK: return UNCORR_PTLP_EGR_BLK_OFFSET; default: - val_print(ACS_PRINT_ERR, "\n Invalid error offset ", 0); + val_print(ERROR, "\n Invalid error offset "); return 0; } } @@ -403,36 +403,35 @@ uint32_t val_exerciser_test_init(void) /* Build BDF table for all PCIe devices */ if (val_pcie_create_device_bdf_table()) { - val_print(ACS_PRINT_WARN, - "\n Create BDF Table Failed, Skipping Exerciser tests...\n", 0); + val_print(WARN, + "\n Create BDF Table Failed, Skipping Exerciser tests...\n"); status = ACS_STATUS_SKIP; return status; } if (pcie_bdf_table_list_flag == 1) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n *** Created device list with valid bdf doesn't match with the" - " platform pcie device hierarchy, Skipping exerciser tests ***\n", - 0); + " platform pcie device hierarchy, Skipping exerciser tests ***\n"); status = ACS_STATUS_SKIP; return status; } - val_print(ACS_PRINT_INFO, "\n Starting Exerciser Setup\n", 0); + val_print(TRACE, "\n Starting Exerciser Setup\n"); /* Create exerciser info table */ val_exerciser_create_info_table(); num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS); if (num_instances == 0) { - val_print(ACS_PRINT_WARN, - "\n No Exerciser Devices Found, Skipping Exerciser tests...\n", 0); + val_print(WARN, + "\n No Exerciser Devices Found, Skipping Exerciser tests...\n"); status = ACS_STATUS_SKIP; return status; } /* Initialize SMMU and disable all contexts initially */ - val_print(ACS_PRINT_INFO, "\n Initializing SMMU\n", 0); + val_print(TRACE, "\n Initializing SMMU\n"); if (val_smmu_init() == ACS_STATUS_ERR) { - val_print(ACS_PRINT_ERR, "\n val_smmu_init() failed \n", 0); + val_print(ERROR, "\n val_smmu_init() failed \n"); status = ACS_STATUS_SKIP; return status; } @@ -444,9 +443,9 @@ uint32_t val_exerciser_test_init(void) /* Configure ITS once */ if (g_its_init != 1) { - val_print(ACS_PRINT_INFO, "\n Initializing ITS\n", 0); + val_print(TRACE, "\n Initializing ITS\n"); if (val_gic_its_configure() == ACS_STATUS_ERR) { - val_print(ACS_PRINT_ERR, "\n val_gic_its_configure() failed \n", 0); + val_print(ERROR, "\n val_gic_its_configure() failed \n"); status = ACS_STATUS_SKIP; return status; } diff --git a/val/src/acs_gic.c b/val/src/acs_gic.c index cd22d96e..9690a7a4 100644 --- a/val/src/acs_gic.c +++ b/val/src/acs_gic.c @@ -38,10 +38,10 @@ val_gic_create_info_table(uint64_t *gic_info_table) uint32_t gic_version, num_msi_frame; if (gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return ACS_STATUS_ERR; } - val_print(ACS_PRINT_INFO, " Creating GIC INFO table\n", 0); + val_print(TRACE, " Creating GIC INFO table\n"); g_gic_info_table = (GIC_INFO_TABLE *)gic_info_table; @@ -51,23 +51,23 @@ val_gic_create_info_table(uint64_t *gic_info_table) gic_version = val_gic_get_info(GIC_INFO_VERSION); num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if ((gic_version != 2) || (num_msi_frame == 0)) /* check if not a GICv2m system */ - val_print(ACS_PRINT_TEST, " GIC INFO: GIC version : v%d\n", gic_version); + val_print(INFO, " GIC INFO: GIC version : v%d\n", gic_version); else - val_print(ACS_PRINT_TEST, " GIC INFO: GIC version : v2m\n", 0); + val_print(INFO, " GIC INFO: GIC version : v2m\n"); - val_print(ACS_PRINT_TEST, " GIC_INFO: Number of GICD : %4d\n", + val_print(INFO, " GIC_INFO: Number of GICD : %4d\n", g_gic_info_table->header.num_gicd); - val_print(ACS_PRINT_TEST, " GIC_INFO: Number of GICR RD : %4d\n", + val_print(INFO, " GIC_INFO: Number of GICR RD : %4d\n", g_gic_info_table->header.num_gicr_rd); if (g_gic_info_table->header.num_gicr_rd == 0) { - val_print(ACS_PRINT_TEST, " GIC_INFO: Number of GICC RD : %4d\n", + val_print(INFO, " GIC_INFO: Number of GICC RD : %4d\n", g_gic_info_table->header.num_gicc_rd); } - val_print(ACS_PRINT_TEST, " GIC_INFO: Number of ITS : %4d\n", + val_print(INFO, " GIC_INFO: Number of ITS : %4d\n", g_gic_info_table->header.num_its); if (g_gic_info_table->header.num_gicd == 0) { - val_print(ACS_PRINT_ERR,"\n ** CRITICAL ERROR: GIC Distributor count is 0 **\n", 0); + val_print(ERROR, "\n ** CRITICAL ERROR: GIC Distributor count is 0 **\n"); return ACS_STATUS_ERR; } @@ -94,8 +94,8 @@ val_gic_free_info_table(void) g_gic_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_gic_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_gic_info_table pointer is already NULL"); } } @@ -114,7 +114,7 @@ val_get_gicd_base(void) GIC_INFO_ENTRY *gic_entry; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GIC INFO table not available\n", 0); + val_print(ERROR, "GIC INFO table not available\n"); return 0; } @@ -172,7 +172,7 @@ val_gic_get_pe_rdbase(uint64_t mpidr) /* If System doesn't have GICR RD strcture, then use GICCC RD base */ if (g_gic_info_table->header.num_gicr_rd == 0) { gicrd_base = val_get_gicr_base(&gicrd_baselen, 0); - val_print(ACS_PRINT_DEBUG, " gicrd_base 0x%lx\n", gicrd_base); + val_print(DEBUG, " gicrd_base 0x%lx\n", gicrd_base); /* If information is present in GICC Structure */ if (gicrd_baselen == 0) @@ -188,13 +188,13 @@ val_gic_get_pe_rdbase(uint64_t mpidr) /* Use GICR RD base structure */ while (gicr_rdindex < g_gic_info_table->header.num_gicr_rd) { gicrd_base = val_get_gicr_base(&gicrd_baselen, gicr_rdindex); - val_print(ACS_PRINT_INFO, " gicr_rdindex %d", gicr_rdindex); - val_print(ACS_PRINT_INFO, " gicrd_base 0x%lx\n", gicrd_base); + val_print(TRACE, " gicr_rdindex %d", gicr_rdindex); + val_print(TRACE, " gicrd_base 0x%lx\n", gicrd_base); pe_gicrd_base = gicrd_base; while (pe_gicrd_base < (gicrd_base + gicrd_baselen)) { - val_print(ACS_PRINT_INFO, " GICR_TYPER 0x%lx\n", + val_print(TRACE, " GICR_TYPER 0x%lx\n", val_mmio_read64(pe_gicrd_base + GICR_TYPER)); affinity = (val_mmio_read64(pe_gicrd_base + GICR_TYPER) & GICR_TYPER_AFF) >> 32; @@ -226,7 +226,7 @@ val_get_gicr_base(uint32_t *rdbase_len, uint32_t gicr_rd_index) GIC_INFO_ENTRY *gic_entry; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GIC INFO table not available\n", 0); + val_print(ERROR, "GIC INFO table not available\n"); return 0; } gic_entry = g_gic_info_table->gic_info; @@ -264,7 +264,7 @@ val_get_gich_base(void) GIC_INFO_ENTRY *gic_entry; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GIC INFO table not available\n", 0); + val_print(ERROR, "GIC INFO table not available\n"); return 0; } @@ -292,7 +292,7 @@ val_get_cpuif_base(void) GIC_INFO_ENTRY *gic_entry; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GIC INFO table not available\n", 0); + val_print(ERROR, "GIC INFO table not available\n"); return 0; } @@ -323,7 +323,7 @@ val_gic_get_info(GIC_INFO_e type) uint32_t rdbase_len; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Get GIC info called before gic info table is filled ", 0); + val_print(ERROR, "\n Get GIC info called before gic info table is filled "); return 0; } @@ -331,7 +331,7 @@ val_gic_get_info(GIC_INFO_e type) case GIC_INFO_VERSION: if (g_gic_info_table->header.gic_version != 0) { - val_print(ACS_PRINT_INFO, "\n gic version from info table = %d\n", + val_print(TRACE, "\n gic version from info table = %d\n", g_gic_info_table->header.gic_version); return g_gic_info_table->header.gic_version; } @@ -368,7 +368,7 @@ val_gic_get_info(GIC_INFO_e type) return g_gic_info_table->header.num_gicr_rd; default: - val_print(ACS_PRINT_ERR, "\n GIC Info - TYPE not recognized %d ", type); + val_print(ERROR, "\n GIC Info - TYPE not recognized %d ", type); break; } return ACS_STATUS_ERR; @@ -417,7 +417,7 @@ uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e uint32_t config_bit_shift; if (int_id > val_get_max_intid()) { - val_print(ACS_PRINT_ERR, "\n Invalid Interrupt ID number 0x%x ", int_id); + val_print(ERROR, "\n Invalid Interrupt ID number 0x%x ", int_id); return ACS_STATUS_ERR; } @@ -446,7 +446,7 @@ val_gic_espi_supported(void) espi_support = val_gic_espi_support(); - val_print(ACS_PRINT_INFO, "\n ESPI supported %d ", espi_support); + val_print(TRACE, "\n ESPI supported %d ", espi_support); return espi_support; } @@ -500,8 +500,8 @@ uint32_t val_gic_route_interrupt_to_pe(uint32_t int_id, uint64_t mpidr) val_mmio_write64(val_get_gicd_base() + GICD_IROUTER + (8 * int_id), cpuaffinity); } else{ - val_print(ACS_PRINT_ERR, "\n Only SPIs can be routed, ", 0); - val_print(ACS_PRINT_ERR, "interrupt with INTID = %d cannot be routed", int_id); + val_print(ERROR, "\n Only SPIs can be routed, "); + val_print(ERROR, "interrupt with INTID = %d cannot be routed", int_id); } return 0; @@ -548,7 +548,7 @@ void val_gic_clear_interrupt(uint32_t int_id) ((uint32_t)1 << reg_shift)); } else - val_print(ACS_PRINT_ERR, "\n Invalid SPI interrupt ID number %d", int_id); + val_print(ERROR, "\n Invalid SPI interrupt ID number %d", int_id); } /** @@ -567,7 +567,7 @@ uint32_t val_gic_get_espi_intr_trigger_type(uint32_t int_id, uint32_t config_bit_shift; if (!(int_id >= 4096 && int_id <= val_gic_max_espi_val())) { - val_print(ACS_PRINT_ERR, "\n Invalid Extended Int ID number 0x%x ", int_id); + val_print(ERROR, "\n Invalid Extended Int ID number 0x%x ", int_id); return ACS_STATUS_ERR; } @@ -599,7 +599,7 @@ void val_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_ uint32_t reg_offset; uint32_t config_bit_shift; - val_print(ACS_PRINT_DEBUG, "\n Setting Trigger type as %d", trigger_type); + val_print(DEBUG, "\n Setting Trigger type as %d", trigger_type); reg_offset = int_id / GICD_ICFGR_INTR_STRIDE; config_bit_shift = GICD_ICFGR_INTR_CONFIG1(int_id); @@ -611,7 +611,7 @@ void val_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_ else reg_value = reg_value & (~((uint32_t)1 << config_bit_shift)); - val_print(ACS_PRINT_INFO, "\n Writing to Register Address : 0x%llx ", + val_print(TRACE, "\n Writing to Register Address : 0x%llx ", val_get_gicd_base() + GICD_ICFGR + (4 * reg_offset)); val_mmio_write(val_get_gicd_base() + GICD_ICFGR + (4 * reg_offset), reg_value); diff --git a/val/src/acs_gic_support.c b/val/src/acs_gic_support.c index 984a1b74..027da426 100644 --- a/val/src/acs_gic_support.c +++ b/val/src/acs_gic_support.c @@ -137,7 +137,7 @@ val_gic_install_isr(uint32_t int_id, void (*isr)(void)) if (((int_id > val_get_max_intid()) && (!val_gic_is_valid_lpi(int_id)) && (!val_gic_is_valid_espi(int_id)) && (!val_gic_is_valid_eppi(int_id))) || (int_id == 0)) { - val_print(ACS_PRINT_ERR, "\n Invalid Interrupt ID number 0x%x ", int_id); + val_print(ERROR, "\n Invalid Interrupt ID number 0x%x ", int_id); return ACS_STATUS_ERR; } #endif @@ -218,8 +218,7 @@ uint32_t val_gic_its_configure() /* Allocate memory to store ITS info */ g_gic_its_info = (GIC_ITS_INFO *) val_aligned_alloc(MEM_ALIGN_4K, 1024); if (!g_gic_its_info) { - val_print(ACS_PRINT_ERR, " ITS Configure: memory allocation failed\n", - 0); + val_print(ERROR, " ITS Configure: memory allocation failed\n"); return ACS_STATUS_ERR; } @@ -252,14 +251,13 @@ uint32_t val_gic_its_configure() /* Return if no ITS */ if (g_gic_its_info->GicNumIts == 0) { - val_print(ACS_PRINT_DEBUG, " ITS Configure: No ITS Found\n", 0); + val_print(DEBUG, " ITS Configure: No ITS Found\n"); goto its_fail; } /* Base Address Check. */ if ((g_gic_its_info->GicRdBase == 0) || (g_gic_its_info->GicDBase == 0)) { - val_print(ACS_PRINT_DEBUG, " ITS Configure: GICD/GICRD Base addr failed\n", - 0); + val_print(DEBUG, " ITS Configure: GICD/GICRD Base addr failed\n"); goto its_fail; } @@ -267,11 +265,11 @@ uint32_t val_gic_its_configure() && val_its_gicr_lpi_support(g_gic_its_info->GicRdBase)) { Status = val_its_init(); if ((Status)) { - val_print(ACS_PRINT_DEBUG, " ITS Configure: its_init failed\n", 0); + val_print(DEBUG, " ITS Configure: its_init failed\n"); goto its_fail; } } else { - val_print(ACS_PRINT_DEBUG, " ITS Configure: LPI unsupported\n", 0); + val_print(DEBUG, " ITS Configure: LPI unsupported\n"); goto its_fail; } @@ -281,8 +279,8 @@ uint32_t val_gic_its_configure() its_fail: - val_print(ACS_PRINT_DEBUG, " ITS Init failed: ", 0); - val_print(ACS_PRINT_DEBUG, "LPI Interrupt related test may not pass\n", 0); + val_print(DEBUG, " ITS Init failed: "); + val_print(DEBUG, "LPI Interrupt related test may not pass\n"); val_memory_free_aligned((void *)g_gic_its_info); return ACS_STATUS_ERR; @@ -478,13 +476,13 @@ void val_gic_free_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id, its_index = get_its_index(its_id); if (its_index >= g_gic_its_info->GicNumIts) { - val_print(ACS_PRINT_ERR, "\n Could not find ITS ID [%x]", its_id); + val_print(ERROR, "\n Could not find ITS ID [%x]", its_id); return; } if ((g_gic_its_info->GicRdBase == 0) || (g_gic_its_info->GicDBase == 0)) { - val_print(ACS_PRINT_ERR, "\n GICD/GICRD Base Invalid value", 0); + val_print(ERROR, "\n GICD/GICRD Base Invalid value"); return; } @@ -522,13 +520,13 @@ uint32_t val_gic_request_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id, its_index = get_its_index(its_id); if (its_index >= g_gic_its_info->GicNumIts) { - val_print(ACS_PRINT_ERR, "\n Could not find ITS ID [%x]", its_id); + val_print(ERROR, "\n Could not find ITS ID [%x]", its_id); return ACS_STATUS_ERR; } if ((g_gic_its_info->GicRdBase == 0) || (g_gic_its_info->GicDBase == 0)) { - val_print(ACS_PRINT_DEBUG, "\n GICD/GICRD Base Invalid value", 0); + val_print(DEBUG, "\n GICD/GICRD Base Invalid value"); return ACS_STATUS_ERR; } @@ -570,7 +568,7 @@ uint32_t val_gic_its_get_base(uint32_t its_id, uint64_t *its_base) its_index = get_its_index(its_id); if (its_index >= g_gic_its_info->GicNumIts) { - val_print(ACS_PRINT_ERR, "\n Could not find ITS ID [%x]", its_id); + val_print(ERROR, "\n Could not find ITS ID [%x]", its_id); return ACS_STATUS_ERR; } diff --git a/val/src/acs_gic_v2m.c b/val/src/acs_gic_v2m.c index dd35cb8c..b9dc2cca 100644 --- a/val/src/acs_gic_v2m.c +++ b/val/src/acs_gic_v2m.c @@ -39,14 +39,14 @@ uint32_t val_gic_v2m_parse_info(void) uint32_t i; if (g_gic_info_table == NULL) { - val_print(ACS_PRINT_DEBUG, "GIC INFO table not available\n", 0); + val_print(DEBUG, "GIC INFO table not available\n"); return ACS_STATUS_SKIP; } /* Allocate memory to store MSI Frame info */ g_v2m_msi_info = (GICv2m_MSI_FRAME_INFO *) val_aligned_alloc(MEM_ALIGN_4K, 1024); if (!g_v2m_msi_info) { - val_print(ACS_PRINT_DEBUG, "\n GICv2m : MSI Frame Info Failed.", 0); + val_print(DEBUG, "\n GICv2m : MSI Frame Info Failed."); return ACS_STATUS_SKIP; } @@ -84,7 +84,7 @@ uint64_t val_gic_v2m_get_info(V2M_MSI_INFO_e type, uint32_t instance) uint32_t spi_base, spi_count; if (g_v2m_msi_info == NULL) { - val_print(ACS_PRINT_ERR, "\n Get GICv2m info called before table is filled ", 0); + val_print(ERROR, "\n Get GICv2m info called before table is filled "); return 0; } @@ -118,7 +118,7 @@ uint64_t val_gic_v2m_get_info(V2M_MSI_INFO_e type, uint32_t instance) return g_v2m_msi_info->msi_info[instance].flags; default: - val_print(ACS_PRINT_ERR, "\n V2M_MSI_INFO - TYPE not recognized %d ", type); + val_print(ERROR, "\n V2M_MSI_INFO - TYPE not recognized %d ", type); break; } return ACS_STATUS_ERR; diff --git a/val/src/acs_interface.c b/val/src/acs_interface.c index a4431424..c7153cb2 100644 --- a/val/src/acs_interface.c +++ b/val/src/acs_interface.c @@ -257,10 +257,10 @@ int64_t val_drtm_lock_tcb_hashes(void) uint32_t val_drtm_reserved_bits_check_is_zero(uint32_t reserved_bits) { if (reserved_bits != VAL_DRTM_RESERVED_BYTE_ZERO) { - val_print(ACS_PRINT_ERR, "\n CHECK RSVD BITS: FAILED [0x%08x]", reserved_bits); + val_print(ERROR, "\n CHECK RSVD BITS: FAILED [0x%08x]", reserved_bits); return ACS_STATUS_FAIL; } else - val_print(ACS_PRINT_DEBUG, "\n CHECK RSVD BITS: PASSED", 0); + val_print(DEBUG, "\n CHECK RSVD BITS: PASSED"); return ACS_STATUS_PASS; } @@ -275,7 +275,7 @@ uint32_t val_drtm_get_psci_ver(void) pal_pe_call_smc(&smc_args, CONDUIT_SMC); - val_print(ACS_PRINT_DEBUG, "\n PSCI VERSION = %X", smc_args.Arg0); + val_print(DEBUG, "\n PSCI VERSION = %X", smc_args.Arg0); return smc_args.Arg0; } @@ -291,7 +291,7 @@ uint32_t val_drtm_get_smccc_ver(void) pal_pe_call_smc(&smc_args, CONDUIT_SMC); - val_print(ACS_PRINT_DEBUG, "\n SMCCC VERSION = %X", smc_args.Arg0); + val_print(DEBUG, "\n SMCCC VERSION = %X", smc_args.Arg0); return smc_args.Arg0; } @@ -306,7 +306,7 @@ uint32_t create_mem_prot_table(uint64_t *mem_prot_table_address, uint64_t *mem_p /* Check max number of regions */ max_mem_regions = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 8, 23); if (max_mem_regions < 1) { - val_print(ACS_PRINT_ERR, "\n Maximum Region is 0 for Memory Descriptor Table", 0); + val_print(ERROR, "\n Maximum Region is 0 for Memory Descriptor Table"); return ACS_STATUS_FAIL; } @@ -317,7 +317,7 @@ uint32_t create_mem_prot_table(uint64_t *mem_prot_table_address, uint64_t *mem_p mem_desc_table = (DRTM_MEMORY_REGION_DESCRIPTOR_TABLE *) ((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, mem_desc_table_size)); if (!mem_desc_table) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for Memory Descriptor Table", 0); + val_print(ERROR, "\n Failed to allocate memory for Memory Descriptor Table"); return ACS_STATUS_FAIL; } @@ -358,7 +358,7 @@ int64_t val_drtm_init_drtm_params(DRTM_PARAMETERS *drtm_params) uint64_t mem_prot_table_size = 0; if (!drtm_params) { - val_print(ACS_PRINT_ERR, "\n Invalid DRTM Params pointer", 0); + val_print(ERROR, "\n Invalid DRTM Params pointer"); return ACS_STATUS_FAIL; } @@ -371,7 +371,7 @@ int64_t val_drtm_init_drtm_params(DRTM_PARAMETERS *drtm_params) /* Get Memory Protection Type */ if (g_drtm_features.dma_prot_features.status > DRTM_ACS_SUCCESS) { mem_prot_type = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7); - val_print(ACS_PRINT_DEBUG, "\n Protection Type from Features : %x", mem_prot_type); + val_print(DEBUG, "\n Protection Type from Features : %x", mem_prot_type); if (mem_prot_type == DRTM_DMA_FEATURES_DMA_PROTECTION_ALL) launch_feat_mem_prot = DRTM_LAUNCH_FEAT_MEM_PROT_ALL_SUPP << @@ -380,7 +380,7 @@ int64_t val_drtm_init_drtm_params(DRTM_PARAMETERS *drtm_params) launch_feat_mem_prot = DRTM_LAUNCH_FEAT_MEM_PROT_REGION_SUPP << DRTM_LAUNCH_FEATURES_SHIFT_MEM_PROTECTION; - val_print(ACS_PRINT_DEBUG, "\n Setting DRTM Params Protection Type : %x", + val_print(DEBUG, "\n Setting DRTM Params Protection Type : %x", launch_feat_mem_prot); } @@ -399,14 +399,14 @@ int64_t val_drtm_init_drtm_params(DRTM_PARAMETERS *drtm_params) dlme_base_addr = (uint64_t)val_aligned_alloc(DRTM_SIZE_4K, dlme_region_size); if (!dlme_base_addr) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for DLME region", 0); + val_print(ERROR, "\n Failed to allocate memory for DLME region"); return ACS_STATUS_FAIL; } status = val_memory_set_wb_executable((void *)(dlme_base_addr + free_space_1_size), dlme_image_size); if (status) { - val_print(ACS_PRINT_ERR, "\n Failed to Set executable memory for DLME Image", 0); + val_print(ERROR, "\n Failed to Set executable memory for DLME Image"); return ACS_STATUS_FAIL; } @@ -416,7 +416,7 @@ int64_t val_drtm_init_drtm_params(DRTM_PARAMETERS *drtm_params) if (mem_prot_type == DRTM_DMA_FEATURES_DMA_PROTECTION_REGION) { status = create_mem_prot_table(&mem_prot_table_address, &mem_prot_table_size); if (status) { - val_print(ACS_PRINT_ERR, "\n Could Not Fill Memory Region Descriptor Table", 0); + val_print(ERROR, "\n Could Not Fill Memory Region Descriptor Table"); return ACS_STATUS_FAIL; } } @@ -485,16 +485,16 @@ int64_t val_drtm_check_dl_result(uint64_t dlme_base_addr, uint64_t dlme_data_off /* in the dlme x1 should have dlme_data_offset */ /* If both condition are met then PASS */ if (g_drtm_acs_dl_result->x0 != dlme_base_addr) { - val_print(ACS_PRINT_ERR, "\n Invalid x0 after dynamic launch", 0); - val_print(ACS_PRINT_ERR, "\n Expected 0x%lx,", dlme_base_addr); - val_print(ACS_PRINT_ERR, " got 0x%lx", g_drtm_acs_dl_result->x0); + val_print(ERROR, "\n Invalid x0 after dynamic launch"); + val_print(ERROR, "\n Expected 0x%lx,", dlme_base_addr); + val_print(ERROR, " got 0x%lx", g_drtm_acs_dl_result->x0); status = ACS_STATUS_FAIL; } if (g_drtm_acs_dl_result->x1 != dlme_data_offset) { - val_print(ACS_PRINT_ERR, "\n Invalid x1 after dynamic launch", 0); - val_print(ACS_PRINT_ERR, "\n Expected 0x%lx,", dlme_data_offset); - val_print(ACS_PRINT_ERR, " got 0x%lx", g_drtm_acs_dl_result->x1); + val_print(ERROR, "\n Invalid x1 after dynamic launch"); + val_print(ERROR, "\n Expected 0x%lx,", dlme_data_offset); + val_print(ERROR, " got 0x%lx", g_drtm_acs_dl_result->x1); status = ACS_STATUS_FAIL; } return status; diff --git a/val/src/acs_iovirt.c b/val/src/acs_iovirt.c index f4cf366c..b7ba3d6e 100644 --- a/val/src/acs_iovirt.c +++ b/val/src/acs_iovirt.c @@ -41,7 +41,7 @@ val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index) if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_SMMU_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_SMMU_INFO: iovirt info table is not created\n"); return 0; } @@ -66,7 +66,7 @@ val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index) case SMMU_IOVIRT_BLOCK: return (uint64_t)block; default: - val_print(ACS_PRINT_ERR, "This SMMU info option not supported %d\n", type); + val_print(ERROR, "This SMMU info option not supported %d\n", type); return 0; } } @@ -76,7 +76,7 @@ val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index) if (index > j-1) { - val_print(ACS_PRINT_ERR, "GET_SMMU_INFO: Index (%d) is greater than num of SMMU\n", index); + val_print(ERROR, "GET_SMMU_INFO: Index (%d) is greater than num of SMMU\n", index); return 0; } return j; @@ -99,7 +99,7 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_PCIe_RC_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_PCIe_RC_INFO: iovirt info table is not created\n"); return 0; } @@ -128,7 +128,7 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) case RC_SMMU_BASE: return block->data.rc.smmu_base; default: - val_print(ACS_PRINT_ERR, "This PCIe RC info option not supported %d\n", type); + val_print(ERROR, "This PCIe RC info option not supported %d\n", type); return 0; } } @@ -137,7 +137,7 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) } if (index > j-1) { - val_print(ACS_PRINT_ERR, "GET_PCIe_RC_INFO: Index (%d) is greater than num of PCIe-RC\n", + val_print(ERROR, "GET_PCIe_RC_INFO: Index (%d) is greater than num of PCIe-RC\n", index); return 0; } @@ -167,11 +167,11 @@ val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, NODE_DATA_MAP *map; if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: iovirt info table is not created", 0); + val_print(ERROR, "\n GET_DEVICE_ID: iovirt info table is not created"); return ACS_STATUS_ERR; } if (!device_id) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid parameters", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid parameters"); return ACS_STATUS_ERR; } @@ -198,8 +198,8 @@ val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, } } if (!mapping_found) { - val_print(ACS_PRINT_ERR, - "\n RID to Stream/Dev ID map not found ", 0); + val_print(ERROR, + "\n RID to Stream/Dev ID map not found "); return ACS_STATUS_ERR; } /* If output reference node is to ITS group, 'id' is device id */ @@ -235,13 +235,13 @@ val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, } else { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid mapping for RC in IORT", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid mapping for RC in IORT"); return ACS_STATUS_ERR; } if (!mapping_found) { - val_print(ACS_PRINT_ERR, - "\n GET_DEVICE_ID: Stream ID to Device ID mapping not found", 0); + val_print(ERROR, + "\n GET_DEVICE_ID: Stream ID to Device ID mapping not found"); return ACS_STATUS_ERR; } @@ -270,40 +270,40 @@ val_iovirt_create_info_table(uint64_t *iovirt_info_table) if (iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "\n Input for Create Info table cannot be NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating SMMU INFO table\n", 0); + val_print(TRACE, " Creating SMMU INFO table\n"); g_iovirt_info_table = (IOVIRT_INFO_TABLE *)iovirt_info_table; pal_iovirt_create_info_table(g_iovirt_info_table); g_num_smmus = (uint32_t)val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); - val_print(ACS_PRINT_TEST, + val_print(INFO, " SMMU_INFO: Number of SMMU CTRL : %d\n", g_num_smmus); for (i = 0; i < g_num_smmus; i++) { smmu_base = val_smmu_get_info(SMMU_CTRL_BASE, i); - val_print(ACS_PRINT_DEBUG, "\n SMMU index %x, ", i); - val_print(ACS_PRINT_DEBUG, "Base : 0x%llx", smmu_base); + val_print(DEBUG, "\n SMMU index %x, ", i); + val_print(DEBUG, "Base : 0x%llx", smmu_base); #ifndef TARGET_LINUX - val_print(ACS_PRINT_DEBUG, "\n Check for SMMU index %x entry in memmap", i); + val_print(DEBUG, "\n Check for SMMU index %x entry in memmap", i); if (val_mmu_update_entry(smmu_base, SMMU_MAP_SIZE, DEVICE_nGnRnE)) - val_print(ACS_PRINT_WARN, "\n Adding SMMU index %x entry failed", i); + val_print(WARN, "\n Adding SMMU index %x entry failed", i); #endif smmu_ver = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, i); - val_print(ACS_PRINT_TEST, + val_print(INFO, " SMMU_INFO: SMMU index %.2d ", i); - val_print(ACS_PRINT_TEST, "version : v%d", smmu_ver); + val_print(INFO, "version : v%d", smmu_ver); if (smmu_ver == 3) { smmu_minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, i), 0, 3); - val_print(ACS_PRINT_TEST, ".%d", smmu_minor); + val_print(INFO, ".%d", smmu_minor); } - val_print(ACS_PRINT_TEST, "\n", smmu_ver); + val_print(INFO, "\n", smmu_ver); } } @@ -322,8 +322,8 @@ val_iovirt_free_info_table(void) g_iovirt_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_iovirt_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_iovirt_info_table pointer is already NULL"); } } @@ -351,7 +351,7 @@ val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid) } } - val_print(ACS_PRINT_INFO, "\n RC with segment number %d is not behind SMMU", rc_seg_num); + val_print(TRACE, "\n RC with segment number %d is not behind SMMU", rc_seg_num); return ACS_INVALID_INDEX; } @@ -409,7 +409,7 @@ val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index) if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_NAMED_COMP_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_NAMED_COMP_INFO: iovirt info table is not created\n"); return 0; /* imply no named components parsed */ } @@ -418,7 +418,7 @@ val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index) /* check if index in range */ if (index > g_iovirt_info_table->num_named_components - 1) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "GET_NAMED_COMP_INFO: Index (%d) is greater than num of Named components\n", index); return INVALID_NAMED_COMP_INFO; @@ -444,7 +444,7 @@ val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index) case NAMED_COMP_SMMU_BASE: return block->data.named_comp.smmu_base; default: - val_print(ACS_PRINT_ERR, + val_print(ERROR, "This Named component info option not supported %d\n", type); return INVALID_NAMED_COMP_INFO; } @@ -479,18 +479,18 @@ val_iovirt_get_named_comp_device_info(const char *dev_name, uint32_t identifier, NODE_DATA_MAP *map; if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: iovirt info table is not created", 0); + val_print(ERROR, "\n GET_DEVICE_ID: iovirt info table is not created"); return ACS_STATUS_ERR; } if ((device_id == NULL) || (dev_name == NULL)) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid parameters", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid parameters"); return ACS_STATUS_ERR; } while ((dev_len < MAX_NAMED_COMP_LENGTH) && (dev_name[dev_len] != '\0')) dev_len++; if (dev_len == 0u) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid device name", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid device name"); return ACS_STATUS_ERR; } @@ -516,7 +516,7 @@ val_iovirt_get_named_comp_device_info(const char *dev_name, uint32_t identifier, } if (!mapping_found) { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Named component mapping not found", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Named component mapping not found"); return ACS_STATUS_ERR; } @@ -537,7 +537,7 @@ val_iovirt_get_named_comp_device_info(const char *dev_name, uint32_t identifier, } } if (!mapping_found) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n GET_DEVICE_ID: Stream ID to Device ID mapping not found", 0); return ACS_STATUS_ERR; } @@ -545,11 +545,11 @@ val_iovirt_get_named_comp_device_info(const char *dev_name, uint32_t identifier, if (block->type == IOVIRT_NODE_ITS_GROUP) { itsid = block->data_map[0].id[0]; } else { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid mapping for Named component", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid mapping for Named component"); return ACS_STATUS_ERR; } } else { - val_print(ACS_PRINT_ERR, "\n GET_DEVICE_ID: Invalid mapping for Named component", 0); + val_print(ERROR, "\n GET_DEVICE_ID: Invalid mapping for Named component"); return ACS_STATUS_ERR; } @@ -576,7 +576,7 @@ val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index) if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_PMCG_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_PMCG_INFO: iovirt info table is not created\n"); return 0; } @@ -603,7 +603,7 @@ val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index) case PMCG_NODE_SMMU_BASE: return block->data.pmcg.smmu_base; default: - val_print(ACS_PRINT_ERR, "This PMCG info option not supported %d\n", type); + val_print(ERROR, "This PMCG info option not supported %d\n", type); return 0; } } @@ -613,7 +613,7 @@ val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index) if (index > j-1) { - val_print(ACS_PRINT_ERR, "GET_PMCG_INFO: Index (%d) is greater than num of PMCG\n", index); + val_print(ERROR, "GET_PMCG_INFO: Index (%d) is greater than num of PMCG\n", index); return 0; } return j; @@ -627,7 +627,7 @@ val_iovirt_get_rc_index(uint32_t rc_seg_num) if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_PCIe_RC_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_PCIe_RC_INFO: iovirt info table is not created\n"); return 0; } @@ -646,7 +646,7 @@ val_iovirt_get_rc_index(uint32_t rc_seg_num) } if (i >= g_iovirt_info_table->num_blocks) { - val_print(ACS_PRINT_ERR, "GET_PCIe_RC_INFO: segemnt (%d) is not valid\n", rc_seg_num); + val_print(ERROR, "GET_PCIe_RC_INFO: segemnt (%d) is not valid\n", rc_seg_num); return ACS_INVALID_INDEX; } return j; @@ -674,11 +674,11 @@ val_iovirt_get_its_info( if (g_iovirt_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_ITS_INFO: iovirt info table is not created\n", 0); + val_print(ERROR, "GET_ITS_INFO: iovirt info table is not created\n"); return ACS_STATUS_ERR; } if (!return_value) { - val_print(ACS_PRINT_ERR, "GET_ITS_INFO: Return pointer is NULL\n", 0); + val_print(ERROR, "GET_ITS_INFO: Return pointer is NULL\n"); return ACS_STATUS_ERR; } @@ -732,7 +732,7 @@ val_iovirt_get_its_info( /* ITS_ID not found in current group, return error */ return ACS_INVALID_INDEX; default: - val_print(ACS_PRINT_ERR, "This ITS info option not supported %d\n", type); + val_print(ERROR, "This ITS info option not supported %d\n", type); return ACS_STATUS_ERR; } break; @@ -741,7 +741,7 @@ val_iovirt_get_its_info( } } - val_print(ACS_PRINT_ERR, "GET_ITS_INFO: ITS Group not found %d\n", group_index); + val_print(ERROR, "GET_ITS_INFO: ITS Group not found %d\n", group_index); return ACS_INVALID_INDEX; } diff --git a/val/src/acs_memory.c b/val/src/acs_memory.c index a2226628..f1b61192 100644 --- a/val/src/acs_memory.c +++ b/val/src/acs_memory.c @@ -82,9 +82,8 @@ val_memory_free_info_table(void) g_memory_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_memory_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_memory_info_table pointer is already NULL"); } } @@ -103,7 +102,7 @@ val_memory_create_info_table(uint64_t *memory_info_table) { g_memory_info_table = (MEMORY_INFO_TABLE *)memory_info_table; - val_print(ACS_PRINT_INFO, " Creating MEMORY INFO table\n", 0); + val_print(TRACE, " Creating MEMORY INFO table\n"); pal_memory_create_info_table(g_memory_info_table); @@ -161,7 +160,7 @@ val_memory_get_info(addr_t addr, uint64_t *attr) return g_memory_info_table->info[index].type; } index++; - // val_print(ACS_PRINT_INFO," .", 0); + // val_print(TRACE," ."); } return MEM_TYPE_NOT_POPULATED; @@ -192,13 +191,13 @@ val_memory_ioremap(void *addr, uint32_t size, uint32_t attr, void **baseptr) status = val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr); if (status) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation attributes via TCR", 0); + val_print(ERROR, "\n Unable to get translation attributes via TCR"); return status; } status = val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr); if (status) { - val_print(ACS_PRINT_ERR, "\n Unable to get translation table via TBBR", 0); + val_print(ERROR, "\n Unable to get translation table via TBBR"); return status; } @@ -459,7 +458,7 @@ uint32_t val_memory_region_has_52bit_addr(void) uint32_t index = 0; while (g_memory_info_table->info[index].type != MEMORY_TYPE_LAST_ENTRY) { - val_print(ACS_PRINT_INFO, " \n Mem Phy Addr %lx", + val_print(TRACE, " \n Mem Phy Addr %lx", g_memory_info_table->info[index].phy_addr); if (CHECK_ADDR_52BIT(g_memory_info_table->info[index].phy_addr)) return 1; @@ -504,8 +503,8 @@ val_memory_get_addr(MEMORY_INFO_e mem_type, uint32_t instance, uint64_t *attr) return g_memory_info_table->info[i].phy_addr; } - val_print(ACS_PRINT_INFO, "\n Instance 0x%x not found ", instance); - val_print(ACS_PRINT_INFO, "for memory type 0x%x", mem_type); + val_print(TRACE, "\n Instance 0x%x not found ", instance); + val_print(TRACE, "for memory type 0x%x", mem_type); return 0; } diff --git a/val/src/acs_mmu.c b/val/src/acs_mmu.c index a6948d8b..ae513919 100644 --- a/val/src/acs_mmu.c +++ b/val/src/acs_mmu.c @@ -45,12 +45,12 @@ val_mmu_check_for_entry(uint64_t addr) /* Get translation attributes from TCR and translation table base from TTBR TTBR0 is used since we are accessing lower address region */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &tcr)) { - val_print(ACS_PRINT_ERR, "\n Failed to fetch TCR", 0); + val_print(ERROR, "\n Failed to fetch TCR"); return 1; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n Failed to fetch TTBR0", 0); + val_print(ERROR, "\n Failed to fetch TTBR0"); return 1; } @@ -80,25 +80,25 @@ val_mmu_check_for_entry(uint64_t addr) /* index the translation table and read the entry */ ttable_entry = tt_base_virt[index]; - val_print(ACS_PRINT_INFO, "\n Translation table level = %d", this_level); - val_print(ACS_PRINT_INFO, "\n Table base address = 0x%llx", + val_print(TRACE, "\n Translation table level = %d", this_level); + val_print(TRACE, "\n Table base address = 0x%llx", (uint64_t)tt_base_virt); - val_print(ACS_PRINT_INFO, "\n Table entry index = %d", index); - val_print(ACS_PRINT_INFO, "\n Table entry = 0x%llx", + val_print(TRACE, "\n Table entry index = %d", index); + val_print(TRACE, "\n Table entry = 0x%llx", ttable_entry); - val_print(ACS_PRINT_INFO, "\n VA bits remaining to be resolve = %d", bits_remaining); + val_print(TRACE, "\n VA bits remaining to be resolve = %d", bits_remaining); /* check whether the table entry is invalid */ if (IS_PGT_ENTRY_INVALID(ttable_entry)) { - val_print(ACS_PRINT_DEBUG, "\n VA not mapped in translation table", 0); + val_print(DEBUG, "\n VA not mapped in translation table"); return 1; } /* As per Arm ARM, entry of type "table descriptor" is only valid at translation level 0 */ if (this_level == 0 && !IS_PGT_ENTRY_TABLE(ttable_entry)) { - val_print(ACS_PRINT_DEBUG, - "\n VA not mapped correctly in translation table", 0); + val_print(DEBUG, + "\n VA not mapped correctly in translation table"); return 1; } @@ -106,12 +106,12 @@ val_mmu_check_for_entry(uint64_t addr) /* at level 3 table entry should be of type "page descriptor" with ttable_entry[1:0] bits = b11 */ if (!IS_PGT_ENTRY_PAGE(ttable_entry)) { - val_print(ACS_PRINT_DEBUG, - "\n VA not mapped correctly in translation table", 0); + val_print(DEBUG, + "\n VA not mapped correctly in translation table"); return 1; } else { - val_print(ACS_PRINT_DEBUG, "\n VA translation successful", 0); + val_print(DEBUG, "\n VA translation successful"); return 0; } } @@ -121,7 +121,7 @@ val_mmu_check_for_entry(uint64_t addr) level 3 can only have entry of type page descriptor (Refer Arm ARM for more info) */ if (IS_PGT_ENTRY_BLOCK(ttable_entry) && this_level != 0) { - val_print(ACS_PRINT_DEBUG, "\n VA translation successful", 0); + val_print(DEBUG, "\n VA translation successful"); return 0; } @@ -165,11 +165,11 @@ val_mmu_add_entry(uint64_t base_addr, uint64_t size, uint64_t attr) /* Get translation attributes from TCR and translation table base from TTBR */ if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { - val_print(ACS_PRINT_ERR, "\n Failed to fetch TCR", 0); + val_print(ERROR, "\n Failed to fetch TCR"); return 1; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { - val_print(ACS_PRINT_ERR, "\n Failed to fetch TTBR0", 0); + val_print(ERROR, "\n Failed to fetch TTBR0"); return 1; } @@ -181,8 +181,8 @@ val_mmu_add_entry(uint64_t base_addr, uint64_t size, uint64_t attr) /* realise OAS and IAS from TCR register */ pgt_desc.oas = oas_bit_arr[pgt_desc.tcr.ps]; pgt_desc.ias = 64 - pgt_desc.tcr.tsz; - val_print(ACS_PRINT_DEBUG, "\n Input addr size in bits (ias) = %d", pgt_desc.ias); - val_print(ACS_PRINT_DEBUG, "\n Output addr size in bits (oas) = %d\n", pgt_desc.oas); + val_print(DEBUG, "\n Input addr size in bits (ias) = %d", pgt_desc.ias); + val_print(DEBUG, "\n Output addr size in bits (oas) = %d\n", pgt_desc.oas); /* populate mem descriptor structure with addr region to be mapped and attributes */ mem_desc.virtual_address = base_addr; @@ -197,7 +197,7 @@ val_mmu_add_entry(uint64_t base_addr, uint64_t size, uint64_t attr) /* update translation table entry(s) for addr region defined by memory descriptor structure */ if (val_pgt_create(&mem_desc, &pgt_desc)) { - val_print(ACS_PRINT_ERR, " Failed to create MMU translation entry(s)\n", 0); + val_print(ERROR, " Failed to create MMU translation entry(s)\n"); return 1; } return 0; @@ -217,7 +217,7 @@ uint32_t val_mmu_update_entry(uint64_t address, uint32_t size, uint64_t attr) /* If entry is already present return success */ if (!val_mmu_check_for_entry(address)) { - val_print(ACS_PRINT_DEBUG, "\n Address is already mapped\n", 0); + val_print(DEBUG, "\n Address is already mapped\n"); return 0; } @@ -290,7 +290,7 @@ void val_setup_mair_register(void) continue; if (free_cnt == 0) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n MAIR register full, could not add attribute 0x%02x", new_attr); break; } @@ -304,8 +304,8 @@ void val_setup_mair_register(void) if (mair_val != current_mair) val_mair_write(mair_val, currentEL); - val_print(ACS_PRINT_DEBUG, "\n Previous MAIR register value 0x%lx", current_mair); - val_print(ACS_PRINT_DEBUG, "\n Current MAIR register value 0x%lx\n", mair_val); + val_print(DEBUG, "\n Previous MAIR register value 0x%lx", current_mair); + val_print(DEBUG, "\n Current MAIR register value 0x%lx\n", mair_val); return; } @@ -332,8 +332,8 @@ uint32_t val_setup_mmu(void) pgt_desc.pgt_base = (uint64_t) tt_l0_base; pgt_desc.stage = PGT_STAGE1; - val_print(ACS_PRINT_DEBUG, " mmu: ias=%d\n", pgt_desc.ias); - val_print(ACS_PRINT_DEBUG, " mmu: oas=%d\n", pgt_desc.oas); + val_print(DEBUG, " mmu: ias=%d\n", pgt_desc.ias); + val_print(DEBUG, " mmu: oas=%d\n", pgt_desc.oas); /* Map regions */ @@ -349,9 +349,9 @@ uint32_t val_setup_mmu(void) mem_desc->length = mmap_region_list[i].length; mem_desc->attributes = mmap_region_list[i].attributes; - val_print(ACS_PRINT_DEBUG, "\n Creating page table for region : 0x%lx", + val_print(DEBUG, "\n Creating page table for region : 0x%lx", mem_desc->virtual_address); - val_print(ACS_PRINT_DEBUG, "- 0x%lx\n", (mem_desc->virtual_address + mem_desc->length) - 1); + val_print(DEBUG, "- 0x%lx\n", (mem_desc->virtual_address + mem_desc->length) - 1); if (val_pgt_create(mem_desc, &pgt_desc)) { @@ -391,8 +391,8 @@ uint32_t val_enable_mmu(void) val_tcr_write(tcr, currentEL); - val_print(ACS_PRINT_DEBUG, " val_setup_mmu: TG0=0x%x\n", TCR_TG0); - val_print(ACS_PRINT_DEBUG, " val_setup_mmu: tcr=0x%lx\n", tcr); + val_print(DEBUG, " val_setup_mmu: TG0=0x%x\n", TCR_TG0); + val_print(DEBUG, " val_setup_mmu: tcr=0x%lx\n", tcr); /* Enable MMU */ val_sctlr_write((1 << 0) | // M=1 Enable the stage 1 MMU @@ -401,8 +401,8 @@ uint32_t val_enable_mmu(void) val_sctlr_read(currentEL), currentEL); - val_print(ACS_PRINT_DEBUG, " val_enable_mmu: successful\n", 0); - val_print(ACS_PRINT_DEBUG, " System Control EL2 is %llx", val_sctlr_read(currentEL)); + val_print(DEBUG, " val_enable_mmu: successful\n"); + val_print(DEBUG, " System Control EL2 is %llx", val_sctlr_read(currentEL)); return ACS_STATUS_PASS; } diff --git a/val/src/acs_mpam.c b/val/src/acs_mpam.c index 3385ef3a..18dad63f 100644 --- a/val/src/acs_mpam.c +++ b/val/src/acs_mpam.c @@ -94,13 +94,13 @@ mpam_reg_offset_name(uint32_t reg_offset) #define MPAM_PRINT_REG(op, reg_offset, value) \ do { \ char8_t *name__ = mpam_reg_offset_name(reg_offset); \ - val_print(ACS_PRINT_DEBUG, "\n MPAM_" op " ", 0); \ + val_print(DEBUG, "\n MPAM_" op " "); \ if (name__ != NULL) { \ - val_print(ACS_PRINT_DEBUG, name__, 0); \ + val_print(DEBUG, name__); \ } else { \ - val_print(ACS_PRINT_DEBUG, "0x%x", reg_offset); \ + val_print(DEBUG, "0x%x", reg_offset); \ } \ - val_print(ACS_PRINT_DEBUG, " : 0x%llx", \ + val_print(DEBUG, " : 0x%llx", \ (unsigned long long)(value)); \ } while (0) @@ -172,12 +172,12 @@ val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) MPAM_MSC_NODE *msc_entry; if (g_mpam_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n MPAM info table not found", 0); + val_print(WARN, "\n MPAM info table not found"); return MPAM_INVALID_INFO; } if (msc_index >= g_mpam_info_table->msc_count) { - val_print(ACS_PRINT_ERR, "Invalid MSC index = 0x%lx ", msc_index); + val_print(ERROR, "Invalid MSC index = 0x%lx ", msc_index); return 0; } @@ -186,9 +186,9 @@ val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) for (i = 0; i < g_mpam_info_table->msc_count; i++, msc_entry = MPAM_NEXT_MSC(msc_entry)) { if (msc_index == i) { if (rsrc_index > msc_entry->rsrc_count - 1) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid MSC resource index = 0x%lx for", rsrc_index); - val_print(ACS_PRINT_ERR, "MSC index = 0x%lx ", msc_index); + val_print(ERROR, "MSC index = 0x%lx ", msc_index); return MPAM_INVALID_INFO; } switch (type) { @@ -221,7 +221,7 @@ val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) case MPAM_MSC_INTERFACE_TYPE: return msc_entry->intrf_type; default: - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n This MPAM info option for type %d is not supported", type); return MPAM_INVALID_INFO; } @@ -245,7 +245,7 @@ val_srat_get_info(SRAT_INFO_e type, uint64_t data) uint32_t i = 0; if (g_srat_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n SRAT info table not found", 0); + val_print(WARN, "\n SRAT info table not found"); return SRAT_INVALID_INFO; } @@ -300,7 +300,7 @@ val_srat_get_info(SRAT_INFO_e type, uint64_t data) return SRAT_INVALID_INFO; break; default: - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n This SRAT info option for type %d is not supported", type); break; } @@ -319,12 +319,12 @@ val_srat_get_prox_domain(uint64_t mem_range_index) uint32_t i = 0; if (g_srat_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n SRAT info table not found", 0); + val_print(WARN, "\n SRAT info table not found"); return SRAT_INVALID_INFO; } if (mem_range_index >= g_srat_info_table->num_of_mem_ranges) { - val_print(ACS_PRINT_WARN, "\n Invalid index", 0); + val_print(WARN, "\n Invalid index"); return SRAT_INVALID_INFO; } @@ -349,7 +349,7 @@ uint32_t val_mpam_get_msc_count(void) { if (g_mpam_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n MPAM info table not found", 0); + val_print(WARN, "\n MPAM info table not found"); return 0; } else @@ -664,7 +664,7 @@ val_mpam_msc_get_mscbw(uint32_t msc_index, uint32_t rsrc_index) prox_domain = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); if (g_hmat_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n HMAT info table not found", 0); + val_print(WARN, "\n HMAT info table not found"); return HMAT_INVALID_INFO; } @@ -674,7 +674,7 @@ val_mpam_msc_get_mscbw(uint32_t msc_index, uint32_t rsrc_index) g_hmat_info_table->bw_info[i].read_bw); } } - val_print(ACS_PRINT_WARN, "\n Invalid Proximity domain 0x%lx", prox_domain); + val_print(WARN, "\n Invalid Proximity domain 0x%lx", prox_domain); return HMAT_INVALID_INFO; } @@ -1010,7 +1010,7 @@ void val_mpam_create_info_table(uint64_t *mpam_info_table) { if (mpam_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL\n", 0); + val_print(ERROR, "\n Pre-allocated memory pointer is NULL\n"); return; } @@ -1018,9 +1018,9 @@ val_mpam_create_info_table(uint64_t *mpam_info_table) #ifndef TARGET_LINUX pal_mpam_create_info_table(g_mpam_info_table); - val_print(ACS_PRINT_TEST, + val_print(INFO, " MPAM INFO: Number of MSC nodes : %d\n", g_mpam_info_table->msc_count); - val_print(ACS_PRINT_DEBUG, "Memory mapping MSC nodes\n", 0); + val_print(DEBUG, "Memory mapping MSC nodes\n"); /* TODO - Check if MSC memory mapping requires a flag/ cmdline option */ memory_map_msc(); @@ -1039,7 +1039,7 @@ val_mpam_update_msc_device_names(void) { #ifndef TARGET_LINUX if (g_mpam_info_table == NULL) { - val_print(ACS_PRINT_ERR, "MPAM info table is not created\n", 0); + val_print(ERROR, "MPAM info table is not created\n"); return; } pal_mpam_parse_dsdt_info(g_mpam_info_table); @@ -1059,7 +1059,7 @@ val_mpam_free_info_table(void) g_mpam_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n WARNING: g_mpam_info_table pointer is already NULL", 0); } @@ -1081,15 +1081,15 @@ val_mpam_get_msc_device_info(uint32_t msc_index, uint32_t *device_id, uint32_t * MPAM_MSC_NODE *msc_node; if (g_mpam_info_table == NULL) { - val_print(ACS_PRINT_ERR, "MPAM info table is not created\n", 0); + val_print(ERROR, "MPAM info table is not created\n"); return ACS_STATUS_ERR; } if (device_id == NULL) { - val_print(ACS_PRINT_ERR, "MPAM info invalid params\n", 0); + val_print(ERROR, "MPAM info invalid params\n"); return ACS_STATUS_ERR; } if (msc_index >= g_mpam_info_table->msc_count) { - val_print(ACS_PRINT_ERR, "MPAM info invalid MSC index %d\n", msc_index); + val_print(ERROR, "MPAM info invalid MSC index %d\n", msc_index); return ACS_STATUS_ERR; } @@ -1100,20 +1100,20 @@ val_mpam_get_msc_device_info(uint32_t msc_index, uint32_t *device_id, uint32_t * identifier = msc_node->identifier; device_name = msc_node->device_obj_name; if (device_name[0] == '\0') { - val_print(ACS_PRINT_ERR, "MPAM info missing device name for MSC %d\n", msc_index); + val_print(ERROR, "MPAM info missing device name for MSC %d\n", msc_index); return ACS_STATUS_ERR; } uint32_t status = val_iovirt_get_named_comp_device_info(device_name, identifier, device_id, its_id); if (status == 0) { - val_print(ACS_PRINT_INFO, " MPAM MSC Device info: idx=%d", msc_index); - val_print(ACS_PRINT_INFO, " id=0x%x", identifier); - val_print(ACS_PRINT_INFO, " dev=0x%x", *device_id); - val_print(ACS_PRINT_INFO, " its=0x%x\n", its_id ? *its_id : 0); + val_print(TRACE, " MPAM MSC Device info: idx=%d", msc_index); + val_print(TRACE, " id=0x%x", identifier); + val_print(TRACE, " dev=0x%x", *device_id); + val_print(TRACE, " its=0x%x\n", its_id ? *its_id : 0); } else { - val_print(ACS_PRINT_ERR, " MPAM MSC devinfo failed: idx=%d", msc_index); - val_print(ACS_PRINT_ERR, " id=0x%x\n", identifier); + val_print(ERROR, " MPAM MSC devinfo failed: idx=%d", msc_index); + val_print(ERROR, " id=0x%x\n", identifier); } return status; } @@ -1130,7 +1130,7 @@ void val_hmat_create_info_table(uint64_t *hmat_info_table) { if (hmat_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL\n", 0); + val_print(ERROR, "\n Pre-allocated memory pointer is NULL\n"); return; } #ifndef TARGET_LINUX @@ -1139,7 +1139,7 @@ val_hmat_create_info_table(uint64_t *hmat_info_table) pal_hmat_create_info_table(g_hmat_info_table); if (g_hmat_info_table->num_of_mem_prox_domain != 0) - val_print(ACS_PRINT_TEST, + val_print(INFO, " HMAT INFO: Number of Prox domains : %d\n", g_hmat_info_table->num_of_mem_prox_domain); #endif @@ -1168,7 +1168,7 @@ void val_srat_create_info_table(uint64_t *srat_info_table) { if (srat_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL\n", 0); + val_print(ERROR, "\n Pre-allocated memory pointer is NULL\n"); return; } #ifndef TARGET_LINUX @@ -1177,7 +1177,7 @@ val_srat_create_info_table(uint64_t *srat_info_table) pal_srat_create_info_table(g_srat_info_table); if (g_srat_info_table->num_of_mem_ranges != 0) - val_print(ACS_PRINT_TEST, + val_print(INFO, " SRAT INFO: Number of Memory Ranges : %d\n", g_srat_info_table->num_of_mem_ranges); #endif @@ -1413,7 +1413,7 @@ void val_mpam_configure_cmin(uint32_t msc_index, uint16_t partid, uint32_t cmin_ num_fractional_bits = val_mpam_get_cmax_wd(msc_index); if (num_fractional_bits > 16) { - val_print(ACS_PRINT_ERR, "\n Number of fractional bits = %d not permitted", + val_print(ERROR, "\n Number of fractional bits = %d not permitted", num_fractional_bits); num_fractional_bits = 16; } @@ -1711,7 +1711,7 @@ val_mpam_mmr_read(uint32_t msc_index, uint32_t reg_offset) MPAM_PRINT_REG("Read", reg_offset, value); return value; } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid interface type reported for MPAM MSC index = %x", msc_index); return 0; /* zero considered as safe return */ } @@ -1748,7 +1748,7 @@ val_mpam_mmr_read64(uint32_t msc_index, uint32_t reg_offset) MPAM_PRINT_REG("Read", reg_offset, value); return value; } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid interface type reported for MPAM MSC index = %x", msc_index); return 0; /* zero considered as safe return */ } @@ -1780,7 +1780,7 @@ val_mpam_mmr_write(uint32_t msc_index, uint32_t reg_offset, uint32_t data) val_mpam_pcc_write(msc_index, reg_offset, data); MPAM_PRINT_REG("Write", reg_offset, data); } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid interface type reported for MPAM MSC index = %x", msc_index); } val_mem_issue_dsb(); @@ -1813,7 +1813,7 @@ val_mpam_mmr_write64(uint32_t msc_index, uint32_t reg_offset, uint64_t data) val_mpam_pcc_write(msc_index, reg_offset + 4, (uint32_t)(data >> 32)); MPAM_PRINT_REG("Write", reg_offset, data); } else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Invalid interface type reported for MPAM MSC index = %x", msc_index); } val_mem_issue_dsb(); @@ -1857,11 +1857,11 @@ val_mpam_pcc_read(uint32_t msc_index, uint32_t reg_offset) (uint32_t)subspace_id, *(uint32_t *)&header, (void *)¶meter, sizeof(parameter)); if (response == NULL || response->status != MPAM_PCC_CMD_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to read MPAM register with offset (0x%x) via PCC", reg_offset); - val_print(ACS_PRINT_ERR, " for MSC index = 0x%x", msc_index); + val_print(ERROR, " for MSC index = 0x%x", msc_index); if (response != NULL) { - val_print(ACS_PRINT_ERR, "\n PCC command response code = 0x%x", response->status); + val_print(ERROR, "\n PCC command response code = 0x%x", response->status); } return MPAM_PCC_SAFE_RETURN; } else { @@ -1908,11 +1908,11 @@ val_mpam_pcc_write(uint32_t msc_index, uint32_t reg_offset, uint32_t data) (uint32_t)subspace_id, *(uint32_t *)&header, (void *)¶meter, sizeof(parameter)); if (response == NULL || response->status != MPAM_PCC_CMD_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to read MPAM register with offset (0x%x) via PCC", reg_offset); - val_print(ACS_PRINT_ERR, " for MSC index = 0x%x", msc_index); + val_print(ERROR, " for MSC index = 0x%x", msc_index); if (response != NULL) { - val_print(ACS_PRINT_ERR, "\n PCC command response code = 0x%x", response->status); + val_print(ERROR, "\n PCC command response code = 0x%x", response->status); } return; } @@ -1957,7 +1957,7 @@ uint32_t val_alloc_shared_memcpybuf(uint64_t mem_base, uint64_t buffer_size, uin buffer = (void *)val_memory_alloc(pe_count * sizeof(uint64_t)); if (!buffer) { - val_print(ACS_PRINT_ERR, "Allocate Pool for shared memcpy buf failed\n", 0); + val_print(ERROR, "Allocate Pool for shared memcpy buf failed\n"); return 0; } @@ -1969,7 +1969,7 @@ uint32_t val_alloc_shared_memcpybuf(uint64_t mem_base, uint64_t buffer_size, uin buffer_size); if (g_shared_memcpy_buffer[pe_index] == NULL) { - val_print(ACS_PRINT_ERR, "Alloc address for shared memcpy buffer failed %x\n", pe_index); + val_print(ERROR, "Alloc address for shared memcpy buffer failed %x\n", pe_index); val_mem_free_shared_memcpybuf(pe_index); return 0; } @@ -2012,16 +2012,16 @@ uint32_t val_mpam_program_el2(uint16_t partid, uint8_t pmg) pe_max_partid = (mpamidr >> MPAMIDR_PARTID_MAX_SHIFT) & MPAMIDR_PARTID_MAX_MASK; if (partid > pe_max_partid) { - val_print(ACS_PRINT_ERR, "\n PARTID value (0x%x)", partid); - val_print(ACS_PRINT_ERR, " specified more than PE supported value (0x%x)", pe_max_partid); + val_print(ERROR, "\n PARTID value (0x%x)", partid); + val_print(ERROR, " specified more than PE supported value (0x%x)", pe_max_partid); return 1; } /* Extract max PMG supported by MPAMIDR_EL1 */ pe_max_pmg = (mpamidr >> MPAMIDR_PMG_MAX_SHIFT) & MPAMIDR_PMG_MAX_MASK; if (pmg > pe_max_pmg) { - val_print(ACS_PRINT_ERR, "\n PMG value (0x%x)", pmg); - val_print(ACS_PRINT_ERR, " specified more than PE supported value (0x%x)", pe_max_pmg); + val_print(ERROR, "\n PMG value (0x%x)", pmg); + val_print(ERROR, " specified more than PE supported value (0x%x)", pe_max_pmg); return 1; } @@ -2035,7 +2035,7 @@ uint32_t val_mpam_program_el2(uint16_t partid, uint8_t pmg) mpam2_el2 |= (((uint64_t)pmg << MPAMn_ELx_PMG_D_SHIFT) | ((uint64_t)partid << MPAMn_ELx_PARTID_D_SHIFT)); - val_print(ACS_PRINT_DEBUG, "\n Writing MPAM2_EL2: 0x%llx", mpam2_el2); + val_print(DEBUG, "\n Writing MPAM2_EL2: 0x%llx", mpam2_el2); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); return 0; @@ -2055,8 +2055,8 @@ val_mpam_msc_endis_partid(uint32_t msc_index, bool enable, bool nfu_flag, uint16 /* Check if the PARTID is valid */ if (partid >= val_mpam_get_max_partid(msc_index)) { - val_print(ACS_PRINT_ERR, "\n PARTID value (0x%x)", partid); - val_print(ACS_PRINT_ERR, " specified more than MSC supported value (0x%x)", + val_print(ERROR, "\n PARTID value (0x%x)", partid); + val_print(ERROR, " specified more than MSC supported value (0x%x)", val_mpam_get_max_partid(msc_index)); return 1; } @@ -2097,7 +2097,7 @@ val_mpam_reset_csumon(uint32_t msc_index, uint16_t mon_sel) /* if CSUMON_IDR.CSU_RO == 1, accesses to this register are R0 */ if (BITFIELD_READ(CSUMON_IDR_CSU_RO, val_mpam_mmr_read(msc_index, REG_MPAMF_CSUMON_IDR))) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n Cannot reset CSU monitor value as it is Read-Only", 0); return 1; } @@ -2122,7 +2122,7 @@ val_mpam_write_csumon(uint32_t msc_index, uint32_t value) /* if CSUMON_IDR.CSU_RO == 1, accesses to this register are R0 */ if (BITFIELD_READ(CSUMON_IDR_CSU_RO, val_mpam_mmr_read(msc_index, REG_MPAMF_CSUMON_IDR))) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n Cannot write CSU monitor value as it is Read-Only", 0); return 1; } @@ -2242,12 +2242,12 @@ val_mpam_msc_request_msi(uint32_t msc_index, uint32_t device_id, uint32_t its_id its_index = mpam_get_its_index(its_id); if (its_index >= g_gic_its_info->GicNumIts) { - val_print(ACS_PRINT_ERR, "\n Could not find ITS ID [%x]", its_id); + val_print(ERROR, "\n Could not find ITS ID [%x]", its_id); return ACS_STATUS_ERR; } if ((g_gic_its_info->GicRdBase == 0) || (g_gic_its_info->GicDBase == 0)) { - val_print(ACS_PRINT_DEBUG, "\n GICD/GICRD Base Invalid value", 0); + val_print(DEBUG, "\n GICD/GICRD Base Invalid value"); return ACS_STATUS_ERR; } diff --git a/val/src/acs_msc_error.c b/val/src/acs_msc_error.c index c70c8d01..6e5edfd6 100644 --- a/val/src/acs_msc_error.c +++ b/val/src/acs_msc_error.c @@ -42,7 +42,7 @@ uint32_t val_mpam_msc_reset_errcode(uint32_t msc_index) ((uint64_t)ESR_RIS_MASK << ESR_RIS_SHIFT) | ((uint64_t)ESR_OVRWR_MASK << ESR_OVRWR_SHIFT)); - val_print(ACS_PRINT_DEBUG, "\n Mask applied is %llx", mask); + val_print(DEBUG, "\n Mask applied is %llx", mask); /* Update ESR and write back to the register */ esr_value &= mask; val_mpam_mmr_write64(msc_index, REG_MPAMF_ESR, esr_value); @@ -52,7 +52,7 @@ uint32_t val_mpam_msc_reset_errcode(uint32_t msc_index) val_time_delay_ms(100 * ONE_MILLISECOND); esr_errcode = val_mpam_msc_get_errcode(msc_index); if (esr_errcode != ESR_ERRCODE_NO_ERROR) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Cannot clear errorcode for MSC %d", msc_index); return 0; } @@ -101,10 +101,10 @@ uint32_t val_mpam_msc_generate_psr_error(uint32_t msc_index) /* Extract max PARTID supported by this MSC */ max_partid = val_mpam_get_max_partid(msc_index); - val_print(ACS_PRINT_DEBUG, "\n Max PARTID is %d", max_partid); + val_print(DEBUG, "\n Max PARTID is %d", max_partid); if (max_partid == MPAMIDR_PARTID_MAX_MASK) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n MSC index %d: Max PARTID is 0xFFFF; cannot test out-of-range PARTID. Skipping MSC", msc_index); return ACS_STATUS_SKIP; @@ -116,13 +116,13 @@ uint32_t val_mpam_msc_generate_psr_error(uint32_t msc_index) ~(PART_SEL_PARTID_SEL_MASK << PART_SEL_PARTID_SEL_SHIFT)) | BITFIELD_SET(PART_SEL_PARTID_SEL, (max_partid + 1)); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, part_sel_value); - val_print(ACS_PRINT_DEBUG, "\n PARTID written to MPAMCFG_PART_SEL is %d", + val_print(DEBUG, "\n PARTID written to MPAMCFG_PART_SEL is %d", (max_partid + 1)); /* Check whether MPAMCFG_PART_SEL.PARTID_SEL is updated */ part_sel_read = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); partid_sel_read = BITFIELD_READ(PART_SEL_PARTID_SEL, part_sel_read); - val_print(ACS_PRINT_DEBUG, "\n PARTID read from MPAMCFG_PART_SEL is %d", + val_print(DEBUG, "\n PARTID read from MPAMCFG_PART_SEL is %d", partid_sel_read); if (partid_sel_read == (uint32_t)(max_partid + 1)) { @@ -147,7 +147,7 @@ void val_mpam_msc_generate_msr_error(uint32_t msc_index, uint16_t mon_count) { /* Write (mon_count+1) to MON_SEL register to generate MSR error */ val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MON_SEL, mon_count + 1); - val_print(ACS_PRINT_DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %d", mon_count + 1); + val_print(DEBUG, "\n Value written to MSMON_CFG_MON_SEL is %d", mon_count + 1); val_mem_issue_dsb(); return; @@ -173,17 +173,17 @@ uint32_t val_mpam_msc_generate_por_error(uint32_t msc_index) /* Extract max PARTID supported by this MSC */ msc_max_partid = val_mpam_get_max_partid(msc_index); - val_print(ACS_PRINT_DEBUG, "\n MSC Max PARTID is %d", msc_max_partid); + val_print(DEBUG, "\n MSC Max PARTID is %d", msc_max_partid); /* Extract max PARTID supported by MPAMIDR_EL1 */ mpamidr = read_mpamidr_el1(); pe_max_partid = (mpamidr >> MPAMIDR_PARTID_MAX_SHIFT) & MPAMIDR_PARTID_MAX_MASK; - val_print(ACS_PRINT_DEBUG, "\n PE Max PARTID is %d", pe_max_partid); + val_print(DEBUG, "\n PE Max PARTID is %d", pe_max_partid); /* Check if MSC PARTID support exceeds PE PARTID generation range */ if (msc_max_partid >= pe_max_partid) { - val_print(ACS_PRINT_WARN, "\n msc_index is %d", msc_index); - val_print(ACS_PRINT_WARN, "\n Skipping MSC as MSC PARTID >= PE PARTID", 0); + val_print(WARN, "\n msc_index is %d", msc_index); + val_print(WARN, "\n Skipping MSC as MSC PARTID >= PE PARTID"); return ACS_STATUS_SKIP; } @@ -194,7 +194,7 @@ uint32_t val_mpam_msc_generate_por_error(uint32_t msc_index) mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PARTID_D_SHIFT+15, MPAMn_ELx_PARTID_D_SHIFT); mpam2_el2 |= ((msc_max_partid + 1) << MPAMn_ELx_PARTID_D_SHIFT); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAM2_EL2 Reg: %llx", mpam2_el2); + val_print(DEBUG, "\n Value written to MPAM2_EL2 Reg: %llx", mpam2_el2); /* Create buffers to perform memcopy with out-of-range PARTID */ src_buf = (void *)val_aligned_alloc(MEM_ALIGN_4K, SIZE_1K); @@ -233,17 +233,17 @@ uint32_t val_mpam_msc_generate_pmgor_error(uint32_t msc_index) /* Extract max PMG supported by this MSC */ msc_max_pmg = val_mpam_get_max_pmg(msc_index); - val_print(ACS_PRINT_DEBUG, "\n MSC Max PMG is %d", msc_max_pmg); + val_print(DEBUG, "\n MSC Max PMG is %d", msc_max_pmg); /* Extract max PMG supported by MPAMIDR_EL1 */ mpamidr = val_mpam_reg_read(MPAMIDR_EL1); pe_max_pmg = (mpamidr >> MPAMIDR_PMG_MAX_SHIFT) & MPAMIDR_PMG_MAX_MASK; - val_print(ACS_PRINT_DEBUG, "\n PE Max PMG is %d", pe_max_pmg); + val_print(DEBUG, "\n PE Max PMG is %d", pe_max_pmg); /* Check if MSC PMG support exceeds PE PMG generation range */ if (msc_max_pmg >= pe_max_pmg) { - val_print(ACS_PRINT_WARN, "\n msc_index is %d", msc_index); - val_print(ACS_PRINT_WARN, "\n Skipping MSC as MSC pmg >= PE pmg", 0); + val_print(WARN, "\n msc_index is %d", msc_index); + val_print(WARN, "\n Skipping MSC as MSC pmg >= PE pmg"); return ACS_STATUS_SKIP; } @@ -259,7 +259,7 @@ uint32_t val_mpam_msc_generate_pmgor_error(uint32_t msc_index) /* Write MSC out-of-range PMG (msc_max_pmg+1) to MPAM2_EL2 */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2); - val_print(ACS_PRINT_DEBUG, "\n Value written to MPAM2_EL2 Reg: %llx", mpam2_el2); + val_print(DEBUG, "\n Value written to MPAM2_EL2 Reg: %llx", mpam2_el2); /* Create buffers to perform memcopy with out-of-range PMG */ src_buf = (void *)val_aligned_alloc(MEM_ALIGN_4K, SIZE_1K); @@ -293,7 +293,7 @@ void val_mpam_msc_generate_msmon_config_error(uint32_t msc_index, uint16_t mon_c /* Extract max PARTID supported by this MSC */ max_partid = val_mpam_get_max_partid(msc_index); - val_print(ACS_PRINT_DEBUG, "\n MSC Max PARTID is %d", max_partid); + val_print(DEBUG, "\n MSC Max PARTID is %d", max_partid); /* Write (mon_count-1) to MON_SEL register to configure the last monitor */ val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MON_SEL, mon_count - 1); diff --git a/val/src/acs_pcc.c b/val/src/acs_pcc.c index 9391d5c4..a26b6288 100644 --- a/val/src/acs_pcc.c +++ b/val/src/acs_pcc.c @@ -122,7 +122,7 @@ void /* if platform not setting complete, return with failure */ if (loop_cnt == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Platform fails to set command complete reg for PCC subspace id : 0x%x", subspace_id); return NULL; @@ -164,7 +164,7 @@ void /* if platform not setting complete, return with failure */ if (loop_cnt == 0) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Platform fails to set command complete, post command for PCC subspace id : 0x%x", subspace_id); return NULL; @@ -191,8 +191,7 @@ val_pcc_free_info_table(void) g_pcc_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_pcc_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_pcc_info_table pointer is already NULL"); } } diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c index a5fd1835..1367228d 100644 --- a/val/src/acs_pcie.c +++ b/val/src/acs_pcie.c @@ -56,12 +56,12 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) uint32_t i = 0; if ((bus >= PCIE_MAX_BUS) || (dev >= PCIE_MAX_DEV) || (func >= PCIE_MAX_FUNC)) { - val_print(ACS_PRINT_ERR, "\n Invalid Bus/Dev/Func %x", bdf); + val_print(ERROR, "\n Invalid Bus/Dev/Func %x", bdf); return PCIE_NO_MAPPING; } if (g_pcie_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n PCIe_CFG_RD PCIE info table is not created", 0); + val_print(ERROR, "\n PCIe_CFG_RD PCIE info table is not created"); return PCIE_NO_MAPPING; } @@ -78,7 +78,7 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) } if (ecam_base == 0) { - val_print(ACS_PRINT_ERR, "\n PCIe_CFG_RD ECAM Base is zero %.8x", bdf); + val_print(ERROR, "\n PCIe_CFG_RD ECAM Base is zero %.8x", bdf); return PCIE_NO_MAPPING; } @@ -132,12 +132,12 @@ val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data) if ((bus >= PCIE_MAX_BUS) || (dev >= PCIE_MAX_DEV) || (func >= PCIE_MAX_FUNC)) { - val_print(ACS_PRINT_ERR, "\n Invalid Bus/Dev/Func %x", bdf); + val_print(ERROR, "\n Invalid Bus/Dev/Func %x", bdf); return; } if (g_pcie_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Write PCIe_CFG: PCIE info table is not created", 0); + val_print(ERROR, "\n Write PCIe_CFG: PCIE info table is not created"); return; } @@ -154,7 +154,7 @@ val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data) } if (ecam_base == 0) { - val_print(ACS_PRINT_ERR, "\n PCIe_CFG_WR ECAM Base is zero %.8x", bdf); + val_print(ERROR, "\n PCIe_CFG_WR ECAM Base is zero %.8x", bdf); return; } @@ -239,12 +239,12 @@ uint64_t val_pcie_get_bdf_config_addr(uint32_t bdf) uint32_t i = 0; if ((bus >= PCIE_MAX_BUS) || (dev >= PCIE_MAX_DEV) || (func >= PCIE_MAX_FUNC)) { - val_print(ACS_PRINT_ERR, "\n Invalid Bus/Dev/Func %x", bdf); + val_print(ERROR, "\n Invalid Bus/Dev/Func %x", bdf); return 0; } if (g_pcie_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n PCIe_CFG: PCIE info table is not created", 0); + val_print(ERROR, "\n PCIe_CFG: PCIE info table is not created"); return 0; } @@ -262,7 +262,7 @@ uint64_t val_pcie_get_bdf_config_addr(uint32_t bdf) } if (ecam_base == 0) { - val_print(ACS_PRINT_ERR, "\n BDF config Read PCIe_CFG: ECAM Base is zero %x", bdf); + val_print(ERROR, "\n BDF config Read PCIe_CFG: ECAM Base is zero %x", bdf); return 0; } @@ -321,7 +321,7 @@ val_pcie_print_device_info(void) if (bdf_tbl_ptr->num_entries == 0) { - val_print(ACS_PRINT_ERR, " PCIE_INFO: No entries in BDF Table\n", 0); + val_print(ERROR, " PCIE_INFO: No entries in BDF Table\n"); return; } @@ -365,16 +365,16 @@ val_pcie_print_device_info(void) } } - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of RCiEP : %4d\n", num_rciep); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of RCEC : %4d\n", num_rcec); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of EP : %4d\n", num_ep); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of RP : %4d\n", num_rp); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of iEP_EP : %4d\n", num_iep); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of iEP_RP : %4d\n", num_irp); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of UP of switch : %4d\n", num_up); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of DP of switch : %4d\n", num_dp); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of PCI/PCIe Bridge : %4d\n", num_pci_pcie); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of PCIe/PCI Bridge : %4d\n", num_pcie_pci); + val_print(INFO, " PCIE_INFO: Number of RCiEP : %4d\n", num_rciep); + val_print(INFO, " PCIE_INFO: Number of RCEC : %4d\n", num_rcec); + val_print(INFO, " PCIE_INFO: Number of EP : %4d\n", num_ep); + val_print(INFO, " PCIE_INFO: Number of RP : %4d\n", num_rp); + val_print(INFO, " PCIE_INFO: Number of iEP_EP : %4d\n", num_iep); + val_print(INFO, " PCIE_INFO: Number of iEP_RP : %4d\n", num_irp); + val_print(INFO, " PCIE_INFO: Number of UP of switch : %4d\n", num_up); + val_print(INFO, " PCIE_INFO: Number of DP of switch : %4d\n", num_dp); + val_print(INFO, " PCIE_INFO: Number of PCI/PCIe Bridge : %4d\n", num_pci_pcie); + val_print(INFO, " PCIE_INFO: Number of PCIe/PCI Bridge : %4d\n", num_pcie_pci); while (ecam_index < (uint32_t)val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) { @@ -384,8 +384,8 @@ val_pcie_print_device_info(void) tbl_index = 0; bdf_counter = 0; - val_print(ACS_PRINT_INFO, "\n ECAM %d:", ecam_index); - val_print(ACS_PRINT_INFO, " Base 0x%llx\n", ecam_base); + val_print(TRACE, "\n ECAM %d:", ecam_index); + val_print(TRACE, " Base 0x%llx\n", ecam_base); while (tbl_index < bdf_tbl_ptr->num_entries) { @@ -416,17 +416,17 @@ val_pcie_print_device_info(void) { bdf_counter = 1; bdf = PCIE_CREATE_BDF(seg_num, bus_num, dev_num, func_num); - val_print(ACS_PRINT_INFO, " BDF: 0x%x\n", bdf); - val_print(ACS_PRINT_INFO, " Seg: 0x%x, ", seg_num); - val_print(ACS_PRINT_INFO, "Bus: 0x%02x, ", bus_num); - val_print(ACS_PRINT_INFO, "Dev: 0x%02x, ", dev_num); - val_print(ACS_PRINT_INFO, "Func: 0x%x, ", func_num); - val_print(ACS_PRINT_INFO, "Dev ID: 0x%04x, ", device_id); - val_print(ACS_PRINT_INFO, "Vendor ID: 0x%04x\n", vendor_id); + val_print(TRACE, " BDF: 0x%x\n", bdf); + val_print(TRACE, " Seg: 0x%x, ", seg_num); + val_print(TRACE, "Bus: 0x%02x, ", bus_num); + val_print(TRACE, "Dev: 0x%02x, ", dev_num); + val_print(TRACE, "Func: 0x%x, ", func_num); + val_print(TRACE, "Dev ID: 0x%04x, ", device_id); + val_print(TRACE, "Vendor ID: 0x%04x\n", vendor_id); } } if (bdf_counter == 0) - val_print(ACS_PRINT_INFO, " No BDF devices in ECAM region index %d\n", ecam_index); + val_print(TRACE, " No BDF devices in ECAM region index %d\n", ecam_index); ecam_index++; } @@ -447,17 +447,17 @@ val_pcie_create_info_table(uint64_t *pcie_info_table) uint32_t num_ecam; if (pcie_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating PCIe INFO table\n", 0); + val_print(TRACE, " Creating PCIe INFO table\n"); g_pcie_info_table = (PCIE_INFO_TABLE *)pcie_info_table; pal_pcie_create_info_table(g_pcie_info_table); num_ecam = (uint32_t)val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - val_print(ACS_PRINT_TEST, " PCIE_INFO: Number of ECAM regions : %ld\n", num_ecam); + val_print(INFO, " PCIE_INFO: Number of ECAM regions : %ld\n", num_ecam); if (num_ecam == 0) return; @@ -465,14 +465,14 @@ val_pcie_create_info_table(uint64_t *pcie_info_table) /* Create the list of valid Pcie Device Functions */ if (val_pcie_create_device_bdf_table()) { - val_print(ACS_PRINT_ERR, " Create Bdf table failed.\n", 0); + val_print(ERROR, " Create Bdf table failed.\n"); return; } if (pal_pcie_check_device_list()) { pcie_bdf_table_list_flag = 1; - val_print(ACS_PRINT_ERR, "Pcie device list doesn't match \ - with platform pcie device hierarchy\n", 0); + val_print(ERROR, "Pcie device list doesn't match \ + with platform pcie device hierarchy\n"); } val_pcie_print_device_info(); @@ -497,13 +497,13 @@ uint32_t val_pcie_populate_device_rootport(void) for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) { bdf = bdf_tbl_ptr->device[tbl_index].bdf; - val_print(ACS_PRINT_DEBUG, " Dev bdf 0x%06x", bdf); + val_print(DEBUG, " Dev bdf 0x%06x", bdf); /* Checks if the BDF has RootPort */ val_pcie_get_rootport(bdf, &rp_bdf); bdf_tbl_ptr->device[tbl_index].rp_bdf = rp_bdf; - val_print(ACS_PRINT_DEBUG, " RP bdf 0x%06x\n", rp_bdf); + val_print(DEBUG, " RP bdf 0x%06x\n", rp_bdf); } return 0; } @@ -543,8 +543,8 @@ val_pcie_create_device_bdf_table() PCIE_DEVICE_BDF_TABLE_SZ); if (!g_pcie_bdf_table) { - val_print(ACS_PRINT_ERR, - " PCIe BDF table memory allocation failed\n", 0); + val_print(ERROR, + " PCIe BDF table memory allocation failed\n"); return 1; } @@ -554,7 +554,7 @@ val_pcie_create_device_bdf_table() num_ecam = (uint32_t)val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_ERR, " No ECAMs discovered\n ", 0); + val_print(ERROR, " No ECAMs discovered\n "); return 1; } @@ -569,7 +569,7 @@ val_pcie_create_device_bdf_table() for (bus_index = start_bus; bus_index <= end_bus; bus_index++) { if (pal_pcie_check_bus_valid(bus_index)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " Bus 0x%x marked as invalid in Platform API...Skipping\n", bus_index); continue; } @@ -585,7 +585,7 @@ val_pcie_create_device_bdf_table() if (val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) { /* Return if there is a bdf mapping issue */ - val_print(ACS_PRINT_ERR, "\n BDF 0x%x mapping issue", bdf); + val_print(ERROR, "\n BDF 0x%x mapping issue", bdf); return 1; } @@ -594,7 +594,7 @@ val_pcie_create_device_bdf_table() { /* Skip if the device is a host bridge */ if (val_pcie_is_host_bridge(bdf)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " BDF 0x%x is a Host Bridge...Skipping\n", bdf); continue; } @@ -616,14 +616,14 @@ val_pcie_create_device_bdf_table() &cid_offset); if (p_cap != PCIE_SUCCESS) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " BDF 0x%x PCI Express capability not present...Skipping\n", bdf); continue; } status = pal_pcie_check_device_valid(bdf); if (status) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " BDF 0x%x Marked as invalid in Platform API...Skipping\n", bdf); continue; } @@ -653,7 +653,7 @@ val_pcie_create_device_bdf_table() /* Sanity Check : Confirm all EP (normal, integrated) have a rootport */ val_pcie_populate_device_rootport(); - val_print(ACS_PRINT_TEST, + val_print(INFO, " PCIE_INFO: Number of BDFs found : %d\n", g_pcie_bdf_table->num_entries); return 0; @@ -742,8 +742,8 @@ val_pcie_free_info_table(void) g_pcie_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_pcie_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_pcie_info_table pointer is already NULL"); } } @@ -762,13 +762,13 @@ val_pcie_get_info(PCIE_INFO_e type, uint32_t index) { if (g_pcie_info_table == NULL) { - val_print(ACS_PRINT_ERR, "GET_PCIe_INFO: PCIE info table is not created\n", 0); + val_print(ERROR, "GET_PCIe_INFO: PCIE info table is not created\n"); return 0; } if (index >= g_pcie_info_table->num_entries) { if (g_pcie_info_table->num_entries != 0) - val_print(ACS_PRINT_ERR, "Invalid index %d > num of entries\n", index); + val_print(ERROR, "Invalid index %d > num of entries\n", index); return 0; } @@ -784,7 +784,7 @@ val_pcie_get_info(PCIE_INFO_e type, uint32_t index) case PCIE_INFO_SEGMENT: return g_pcie_info_table->block[index].segment_num; default: - val_print(ACS_PRINT_ERR, "This PCIE info option not supported %d\n", type); + val_print(ERROR, "This PCIE info option not supported %d\n", type); break; } @@ -1127,7 +1127,7 @@ val_pcie_enable_dpc(uint32_t bdf, uint32_t err_type) status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, "DPC Capability not supported \n", 0); + val_print(DEBUG, "DPC Capability not supported \n"); return; } @@ -1154,7 +1154,7 @@ val_pcie_disable_dpc(uint32_t bdf) status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); if (status == PCIE_CAP_NOT_FOUND) { - val_print(ACS_PRINT_DEBUG, "DPC Capability not supported \n", 0); + val_print(DEBUG, "DPC Capability not supported \n"); return; } @@ -1340,14 +1340,14 @@ uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry) id = bf_entry->ecap_id; break; default: - val_print(ACS_PRINT_ERR, "\n Invalid reg_type 0x%x ", bf_entry->reg_type); + val_print(ERROR, "\n Invalid reg_type 0x%x ", bf_entry->reg_type); return 1; } if (status != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PCIe Capability 0x%x", id); - val_print(ACS_PRINT_ERR, " not found for BDF 0x%x", bdf); + val_print(ERROR, "\n PCIe Capability 0x%x", id); + val_print(ERROR, " not found for BDF 0x%x", bdf); return status; } @@ -1364,10 +1364,10 @@ uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry) /* Check if bit-field value is proper */ if (bf_value != bf_entry->cfg_value) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x ", bdf); - val_print(ACS_PRINT_ERR, bf_entry->err_str1, 0); - val_print(ACS_PRINT_ERR, " 0x%x", bf_value); - val_print(ACS_PRINT_ERR, " instead of 0x%x", bf_entry->cfg_value); + val_print(ERROR, "\n BDF 0x%x ", bdf); + val_print(ERROR, bf_entry->err_str1); + val_print(ERROR, " 0x%x", bf_value); + val_print(ERROR, " instead of 0x%x", bf_entry->cfg_value); if (!val_strncmp(bf_entry->err_str1, "WARNING", WARN_STR_LEN)) return 0; return 1; @@ -1415,17 +1415,17 @@ uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry) val_pcie_write_cfg(bdf, cap_base + reg_offset, temp_reg_value); break; default: - val_print(ACS_PRINT_ERR, "\n Invalid Attribute 0x%x ", bf_entry->attr); + val_print(ERROR, "\n Invalid Attribute 0x%x ", bf_entry->attr); return 1; } if (reg_overwrite_value != reg_value) { - val_print(ACS_PRINT_ERR, "\n BDF 0x%x ", bdf); - val_print(ACS_PRINT_ERR, bf_entry->err_str2, 0); - val_print(ACS_PRINT_ERR, " 0x%x", + val_print(ERROR, "\n BDF 0x%x ", bdf); + val_print(ERROR, bf_entry->err_str2); + val_print(ERROR, " 0x%x", reg_overwrite_value >> REG_SHIFT(alignment_byte_cnt, bf_entry->start)); - val_print(ACS_PRINT_ERR, " instead of 0x%x", + val_print(ERROR, " instead of 0x%x", reg_value >> REG_SHIFT(alignment_byte_cnt, bf_entry->start)); if (!val_strncmp(bf_entry->err_str2, "WARNING", WARN_STR_LEN)) return 0; @@ -1433,7 +1433,7 @@ uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry) } /* Return pass status */ - val_print(ACS_PRINT_INFO, "\n BDF 0x%x PASS", bdf); + val_print(TRACE, "\n BDF 0x%x PASS", bdf); return 0; } @@ -1460,7 +1460,7 @@ val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t num_bitfield num_fails = num_pass = tbl_index = 0; - val_print(ACS_PRINT_INFO, "\n Number of bit-field entries to check %d", + val_print(TRACE, "\n Number of bit-field entries to check %d", num_bitfield_entries); while (tbl_index < g_pcie_bdf_table->num_entries) @@ -1503,7 +1503,7 @@ val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t num_bitfield if (num_pass > 0 || num_fails > 0) return num_fails; else { - val_print(ACS_PRINT_ERR, "\n No PCIe device of type %d present", dp_type); + val_print(ERROR, "\n No PCIe device of type %d present", dp_type); return ACS_STATUS_SKIP; } } @@ -1556,7 +1556,7 @@ val_pcie_get_mmio_bar(uint32_t bdf, void *base) status = pal_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &data, bdf, ecam); if (status == NOT_IMPLEMENTED) { - val_print(ACS_PRINT_ERR, "\n pal_exerciser_get_data() not implemented", 0); + val_print(ERROR, "\n pal_exerciser_get_data() not implemented"); } /* data.bar_space.base_addr will be zero if no MMIO bar are present for the function */ @@ -1713,7 +1713,7 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) dp_type = val_pcie_device_port_type(bdf); - val_print(ACS_PRINT_INFO, " type 0x%02x", dp_type); + val_print(TRACE, " type 0x%02x", dp_type); /* If the device is RP or iEP_RP, set its rootport value to same */ if ((dp_type == RP) || (dp_type == iEP_RP)) @@ -1752,7 +1752,7 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) } /* Return failure */ - val_print(ACS_PRINT_ERR, " PCIe Hierarchy fail: RP of bdf 0x%x not found\n", bdf); + val_print(ERROR, " PCIe Hierarchy fail: RP of bdf 0x%x not found\n", bdf); *rp_bdf = 0; return 1; @@ -1907,8 +1907,8 @@ void val_pcie_read_acsctrl(uint32_t arr[][1]) val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, ®_value); arr[tbl_index][0] = reg_value; - val_print(ACS_PRINT_INFO, "\n ACS Control Reg value read for BDF 0x%x is", bdf); - val_print(ACS_PRINT_INFO, " %llx", arr[tbl_index][0]); + val_print(TRACE, "\n ACS Control Reg value read for BDF 0x%x is", bdf); + val_print(TRACE, " %llx", arr[tbl_index][0]); tbl_index++; } @@ -1940,8 +1940,8 @@ void val_pcie_write_acsctrl(uint32_t arr[][1]) val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base); val_pcie_write_cfg(bdf, cap_base + ACSCR_OFFSET, arr[tbl_index][0]); - val_print(ACS_PRINT_INFO, "\n ACS Control Reg value written for BDF 0x%x is", bdf); - val_print(ACS_PRINT_INFO, " %llx", arr[tbl_index][0]); + val_print(TRACE, "\n ACS Control Reg value written for BDF 0x%x is", bdf); + val_print(TRACE, " %llx", arr[tbl_index][0]); tbl_index++; } @@ -2010,28 +2010,28 @@ val_pcie_link_cap_support(uint32_t bdf) val_pcie_read_cfg(bdf, pciecs_base + LCAPR_OFFSET, ®_value); if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n Link Capabilities reg check failed", 0); + val_print(ERROR, "\n Link Capabilities reg check failed"); return 1; } reg_value = 0xFFFFFFFF; val_pcie_read_cfg(bdf, pciecs_base + LCTRLR_OFFSET, ®_value); if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n Link Capabilities control and status check failed", 0); + val_print(ERROR, "\n Link Capabilities control and status check failed"); return 1; } reg_value = 0xFFFFFFFF; val_pcie_read_cfg(bdf, pciecs_base + LCAP2R_OFFSET, ®_value); if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n Link Capabilities 2 reg check failed", 0); + val_print(ERROR, "\n Link Capabilities 2 reg check failed"); return 1; } reg_value = 0xFFFFFFFF; val_pcie_read_cfg(bdf, pciecs_base + LCTL2R_OFFSET, ®_value); if (reg_value != 0) { - val_print(ACS_PRINT_ERR, "\n Link Capabilities 2 control and status check failed", 0); + val_print(ERROR, "\n Link Capabilities 2 control and status check failed"); return 1; } @@ -2404,8 +2404,8 @@ pcie_bdf_list_t *val_pcie_get_pcie_peripheral_bdf_list(void) } if (peri_count == 0) { - val_print(ACS_PRINT_DEBUG, "\n No peripherals detected not " - "creating pcie_pheripherals_bdf_list", 0); + val_print(DEBUG, "\n No peripherals detected not " + "creating pcie_pheripherals_bdf_list"); return NULL; } @@ -2415,22 +2415,22 @@ pcie_bdf_list_t *val_pcie_get_pcie_peripheral_bdf_list(void) /* Check if memory allocated */ if (pcie_pheripherals_bdf_list == NULL) { - val_print(ACS_PRINT_ERR, "\n Failed to allocate memory for pcie_pheripherals_bdf_list." - , 0); + val_print(ERROR, "\n Failed to allocate memory for pcie_pheripherals_bdf_list." + ); return NULL; } /* Init the bdf count */ pcie_pheripherals_bdf_list->count = 0; - val_print(ACS_PRINT_DEBUG, "\n Creating pcie_pheripherals_bdf_list ...", 0); + val_print(DEBUG, "\n Creating pcie_pheripherals_bdf_list ..."); for (i = 0; i < peri_count; i++) { dev_bdf = (uint32_t)val_peripheral_get_info (ANY_BDF, i); if (dev_bdf == 0) continue; - val_print(ACS_PRINT_DEBUG, "\n Dev bdf 0x%x", dev_bdf); + val_print(DEBUG, "\n Dev bdf 0x%x", dev_bdf); dev_type = val_pcie_get_device_type(dev_bdf); /* 1: Normal PCIe device, 2: PCIe Host bridge, 3: PCIe bridge device, else: INVALID */ @@ -2441,7 +2441,7 @@ pcie_bdf_list_t *val_pcie_get_pcie_peripheral_bdf_list(void) } if (!val_pcie_device_driver_present(dev_bdf)) { - val_print(ACS_PRINT_DEBUG, "\n Driver not present for bdf 0x%x", dev_bdf); + val_print(DEBUG, "\n Driver not present for bdf 0x%x", dev_bdf); continue; } @@ -2472,7 +2472,7 @@ val_is_transaction_pending_set(uint32_t bdf) status = val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); if (status) { - val_print(ACS_PRINT_ERR, "\n Error in reading transaction pending bit", 0); + val_print(ERROR, "\n Error in reading transaction pending bit"); return 1; } @@ -2540,13 +2540,13 @@ uint32_t val_pcie_ari_forwarding_support(uint32_t bdf) /* Locate PCI Express Capability */ if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base) != PCIE_SUCCESS) { - val_print(ACS_PRINT_ERR, "\n PCI Capability not found for bdf 0x%x", bdf); + val_print(ERROR, "\n PCI Capability not found for bdf 0x%x", bdf); return NOT_IMPLEMENTED; } /* Read Device Capabilities 2 register (offset 0x24 from PCIe Cap base) */ if (val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value)) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Failed to read Device Capabilities 2 register for bdf 0x%x", bdf); return NOT_IMPLEMENTED; } diff --git a/val/src/acs_pe.c b/val/src/acs_pe.c index 119725be..d92988b2 100644 --- a/val/src/acs_pe.c +++ b/val/src/acs_pe.c @@ -497,7 +497,7 @@ void val_cache_create_info_table(uint64_t *cache_info_table) { if (cache_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL\n", 0); + val_print(ERROR, "\n Pre-allocated memory pointer is NULL\n"); return; } @@ -506,7 +506,7 @@ val_cache_create_info_table(uint64_t *cache_info_table) pal_cache_create_info_table(g_cache_info_table, g_pe_info_table); if (g_cache_info_table->num_of_cache != 0) { - val_print(ACS_PRINT_TEST, + val_print(INFO, " CACHE_INFO: Number of cache nodes : %4d\n", g_cache_info_table->num_of_cache); } @@ -527,9 +527,8 @@ val_cache_free_info_table(void) g_cache_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_cache_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_cache_info_table pointer is already NULL"); } } @@ -547,7 +546,7 @@ val_cache_get_info(CACHE_INFO_e type, uint32_t cache_index) char *cache_info_type[] = {"cache_type", "cache_size", "cache_identifier", "associativity"}; if (cache_index >= g_cache_info_table->num_of_cache) { - val_print(ACS_PRINT_ERR, "\n invalid cache index: %d", cache_index); + val_print(ERROR, "\n invalid cache index: %d", cache_index); return 0; } entry = &(g_cache_info_table->cache_info[cache_index]); @@ -573,14 +572,14 @@ val_cache_get_info(CACHE_INFO_e type, uint32_t cache_index) case CACHE_PRIVATE_FLAG: return entry->is_private; default: - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n cache option not supported %d\n", type); return INVALID_CACHE_INFO; } - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n cache %d has invalid ", cache_index); - val_print(ACS_PRINT_ERR, cache_info_type[type], 0); + val_print(ERROR, cache_info_type[type]); return INVALID_CACHE_INFO; } @@ -616,7 +615,7 @@ val_cache_get_llc_index(void) return llc_idx; } else { - val_print(ACS_PRINT_DEBUG, "\n CACHE INFO table invalid", 0); + val_print(DEBUG, "\n CACHE INFO table invalid"); return CACHE_TABLE_EMPTY; } } @@ -636,7 +635,7 @@ val_cache_get_pe_l1_cache_res(uint32_t res_index) if (res_index < MAX_L1_CACHE_RES) return entry->level_1_res[res_index]; else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Requested resource index exceeds maximum index value %d\n", MAX_L1_CACHE_RES); return DEFAULT_CACHE_IDX; } @@ -681,7 +680,7 @@ uint32_t val_pe_feat_check(PE_FEAT_NAME pe_feature) else return ACS_STATUS_FAIL; default: - val_print(ACS_PRINT_ERR, "\nPE_FEAT_CHECK: Invalid PE feature", 0); + val_print(ERROR, "\nPE_FEAT_CHECK: Invalid PE feature"); return ACS_STATUS_FAIL; } } @@ -700,6 +699,6 @@ uint32_t val_cache_get_associativity(uint64_t cache_id) return val_cache_get_info(CACHE_ASSOCIATIVITY, cache_index); } - val_print(ACS_PRINT_ERR, "\n Invalid Cache ID: %d", cache_id); + val_print(ERROR, "\n Invalid Cache ID: %d", cache_id); return 0; } diff --git a/val/src/acs_pe_infra.c b/val/src/acs_pe_infra.c index 4f090223..7b456f84 100644 --- a/val/src/acs_pe_infra.c +++ b/val/src/acs_pe_infra.c @@ -57,22 +57,22 @@ val_pe_create_info_table(uint64_t *pe_info_table) return ACS_STATUS_ERR; if (gPsciConduit == CONDUIT_UNKNOWN) { - val_print(ACS_PRINT_WARN, " FADT not found, assuming SMC as PSCI conduit\n", 0); + val_print(WARN, " FADT not found, assuming SMC as PSCI conduit\n"); gPsciConduit = CONDUIT_SMC; } else if (gPsciConduit == CONDUIT_NONE) { - val_print(ACS_PRINT_WARN, " PSCI not supported, assuming SMC as conduit for tests\n" - " Multi-PE and wakeup tests likely to fail\n", 0); + val_print(WARN, " PSCI not supported, assuming SMC as conduit for tests\n"); + val_print(WARN, " Multi-PE and wakeup tests likely to fail\n"); gPsciConduit = CONDUIT_SMC; } else if (gPsciConduit == CONDUIT_HVC) { - val_print(ACS_PRINT_INFO, " Using HVC as PSCI conduit\n", 0); + val_print(TRACE, " Using HVC as PSCI conduit\n"); } else { - val_print(ACS_PRINT_INFO, " Using SMC as PSCI conduit\n", 0); + val_print(TRACE, " Using SMC as PSCI conduit\n"); } - val_print(ACS_PRINT_INFO, " Creating PE INFO table\n", 0); + val_print(TRACE, " Creating PE INFO table\n"); if (pe_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input memory for PE Info table cannot be NULL\n", 0); + val_print(ERROR, "Input memory for PE Info table cannot be NULL\n"); return ACS_STATUS_ERR; } @@ -81,22 +81,22 @@ val_pe_create_info_table(uint64_t *pe_info_table) pal_pe_create_info_table(g_pe_info_table); val_data_cache_ops_by_va((addr_t)&g_pe_info_table, CLEAN_AND_INVALIDATE); - val_print(ACS_PRINT_TEST, " PE_INFO: Number of PE detected : %4d\n", val_pe_get_num()); + val_print(INFO, " PE_INFO: Number of PE detected : %4d\n", val_pe_get_num()); if (val_pe_get_num() == 0) { - val_print(ACS_PRINT_ERR, "\n *** CRITICAL ERROR: Num PE is 0x0 ***\n", 0); + val_print(ERROR, "\n *** CRITICAL ERROR: Num PE is 0x0 ***\n"); return ACS_STATUS_ERR; } #ifndef TARGET_LINUX -val_print(ACS_PRINT_TEST, " Primary PE: MIDR_EL1 : 0x%llx \n", +val_print(INFO, " Primary PE: MIDR_EL1 : 0x%llx \n", val_pe_reg_read(MIDR_EL1)); #endif /* store primary PE index for debug message printing purposes on multi PE tests */ g_primary_pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_DEBUG, " PE_INFO: Primary PE index : %4d\n", + val_print(DEBUG, " PE_INFO: Primary PE index : %4d\n", g_primary_pe_index); return ACS_STATUS_PASS; @@ -117,8 +117,8 @@ val_pe_free_info_table(void) g_pe_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_pe_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_pe_info_table pointer is already NULL"); } } @@ -261,7 +261,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) int timeout = TIMEOUT_LARGE; if (index > g_pe_info_table->header.num_of_pe) { - val_print(ACS_PRINT_ERR, "Input Index exceeds Num of PE %x\n", index); + val_print(ERROR, "Input Index exceeds Num of PE %x\n", index); val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); return; } @@ -279,8 +279,8 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) } while (g_smc_args.Arg0 == (uint64_t)ARM_SMC_PSCI_RET_ALREADY_ON && timeout--); if (g_smc_args.Arg0 == (uint64_t)ARM_SMC_PSCI_RET_ALREADY_ON) { - val_print(ACS_PRINT_ERR, "\n PSCI_CPU_ON: cpu already on", 0); - val_print(ACS_PRINT_WARN, "\n WARNING: Skipping test for PE index %d " + val_print(ERROR, "\n PSCI_CPU_ON: cpu already on"); + val_print(WARN, "\n WARNING: Skipping test for PE index %d " "since it is already on\n", index); val_set_status(index, RESULT_SKIP(0, 0x120 - (int)g_smc_args.Arg0)); @@ -288,11 +288,11 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) } else { if(g_smc_args.Arg0 == 0) { - val_print(ACS_PRINT_INFO, "\n PSCI_CPU_ON: success", 0); + val_print(TRACE, "\n PSCI_CPU_ON: success"); return; } else - val_print(ACS_PRINT_ERR, "\n PSCI_CPU_ON: failure[%d]", g_smc_args.Arg0); + val_print(ERROR, "\n PSCI_CPU_ON: failure[%d]", g_smc_args.Arg0); } val_set_status(index, RESULT_FAIL(0, 0x120 - (int)g_smc_args.Arg0)); @@ -312,7 +312,7 @@ val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)) { if (exception_type > 3) { - val_print(ACS_PRINT_ERR, "Invalid Exception type %x\n", exception_type); + val_print(ERROR, "Invalid Exception type %x\n", exception_type); return ACS_STATUS_ERR; } #ifndef TARGET_LINUX @@ -383,23 +383,23 @@ void val_pe_default_esr(uint64_t interrupt_type, void *context) { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(ACS_PRINT_WARN, "\n Unexpected exception of type %d occurred", interrupt_type); + val_print(WARN, "\n Unexpected exception of type %d occurred", interrupt_type); #ifndef TARGET_LINUX if (pal_target_is_dt()) { - val_print(ACS_PRINT_WARN, "\n FAR reported = 0x%llx", bsa_gic_get_far()); - val_print(ACS_PRINT_WARN, "\n ESR reported = 0x%llx", bsa_gic_get_esr()); + val_print(WARN, "\n FAR reported = 0x%llx", bsa_gic_get_far()); + val_print(WARN, "\n ESR reported = 0x%llx", bsa_gic_get_esr()); val_set_status(index, RESULT_FAIL(0, 1)); val_pe_update_elr(context, g_exception_ret_addr); return; } if (pal_target_is_bm()) { - val_print(ACS_PRINT_WARN, "\n FAR reported = 0x%llx", bsa_gic_get_far()); - val_print(ACS_PRINT_WARN, "\n ESR reported = 0x%llx", bsa_gic_get_esr()); + val_print(WARN, "\n FAR reported = 0x%llx", bsa_gic_get_far()); + val_print(WARN, "\n ESR reported = 0x%llx", bsa_gic_get_esr()); } else { - val_print(ACS_PRINT_WARN, "\n FAR reported = 0x%llx", val_pe_get_far(context)); - val_print(ACS_PRINT_WARN, "\n ESR reported = 0x%llx", val_pe_get_esr(context)); + val_print(WARN, "\n FAR reported = 0x%llx", val_pe_get_far(context)); + val_print(WARN, "\n ESR reported = 0x%llx", val_pe_get_esr(context)); } #endif @@ -500,17 +500,17 @@ val_pe_get_primary_index(void) void val_smbios_create_info_table(uint64_t *smbios_info_table) { - val_print(ACS_PRINT_INFO, " Creating SMBIOS INFO table\n", 0); + val_print(TRACE, " Creating SMBIOS INFO table\n"); if (smbios_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input memory for SMBIOS Info table cannot be NULL\n", 0); + val_print(ERROR, "Input memory for SMBIOS Info table cannot be NULL\n"); return; } g_smbios_info_table = (PE_SMBIOS_PROCESSOR_INFO_TABLE *)smbios_info_table; pal_smbios_create_info_table(g_smbios_info_table); - val_print(ACS_PRINT_TEST, " SMBIOS: Num of slots : %4d\n", + val_print(INFO, " SMBIOS: Num of slots : %4d\n", g_smbios_info_table->slot_count); } @@ -545,8 +545,8 @@ val_smbios_free_info_table() g_smbios_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_smbios_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_smbios_info_table pointer is already NULL"); } } #endif diff --git a/val/src/acs_peripherals.c b/val/src/acs_peripherals.c index 1b0e371d..e628b3d7 100644 --- a/val/src/acs_peripherals.c +++ b/val/src/acs_peripherals.c @@ -217,7 +217,7 @@ val_peripheral_dump_info(void) num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (num_ecam == 0) { - val_print(ACS_PRINT_DEBUG, "\n No ECAM is present", 0); + val_print(DEBUG, "\n No ECAM is present"); return; } @@ -230,7 +230,7 @@ val_peripheral_dump_info(void) for (bus = start_bus; bus <= end_bus; bus++) { if (pal_pcie_check_bus_valid(bus)) { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, " Bus 0x%x marked as invalid in Platform API...Skipping\n", bus); continue; } @@ -244,8 +244,8 @@ val_peripheral_dump_info(void) if (reg_value == PCIE_UNKNOWN_RESPONSE) continue; val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); - val_print(ACS_PRINT_DEBUG, "\n BDF is %x", dev_bdf); - val_print(ACS_PRINT_DEBUG, "\n Class code is %x", reg_value); + val_print(DEBUG, "\n BDF is %x", dev_bdf); + val_print(DEBUG, "\n Class code is %x", reg_value); base_cc = reg_value >> TYPE01_BCC_SHIFT; if (base_cc == CNTRL_CC) ntwk++; @@ -261,9 +261,9 @@ val_peripheral_dump_info(void) } - val_print(ACS_PRINT_DEBUG, "\n Peripheral: Num of Network ctrl : %d\n", ntwk); - val_print(ACS_PRINT_DEBUG, " Peripheral: Num of Storage ctrl : %d\n", strg); - val_print(ACS_PRINT_DEBUG, " Peripheral: Num of Display ctrl : %d\n", dply); + val_print(DEBUG, "\n Peripheral: Num of Network ctrl : %d\n", ntwk); + val_print(DEBUG, " Peripheral: Num of Storage ctrl : %d\n", strg); + val_print(DEBUG, " Peripheral: Num of Display ctrl : %d\n", dply); } @@ -289,18 +289,18 @@ val_peripheral_create_info_table(uint64_t *peripheral_info_table) { g_peripheral_info_table = (PERIPHERAL_INFO_TABLE *)peripheral_info_table; - val_print(ACS_PRINT_INFO, " Creating PERIPHERAL INFO table\n", 0); + val_print(TRACE, " Creating PERIPHERAL INFO table\n"); pal_peripheral_create_info_table(g_peripheral_info_table); - val_print(ACS_PRINT_TEST, " Peripheral: Num of USB controllers : %d\n", + val_print(INFO, " Peripheral: Num of USB controllers : %d\n", val_peripheral_get_info(NUM_USB, 0)); - val_print(ACS_PRINT_TEST, " Peripheral: Num of SATA controllers : %d\n", + val_print(INFO, " Peripheral: Num of SATA controllers : %d\n", val_peripheral_get_info(NUM_SATA, 0)); - val_print(ACS_PRINT_TEST, " Peripheral: Num of UART controllers : %d\n", + val_print(INFO, " Peripheral: Num of UART controllers : %d\n", val_peripheral_get_info(NUM_UART, 0)); - if (g_print_level <= ACS_PRINT_INFO) + if (g_print_level <= TRACE) val_peripheral_dump_info(); } @@ -321,8 +321,8 @@ val_peripheral_free_info_table(void) g_peripheral_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_peripheral_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_peripheral_info_table pointer is already NULL"); } } diff --git a/val/src/acs_pfdi.c b/val/src/acs_pfdi.c index 9efad152..8b63e387 100644 --- a/val/src/acs_pfdi.c +++ b/val/src/acs_pfdi.c @@ -60,10 +60,10 @@ val_pfdi_check_implementation(void) uint32_t val_pfdi_reserved_bits_check_is_zero(uint32_t reserved_bits) { if (reserved_bits != VAL_PFDI_RESERVED_BYTE_ZERO) { - val_print(ACS_PRINT_ERR, "\n CHECK RSVD BITS: FAILED [0x%08x]", reserved_bits); + val_print(ERROR, "\n CHECK RSVD BITS: FAILED [0x%08x]", reserved_bits); return ACS_STATUS_FAIL; } else - val_print(ACS_PRINT_DEBUG, "\n CHECK RSVD BITS: PASSED", 0); + val_print(DEBUG, "\n CHECK RSVD BITS: PASSED"); return ACS_STATUS_PASS; } diff --git a/val/src/acs_pgt.c b/val/src/acs_pgt.c index f1a17eb3..34c387e1 100644 --- a/val/src/acs_pgt.c +++ b/val/src/acs_pgt.c @@ -24,7 +24,7 @@ #define get_min(a, b) ((a) < (b))?(a):(b) -#define PGT_DEBUG_LEVEL ACS_PRINT_INFO +#define PGT_DEBUG_LEVEL TRACE IOREMMAP_LIST *ioremmap_list; @@ -126,7 +126,7 @@ uint32_t get_entries_per_level(uint32_t page_size) case(PAGE_SIZE_64K): //64kb granule return MAX_ENTRIES_64K; default: - val_print(ACS_PRINT_ERR, "\n %llx granularity not supported.", page_size); + val_print(ERROR, "\n %llx granularity not supported.", page_size); return 0; } } @@ -143,7 +143,7 @@ uint64_t get_block_size(uint32_t level) else if (page_size == PAGE_SIZE_16K) return (uint64_t)(page_size * entries * entries * 2); // only 2 lookup tables in L0 else { - val_print(ACS_PRINT_ERR, "\n L0 tables not supported for page size %llx", + val_print(ERROR, "\n L0 tables not supported for page size %llx", page_size); return 0; } @@ -371,7 +371,7 @@ uint64_t val_pgt_ioremap_attr(pgt_descriptor_t pgt_desc, uint64_t *pte = val_find_pte(pgt_desc, a); if (!pte) { - val_print(ACS_PRINT_INFO, "Cannot find PTE for 0x%lx\n", a); + val_print(TRACE, "Cannot find PTE for 0x%lx\n", a); continue; } flag = 1; @@ -502,9 +502,8 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto tt_base_next_level = val_memory_alloc_pages(1); if (tt_base_next_level == NULL) { - val_print(ACS_PRINT_ERR, - "\n fill_translation_table: page allocation failed ", - 0); + val_print(ERROR, + "\n fill_translation_table: page allocation failed "); return ACS_STATUS_ERR; } val_memory_set(tt_base_next_level, page_size, 0); @@ -631,7 +630,7 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t * if (pgt_desc->pgt_base == (uint64_t) NULL) { tt_base = (uint64_t *) val_memory_alloc_pages(1); if (tt_base == NULL) { - val_print(ACS_PRINT_ERR, "\n val_pgt_create: page allocation failed ", 0); + val_print(ERROR, "\n val_pgt_create: page allocation failed "); return ACS_STATUS_ERR; } val_memory_set(tt_base, page_size, 0); @@ -654,21 +653,20 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t * if ((mem_desc->virtual_address & (uint64_t)(page_size - 1)) != 0 || (mem_desc->physical_address & (uint64_t)(page_size - 1)) != 0) { - val_print(ACS_PRINT_ERR, "\n val_pgt_create: addr alignment err ", 0); + val_print(ERROR, "\n val_pgt_create: addr alignment err "); return ACS_STATUS_ERR; } if (mem_desc->physical_address >= (0x1ull << pgt_desc->oas)) { - val_print(ACS_PRINT_ERR, - "\n val_pgt_create: output address size error ", - 0); + val_print(ERROR, + "\n val_pgt_create: output address size error "); return ACS_STATUS_ERR; } if (mem_desc->virtual_address >= (0x1ull << pgt_desc->ias)) { - val_print(ACS_PRINT_WARN, + val_print(WARN, "\n val_pgt_create: input address size error, " "truncating to %d-bits ", pgt_desc->ias); diff --git a/val/src/acs_pmu.c b/val/src/acs_pmu.c index eb0635ec..0232f766 100644 --- a/val/src/acs_pmu.c +++ b/val/src/acs_pmu.c @@ -50,7 +50,7 @@ val_pmu_reg_read ( case PMCNTENSET_EL0: return read_pmcntenset_el0(); default: - val_print(ACS_PRINT_ERR, "\n FATAL - Unsupported PMU register read \n", 0); + val_print(ERROR, "\n FATAL - Unsupported PMU register read \n"); } return 0x0; @@ -84,7 +84,7 @@ val_pmu_reg_write ( write_pmcntenset_el0(WriteData); break; default: - val_print(ACS_PRINT_ERR, "\n FATAL - Unsupported PMU register read \n", 0); + val_print(ERROR, "\n FATAL - Unsupported PMU register read \n"); } } @@ -168,7 +168,7 @@ val_pmu_create_info_table(uint64_t *pmu_info_table) uint32_t reg_value; if (pmu_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\nInput for Create PMU Info table cannot be NULL", 0); + val_print(ERROR, "\nInput for Create PMU Info table cannot be NULL"); return; } @@ -176,21 +176,21 @@ val_pmu_create_info_table(uint64_t *pmu_info_table) pal_pmu_create_info_table(g_pmu_info_table); - val_print(ACS_PRINT_TEST, " PMU_INFO: Number of PMU units : %4d\n", + val_print(INFO, " PMU_INFO: Number of PMU units : %4d\n", g_pmu_info_table->pmu_count); for (node_index = 0; node_index < g_pmu_info_table->pmu_count; node_index++) { - val_print(ACS_PRINT_INFO, " PMU node index: %4d\n", node_index); + val_print(TRACE, " PMU node index: %4d\n", node_index); base = val_pmu_get_info(PMU_NODE_BASE0, node_index); val_mmu_update_entry(base, 0x1000, DEVICE_nGnRnE); - val_print(ACS_PRINT_INFO, " PMU node mapped \n", 0); + val_print(TRACE, " PMU node mapped \n"); reg_value = BITFIELD_READ(PMDEVARCH_ARCHITECT, val_mmio_read(base + REG_PMDEVARCH)); /* 0x23B is value for Arm Limited */ if (reg_value == 0x23B) val_pmu_set_node_coresight_complaint(0x1, node_index); else { val_pmu_set_node_coresight_complaint(0x0, node_index); - val_print(ACS_PRINT_ERR, "\n PMU node index %d is not CS complaint", node_index); + val_print(ERROR, "\n PMU node index %d is not CS complaint", node_index); } } @@ -206,12 +206,12 @@ val_pmu_set_node_coresight_complaint(uint32_t flag, uint32_t node_index) PMU_INFO_BLOCK *entry; if (g_pmu_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n APMT info table not found", 0); + val_print(WARN, "\n APMT info table not found"); return; } if (node_index > g_pmu_info_table->pmu_count) { - val_print(ACS_PRINT_WARN, "\n Invalid Node index ", 0); + val_print(WARN, "\n Invalid Node index "); return; } @@ -230,9 +230,8 @@ val_pmu_free_info_table(void) g_pmu_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_pmu_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_pmu_info_table pointer is already NULL"); } } @@ -251,12 +250,12 @@ val_pmu_get_info(PMU_INFO_e type, uint32_t node_index) PMU_INFO_BLOCK *entry; if (g_pmu_info_table == NULL) { - val_print(ACS_PRINT_WARN, "\n APMT info table not found", 0); + val_print(WARN, "\n APMT info table not found"); return 0; } if (node_index > g_pmu_info_table->pmu_count) { - val_print(ACS_PRINT_WARN, "\n Invalid Node index ", 0); + val_print(WARN, "\n Invalid Node index "); return 0; } @@ -280,7 +279,7 @@ val_pmu_get_info(PMU_INFO_e type, uint32_t node_index) case PMU_NODE_CS_COM: return entry->coresight_compliant; default: - val_print(ACS_PRINT_ERR, "\n This PMU info option is not supported : %d ", type); + val_print(ERROR, "\n This PMU info option is not supported : %d ", type); return 0; } } @@ -554,7 +553,7 @@ val_pmu_get_node_index(uint64_t node_instance_primary, PMU_NODE_INFO_TYPE node_t return node_index; } } - val_print(ACS_PRINT_DEBUG, "\n PMU node for given node primary instance not found ", 0); + val_print(DEBUG, "\n PMU node for given node primary instance not found "); return PMU_INVALID_INDEX; } @@ -647,7 +646,7 @@ val_pmu_get_index_acpiid(uint64_t interface_acpiid) return node_index; } } - val_print(ACS_PRINT_DEBUG, "\n PMU node for given acpi id not found ", 0); + val_print(DEBUG, "\n PMU node for given acpi id not found "); return PMU_INVALID_INDEX; } @@ -678,15 +677,15 @@ test_status_t is_coresight_pmu_present(void) /* Check if PMU nodes present in the system */ node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); - val_print(ACS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + val_print(DEBUG, "\n PMU NODES = %d", node_count); if (node_count == 0) { - val_print(ACS_PRINT_TEST, "\n No PMU nodes found in APMT table", 0); - val_print(ACS_PRINT_TEST, "\n The test must be considered fail" - " if system has CoreSight PMU", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); - return TEST_WARN; + val_print(INFO, "\n No PMU nodes found in APMT table"); + val_print(INFO, "\n The test must be considered fail" + " if system has CoreSight PMU"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); + return TEST_SKIP; } /* The test uses PMU CoreSight arch register map, skip if pmu node is not cs */ @@ -694,9 +693,9 @@ test_status_t is_coresight_pmu_present(void) cs_com |= val_pmu_get_info(PMU_NODE_CS_COM, node_index); } if (cs_com != 0x1) { - val_print(ACS_PRINT_TEST, "\n No CoreSight PMU nodes found", 0); - val_print(ACS_PRINT_TEST, "\n For non CoreSight PMU, manually verify A.4 PMU rules " - "in the SBSA specification", 0); + val_print(INFO, "\n No CoreSight PMU nodes found"); + val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " + "in the SBSA specification"); return TEST_WARN; } diff --git a/val/src/acs_ras.c b/val/src/acs_ras.c index 8b874e50..e71543a7 100644 --- a/val/src/acs_ras.c +++ b/val/src/acs_ras.c @@ -38,7 +38,7 @@ val_ras_create_info_table(uint64_t *ras_info_table) { if (ras_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return ACS_STATUS_ERR; } @@ -46,7 +46,7 @@ val_ras_create_info_table(uint64_t *ras_info_table) pal_ras_create_info_table(g_ras_info_table); - val_print(ACS_PRINT_TEST, " RAS_INFO: Number of RAS nodes : %4d\n", + val_print(INFO, " RAS_INFO: Number of RAS nodes : %4d\n", g_ras_info_table->num_nodes); return ACS_STATUS_PASS; @@ -63,9 +63,8 @@ val_ras_free_info_table(void) g_ras_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_ras_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_ras_info_table pointer is already NULL"); } } @@ -82,7 +81,7 @@ val_ras2_create_info_table(uint64_t *ras2_info_table) { if (ras2_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\nInput for RAS2 feat create info table cannot be NULL\n", 0); + val_print(ERROR, "\nInput for RAS2 feat create info table cannot be NULL\n"); return; } @@ -91,9 +90,9 @@ val_ras2_create_info_table(uint64_t *ras2_info_table) pal_ras2_create_info_table(g_ras2_info_table); - val_print(ACS_PRINT_TEST, " RAS2_INFO: Number of RAS2 entries : %4d\n", + val_print(INFO, " RAS2_INFO: Number of RAS2 entries : %4d\n", g_ras2_info_table->num_all_block); - val_print(ACS_PRINT_TEST, " RAS2_INFO: Num of RAS2 memory entries: %4d\n", + val_print(INFO, " RAS2_INFO: Num of RAS2 memory entries: %4d\n", g_ras2_info_table->num_of_mem_block); #endif return; @@ -206,7 +205,7 @@ val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) /* Returns the PFG Support */ value = val_ras_reg_read(param1, RAS_ERR_FR, 0); if (value == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<0>FR register for RAS node index: 0x%lx", param1); return ACS_STATUS_FAIL; @@ -238,7 +237,7 @@ val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) break; case RAS_INFO_NODE_INDEX_FOR_AFF: /* Returns the Node Index For the PE node for MPIDR = param1 */ - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n RAS_GET_INFO : Param1 = 0x%x ", param1); for (j = 0; j < g_ras_info_table->num_nodes; j++) { @@ -256,7 +255,7 @@ val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) else { pe_affinity = val_ras_reg_read(j, RAS_ERR_ERRDEVAFF, 0); if (pe_affinity == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_GET_INFO : Invalid pe_affinity (ERR_ERRDEVAFF) for RAS node = %d ", j); return ACS_STATUS_FAIL; @@ -275,7 +274,7 @@ val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) /* get processor UID */ pe_uid = val_pe_get_uid(param1); if (pe_uid == INVALID_PE_INFO) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_GET_INFO : Invalid PE UID for MPIDR = %lx", param1); return ACS_STATUS_FAIL; @@ -287,7 +286,7 @@ val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) } } } - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_GET_INFO : No PE RAS node matches with MPIDR = %lx", param1); return ACS_STATUS_FAIL; @@ -316,7 +315,7 @@ val_ras2_get_mem_info(RAS2_MEM_INFO_e type, uint32_t index) RAS2_BLOCK *block; if (g_ras2_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\nRAS2_GET_MEM_INFO : ras2 info table is not created\n", 0); + val_print(ERROR, "\nRAS2_GET_MEM_INFO : ras2 info table is not created\n"); return 0; /* imply no ras2_info entries */ } @@ -325,7 +324,7 @@ val_ras2_get_mem_info(RAS2_MEM_INFO_e type, uint32_t index) /* check if index in range */ if (index > g_ras2_info_table->num_of_mem_block - 1) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\nRAS2_GET_MEM_INFO: Index (%d) is greater than num of RAS2 mem blocks\n", index); return INVALID_RAS2_INFO; @@ -343,7 +342,7 @@ val_ras2_get_mem_info(RAS2_MEM_INFO_e type, uint32_t index) case RAS2_SCRUB_SUPPORT: return block->block_info.mem_feat_info.patrol_scrub_support; default: - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\nThis RAS2 memory info option not supported: %d\n", type); return INVALID_RAS2_INFO; } @@ -379,7 +378,7 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) /* Check if err record index is valid */ val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); if ((err_rec_idx - start_rec_index) >= num_err_recs) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : Invalid Input error record index(%d)\n", err_rec_idx); return INVALID_RAS_REG_VAL; } @@ -388,9 +387,9 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_impl_bitmap); if ((err_rec_impl_bitmap >> err_rec_idx) & 0x1) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : Error record index(%d) is unimplemented ", err_rec_idx); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "for node with index: %d\n", node_index); return INVALID_RAS_REG_VAL; } @@ -423,9 +422,9 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) if (err_rec_idx == start_rec_index) offset = ERR_PFGCDN_OFFSET + (64 * start_rec_index); else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : ERR<%d>PFGCDN is RES0 for node index :", err_rec_idx); - val_print(ACS_PRINT_ERR, " %d", node_index); + val_print(ERROR, " %d", node_index); return INVALID_RAS_REG_VAL; } break; @@ -434,9 +433,9 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) if (err_rec_idx == start_rec_index) offset = ERR_PFGCTL_OFFSET + (64 * start_rec_index); else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : ERR<%d>PFGCTL is RES0 for node index :", err_rec_idx); - val_print(ACS_PRINT_ERR, " %d", node_index); + val_print(ERROR, " %d", node_index); return INVALID_RAS_REG_VAL; } break; @@ -465,9 +464,9 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) if (err_rec_idx == start_rec_index) value = read_erxpfgcdn_el1(); else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : ERR<%d>PFGCDN is RES0 for the node index :", err_rec_idx); - val_print(ACS_PRINT_ERR, " %d", node_index); + val_print(ERROR, " %d", node_index); return INVALID_RAS_REG_VAL; } break; @@ -476,9 +475,9 @@ val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) if (err_rec_idx == start_rec_index) value = read_erxpfgctl_el1(); else { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n RAS_REG_READ : ERR<%d>PFGCTL is RES0 for the node index :", err_rec_idx); - val_print(ACS_PRINT_ERR, " %d", node_index); + val_print(ERROR, " %d", node_index); return INVALID_RAS_REG_VAL; } break; @@ -654,12 +653,12 @@ ras_pfg_access_node(uint32_t node_index) /* Access to the Node register, Might need an imp def way here */ reg_value = val_ras_reg_read(node_index, RAS_ERR_CTLR, 0); if (reg_value == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<0>CTLR register for RAS node index: 0x%lx", node_index); } - val_print(ACS_PRINT_INFO, " Access RAS Node, CTLR : 0x%llx\n", reg_value); + val_print(TRACE, " Access RAS Node, CTLR : 0x%llx\n", reg_value); } /** @@ -683,10 +682,10 @@ val_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) reg_value = val_ras_reg_read(in_param.node_index, RAS_ERR_PFGCTL, in_param.rec_index); if (reg_value == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<%d>PFGCTL register for ", in_param.rec_index); - val_print(ACS_PRINT_ERR, + val_print(ERROR, "RAS node index: 0x%lx", in_param.node_index); return ACS_STATUS_FAIL; @@ -725,7 +724,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type) err_status = val_ras_reg_read(node_index, RAS_ERR_STATUS, 0); if (err_status == INVALID_RAS_REG_VAL) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n Couldn't read ERR<0>STATUS register for RAS node index: 0x%lx", node_index); return ACS_STATUS_FAIL; @@ -733,7 +732,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type) /* Check Status Register Validity in Ras Node */ if (!(err_status & ERR_STATUS_V_MASK)) { - val_print(ACS_PRINT_DEBUG, "\n Status Reg Not Valid, for node %d", node_index); + val_print(DEBUG, "\n Status Reg Not Valid, for node %d", node_index); status = ACS_STATUS_FAIL; } @@ -756,7 +755,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type) /* Check Error Bit in Ras Node */ if (!(err_status & err_type_mask)) { - val_print(ACS_PRINT_DEBUG, "\n ERR Status Type Fail, for node %d", node_index); + val_print(DEBUG, "\n ERR Status Type Fail, for node %d", node_index); status = ACS_STATUS_FAIL; } diff --git a/val/src/acs_smmu.c b/val/src/acs_smmu.c index c1cbc70d..de8b4049 100644 --- a/val/src/acs_smmu.c +++ b/val/src/acs_smmu.c @@ -58,7 +58,7 @@ val_smmu_start_monitor_dev(uint32_t ctrl_index) ap = (void *)val_dma_get_info(DMA_PORT_INFO, ctrl_index); if (ap == NULL) { - val_print(ACS_PRINT_ERR, "Invalid Controller index %d\n", ctrl_index); + val_print(ERROR, "Invalid Controller index %d\n", ctrl_index); return ACS_STATUS_ERR; } @@ -82,7 +82,7 @@ val_smmu_stop_monitor_dev(uint32_t ctrl_index) ap = (void *)val_dma_get_info(DMA_PORT_INFO, ctrl_index); if (ap == NULL) { - val_print(ACS_PRINT_ERR, "Invalid Controller index %d\n", ctrl_index); + val_print(ERROR, "Invalid Controller index %d\n", ctrl_index); return ACS_STATUS_ERR; } @@ -112,10 +112,10 @@ val_smmu_check_device_iova(uint32_t ctrl_index, addr_t dma_addr) ap = (void *)val_dma_get_info(DMA_PORT_INFO, ctrl_index); if (ap == NULL) { - val_print(ACS_PRINT_ERR, "Invalid Controller index %d\n", ctrl_index); + val_print(ERROR, "Invalid Controller index %d\n", ctrl_index); return ACS_STATUS_ERR; } - val_print(ACS_PRINT_DEBUG, "Input dma addr = %lx\n", dma_addr); + val_print(DEBUG, "Input dma addr = %lx\n", dma_addr); status = pal_smmu_check_device_iova(ap, dma_addr); diff --git a/val/src/acs_status.c b/val/src/acs_status.c index 414ae237..1af59237 100644 --- a/val/src/acs_status.c +++ b/val/src/acs_status.c @@ -43,50 +43,50 @@ val_report_status(uint32_t index, uint32_t status, char8_t *ruleid) return; if (IS_TEST_FAIL(status)) { - val_print(ACS_PRINT_ERR, "\n Failed on PE - %4d", index); + val_print(ERROR, "\nFailed on PE - %4d\n", index); } if (IS_TEST_SKIP(status)) { - val_print(ACS_PRINT_ERR, "\n Skipped on PE - %4d", index); + val_print(ERROR, "\nSkipped on PE - %4d\n", index); } if (IS_TEST_PASS(status)) { - val_print(ACS_PRINT_DEBUG, "\n ", 0); - val_print(ACS_PRINT_DEBUG, ruleid, 0); - val_print(ACS_PRINT_DEBUG, "\n ", 0); - val_print(ACS_PRINT_TEST, " : Result: PASS\n", status); + val_print(DEBUG, "\n "); + val_print(DEBUG, ruleid); + val_print(DEBUG, "\n "); + val_print(INFO, " : Result: PASS\n", status); } else if (IS_TEST_WARN(status)) { - val_print(ACS_PRINT_TEST, " : Result: WARN\n", 0); + val_print(INFO, " : Result: WARN\n"); } else if (IS_TEST_FAIL(status)) { if (ruleid) { - val_print(ACS_PRINT_ERR, "\n ", 0); - val_print(ACS_PRINT_ERR, ruleid, 0); - val_print(ACS_PRINT_ERR, "\n Checkpoint -- %2d ", + val_print(INFO, "\n "); + val_print(INFO, ruleid); + val_print(ERROR, "\n Checkpoint -- %2d ", status & STATUS_MASK); } - val_print(ACS_PRINT_ERR, " : Result: FAIL\n", 0); + val_print(ERROR, " : Result: FAIL\n"); } else if (IS_TEST_SKIP(status)) { if (ruleid) { - val_print(ACS_PRINT_ERR, "\n ", 0); - val_print(ACS_PRINT_ERR, ruleid, 0); - val_print(ACS_PRINT_WARN, "\n Checkpoint -- %2d ", + val_print(INFO, "\n "); + val_print(INFO, ruleid); + val_print(WARN, "\n Checkpoint -- %2d ", status & STATUS_MASK); } - val_print(ACS_PRINT_WARN, " : Result: SKIPPED\n", 0); + val_print(WARN, " : Result: SKIPPED\n"); } else if (IS_TEST_START(status)) - val_print(ACS_PRINT_INFO, "\n START", status); + val_print(INFO, "\n START", status); else if (IS_TEST_END(status)) - val_print(ACS_PRINT_INFO, " END\n\n", status); + val_print(INFO, " END\n\n", status); else - val_print(ACS_PRINT_ERR, ": Result: %8x\n", status); + val_print(INFO, ": Result: %8x\n", status); } diff --git a/val/src/acs_test_infra.c b/val/src/acs_test_infra.c index 3da5caac..a732bd30 100644 --- a/val/src/acs_test_infra.c +++ b/val/src/acs_test_infra.c @@ -24,26 +24,6 @@ uint32_t g_override_skip; -/** - @brief This API calls PAL layer to print a formatted string - to the output console. - 1. Caller - Application layer - 2. Prerequisite - None. - - @param level the print verbosity (1 to 5) - @param string formatted ASCII string - @param data 64-bit data. set to 0 if no data is to sent to console. - - @return None - **/ -void -val_print(uint32_t level, char8_t *string, uint64_t data) -{ - if (level >= g_print_level) - pal_print(string, data); -} - - /** @brief Print standardized log context prefix. 1. Caller - Application/VAL layers @@ -79,12 +59,12 @@ val_log_context(char8_t *file, char8_t *func, uint32_t line) marker++; } - val_print(ACS_PRINT_DEBUG, "\n ", 0); - val_print(ACS_PRINT_DEBUG, trimmed_file, 0); - val_print(ACS_PRINT_DEBUG, ":", 0); - val_print(ACS_PRINT_DEBUG, "%d", line); - val_print(ACS_PRINT_DEBUG, " ", 0); - val_print(ACS_PRINT_DEBUG, func, 0); + val_print(DEBUG, "\n "); + val_print(DEBUG, trimmed_file); + val_print(DEBUG, ":"); + val_print(DEBUG, "%d", line); + val_print(DEBUG, " "); + val_print(DEBUG, func); } /** @@ -119,9 +99,9 @@ void val_print_primary_pe(uint32_t level, char8_t *string, uint64_t data, uint32 void val_print_test_start(char8_t *string) { - val_print(ACS_PRINT_TEST, "\n *** Starting ", 0); - val_print(ACS_PRINT_TEST, string, 0); - val_print(ACS_PRINT_TEST, " tests ***\n", 0); + val_print(INFO, "\n *** Starting "); + val_print(INFO, string); + val_print(INFO, " tests ***\n"); } /** @@ -138,20 +118,20 @@ val_print_test_start(char8_t *string) void val_print_test_end(uint32_t status, char8_t *string) { - val_print(ACS_PRINT_TEST, "\n ", 0); + val_print(INFO, "\n "); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_TEST, "One or more ", 0); - val_print(ACS_PRINT_TEST, string, 0); - val_print(ACS_PRINT_TEST, " tests failed or were skipped.", 0); + val_print(INFO, "One or more "); + val_print(INFO, string); + val_print(INFO, " tests failed or were skipped."); } else { - val_print(ACS_PRINT_TEST, "All ", 0); - val_print(ACS_PRINT_TEST, string, 0); - val_print(ACS_PRINT_TEST, " tests passed.", 0); + val_print(INFO, "All "); + val_print(INFO, string); + val_print(INFO, " tests passed."); } - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); } @@ -166,20 +146,20 @@ val_print_test_end(uint32_t status, char8_t *string) void val_print_acs_test_status_summary(void) { - val_print(ACS_PRINT_TEST, "\n---------- ACS Summary ----------\n", 0); - val_print(ACS_PRINT_TEST, " Total Rules Run : %d\n", + val_print(INFO, "\n---------- ACS Summary ----------\n"); + val_print(INFO, " Total Rules Run : %d\n", g_rule_test_stats.total_rules_run); - val_print(ACS_PRINT_TEST, " Passed : %d\n", g_rule_test_stats.passed); - val_print(ACS_PRINT_TEST, " Passed (*Partial) : %d\n", + val_print(INFO, " Passed : %d\n", g_rule_test_stats.passed); + val_print(INFO, " Passed (*Partial) : %d\n", g_rule_test_stats.partial_coverage); - val_print(ACS_PRINT_TEST, " Warnings : %d\n", g_rule_test_stats.warnings); - val_print(ACS_PRINT_TEST, " Skipped : %d\n", g_rule_test_stats.skipped); - val_print(ACS_PRINT_TEST, " Failed : %d\n", g_rule_test_stats.failed); - val_print(ACS_PRINT_TEST, " PAL Not Supported : %d\n", + val_print(INFO, " Warnings : %d\n", g_rule_test_stats.warnings); + val_print(INFO, " Skipped : %d\n", g_rule_test_stats.skipped); + val_print(INFO, " Failed : %d\n", g_rule_test_stats.failed); + val_print(INFO, " PAL Not Supported : %d\n", g_rule_test_stats.pal_not_supported); - val_print(ACS_PRINT_TEST, " Test Not Implemented : %d\n", + val_print(INFO, " Test Not Implemented : %d\n", g_rule_test_stats.not_implemented); - val_print(ACS_PRINT_TEST, "---------------------------------\n", 0); + val_print(INFO, "---------------------------------\n"); /* Reset global rule/test status counters after printing summary */ g_rule_test_stats.total_rules_run = 0; @@ -458,8 +438,8 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe) g_override_skip = 1; - val_print(ACS_PRINT_ERR, "%4d : ", test_num); //Always print this - val_print(ACS_PRINT_TEST, desc, 0); + val_print(INFO, "%4d : ", test_num); //Always print this + val_print(INFO, desc); val_report_status(0, ACS_START(test_num), NULL); val_pe_initialize_default_exception_handler(val_pe_default_esr); @@ -535,7 +515,7 @@ val_set_test_data(uint32_t index, uint64_t addr, uint64_t test_data) if(index > val_pe_get_num()) { - val_print(ACS_PRINT_ERR, "\n Incorrect PE index = %d", index); + val_print(ERROR, "\n Incorrect PE index = %d", index); return; } @@ -570,7 +550,7 @@ val_get_test_data(uint32_t index, uint64_t *data0, uint64_t *data1) if(index > val_pe_get_num()) { - val_print(ACS_PRINT_ERR, "\n Incorrect PE index = %d", index); + val_print(ERROR, "\n Incorrect PE index = %d", index); return; } @@ -719,7 +699,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid) for (i = 0; i < num_pe; i++) { status = val_get_status(i); - //val_print(ACS_PRINT_ERR, "Status %4x\n", status); + //val_print(ERROR, "Status %4x\n", status); if (IS_TEST_FAIL_SKIP(status)) { val_report_status(i, status, ruleid); error_flag += 1; @@ -774,9 +754,9 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid) } } if (overall_status == TEST_FAIL) { - val_print(ACS_PRINT_ERR, "\n Failed at checkpoint - %2d", checkpoint); + val_print(ERROR, "\n Failed at checkpoint - %2d", checkpoint); } else if (overall_status == TEST_SKIP) { - val_print(ACS_PRINT_ERR, "\n Skipped at checkpoint - %2d", checkpoint); + val_print(ERROR, "\n Skipped at checkpoint - %2d", checkpoint); } return overall_status; @@ -941,9 +921,9 @@ val_check_for_prerequisite(uint32_t num_pe, uint32_t prereq_status, if (prereq_status != (uint32_t)ACS_STATUS_PASS) { /* Do not execute the current test if the prerequisite rule results in FAIL or SKIP */ - val_print(ACS_PRINT_ERR, "\n Pre-requisite rule ", 0); - val_print(ACS_PRINT_ERR, prereq_config->rule, 0); - val_print(ACS_PRINT_ERR, " did not pass. Skipping the test", 0); + val_print(ERROR, "\n Pre-requisite rule "); + val_print(ERROR, prereq_config->rule); + val_print(ERROR, " did not pass. Skipping the test"); val_set_status(index, RESULT_SKIP(curr_config->test_num, 0)); return ACS_STATUS_SKIP; } diff --git a/val/src/acs_timer.c b/val/src/acs_timer.c index 9473b21d..1cf0c4f5 100644 --- a/val/src/acs_timer.c +++ b/val/src/acs_timer.c @@ -235,10 +235,10 @@ val_timer_create_info_table(uint64_t *timer_info_table) uint64_t freq_mhz; if (timer_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating TIMER INFO table\n", 0); + val_print(TRACE, " Creating TIMER INFO table\n"); g_timer_info_table = (TIMER_INFO_TABLE *)timer_info_table; @@ -257,13 +257,13 @@ val_timer_create_info_table(uint64_t *timer_info_table) freq_mhz = freq_mhz/1000; if (freq_mhz > 1000) { freq_mhz = freq_mhz/1000; - val_print(ACS_PRINT_TEST, " TIMER_INFO: System Counter frequency : %ld MHz\n", freq_mhz); + val_print(INFO, " TIMER_INFO: System Counter frequency : %ld MHz\n", freq_mhz); } else { - val_print(ACS_PRINT_TEST, " TIMER_INFO: System Counter frequency : %ld KHz\n", freq_mhz); + val_print(INFO, " TIMER_INFO: System Counter frequency : %ld KHz\n", freq_mhz); } } - val_print(ACS_PRINT_TEST, " TIMER_INFO: Number of system timers : %4d\n", + val_print(INFO, " TIMER_INFO: Number of system timers : %4d\n", g_timer_info_table->header.num_platform_timer); timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); @@ -276,13 +276,13 @@ val_timer_create_info_table(uint64_t *timer_info_table) gt_entry = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, timer_num); timer_entry = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - val_print(ACS_PRINT_DEBUG, " Add entry %lx entry in memmap", gt_entry); + val_print(DEBUG, " Add entry %lx entry in memmap", gt_entry); if (val_mmu_update_entry(gt_entry, 0x10000, DEVICE_nGnRnE)) - val_print(ACS_PRINT_WARN, "\n Adding %lx entry failed", gt_entry); + val_print(WARN, "\n Adding %lx entry failed", gt_entry); - val_print(ACS_PRINT_DEBUG, "\n Add entry %lx entry in memmap", timer_entry); + val_print(DEBUG, "\n Add entry %lx entry in memmap", timer_entry); if (val_mmu_update_entry(timer_entry, 0x10000, DEVICE_nGnRnE)) - val_print(ACS_PRINT_WARN, "\n Adding %lx entry failed", timer_entry); + val_print(WARN, "\n Adding %lx entry failed", timer_entry); } } @@ -301,7 +301,7 @@ val_timer_free_info_table(void) g_timer_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, + val_print(DEBUG, "\n g_timer_info_table pointer is already NULL", 0); } } diff --git a/val/src/acs_timer_support.c b/val/src/acs_timer_support.c index 95e60c04..b7db6467 100644 --- a/val/src/acs_timer_support.c +++ b/val/src/acs_timer_support.c @@ -29,7 +29,7 @@ uint8_t get_effective_e2h(void) /* if EL2 is not present, effective E2H will be 0 */ if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - val_print(ACS_PRINT_DEBUG, "\n CurrentEL: AARCH64_EL1", 0); + val_print(DEBUG, "\n CurrentEL: AARCH64_EL1"); return 0; } @@ -37,9 +37,9 @@ uint8_t get_effective_e2h(void) uint32_t feat_vhe = VAL_EXTRACT_BITS(read_id_aa64mmfr1_el1(), 8, 11); uint32_t e2h0 = VAL_EXTRACT_BITS(read_s3_0_c0_c7_4(), 24, 27); - val_print(ACS_PRINT_DEBUG, "\n hcr_e2h : 0x%x", hcr_e2h); - val_print(ACS_PRINT_DEBUG, "\n feat_vhe : 0x%x", feat_vhe); - val_print(ACS_PRINT_DEBUG, "\n e2h0 : 0x%x", e2h0); + val_print(DEBUG, "\n hcr_e2h : 0x%x", hcr_e2h); + val_print(DEBUG, "\n feat_vhe : 0x%x", feat_vhe); + val_print(DEBUG, "\n e2h0 : 0x%x", e2h0); if (feat_vhe == 0x0) //ID_AA64MMFR1_EL1.VH effective_e2h = 0; @@ -48,7 +48,7 @@ uint8_t get_effective_e2h(void) else effective_e2h = hcr_e2h; - val_print(ACS_PRINT_DEBUG, "\n effective e2h : 0x%x\n", effective_e2h); + val_print(DEBUG, "\n effective e2h : 0x%x\n", effective_e2h); return effective_e2h; } @@ -121,12 +121,12 @@ ArmArchTimerReadReg ( case CnthCtl: case CnthpCval: - val_print(ACS_PRINT_TEST, "The register is related to Hypervisor Mode. \ - Can't perform requested operation\n ", 0); + val_print(INFO, "The register is related to Hypervisor Mode. \ + Can't perform requested operation\n "); break; default: - val_print(ACS_PRINT_TEST, "Unknown ARM Generic Timer register %x.\n ", Reg); + val_print(INFO, "Unknown ARM Generic Timer register %x.\n ", Reg); } return 0xFFFFFFFF; @@ -154,7 +154,7 @@ ArmArchTimerWriteReg ( switch(Reg) { case CntPct: - val_print(ACS_PRINT_TEST, "Can't write to Read Only Register: CNTPCT\n", 0); + val_print(INFO, "Can't write to Read Only Register: CNTPCT\n"); break; case CntkCtl: @@ -193,7 +193,7 @@ ArmArchTimerWriteReg ( break; case CntvCt: - val_print(ACS_PRINT_TEST, "Can't write to Read Only Register: CNTVCT\n", 0); + val_print(INFO, "Can't write to Read Only Register: CNTVCT\n"); break; case CntpCval: @@ -222,11 +222,11 @@ ArmArchTimerWriteReg ( break; case CnthCtl: case CnthpCval: - val_print(ACS_PRINT_TEST, "The register is related to Hypervisor Mode. \ - Can't perform requested operation\n", 0); + val_print(INFO, "The register is related to Hypervisor Mode. \ + Can't perform requested operation\n"); break; default: - val_print(ACS_PRINT_TEST, "Unknown ARM Generic Timer register %x.\n ", Reg); + val_print(INFO, "Unknown ARM Generic Timer register %x.\n ", Reg); } } diff --git a/val/src/acs_tpm.c b/val/src/acs_tpm.c index 193f0323..e61baf12 100644 --- a/val/src/acs_tpm.c +++ b/val/src/acs_tpm.c @@ -52,7 +52,7 @@ val_tpm2_get_info(TPM2_INFO_e info_type) case TPM2_INFO_INTERFACE_TYPE: return g_tpm2_info_table->tpm_interface; default: - val_print(ACS_PRINT_ERR, " Invalid TPM2 info_type: %d\n", info_type); + val_print(ERROR, " Invalid TPM2 info_type: %d\n", info_type); return TPM2_INFO_INVALID; } @@ -71,10 +71,10 @@ void val_tpm2_create_info_table(uint64_t *tpm2_info_table) { if (tpm2_info_table == NULL) { - val_print(ACS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL\n", 0); + val_print(ERROR, "\n Pre-allocated memory pointer is NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating TPM2 INFO table\n", 0); + val_print(TRACE, " Creating TPM2 INFO table\n"); g_tpm2_info_table = (TPM2_INFO_TABLE *)tpm2_info_table; @@ -107,9 +107,8 @@ val_tpm2_free_info_table(void) g_tpm2_info_table = NULL; } else { - val_print(ACS_PRINT_ERR, - "\n WARNING: g_tpm2_info_table pointer is already NULL", - 0); + val_print(ERROR, + "\n WARNING: g_tpm2_info_table pointer is already NULL"); } } diff --git a/val/src/acs_wakeup.c b/val/src/acs_wakeup.c index a30678af..376dcbde 100644 --- a/val/src/acs_wakeup.c +++ b/val/src/acs_wakeup.c @@ -40,7 +40,7 @@ static uint32_t val_get_psci_ver(void) pal_pe_call_smc(&smc_args, gPsciConduit); - val_print(ACS_PRINT_DEBUG, "\n PSCI VERSION = %X", smc_args.Arg0); + val_print(DEBUG, "\n PSCI VERSION = %X", smc_args.Arg0); return smc_args.Arg0; } @@ -61,7 +61,7 @@ static uint32_t val_get_psci_features(uint64_t psci_func_id) pal_pe_call_smc(&smc_args, gPsciConduit); - val_print(ACS_PRINT_DEBUG, "\n PSCI FEATURS = %d", smc_args.Arg0); + val_print(DEBUG, "\n PSCI FEATURS = %d", smc_args.Arg0); return smc_args.Arg0; } @@ -81,12 +81,12 @@ val_suspend_pe(uint64_t entry, uint32_t context_id) uint32_t power_state; psci_major_ver = (val_get_psci_ver() >> 16); - val_print(ACS_PRINT_DEBUG, "\n PSCI MAJOR VERSION = %X", psci_major_ver); + val_print(DEBUG, "\n PSCI MAJOR VERSION = %X", psci_major_ver); if (psci_major_ver < 1) power_state = 0; else { pwr_state_fmt = (val_get_psci_features(ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64) >> 1); - val_print(ACS_PRINT_DEBUG, "\n PSCI PWR_STATE_FMT = %d ", + val_print(DEBUG, "\n PSCI PWR_STATE_FMT = %d ", pwr_state_fmt); if (pwr_state_fmt == ARM_SMC_ID_PSCI_POWER_STATE_FMT_ORIGINAL) power_state = 0; diff --git a/val/src/acs_wd.c b/val/src/acs_wd.c index a6c05f54..d9ef5f7e 100644 --- a/val/src/acs_wd.c +++ b/val/src/acs_wd.c @@ -70,16 +70,16 @@ val_wd_create_info_table(uint64_t *wd_info_table) { if (wd_info_table == NULL) { - val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL\n", 0); + val_print(ERROR, "Input for Create Info table cannot be NULL\n"); return; } - val_print(ACS_PRINT_INFO, " Creating WATCHDOG INFO table\n", 0); + val_print(TRACE, " Creating WATCHDOG INFO table\n"); g_wd_info_table = (WD_INFO_TABLE *)wd_info_table; pal_wd_create_info_table(g_wd_info_table); - val_print(ACS_PRINT_TEST, " WATCHDOG_INFO: Number of Watchdogs : %4d\n", + val_print(INFO, " WATCHDOG_INFO: Number of Watchdogs : %4d\n", val_wd_get_info(0, WD_INFO_COUNT)); } @@ -98,8 +98,8 @@ val_wd_free_info_table(void) g_wd_info_table = NULL; } else { - val_print(ACS_PRINT_DEBUG, - "\n g_wd_info_table pointer is already NULL", 0); + val_print(DEBUG, + "\n g_wd_info_table pointer is already NULL"); } } diff --git a/val/src/bsa_execute_test.c b/val/src/bsa_execute_test.c index 1f34528d..0a92a2a1 100644 --- a/val/src/bsa_execute_test.c +++ b/val/src/bsa_execute_test.c @@ -66,13 +66,13 @@ void view_print_info(uint32_t view) switch (view) { case OPERATING_SYSTEM: - val_print(ACS_PRINT_ERR, "\nOperating System View:\n", 0); + val_print(ERROR, "\nOperating System View:\n"); break; case HYPERVISOR: - val_print(ACS_PRINT_ERR, "\nHypervisor View:\n", 0); + val_print(ERROR, "\nHypervisor View:\n"); break; case PLATFORM_SECURITY: - val_print(ACS_PRINT_ERR, "\nPlatform Security View:\n", 0); + val_print(ERROR, "\nPlatform Security View:\n"); break; } @@ -100,7 +100,7 @@ val_bsa_pe_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } } @@ -108,7 +108,7 @@ val_bsa_pe_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_PE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } @@ -191,7 +191,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_GIC_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } } @@ -199,7 +199,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_GIC_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } @@ -252,13 +252,13 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if ((gic_version != 2) || (num_msi_frame == 0)) { - val_print(ACS_PRINT_INFO, "\n No GICv2m, Skipping all GICv2m tests\n", 0); + val_print(TRACE, "\n No GICv2m, Skipping all GICv2m tests\n"); goto its_test; } if (val_gic_v2m_parse_info()) { - val_print(ACS_PRINT_INFO, - "\n GICv2m info mismatch, Skipping all GICv2m tests\n", 0); + val_print(TRACE, + "\n GICv2m info mismatch, Skipping all GICv2m tests\n"); goto its_test; } @@ -274,7 +274,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) its_test: if ((val_gic_get_info(GIC_INFO_NUM_ITS) == 0) || (pal_target_is_dt())) { - val_print(ACS_PRINT_DEBUG, "\n No ITS, Skipping all DeviceID & ITS tests\n", 0); + val_print(DEBUG, "\n No ITS, Skipping all DeviceID & ITS tests\n"); goto test_done; } @@ -315,7 +315,7 @@ val_bsa_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_TIMER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Timer tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Timer tests\n"); return ACS_STATUS_SKIP; } } @@ -323,7 +323,7 @@ val_bsa_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_TIMER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Timer tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Timer tests\n"); return ACS_STATUS_SKIP; } @@ -369,7 +369,7 @@ val_bsa_wd_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_WD_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } } @@ -377,14 +377,14 @@ val_bsa_wd_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_WD_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } if (!g_build_sbsa) { /* For SBSA compliance WD is mandatory */ if (val_wd_get_info(0, WD_INFO_COUNT) == 0) { - val_print(ACS_PRINT_WARN, "\n No Watchdog Found, Skipping Watchdog " - "tests...\n", 0); + val_print(WARN, "\n No Watchdog Found, Skipping Watchdog " + "tests...\n"); return ACS_STATUS_SKIP; } } @@ -431,7 +431,7 @@ val_bsa_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PCIE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } } @@ -447,19 +447,19 @@ val_bsa_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Skip the module only if no tests from PCIe module and extended PCIe module are run */ if (skip_status > 1) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } if (pcie_bdf_table_list_flag == 1) { - val_print(ACS_PRINT_WARN, "\n *** Created device list with valid bdf doesn't match \ - with the platform pcie device hierarchy, Skipping PCIE tests ***\n", 0); + val_print(WARN, "\n *** Created device list with valid bdf doesn't match \ + with the platform pcie device hierarchy, Skipping PCIE tests ***\n"); return ACS_STATUS_SKIP; } num_ecam = (uint32_t)val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (!num_ecam) { - val_print(ACS_PRINT_WARN, "\n *** No ECAM region found, Skipping PCIE tests ***\n", 0); + val_print(WARN, "\n *** No ECAM region found, Skipping PCIE tests ***\n"); return ACS_STATUS_SKIP; } @@ -473,22 +473,20 @@ val_bsa_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) status |= p001_entry(num_pe); if (status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_WARN, "\n *** Skipping remaining PCIE tests ***\n", 0); + val_print(WARN, "\n *** Skipping remaining PCIE tests ***\n"); return status; } } if (g_pcie_bdf_table->num_entries == 0) { - val_print(ACS_PRINT_WARN, - "\n No PCIe Devices Found, Skipping PCIe tests...\n", - 0); + val_print(WARN, + "\n No PCIe Devices Found, Skipping PCIe tests...\n"); return ACS_STATUS_SKIP; } if (g_pcie_bdf_table->num_entries == g_pcie_integrated_devices) { - val_print(ACS_PRINT_WARN, - "\n Only integrated PCIe Devices Found, Skipping PCIe tests...\n", - 0); + val_print(WARN, + "\n Only integrated PCIe Devices Found, Skipping PCIe tests...\n"); return ACS_STATUS_SKIP; } @@ -578,7 +576,7 @@ val_bsa_peripheral_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Peripheral tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Peripheral tests\n"); return ACS_STATUS_SKIP; } } @@ -586,7 +584,7 @@ val_bsa_peripheral_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_PER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Peripheral tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Peripheral tests\n"); return ACS_STATUS_SKIP; } @@ -639,7 +637,7 @@ val_bsa_memory_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MEMORY_MAP_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Memory tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Memory tests\n"); return ACS_STATUS_SKIP; } } @@ -647,7 +645,7 @@ val_bsa_memory_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_MEMORY_MAP_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Memory tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Memory tests\n"); return ACS_STATUS_SKIP; } @@ -701,7 +699,7 @@ val_bsa_wakeup_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_WAKEUP_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Wakeup tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Wakeup tests\n"); return ACS_STATUS_SKIP; } } @@ -709,7 +707,7 @@ val_bsa_wakeup_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_WAKEUP_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Wakeup tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Wakeup tests\n"); return ACS_STATUS_SKIP; } @@ -763,7 +761,7 @@ val_bsa_smmu_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_SMMU_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } } @@ -771,13 +769,13 @@ val_bsa_smmu_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_SMMU_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { - val_print(ACS_PRINT_WARN, "\n No SMMU Controller Found, Skipping SMMU tests...\n", 0); + val_print(WARN, "\n No SMMU Controller Found, Skipping SMMU tests...\n"); return ACS_STATUS_SKIP; } @@ -835,7 +833,7 @@ val_bsa_exerciser_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_EXERCISER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Exerciser tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Exerciser tests\n"); return ACS_STATUS_SKIP; } } @@ -843,25 +841,25 @@ val_bsa_exerciser_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_EXERCISER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Exerciser tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Exerciser tests\n"); return ACS_STATUS_SKIP; } /* Create the list of valid Pcie Device Functions */ if (val_exerciser_create_info_table()) { - val_print(ACS_PRINT_WARN, "\n Create BDF Table Failed, Skipping Exerciser tests...\n", 0); + val_print(WARN, "\n Create BDF Table Failed, Skipping Exerciser tests...\n"); return ACS_STATUS_SKIP; } num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS); if (num_instances == 0) { - val_print(ACS_PRINT_WARN, "\n No Exerciser Devices Found, " - "Skipping tests...\n", 0); + val_print(WARN, "\n No Exerciser Devices Found, " + "Skipping tests...\n"); return ACS_STATUS_SKIP; } - val_print(ACS_PRINT_INFO, " Initializing SMMU\n", 0); + val_print(TRACE, " Initializing SMMU\n"); num_smmu = (uint32_t)val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); val_smmu_init(); @@ -871,7 +869,7 @@ val_bsa_exerciser_execute_tests(uint32_t num_pe, uint32_t *g_sw_view) val_smmu_disable(instance); if (g_its_init != 1) { - val_print(ACS_PRINT_INFO, "\n Initializing ITS\n", 0); + val_print(TRACE, "\n Initializing ITS\n"); val_gic_its_configure(); g_its_init = 1; } diff --git a/val/src/drtm_execute_test.c b/val/src/drtm_execute_test.c index 9f4db873..58b64eaf 100644 --- a/val/src/drtm_execute_test.c +++ b/val/src/drtm_execute_test.c @@ -40,7 +40,7 @@ val_drtm_execute_interface_tests(uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_DRTM_INTERFACE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Interface tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Interface tests\n"); return ACS_STATUS_SKIP; } } @@ -48,12 +48,12 @@ val_drtm_execute_interface_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_DRTM_INTERFACE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Interface tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Interface tests\n"); return ACS_STATUS_SKIP; } - val_print(ACS_PRINT_INFO, " Initializing ITS\n", 0); + val_print(TRACE, " Initializing ITS\n"); val_gic_its_configure(); status = ACS_STATUS_PASS; @@ -99,7 +99,7 @@ val_drtm_execute_dl_tests(uint32_t num_pe) num_pe = 1; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_DRTM_DL_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all DL tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all DL tests\n"); return ACS_STATUS_SKIP; } } @@ -107,7 +107,7 @@ val_drtm_execute_dl_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_DRTM_DL_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all DL tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all DL tests\n"); return ACS_STATUS_SKIP; } @@ -115,18 +115,18 @@ val_drtm_execute_dl_tests(uint32_t num_pe) * Less than zero are error case */ if (g_drtm_features.dynamic_launch < DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM query Dynamic Launch feature failed err=%d", status); - val_print(ACS_PRINT_WARN, "\n *** Skipping remaining DL tests ***\n", 0); + val_print(WARN, "\n *** Skipping remaining DL tests ***\n"); return ACS_STATUS_FAIL; } /* Check Min Memory req supported to run this test using drtm features command * Less than or equal to zero are error case */ if (g_drtm_features.min_memory_req.status <= DRTM_ACS_SUCCESS) { - val_print(ACS_PRINT_ERR, + val_print(ERROR, "\n DRTM query Min memory req feature failed err=%d", status); - val_print(ACS_PRINT_WARN, "\n *** Skipping remaining DL tests ***\n", 0); + val_print(WARN, "\n *** Skipping remaining DL tests ***\n"); return ACS_STATUS_FAIL; } diff --git a/val/src/mpam_execute_test.c b/val/src/mpam_execute_test.c index 69a415e2..4e07c5bd 100644 --- a/val/src/mpam_execute_test.c +++ b/val/src/mpam_execute_test.c @@ -40,7 +40,7 @@ val_mpam_execute_error_tests(uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MPAM_ERROR_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all ERROR tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all ERROR tests\n"); return ACS_STATUS_SKIP; } } @@ -48,7 +48,7 @@ val_mpam_execute_error_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_MPAM_ERROR_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all ERROR tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all ERROR tests\n"); return ACS_STATUS_SKIP; } @@ -78,9 +78,9 @@ val_mpam_execute_error_tests(uint32_t num_pe) /* Setup ITS for MSI Tests */ if (g_its_init != 1) { - val_print(ACS_PRINT_INFO, "\n Initializing ITS\n", 0); + val_print(TRACE, "\n Initializing ITS\n"); if (val_gic_its_configure() == ACS_STATUS_ERR) { - val_print(ACS_PRINT_ERR, "\n val_gic_its_configure() failed \n", 0); + val_print(ERROR, "\n val_gic_its_configure() failed \n"); status = ACS_STATUS_SKIP; return status; } @@ -115,8 +115,8 @@ val_mpam_execute_membw_tests(uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MPAM_MEMORY_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, - "\n USER Override - Skipping all Memory Bandwidth tests\n", 0); + val_print(TRACE, + "\n USER Override - Skipping all Memory Bandwidth tests\n"); return ACS_STATUS_SKIP; } } @@ -124,8 +124,8 @@ val_mpam_execute_membw_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_MPAM_MEMORY_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, - "\n USER Override - Skipping all Memory Bandwidth tests\n", 0); + val_print(TRACE, + "\n USER Override - Skipping all Memory Bandwidth tests\n"); return ACS_STATUS_SKIP; } @@ -164,7 +164,7 @@ val_mpam_execute_register_tests(uint32_t num_pe) num_pe = 1; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MPAM_REGISTER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Register tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Register tests\n"); return ACS_STATUS_SKIP; } } @@ -172,7 +172,7 @@ val_mpam_execute_register_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_MPAM_REGISTER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Register tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Register tests\n"); return ACS_STATUS_SKIP; } @@ -210,7 +210,7 @@ val_mpam_execute_cache_tests(uint32_t num_pe) num_pe = 1; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MPAM_CACHE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all CACHE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all CACHE tests\n"); return ACS_STATUS_SKIP; } } @@ -218,7 +218,7 @@ val_mpam_execute_cache_tests(uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_MPAM_CACHE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all CACHE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all CACHE tests\n"); return ACS_STATUS_SKIP; } diff --git a/val/src/pc_bsa_execute_test.c b/val/src/pc_bsa_execute_test.c index c6e1fe73..9ab2ed9f 100644 --- a/val/src/pc_bsa_execute_test.c +++ b/val/src/pc_bsa_execute_test.c @@ -51,7 +51,7 @@ val_pcbsa_pe_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } } @@ -59,7 +59,7 @@ val_pcbsa_pe_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_PE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } @@ -102,7 +102,7 @@ val_pcbsa_gic_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_GIC_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } } @@ -110,14 +110,14 @@ val_pcbsa_gic_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ module_skip = val_check_skip_module(ACS_GIC_TEST_NUM_BASE); if (module_skip) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } val_print_test_start("GIC"); g_curr_module = 1 << GIC_MODULE; - val_print(ACS_PRINT_INFO, " Initializing ITS\n", 0); + val_print(TRACE, " Initializing ITS\n"); val_gic_its_configure(); if (((level >= 1) && (g_pcbsa_only_level == 0)) || (g_pcbsa_only_level == 1)) { @@ -153,7 +153,7 @@ val_pcbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_SMMU_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } } @@ -161,7 +161,7 @@ val_pcbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_SMMU_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } @@ -173,8 +173,8 @@ val_pcbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) status |= i025_entry(num_pe); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_WARN, "\n SMMU Compatibility Check Failed, ", 0); - val_print(ACS_PRINT_WARN, "Skipping SMMU tests...\n", 0); + val_print(WARN, "\n SMMU Compatibility Check Failed, "); + val_print(WARN, "Skipping SMMU tests...\n"); val_print_test_end(status, "SMMU"); return ACS_STATUS_FAIL; } @@ -206,7 +206,7 @@ val_pcbsa_memory_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0 ; i < g_num_skip ; i++) { if (g_skip_test_num[i] == ACS_MEMORY_MAP_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all memory tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all memory tests\n"); return ACS_STATUS_SKIP; } } @@ -214,7 +214,7 @@ val_pcbsa_memory_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in the current module with user override*/ status = val_check_skip_module(ACS_MEMORY_MAP_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all memory tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all memory tests\n"); return ACS_STATUS_SKIP; } @@ -249,7 +249,7 @@ val_pcbsa_wd_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_WD_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, " USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } } @@ -257,7 +257,7 @@ val_pcbsa_wd_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_WD_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } @@ -293,7 +293,7 @@ val_pcbsa_tpm2_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_TPM2_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all TPM2 tests\n", 0); + val_print(TRACE, " USER Override - Skipping all TPM2 tests\n"); return ACS_STATUS_SKIP; } } @@ -301,7 +301,7 @@ val_pcbsa_tpm2_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_TPM2_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all TPM2 tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all TPM2 tests\n"); return ACS_STATUS_SKIP; } @@ -338,7 +338,7 @@ val_pcbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PCIE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } } @@ -346,13 +346,13 @@ val_pcbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_PCIE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } if (pcie_bdf_table_list_flag == 1) { - val_print(ACS_PRINT_WARN, "\n *** Created device list with valid bdf doesn't match \ - with the platform pcie device hierarchy, Skipping PCIE tests ***\n", 0); + val_print(WARN, "\n *** Created device list with valid bdf doesn't match \ + with the platform pcie device hierarchy, Skipping PCIE tests ***\n"); return ACS_STATUS_SKIP; } @@ -367,7 +367,7 @@ val_pcbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) ecam_status = p001_entry(num_pe); status |= ecam_status; if (ecam_status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_WARN, "\n *** Skipping remaining PCIE tests ***\n", 0); + val_print(WARN, "\n *** Skipping remaining PCIE tests ***\n"); val_print_test_end(status, "PCIe"); return status; } diff --git a/val/src/rule_based_execution_helpers.c b/val/src/rule_based_execution_helpers.c index 007f353b..7b805185 100644 --- a/val/src/rule_based_execution_helpers.c +++ b/val/src/rule_based_execution_helpers.c @@ -150,42 +150,42 @@ print_rule_test_start(uint32_t rule_enum, uint32_t indent) /* Print "Running tests" if module change seen. Don't print if MODULE_UNKNOWN was encounterd */ if (prev_module != curr_module && curr_module != MODULE_UNKNOWN) { - val_print(ACS_PRINT_TEST, "\n\n ", 0); + val_print(INFO, "\n\n "); if (indent) - val_print(ACS_PRINT_TEST, " ", 0); - val_print(ACS_PRINT_TEST, "*** Running ", 0); - val_print(ACS_PRINT_TEST, module_name_string[curr_module], 0); - val_print(ACS_PRINT_TEST, " tests ***", 0); + val_print(INFO, " "); + val_print(INFO, "*** Running "); + val_print(INFO, module_name_string[curr_module]); + val_print(INFO, " tests ***"); /* Update prev_module for next call */ prev_module = curr_module; } - val_print(ACS_PRINT_TEST, "\n\n", 0); + val_print(INFO, "\n\n"); /* Print indent spaces */ while (indent) { - val_print(ACS_PRINT_TEST, " ", 0); + val_print(INFO, " "); indent--; } /* Print rule id */ - val_print(ACS_PRINT_TEST, rule_id_string[rule_enum], 0); + val_print(INFO, rule_id_string[rule_enum]); /* TODO Note: Test ID print would be deprecated in future, please use rule id as primary key to identify tests and comment on coverage */ - val_print(ACS_PRINT_TEST, " : ", 0); + val_print(INFO, " : "); if (rule_test_map[rule_enum].test_num == INVALID_ENTRY) { - val_print(ACS_PRINT_TEST, "-", 0); + val_print(INFO, "-"); } else { - val_print(ACS_PRINT_TEST, "%d", rule_test_map[rule_enum].test_num); + val_print(INFO, "%d", rule_test_map[rule_enum].test_num); } - val_print(ACS_PRINT_TEST, " : ", 0); + val_print(INFO, " : "); /* Print rule description */ if (rule_test_map[rule_enum].flag != INVALID_ENTRY) { - val_print(ACS_PRINT_TEST, rule_test_map[rule_enum].rule_desc, 0); + val_print(INFO, rule_test_map[rule_enum].rule_desc); } } @@ -212,25 +212,25 @@ print_pal_validation_info(uint32_t rule_enum, uint32_t indent) return; for (i = 0; i < indent; i++) - val_print(ACS_PRINT_TEST, " ", 0); + val_print(INFO, " "); - val_print(ACS_PRINT_TEST, " Rule is validated by ", 0); + val_print(INFO, " Rule is validated by "); if (other_pals & PLATFORM_BAREMETAL) { - val_print(ACS_PRINT_TEST, "Baremetal", 0); + val_print(INFO, "Baremetal"); first = 0; } if (other_pals & PLATFORM_UEFI) { - if (!first) val_print(ACS_PRINT_TEST, "/", 0); - val_print(ACS_PRINT_TEST, "UEFI", 0); + if (!first) val_print(INFO, "/"); + val_print(INFO, "UEFI"); first = 0; } if (other_pals & PLATFORM_LINUX) { - if (!first) val_print(ACS_PRINT_TEST, "/", 0); - val_print(ACS_PRINT_TEST, "Linux", 0); + if (!first) val_print(INFO, "/"); + val_print(INFO, "Linux"); } - val_print(ACS_PRINT_TEST, " test\n", 0); + val_print(INFO, " test\n"); } /** @@ -251,19 +251,19 @@ print_rule_test_status(uint32_t rule_enum, uint32_t indent, uint32_t status) /* Only count top-level rules (indent == 0) */ uint32_t top_level_rule = (indent == 0); - val_print(ACS_PRINT_TEST, "\n", 0); + val_print(INFO, "\n"); /* Print other PAL(s) that validate this rule */ if (status == TEST_PAL_NS) { print_pal_validation_info(rule_enum, indent); } /* Print indent spaces */ while (indent) { - val_print(ACS_PRINT_TEST, " ", 0); + val_print(INFO, " "); indent--; } - val_print(ACS_PRINT_TEST, " Result: ", 0); - val_print(ACS_PRINT_TEST, " ", 0); + val_print(INFO, " Result: "); + val_print(INFO, " "); /* Update global counters for top-level rules only */ if (top_level_rule) { @@ -272,35 +272,35 @@ print_rule_test_status(uint32_t rule_enum, uint32_t indent, uint32_t status) switch (status) { case TEST_PASS: - val_print(ACS_PRINT_TEST, "PASSED", 0); + val_print(INFO, "PASSED"); if (top_level_rule) g_rule_test_stats.passed++; break; case TEST_PART_COV: - val_print(ACS_PRINT_TEST, "PASSED(*PARTIAL)", 0); + val_print(INFO, "PASSED(*PARTIAL)"); if (top_level_rule) g_rule_test_stats.partial_coverage++; break; case TEST_WARN: - val_print(ACS_PRINT_TEST, "WARNING", 0); + val_print(INFO, "WARNING"); if (top_level_rule) g_rule_test_stats.warnings++; break; case TEST_SKIP: - val_print(ACS_PRINT_TEST, "SKIPPED", 0); + val_print(INFO, "SKIPPED"); if (top_level_rule) g_rule_test_stats.skipped++; break; case TEST_FAIL: - val_print(ACS_PRINT_TEST, "FAILED", 0); + val_print(INFO, "FAILED"); if (top_level_rule) g_rule_test_stats.failed++; break; case TEST_NO_IMP: - val_print(ACS_PRINT_TEST, "NOT TESTED (TEST NOT IMPLEMENTED)", 0); + val_print(INFO, "NOT TESTED (TEST NOT IMPLEMENTED)"); if (top_level_rule) g_rule_test_stats.not_implemented++; break; case TEST_PAL_NS: - val_print(ACS_PRINT_TEST, "NOT TESTED (PAL NOT SUPPORTED)", 0); + val_print(INFO, "NOT TESTED (PAL NOT SUPPORTED)"); if (top_level_rule) g_rule_test_stats.pal_not_supported++; break; default: - val_print(ACS_PRINT_TEST, "STATUS:0x%x", status); + val_print(INFO, "STATUS:0x%x", status); } return; } diff --git a/val/src/rule_based_orchestrator.c b/val/src/rule_based_orchestrator.c index a8a41612..65186453 100644 --- a/val/src/rule_based_orchestrator.c +++ b/val/src/rule_based_orchestrator.c @@ -49,7 +49,7 @@ static uint32_t check_rule_support(RULE_ID_e rule_id) { uint8_t plat_bitmask = rule_test_map[rule_id].platform_bitmask; - // val_print(ACS_PRINT_ERR, "\n plat_bitmask %x", plat_bitmask); + // val_print(ERROR, "\n plat_bitmask %x", plat_bitmask); if (!(g_current_pal & plat_bitmask)) { /* Report if rule is not supported by ACS across all available PALs*/ @@ -421,7 +421,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) RULE_ID_e base_rule_id; RULE_ID_e *base_rule_list; - val_print(ACS_PRINT_ERR, "\n---------------------- Running tests ------------------------", 0); + val_print(INFO, "\n---------------------- Running tests ------------------------"); /* Initialize per-rule status map to TEST_STATUS_UNKNOWN for this run */ rule_status_map_reset(); @@ -435,9 +435,9 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) for (i = 0 ; i < list_size; i++) { /* Invalid rule_test_map entry check */ // if (rule_test_map[rule_list[i]].flag == INVALID_ENTRY) { - // val_print(ACS_PRINT_ERR, "\n", 0); - // val_print(ACS_PRINT_ERR, rule_id_string[rule_list[i]], 0); - // val_print(ACS_PRINT_ERR, " has invalid rule_test_map[] entry.", 0); + // val_print(ERROR, "\n"); + // val_print(ERROR, rule_id_string[rule_list[i]]); + // val_print(ERROR, " has invalid rule_test_map[] entry."); // continue; // } @@ -470,7 +470,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) /* Validate lookup result before dereferencing the map */ if (alias_rule_map_index == INVALID_IDX) { - val_print(ACS_PRINT_ERR, " alias map index not found for rule id: 0x%x", + val_print(ERROR, " alias map index not found for rule id: 0x%x", rule_list[i]); /* Skip executing base rules for an unknown alias */ continue; @@ -502,9 +502,9 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) base_rule_list = alias_rule_map[alias_rule_map_index].base_rule_list; /* Print start header for alias rule */ - val_print(ACS_PRINT_TEST, "\n\n === Start tests for rules referenced by ", 0); - val_print(ACS_PRINT_TEST, rule_id_string[rule_list[i]], 0); - val_print(ACS_PRINT_TEST, " ===", 0); + val_print(INFO, "\n\n === Start tests for rules referenced by "); + val_print(INFO, rule_id_string[rule_list[i]]); + val_print(INFO, " ==="); /* Run the base rules required by the alias; list is sentinel-terminated */ for (j = 0; base_rule_list[j] != RULE_ID_SENTINEL; j++) { @@ -545,7 +545,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) } else { - val_print(ACS_PRINT_ERR, "\n\n Rule failed due to NULL entry \n\r ", 0); + val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r "); base_rule_status = TEST_FAIL; } /* record base rule status */ @@ -579,9 +579,9 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) } /* Print end header for alias rule */ - val_print(ACS_PRINT_TEST, "\n\n === End tests for rules referenced by ", 0); - val_print(ACS_PRINT_TEST, rule_id_string[rule_list[i]], 0); - val_print(ACS_PRINT_TEST, " ===\n", 0); + val_print(INFO, "\n\n === End tests for rules referenced by "); + val_print(INFO, rule_id_string[rule_list[i]]); + val_print(INFO, " ===\n"); } else if (rule_test_map[rule_list[i]].flag == BASE_RULE) { /* Base rule would have single test entry, could be wrapper too */ @@ -592,7 +592,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) } else { - val_print(ACS_PRINT_ERR, "\n\n Rule failed due to NULL entry \n\r ", 0); + val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r ", 0); rule_test_status = TEST_FAIL; } } @@ -602,7 +602,6 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) print_rule_test_status(rule_list[i], 0, rule_test_status); } - val_print(ACS_PRINT_TEST, - "\n-------------------- Suite run complete --------------------\n", - 0); + val_print(INFO, + "\n-------------------- Suite run complete --------------------\n"); } diff --git a/val/src/sbsa_execute_test.c b/val/src/sbsa_execute_test.c index 07ec19d3..60e8b4dc 100644 --- a/val/src/sbsa_execute_test.c +++ b/val/src/sbsa_execute_test.c @@ -54,7 +54,7 @@ val_sbsa_pe_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } } @@ -62,7 +62,7 @@ val_sbsa_pe_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_PE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PE tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PE tests\n"); return ACS_STATUS_SKIP; } @@ -152,7 +152,7 @@ val_sbsa_gic_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_GIC_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, " USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } } @@ -161,7 +161,7 @@ val_sbsa_gic_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ module_skip = val_check_skip_module(ACS_GIC_TEST_NUM_BASE); if (module_skip) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all GIC tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all GIC tests\n"); return ACS_STATUS_SKIP; } @@ -205,7 +205,7 @@ val_sbsa_wd_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_WD_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, " USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } } @@ -213,7 +213,7 @@ val_sbsa_wd_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_WD_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Watchdog tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Watchdog tests\n"); return ACS_STATUS_SKIP; } @@ -246,7 +246,7 @@ val_sbsa_timer_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_TIMER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all Timer tests\n", 0); + val_print(TRACE, " USER Override - Skipping all Timer tests\n"); return ACS_STATUS_SKIP; } } @@ -254,7 +254,7 @@ val_sbsa_timer_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_TIMER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Timer tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Timer tests\n"); return ACS_STATUS_SKIP; } @@ -301,7 +301,7 @@ val_sbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PCIE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } } @@ -317,13 +317,13 @@ val_sbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) /* Skip the module only if no tests from PCIe module and extended PCIe module are run */ if (skip_status > 1) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PCIe tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PCIe tests\n"); return ACS_STATUS_SKIP; } if (pcie_bdf_table_list_flag == 1) { - val_print(ACS_PRINT_WARN, "\n *** Created device list with valid bdf doesn't match \ - with the platform pcie device hierarchy, Skipping PCIE tests ***\n", 0); + val_print(WARN, "\n *** Created device list with valid bdf doesn't match \ + with the platform pcie device hierarchy, Skipping PCIE tests ***\n"); return ACS_STATUS_SKIP; } @@ -337,7 +337,7 @@ val_sbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) ecam_status = p001_entry(num_pe); if (ecam_status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_WARN, "\n *** Skipping remaining PCIE tests ***\n", 0); + val_print(WARN, "\n *** Skipping remaining PCIE tests ***\n"); return status; } @@ -377,8 +377,8 @@ val_sbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe) #endif if (g_pcie_integrated_devices == 0) { - val_print(ACS_PRINT_WARN, "\n *** No integrated PCIe Devices Found, \ - Skipping remaining PCIE tests ***\n", 0); + val_print(WARN, "\n *** No integrated PCIe Devices Found, \ + Skipping remaining PCIE tests ***\n"); return ACS_STATUS_SKIP; } @@ -462,7 +462,7 @@ val_sbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_SMMU_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, " USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } } @@ -470,7 +470,7 @@ val_sbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_SMMU_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all SMMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all SMMU tests\n"); return ACS_STATUS_SKIP; } @@ -483,8 +483,8 @@ val_sbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) status |= i025_entry(num_pe); if (status != ACS_STATUS_PASS) { - val_print(ACS_PRINT_WARN, "\n SMMU Compatibility Check Failed, ", 0); - val_print(ACS_PRINT_WARN, "Skipping SMMU tests...\n", 0); + val_print(WARN, "\n SMMU Compatibility Check Failed, "); + val_print(WARN, "Skipping SMMU tests...\n"); return ACS_STATUS_FAIL; } @@ -550,7 +550,7 @@ val_sbsa_memory_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0 ; i < g_num_skip ; i++) { if (g_skip_test_num[i] == ACS_MEMORY_MAP_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all memory tests\n", 0); + val_print(TRACE, " USER Override - Skipping all memory tests\n"); return ACS_STATUS_SKIP; } } @@ -558,7 +558,7 @@ val_sbsa_memory_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in the current module with user override*/ status = val_check_skip_module(ACS_MEMORY_MAP_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all memory tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all memory tests\n"); return ACS_STATUS_SKIP; } @@ -596,7 +596,7 @@ val_sbsa_exerciser_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_EXERCISER_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping the Exerciser tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping the Exerciser tests\n"); return ACS_STATUS_SKIP; } } @@ -604,33 +604,33 @@ val_sbsa_exerciser_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_EXERCISER_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all Exerciser tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all Exerciser tests\n"); return ACS_STATUS_SKIP; } if (val_pcie_create_device_bdf_table()) { - val_print(ACS_PRINT_WARN, "\n Create BDF Table Failed, Skipping Exerciser tests...\n", 0); + val_print(WARN, "\n Create BDF Table Failed, Skipping Exerciser tests...\n"); return ACS_STATUS_SKIP; } if (pcie_bdf_table_list_flag == 1) { - val_print(ACS_PRINT_WARN, "\n *** Created device list with valid bdf doesn't match \ - with the platform pcie device hierarchy, Skipping exerciser tests ***\n", 0); + val_print(WARN, "\n *** Created device list with valid bdf doesn't match \ + with the platform pcie device hierarchy, Skipping exerciser tests ***\n"); return ACS_STATUS_SKIP; } - val_print(ACS_PRINT_INFO, "\n Starting Exerciser Setup\n", 0); + val_print(TRACE, "\n Starting Exerciser Setup\n"); val_exerciser_create_info_table(); num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS); if (num_instances == 0) { - val_print(ACS_PRINT_WARN, - "\n No Exerciser Devices Found, Skipping Exerciser tests...\n", 0); + val_print(WARN, + "\n No Exerciser Devices Found, Skipping Exerciser tests...\n"); return ACS_STATUS_SKIP; } - val_print(ACS_PRINT_INFO, "\n Initializing SMMU\n", 0); + val_print(TRACE, "\n Initializing SMMU\n"); num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); val_smmu_init(); @@ -639,7 +639,7 @@ val_sbsa_exerciser_execute_tests(uint32_t level, uint32_t num_pe) val_smmu_disable(instance); if (g_its_init != 1) { - val_print(ACS_PRINT_INFO, "\n Initializing ITS\n", 0); + val_print(TRACE, "\n Initializing ITS\n"); val_gic_its_configure(); g_its_init = 1; } @@ -706,7 +706,7 @@ val_sbsa_pmu_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_PMU_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all PMU tests\n", 0); + val_print(TRACE, " USER Override - Skipping all PMU tests\n"); return ACS_STATUS_SKIP; } } @@ -714,14 +714,14 @@ val_sbsa_pmu_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ skip_module = val_check_skip_module(ACS_PMU_TEST_NUM_BASE); if (skip_module) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all PMU tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all PMU tests\n"); return ACS_STATUS_SKIP; } /* check if PE supports PMU extension, else skip all PMU tests */ if (val_pe_feat_check(PE_FEAT_PMU)) { - val_print(ACS_PRINT_TEST, - "\n PE PMU extension unimplemented. Skipping all PMU tests\n", 0); + val_print(INFO, + "\n PE PMU extension unimplemented. Skipping all PMU tests\n"); return ACS_STATUS_SKIP; } @@ -766,7 +766,7 @@ val_sbsa_mpam_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_MPAM_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all MPAM tests\n", 0); + val_print(TRACE, " USER Override - Skipping all MPAM tests\n"); return ACS_STATUS_SKIP; } } @@ -774,14 +774,14 @@ val_sbsa_mpam_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in the current module with user override*/ skip_module = val_check_skip_module(ACS_MPAM_TEST_NUM_BASE); if (skip_module) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all MPAM tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all MPAM tests\n"); return ACS_STATUS_SKIP; } /* check if PE supports MPAM extension, else skip all MPAM tests */ if (val_pe_feat_check(PE_FEAT_MPAM)) { - val_print(ACS_PRINT_TEST, - "\n PE MPAM extension unimplemented. Skipping all MPAM tests\n", 0); + val_print(INFO, + "\n PE MPAM extension unimplemented. Skipping all MPAM tests\n"); return ACS_STATUS_SKIP; } @@ -795,8 +795,8 @@ val_sbsa_mpam_execute_tests(uint32_t level, uint32_t num_pe) msc_node_cnt = val_mpam_get_msc_count(); if (msc_node_cnt == 0) { - val_print(ACS_PRINT_TEST, - "\n MPAM MSCs not found. Skipping remaining MPAM tests\n", 0); + val_print(INFO, + "\n MPAM MSCs not found. Skipping remaining MPAM tests\n"); return ACS_STATUS_SKIP; } @@ -834,7 +834,7 @@ val_sbsa_ras_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_RAS_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all RAS tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all RAS tests\n"); return ACS_STATUS_SKIP; } } @@ -842,14 +842,14 @@ val_sbsa_ras_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ skip_module = val_check_skip_module(ACS_RAS_TEST_NUM_BASE); if (skip_module) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all RAS tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all RAS tests\n"); return ACS_STATUS_SKIP; } /* check if PE supports RAS extension, else skip all RAS tests */ if (val_pe_feat_check(PE_FEAT_RAS)) { - val_print(ACS_PRINT_TEST, - "\n PE RAS extension unimplemented. Skipping all RAS tests\n", 0); + val_print(INFO, + "\n PE RAS extension unimplemented. Skipping all RAS tests\n"); return ACS_STATUS_SKIP; } @@ -857,7 +857,7 @@ val_sbsa_ras_execute_tests(uint32_t level, uint32_t num_pe) status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_ras_nodes); if (status || (num_ras_nodes == 0)) { - val_print(ACS_PRINT_TEST, "\n RAS nodes not found. Skipping all RAS tests\n", 0); + val_print(INFO, "\n RAS nodes not found. Skipping all RAS tests\n"); return ACS_STATUS_SKIP; } @@ -901,7 +901,7 @@ val_sbsa_ete_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_ETE_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all ETE tests \n", 0); + val_print(TRACE, " USER Override - Skipping all ETE tests \n"); return ACS_STATUS_SKIP; } } @@ -909,7 +909,7 @@ val_sbsa_ete_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_ETE_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all ETE tests \n", 0); + val_print(TRACE, "\n USER Override - Skipping all ETE tests \n"); return ACS_STATUS_SKIP; } @@ -920,7 +920,7 @@ val_sbsa_ete_execute_tests(uint32_t level, uint32_t num_pe) ete_status = ete001_entry(num_pe); if (ete_status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_ERR, "\n FEAT_ETE Not Supported, Skipping FEAT_ETE tests \n", 0); + val_print(ERROR, "\n FEAT_ETE Not Supported, Skipping FEAT_ETE tests \n"); } else { ete_status |= ete002_entry(num_pe); ete_status |= ete003_entry(num_pe); @@ -930,7 +930,7 @@ val_sbsa_ete_execute_tests(uint32_t level, uint32_t num_pe) trbe_status = ete005_entry(num_pe); if (trbe_status == ACS_STATUS_FAIL) { - val_print(ACS_PRINT_ERR, "\n FEAT_TRBE Not Supported, Skipping FEAT_TRBE tests \n", 0); + val_print(ERROR, "\n FEAT_TRBE Not Supported, Skipping FEAT_TRBE tests \n"); } else { trbe_status |= ete006_entry(num_pe); trbe_status |= ete007_entry(num_pe); @@ -959,7 +959,7 @@ val_sbsa_nist_execute_tests(uint32_t level, uint32_t num_pe) for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == ACS_NIST_TEST_NUM_BASE) { - val_print(ACS_PRINT_INFO, " USER Override - Skipping all NIST tests\n", 0); + val_print(TRACE, " USER Override - Skipping all NIST tests\n"); return ACS_STATUS_SKIP; } } @@ -967,7 +967,7 @@ val_sbsa_nist_execute_tests(uint32_t level, uint32_t num_pe) /* Check if there are any tests to be executed in current module with user override options*/ status = val_check_skip_module(ACS_NIST_TEST_NUM_BASE); if (status) { - val_print(ACS_PRINT_INFO, "\n USER Override - Skipping all NIST tests\n", 0); + val_print(TRACE, "\n USER Override - Skipping all NIST tests\n"); return ACS_STATUS_SKIP; } diff --git a/val/src/test_wrappers.c b/val/src/test_wrappers.c index 3545f938..01d5c0c8 100644 --- a/val/src/test_wrappers.c +++ b/val/src/test_wrappers.c @@ -445,7 +445,7 @@ v_l1wk_02_05_entry(uint32_t num_pe) #endif if (g_el1skiptrap_mask & EL1SKIPTRAP_CNTPCT) { - val_print(ACS_PRINT_TEST, + val_print(INFO, "\n Skipping rule as EL1 physical timer access not supported", 0); return TEST_SKIP; } diff --git a/val/src/val_logger.c b/val/src/val_logger.c index 92dd0b4b..91846203 100644 --- a/val/src/val_logger.c +++ b/val/src/val_logger.c @@ -702,22 +702,22 @@ uint32_t val_printf(print_verbosity_t verbosity, const char *msg, ...) switch (verbosity) { case TRACE: - print_raw_string("\t\t"); + print_raw_string("\t"); break; case DEBUG: - print_raw_string("\t\t"); + print_raw_string("\t"); break; case INFO: - print_raw_string("\t"); + print_raw_string(""); break; case WARN: - print_raw_string("\t\tWARN : "); + print_raw_string("\tWARN : "); break; case ERROR: - print_raw_string("\t\tERROR: "); + print_raw_string("\tERROR: "); break; case FATAL: - print_raw_string("\t\tFATAL: "); + print_raw_string("\tFATAL: "); break; default: break; From 0dbd94660b65ade09758c5956d621ca3e5c16077 Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Thu, 19 Feb 2026 09:11:24 +0000 Subject: [PATCH 05/13] Add common XLAT library code to VAL of Sysarch-acs - As part of Unified VAL, XLAT library is added into VAL directory - Validated the changes for BSA, SBSA suites on Baremetal RDV3 environment setup Signed-off-by: Avi Nawal Change-Id: I80798a673f140ed40dc5f67ec1934b888d8c3751 --- val/xlat_tables_v2/CMakeLists.txt | 18 + val/xlat_tables_v2/include/arch.h | 980 +++++++++++++ val/xlat_tables_v2/include/arch_features.h | 110 ++ val/xlat_tables_v2/include/arch_helpers.h | 315 +++++ val/xlat_tables_v2/include/asm_macros.S | 298 ++++ .../include/asm_macros_common.S | 117 ++ val/xlat_tables_v2/include/assert.h | 14 + val/xlat_tables_v2/include/assert_macros.S | 33 + val/xlat_tables_v2/include/cdefs.h | 85 ++ val/xlat_tables_v2/include/config.h | 12 + val/xlat_tables_v2/include/debug.h | 78 ++ val/xlat_tables_v2/include/def.h | 49 + val/xlat_tables_v2/include/smc.h | 46 + val/xlat_tables_v2/include/xlat_mmu_helpers.h | 96 ++ val/xlat_tables_v2/include/xlat_tables.h | 102 ++ .../include/xlat_tables_aarch64.h | 97 ++ val/xlat_tables_v2/include/xlat_tables_arch.h | 34 + .../include/xlat_tables_compat.h | 19 + val/xlat_tables_v2/include/xlat_tables_defs.h | 189 +++ .../include/xlat_tables_private.h | 113 ++ val/xlat_tables_v2/include/xlat_tables_v2.h | 422 ++++++ .../include/xlat_tables_v2_helpers.h | 184 +++ val/xlat_tables_v2/src/cache_helpers.S | 280 ++++ val/xlat_tables_v2/src/enable_mmu.S | 99 ++ val/xlat_tables_v2/src/smc.S | 45 + val/xlat_tables_v2/src/xlat_tables_arch.c | 318 +++++ val/xlat_tables_v2/src/xlat_tables_core.c | 1236 +++++++++++++++++ val/xlat_tables_v2/src/xlat_tables_utils.c | 574 ++++++++ 28 files changed, 5963 insertions(+) create mode 100644 val/xlat_tables_v2/CMakeLists.txt create mode 100644 val/xlat_tables_v2/include/arch.h create mode 100644 val/xlat_tables_v2/include/arch_features.h create mode 100644 val/xlat_tables_v2/include/arch_helpers.h create mode 100644 val/xlat_tables_v2/include/asm_macros.S create mode 100644 val/xlat_tables_v2/include/asm_macros_common.S create mode 100644 val/xlat_tables_v2/include/assert.h create mode 100644 val/xlat_tables_v2/include/assert_macros.S create mode 100644 val/xlat_tables_v2/include/cdefs.h create mode 100644 val/xlat_tables_v2/include/config.h create mode 100644 val/xlat_tables_v2/include/debug.h create mode 100644 val/xlat_tables_v2/include/def.h create mode 100644 val/xlat_tables_v2/include/smc.h create mode 100644 val/xlat_tables_v2/include/xlat_mmu_helpers.h create mode 100644 val/xlat_tables_v2/include/xlat_tables.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_aarch64.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_arch.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_compat.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_defs.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_private.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_v2.h create mode 100644 val/xlat_tables_v2/include/xlat_tables_v2_helpers.h create mode 100644 val/xlat_tables_v2/src/cache_helpers.S create mode 100644 val/xlat_tables_v2/src/enable_mmu.S create mode 100644 val/xlat_tables_v2/src/smc.S create mode 100644 val/xlat_tables_v2/src/xlat_tables_arch.c create mode 100644 val/xlat_tables_v2/src/xlat_tables_core.c create mode 100644 val/xlat_tables_v2/src/xlat_tables_utils.c diff --git a/val/xlat_tables_v2/CMakeLists.txt b/val/xlat_tables_v2/CMakeLists.txt new file mode 100644 index 00000000..5d8fa2ac --- /dev/null +++ b/val/xlat_tables_v2/CMakeLists.txt @@ -0,0 +1,18 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +project(xlat-lib LANGUAGES C ASM) + +file(GLOB XLAT_SRC + "${CMAKE_CURRENT_SOURCE_DIR}/include/*.S" + "${CMAKE_CURRENT_SOURCE_DIR}/src/*.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/*.S" +) + +add_library(${XLAT-LIB} STATIC ${XLAT_SRC}) + +target_include_directories(${XLAT-LIB} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include/) diff --git a/val/xlat_tables_v2/include/arch.h b/val/xlat_tables_v2/include/arch.h new file mode 100644 index 00000000..661eb6d0 --- /dev/null +++ b/val/xlat_tables_v2/include/arch.h @@ -0,0 +1,980 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _ARCH_H_ +#define _ARCH_H_ + +#define EL2 2 +#define EL1 1 + +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_M_BIT (1 << 0) + +#define EXTRACT_BIT(regfield, reg) \ + (((reg) >> (regfield##_SHIFT)) & 1ul) + +#define ESR_EL2_EC_SHIFT 26 +#define ESR_EL2_EC_WIDTH 6 +#define ESR_EL2_EC_MASK MASK(ESR_EL2_EC) +#define ESR_EL2_IL_SHIFT 25 +#define ESR_EL2_IL_WIDTH 1 +#define ESR_EL2_IL_MASK MASK(ESR_EL2_EC) + +#define ESR_EL2_ISS_SHIFT 0 +#define ESR_EL2_ISS_WIDTH 25 +#define ESR_EL2_ISS_MASK MASK(ESR_EL2_ISS) + +#define ESR_EL2_EC(val) (val & MASK(ESR_EL2_EC)) + +#define ESR_EL2_EC_WFX INPLACE(ESR_EL2_EC, 1) +#define ESR_EL2_EC_SVC INPLACE(ESR_EL2_EC, 21) +#define ESR_EL2_EC_HVC INPLACE(ESR_EL2_EC, 22) +#define ESR_EL2_EC_SMC INPLACE(ESR_EL2_EC, 23) +#define ESR_EL2_EC_SYSREG INPLACE(ESR_EL2_EC, 24) +#define ESR_EL2_EC_INST_ABORT INPLACE(ESR_EL2_EC, 32) +#define ESR_EL2_EC_DATA_ABORT INPLACE(ESR_EL2_EC, 36) +#define ESR_EL2_EC_DATA_ABORT_SEL INPLACE(ESR_EL2_EC, 37) +#define ESR_EL2_EC_FPU INPLACE(ESR_EL2_EC, 0x7) + +#define ESR_EL2_WFX_TI(val) (val & MASK(ESR_EL2_WFX_TI)) +#define ESR_EL2_ABORT_FSC(val) (val & MASK(ESR_EL2_ABORT_FSC)) + +#define ESR_EL2_WFX_TI_WFI INPLACE(ESR_EL2_WFX_TI, 0x0) +#define ESR_EL2_WFX_TI_WFE INPLACE(ESR_EL2_WFX_TI, 0x1) + + +#define ESR_EL2_WFX_TI_SHIFT 0 +#define ESR_EL2_WFX_TI_WIDTH 2 + +/* Data/Instruction Abort ESR fields */ +#define ESR_EL2_ABORT_ISV_BIT (1UL << 24) + +#define ESR_EL2_ABORT_SAS_SHIFT 22 +#define ESR_EL2_ABORT_SAS_WIDTH 2 +#define ESR_EL2_ABORT_SAS_MASK MASK(ESR_EL2_ABORT_SAS) + +#define ESR_EL2_ABORT_SAS_BYTE_VAL 0 +#define ESR_EL2_ABORT_SAS_HWORD_VAL 1 +#define ESR_EL2_ABORT_SAS_WORD_VAL 2 +#define ESR_EL2_ABORT_SAS_DWORD_VAL 3 + +#define ESR_EL2_ABORT_SSE_BIT (1UL << 21) + +#define ESR_EL2_ABORT_SRT_SHIFT 16 +#define ESR_EL2_ABORT_SRT_WIDTH 5 +#define ESR_EL2_ABORT_SRT_MASK MASK(ESR_EL2_ABORT_SRT) + +#define ESR_EL2_ABORT_SF_BIT (1UL << 15) +#define ESR_EL2_ABORT_FNV_BIT (1UL << 10) +#define ESR_EL2_ABORT_WNR_BIT (1UL << 6) +#define ESR_EL2_ABORT_FSC_SHIFT 0 +#define ESR_EL2_ABORT_FSC_WIDTH 6 +#define ESR_EL2_ABORT_FSC_MASK MASK(ESR_EL2_ABORT_FSC) + +#define ESR_EL2_ABORT_FSC_TRANSLATION_FAULT 0x04 +#define ESR_EL2_ABORT_FSC_PERMISSION_FAULT 0x0c +#define ESR_EL2_ABORT_FSC_PERMISSION_FAULT_L3 0x0f +#define ESR_EL2_ABORT_FSC_LEVEL_SHIFT 0 +#define ESR_EL2_ABORT_FSC_LEVEL_WIDTH 2 +#define ESR_EL2_ABORT_FSC_LEVEL_MASK MASK(ESR_EL2_ABORT_FSC_LEVEL) +#define ESR_EL2_ABORT_FSC_GPF 0x28 + +#define ESR_EL2_SYSREG_TRAP_OP0_SHIFT 20 +#define ESR_EL2_SYSREG_TRAP_OP0_WIDTH 2 +#define ESR_EL2_SYSREG_TRAP_OP0_MASK MASK(ESR_EL2_SYSREG_TRAP_OP0) + +#define ESR_EL2_SYSREG_TRAP_OP2_SHIFT 17 +#define ESR_EL2_SYSREG_TRAP_OP2_WIDTH 3 +#define ESR_EL2_SYSREG_TRAP_OP2_MASK MASK(ESR_EL2_SYSREG_TRAP_OP2) + +#define ESR_EL2_SYSREG_TRAP_OP1_SHIFT 14 +#define ESR_EL2_SYSREG_TRAP_OP1_WIDTH 3 +#define ESR_EL2_SYSREG_TRAP_OP1_MASK MASK(ESR_EL2_SYSREG_TRAP_OP1) + +#define ESR_EL2_SYSREG_TRAP_CRN_SHIFT 10 +#define ESR_EL2_SYSREG_TRAP_CRN_WIDTH 4 +#define ESR_EL2_SYSREG_TRAP_CRN_MASK MASK(ESR_EL2_SYSREG_TRAP_CRN) + +#define ESR_EL2_SYSREG_TRAP_RT_SHIFT 5 +#define ESR_EL2_SYSREG_TRAP_RT_WIDTH 5 +#define ESR_EL2_SYSREG_TRAP_RT_MASK MASK(ESR_EL2_SYSREG_TRAP_RT) + +#define ESR_EL2_SYSREG_TRAP_CRM_SHIFT 1 +#define ESR_EL2_SYSREG_TRAP_CRM_WIDTH 4 +#define ESR_EL2_SYSREG_TRAP_CRM_MASK MASK(ESR_EL2_SYSREG_TRAP_CRM) + +/* WFx ESR fields */ +#define ESR_EL2_WFx_TI_BIT (1UL << 0) + +/* xVC ESR fields */ +#define ESR_EL2_xVC_IMM_SHIFT 0 +#define ESR_EL2_xVC_IMM_WIDTH 16 +#define ESR_EL2_xVC_IMM_MASK MASK(ESR_EL2_xVC_IMM) + +/* System Register encodings */ +#define SYSREG_ID_OP0_SHIFT 19 +#define SYSREG_ID_OP1_SHIFT 16 +#define SYSREG_ID_CRN_SHIFT 12 +#define SYSREG_ID_CRM_SHIFT 8 +#define SYSREG_ID_OP2_SHIFT 5 + +#define SYSREG_ID(op0, op1, crn, crm, op2) \ + ((UL(op0) << SYSREG_ID_OP0_SHIFT) | \ + (UL(op1) << SYSREG_ID_OP1_SHIFT) | \ + (UL(crn) << SYSREG_ID_CRN_SHIFT) | \ + (UL(crm) << SYSREG_ID_CRM_SHIFT) | \ + (UL(op2) << SYSREG_ID_OP2_SHIFT)) + +#define SYSREG_SCTLR_EL1 SYSREG_ID(3, 0, 1, 0, 0) +#define SYSREG_SCTLR_EL3 SYSREG_ID(3, 3, 1, 0, 0) +#define SYSREG_PMCR_EL0 SYSREG_ID(3, 3, 9, 12, 0) + +/******************************************************************************* + * MIDR bit definitions + ******************************************************************************/ +#define MIDR_IMPL_MASK U(0xff) +#define MIDR_IMPL_SHIFT U(0x18) +#define MIDR_VAR_SHIFT U(20) +#define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) +#define MIDR_REV_SHIFT U(0) +#define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) +#define MIDR_PN_MASK U(0xfff) +#define MIDR_PN_SHIFT U(0x4) + +/******************************************************************************* + * MPIDR macros + ******************************************************************************/ +#define MPIDR_MT_MASK (ULL(1) << 24) +#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK +#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) +#define MPIDR_AFFINITY_BITS U(8) +#define MPIDR_AFFLVL_MASK ULL(0xff) +#define MPIDR_AFF0_SHIFT 0 +#define MPIDR_AFF1_SHIFT U(8) +#define MPIDR_AFF2_SHIFT U(16) +#define MPIDR_AFF3_SHIFT U(32) +#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT +//#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) +#define MPIDR_AFFLVL_SHIFT U(3) +#define MPIDR_AFFLVL0 ULL(0x0) +#define MPIDR_AFFLVL1 ULL(0x1) +#define MPIDR_AFFLVL2 ULL(0x2) +#define MPIDR_AFFLVL3 ULL(0x3) +#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n +#define MPIDR_AFFLVL0_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) +/* + * The MPIDR_MAX_AFFLVL count starts from 0. Take care to + * add one while using this macro to define array sizes. + */ +#define MPIDR_MAX_AFFLVL U(2) + +#define MPID_MASK (MPIDR_MT_MASK | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) + +#define MPIDR_AFF_ID(mpid, n) \ + (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) + + +#define MPIDR_AFFINITY_MASK ((MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) + +/* + * An invalid MPID. This value can be used by functions that return an MPID to + * indicate an error. + */ +#define INVALID_MPID U(0xFFFFFFFF) + +/******************************************************************************* + * System register bit definitions + ******************************************************************************/ +/* CLIDR definitions */ +#define LOUIS_SHIFT U(21) +#define LOC_SHIFT U(24) +#define CLIDR_FIELD_WIDTH U(3) + +/* CSSELR definitions */ +#define LEVEL_SHIFT U(1) + +/* Data cache set/way op type defines */ +#define DCISW U(0x0) +#define DCCISW U(0x1) +#define DCCSW U(0x2) + +/* ID_AA64PFR0_EL1 definitions */ +#define ID_AA64PFR0_EL0_SHIFT U(0) +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_EL2_SHIFT U(8) +#define ID_AA64PFR0_EL3_SHIFT U(12) +#define ID_AA64PFR0_AMU_SHIFT U(44) +#define ID_AA64PFR0_AMU_LENGTH U(4) +#define ID_AA64PFR0_AMU_MASK ULL(0xf) +#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) +#define ID_AA64PFR0_AMU_V1 U(0x1) +#define ID_AA64PFR0_AMU_V1P1 U(0x2) +#define ID_AA64PFR0_ELX_MASK ULL(0xf) +#define ID_AA64PFR0_SVE_SHIFT U(32) +#define ID_AA64PFR0_SVE_MASK ULL(0xf) +#define ID_AA64PFR0_SVE_LENGTH U(4) +#define ID_AA64PFR0_MPAM_SHIFT U(40) +#define ID_AA64PFR0_MPAM_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_SHIFT U(48) +#define ID_AA64PFR0_DIT_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_LENGTH U(4) +#define ID_AA64PFR0_DIT_SUPPORTED U(1) +#define ID_AA64PFR0_CSV2_SHIFT U(56) +#define ID_AA64PFR0_CSV2_MASK ULL(0xf) +#define ID_AA64PFR0_CSV2_LENGTH U(4) +#define ID_AA64PFR0_FEAT_RME_SHIFT U(52) +#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) +#define ID_AA64PFR0_FEAT_RME_LENGTH U(4) +#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) +#define ID_AA64PFR0_FEAT_RME_V1 U(1) + +/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ +#define ID_AA64DFR0_PMS_SHIFT U(32) +#define ID_AA64DFR0_PMS_LENGTH U(4) +#define ID_AA64DFR0_PMS_MASK ULL(0xf) + +/* ID_AA64DFR0_EL1.DEBUG definitions */ +#define ID_AA64DFR0_DEBUG_SHIFT U(0) +#define ID_AA64DFR0_DEBUG_LENGTH U(4) +#define ID_AA64DFR0_DEBUG_MASK ULL(0xf) +#define ID_AA64DFR0_DEBUG_BITS (ID_AA64DFR0_DEBUG_MASK << \ + ID_AA64DFR0_DEBUG_SHIFT) +#define ID_AA64DFR0_V8_DEBUG_ARCH_SUPPORTED U(6) +#define ID_AA64DFR0_V8_DEBUG_ARCH_VHE_SUPPORTED U(7) +#define ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED U(8) +#define ID_AA64DFR0_V8_4_DEBUG_ARCH_SUPPORTED U(9) + +/* ID_AA64DFR0_EL1.TraceBuffer definitions */ +#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) +#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) +#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) + +/* ID_DFR0_EL1.Tracefilt definitions */ +#define ID_AA64DFR0_TRACEFILT_SHIFT U(40) +#define ID_AA64DFR0_TRACEFILT_MASK U(0xf) +#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) + +/* ID_AA64DFR0_EL1.TraceVer definitions */ +#define ID_AA64DFR0_TRACEVER_SHIFT U(4) +#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) +#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) + +#define EL_IMPL_NONE ULL(0) +#define EL_IMPL_A64ONLY ULL(1) +#define EL_IMPL_A64_A32 ULL(2) + +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) + +/* ID_AA64ISAR1_EL1 definitions */ +#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 +#define ID_AA64ISAR1_GPI_SHIFT U(28) +#define ID_AA64ISAR1_GPI_WIDTH U(4) +#define ID_AA64ISAR1_GPI_MASK ULL(0xf) +#define ID_AA64ISAR1_GPA_SHIFT U(24) +#define ID_AA64ISAR1_GPA_WIDTH U(4) +#define ID_AA64ISAR1_GPA_MASK ULL(0xf) +#define ID_AA64ISAR1_API_SHIFT U(8) +#define ID_AA64ISAR1_API_WIDTH U(4) +#define ID_AA64ISAR1_API_MASK ULL(0xf) +#define ID_AA64ISAR1_APA_SHIFT U(4) +#define ID_AA64ISAR1_APA_WIDTH U(4) +#define ID_AA64ISAR1_APA_MASK ULL(0xf) + +/* ID_AA64MMFR0_EL1 definitions */ +#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) +#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) + +#define PARANGE_0000 U(32) +#define PARANGE_0001 U(36) +#define PARANGE_0010 U(40) +#define PARANGE_0011 U(42) +#define PARANGE_0100 U(44) +#define PARANGE_0101 U(48) +#define PARANGE_0110 U(52) + +#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) +#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) +#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) + +#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) +#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) + +#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) +#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) + +#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) +#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) + +#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) +#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) +#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) + +/* ID_AA64MMFR1_EL1 definitions */ +#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) +#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) +#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) +#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) +#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) + +/* ID_AA64MMFR2_EL1 definitions */ +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + +#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) +#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) + +#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) +#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) + +#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) +#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) + + + +/* ID_AA64PFR1_EL1 definitions */ +#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) +#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) + +#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ + +#define ID_AA64PFR1_EL1_BT_SHIFT U(0) +#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) + +#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ + +#define ID_AA64PFR1_EL1_MTE_SHIFT U(8) +#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) + +#define MTE_UNIMPLEMENTED ULL(0) +#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ +#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ + +#define ID_AA64PFR1_EL1_SME_SHIFT U(24) +#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) + +/* ID_PFR1_EL1 definitions */ +#define ID_PFR1_VIRTEXT_SHIFT U(12) +#define ID_PFR1_VIRTEXT_MASK U(0xf) +#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ + & ID_PFR1_VIRTEXT_MASK) + +/* SCTLR definitions */ +#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ + (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) + +#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) +#define SCTLR_AARCH32_EL1_RES1 \ + ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ + (U(1) << 4) | (U(1) << 3)) + +#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ + (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) + +//#define SCTLR_M_BIT (ULL(1) << 0) +#define SCTLR_A_BIT (ULL(1) << 1) +#define SCTLR_C_BIT (ULL(1) << 2) +#define SCTLR_SA_BIT (ULL(1) << 3) +#define SCTLR_SA0_BIT (ULL(1) << 4) +#define SCTLR_CP15BEN_BIT (ULL(1) << 5) +#define SCTLR_ITD_BIT (ULL(1) << 7) +#define SCTLR_SED_BIT (ULL(1) << 8) +#define SCTLR_UMA_BIT (ULL(1) << 9) +//#define SCTLR_I_BIT (ULL(1) << 12) +#define SCTLR_EnDB_BIT (ULL(1) << 13) +#define SCTLR_DZE_BIT (ULL(1) << 14) +#define SCTLR_UCT_BIT (ULL(1) << 15) +#define SCTLR_NTWI_BIT (ULL(1) << 16) +#define SCTLR_NTWE_BIT (ULL(1) << 18) +#define SCTLR_WXN_BIT (ULL(1) << 19) +#define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) +#define SCTLR_SPAN_BIT (ULL(1) << 23) +#define SCTLR_E0E_BIT (ULL(1) << 24) +#define SCTLR_EE_BIT (ULL(1) << 25) +#define SCTLR_UCI_BIT (ULL(1) << 26) +#define SCTLR_EnDA_BIT (ULL(1) << 27) +#define SCTLR_EnIB_BIT (ULL(1) << 30) +#define SCTLR_EnIA_BIT (ULL(1) << 31) +#define SCTLR_DSSBS_BIT (ULL(1) << 44) +#define SCTLR_RESET_VAL SCTLR_EL3_RES1 + +/* HSTR_EL2 definitions */ +#define HSTR_EL2_RESET_VAL U(0x0) +#define HSTR_EL2_T_MASK U(0xff) + +/* VTTBR_EL2 definitions */ +#define VTTBR_RESET_VAL ULL(0x0) +#define VTTBR_VMID_MASK ULL(0xff) +#define VTTBR_VMID_SHIFT U(48) +#define VTTBR_BADDR_MASK ULL(0xffffffffffff) +#define VTTBR_BADDR_SHIFT U(0) + +/* HCR definitions */ +#define HCR_AMVOFFEN_BIT (ULL(1) << 51) +#define HCR_API_BIT (ULL(1) << 41) +#define HCR_APK_BIT (ULL(1) << 40) +#define HCR_E2H_BIT (ULL(1) << 34) +#define HCR_TGE_BIT (ULL(1) << 27) +#define HCR_RW_SHIFT U(31) +#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) +#define HCR_AMO_BIT (ULL(1) << 5) +#define HCR_IMO_BIT (ULL(1) << 4) +#define HCR_FMO_BIT (ULL(1) << 3) + +/* ISR definitions */ +#define ISR_A_SHIFT U(8) +#define ISR_I_SHIFT U(7) +#define ISR_F_SHIFT U(6) + +/* CPTR_EL3 definitions */ +#define TCPAC_BIT (U(1) << 31) +#define TAM_BIT (U(1) << 30) +#define TTA_BIT (U(1) << 20) +#define ESM_BIT (U(1) << 12) +#define TFP_BIT (U(1) << 10) +#define CPTR_EZ_BIT (U(1) << 8) +#define CPTR_EL3_RESET_VAL U(0x0) + +/* CPTR_EL2 definitions */ +#define CPTR_EL2_RES1 ((ULL(3) << 12) | (ULL(1) << 9) | (ULL(0xff))) +#define CPTR_EL2_TCPAC_BIT (ULL(1) << 31) +#define CPTR_EL2_TAM_BIT (ULL(1) << 30) +#define CPTR_EL2_SMEN_MASK ULL(0x3) +#define CPTR_EL2_SMEN_SHIFT U(24) +#define CPTR_EL2_TTA_BIT (ULL(1) << 20) +#define CPTR_EL2_TSM_BIT (ULL(1) << 12) +#define CPTR_EL2_TFP_BIT (ULL(1) << 10) +#define CPTR_EL2_TZ_BIT (ULL(1) << 8) +#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (U(1) << 0) +#define DAIF_IRQ_BIT (U(1) << 1) +#define DAIF_ABT_BIT (U(1) << 2) +#define DAIF_DBG_BIT (U(1) << 3) +#define SPSR_DAIF_SHIFT U(6) +#define SPSR_DAIF_MASK U(0xf) + +#define SPSR_AIF_SHIFT U(6) +#define SPSR_AIF_MASK U(0x7) + +#define SPSR_E_SHIFT U(9) +#define SPSR_E_MASK U(0x1) +#define SPSR_E_LITTLE U(0x0) +#define SPSR_E_BIG U(0x1) + +#define SPSR_T_SHIFT U(5) +#define SPSR_T_MASK U(0x1) +#define SPSR_T_ARM U(0x0) +#define SPSR_T_THUMB U(0x1) + +#define SPSR_M_SHIFT U(4) +#define SPSR_M_MASK U(0x1) +#define SPSR_M_AARCH64 U(0x0) +#define SPSR_M_AARCH32 U(0x1) + +#define DISABLE_ALL_EXCEPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) + +/* + * HI-VECTOR address for AArch32 state + */ +#define HI_VECTOR_BASE U(0xFFFF0000) + +/* + * TCR definitions + */ +#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) +#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) +#define TCR_EL1_IPS_SHIFT U(32) +#define TCR_EL2_PS_SHIFT U(16) +#define TCR_EL3_PS_SHIFT U(16) + +#define TCR_TxSZ_MIN ULL(16) +#define TCR_TxSZ_MIN_LPA2 UL(12) +#define TCR_TxSZ_MAX ULL(39) +#define TCR_TxSZ_MAX_TTST ULL(48) + +#define TCR_T0SZ_SHIFT U(0) +#define TCR_T1SZ_SHIFT U(16) + +/* (internal) physical address size bits in EL3/EL1 */ +#define TCR_PS_BITS_4GB ULL(0x0) +#define TCR_PS_BITS_64GB ULL(0x1) +#define TCR_PS_BITS_1TB ULL(0x2) +#define TCR_PS_BITS_4TB ULL(0x3) +#define TCR_PS_BITS_16TB ULL(0x4) +#define TCR_PS_BITS_256TB ULL(0x5) + +#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) +#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) +#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) +#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) +#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) +#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) + +#define TCR_RGN_INNER_NC (ULL(0x0) << 8) +#define TCR_RGN_INNER_WBA (ULL(0x1) << 8) +#define TCR_RGN_INNER_WT (ULL(0x2) << 8) +#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) + +#define TCR_RGN_OUTER_NC (ULL(0x0) << 10) +#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) +#define TCR_RGN_OUTER_WT (ULL(0x2) << 10) +#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) + +#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) +#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) +#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) + +#define TCR_RGN1_INNER_NC (ULL(0x0) << 24) +#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) +#define TCR_RGN1_INNER_WT (ULL(0x2) << 24) +#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) + +#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) +#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) +#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) +#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) + +#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) +#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) +#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) + +#define TCR_TG0_SHIFT U(14) +#define TCR_TG0_MASK ULL(3) +#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) +#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) +#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) + +#define TCR_TG1_SHIFT U(30) +#define TCR_TG1_MASK ULL(3) +#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) +#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) +#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) + +#define TCR_EPD0_BIT (ULL(1) << 7) +#define TCR_EPD1_BIT (ULL(1) << 23) + +#define MODE_SP_SHIFT U(0x0) +#define MODE_SP_MASK U(0x1) +#define MODE_SP_EL0 U(0x0) +#define MODE_SP_ELX U(0x1) + +#define MODE_RW_SHIFT U(0x4) +#define MODE_RW_MASK U(0x1) +#define MODE_RW_64 U(0x0) +#define MODE_RW_32 U(0x1) + +#define MODE_EL_SHIFT U(0x2) +#define MODE_EL_MASK U(0x3) +#define MODE_EL3 U(0x3) +#define MODE_EL2 U(0x2) +#define MODE_EL1 U(0x1) +#define MODE_EL0 U(0x0) + +#define MODE32_SHIFT U(0) +#define MODE32_MASK U(0xf) +#define MODE32_usr U(0x0) +#define MODE32_fiq U(0x1) +#define MODE32_irq U(0x2) +#define MODE32_svc U(0x3) +#define MODE32_mon U(0x6) +#define MODE32_abt U(0x7) +#define MODE32_hyp U(0xa) +#define MODE32_und U(0xb) +#define MODE32_sys U(0xf) + +#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) +#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) +#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) +#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) + +#define SPSR_64(el, sp, daif) \ + ((MODE_RW_64 << MODE_RW_SHIFT) | \ + (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ + (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ + (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) + +#define SPSR_MODE32(mode, isa, endian, aif) \ + ((MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) + +/* + * TTBR Definitions + */ +#define TTBR_CNP_BIT ULL(0x1) + +/* + * CTR_EL0 definitions + */ +#define CTR_CWG_SHIFT U(24) +#define CTR_CWG_MASK U(0xf) +#define CTR_ERG_SHIFT U(20) +#define CTR_ERG_MASK U(0xf) +#define CTR_DMINLINE_SHIFT U(16) +#define CTR_DMINLINE_MASK U(0xf) +#define CTR_L1IP_SHIFT U(14) +#define CTR_L1IP_MASK U(0x3) +#define CTR_IMINLINE_SHIFT U(0) +#define CTR_IMINLINE_MASK U(0xf) + +#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ + +/* Exception Syndrome register bits and bobs */ +#define ESR_EC_SHIFT U(26) +#define ESR_EC_MASK U(0x3f) +#define ESR_EC_LENGTH U(6) +#define EC_UNKNOWN U(0x0) +#define EC_WFE_WFI U(0x1) +#define EC_AARCH32_CP15_MRC_MCR U(0x3) +#define EC_AARCH32_CP15_MRRC_MCRR U(0x4) +#define EC_AARCH32_CP14_MRC_MCR U(0x5) +#define EC_AARCH32_CP14_LDC_STC U(0x6) +#define EC_FP_SIMD U(0x7) +#define EC_AARCH32_CP10_MRC U(0x8) +#define EC_AARCH32_CP14_MRRC_MCRR U(0xc) +#define EC_ILLEGAL U(0xe) +#define EC_AARCH32_SVC U(0x11) +#define EC_AARCH32_HVC U(0x12) +#define EC_AARCH32_SMC U(0x13) +#define EC_AARCH64_SVC U(0x15) +#define EC_AARCH64_HVC U(0x16) +#define EC_AARCH64_SMC U(0x17) +#define EC_AARCH64_SYS U(0x18) +#define EC_IABORT_LOWER_EL U(0x20) +#define EC_IABORT_CUR_EL U(0x21) +#define EC_PC_ALIGN U(0x22) +#define EC_DABORT_LOWER_EL U(0x24) +#define EC_DABORT_CUR_EL U(0x25) +#define EC_SP_ALIGN U(0x26) +#define EC_AARCH32_FP U(0x28) +#define EC_AARCH64_FP U(0x2c) +#define EC_SERROR U(0x2f) + +/* + * External Abort bit in Instruction and Data Aborts synchronous exception + * syndromes. + */ +#define ESR_ISS_EABORT_EA_BIT U(9) + +#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) + +/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ +#define RMR_RESET_REQUEST_SHIFT U(0x1) +#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) + +/******************************************************************************* + * Definitions of register offsets, fields and macros for CPU system + * instructions. + ******************************************************************************/ + +#define TLBI_ADDR_SHIFT U(12) +#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) +#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) + + +/******************************************************************************* + * Definitions for system register interface to SVE + ******************************************************************************/ +#define ZCR_EL3 S3_6_C1_C2_0 +#define ZCR_EL2 S3_4_C1_C2_0 + +/* ZCR_EL3 definitions */ +#define ZCR_EL3_LEN_MASK U(0xf) + +/* ZCR_EL2 definitions */ +#define ZCR_EL2_LEN_MASK U(0xf) + +/******************************************************************************* + * Definitions for system register interface to SME + ******************************************************************************/ +#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 +#define SVCR S3_3_C4_C2_2 +#define TPIDR2_EL0 S3_3_C13_C0_5 +#define SMCR_EL2 S3_4_C1_C2_6 + +/* ID_AA64SMFR0_EL1 definitions */ +#define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) + +/* SVCR definitions */ +#define SVCR_ZA_BIT (U(1) << 1) +#define SVCR_SM_BIT (U(1) << 0) + +/* SMPRI_EL1 definitions */ +#define SMPRI_EL1_PRIORITY_SHIFT U(0) +#define SMPRI_EL1_PRIORITY_MASK U(0xf) + +/* SMPRIMAP_EL2 definitions */ +/* Register is composed of 16 priority map fields of 4 bits numbered 0-15. */ +#define SMPRIMAP_EL2_MAP_SHIFT(pri) U((pri) * 4) +#define SMPRIMAP_EL2_MAP_MASK U(0xf) + +/* SMCR_ELx definitions */ +#define SMCR_ELX_LEN_SHIFT U(0) +#define SMCR_ELX_LEN_MASK U(0x1ff) +#define SMCR_ELX_FA64_BIT (U(1) << 31) + +/******************************************************************************* + * Definitions of MAIR encodings for device and normal memory + ******************************************************************************/ +/* + * MAIR encodings for device memory attributes. + */ +#define MAIR_DEV_nGnRnE ULL(0x0) +#define MAIR_DEV_nGnRE ULL(0x4) +#define MAIR_DEV_nGRE ULL(0x8) +#define MAIR_DEV_GRE ULL(0xc) + +/* + * MAIR encodings for normal memory attributes. + * + * Cache Policy + * WT: Write Through + * WB: Write Back + * NC: Non-Cacheable + * + * Transient Hint + * NTR: Non-Transient + * TR: Transient + * + * Allocation Policy + * RA: Read Allocate + * WA: Write Allocate + * RWA: Read and Write Allocate + * NA: No Allocation + */ +#define MAIR_NORM_WT_TR_WA ULL(0x1) +#define MAIR_NORM_WT_TR_RA ULL(0x2) +#define MAIR_NORM_WT_TR_RWA ULL(0x3) +#define MAIR_NORM_NC ULL(0x4) +#define MAIR_NORM_WB_TR_WA ULL(0x5) +#define MAIR_NORM_WB_TR_RA ULL(0x6) +#define MAIR_NORM_WB_TR_RWA ULL(0x7) +#define MAIR_NORM_WT_NTR_NA ULL(0x8) +#define MAIR_NORM_WT_NTR_WA ULL(0x9) +#define MAIR_NORM_WT_NTR_RA ULL(0xa) +#define MAIR_NORM_WT_NTR_RWA ULL(0xb) +#define MAIR_NORM_WB_NTR_NA ULL(0xc) +#define MAIR_NORM_WB_NTR_WA ULL(0xd) +#define MAIR_NORM_WB_NTR_RA ULL(0xe) +#define MAIR_NORM_WB_NTR_RWA ULL(0xf) + +#define MAIR_NORM_OUTER_SHIFT U(4) + +#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ + ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) + +/* PAR_EL1 fields */ +#define PAR_F_SHIFT U(0) +#define PAR_F_MASK ULL(0x1) +#define PAR_ADDR_SHIFT U(12) +#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ + +/******************************************************************************* + * Armv8.1 Registers - Privileged Access Never Registers + ******************************************************************************/ +#define PAN S3_0_C4_C2_3 +#define PAN_BIT BIT(22) + +/******************************************************************************* + * Armv8.3 Pointer Authentication Registers + ******************************************************************************/ +#define APIAKeyLo_EL1 S3_0_C2_C1_0 +#define APIAKeyHi_EL1 S3_0_C2_C1_1 +#define APIBKeyLo_EL1 S3_0_C2_C1_2 +#define APIBKeyHi_EL1 S3_0_C2_C1_3 +#define APDAKeyLo_EL1 S3_0_C2_C2_0 +#define APDAKeyHi_EL1 S3_0_C2_C2_1 +#define APDBKeyLo_EL1 S3_0_C2_C2_2 +#define APDBKeyHi_EL1 S3_0_C2_C2_3 +#define APGAKeyLo_EL1 S3_0_C2_C3_0 +#define APGAKeyHi_EL1 S3_0_C2_C3_1 + +/******************************************************************************* + * Armv8.4 Data Independent Timing Registers + ******************************************************************************/ +#define DIT S3_3_C4_C2_5 +#define DIT_BIT BIT(24) + +/******************************************************************************* + * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field + ******************************************************************************/ +#define SSBS S3_3_C4_C2_6 + +/******************************************************************************* + * Armv8.5 - Memory Tagging Extension Registers + ******************************************************************************/ +#define TFSRE0_EL1 S3_0_C5_C6_1 +#define TFSR_EL1 S3_0_C5_C6_0 +#define RGSR_EL1 S3_0_C1_C0_5 +#define GCR_EL1 S3_0_C1_C0_6 + +/******************************************************************************* + * Armv8.6 - Fine Grained Virtualization Traps Registers + ******************************************************************************/ +#define HFGRTR_EL2 S3_4_C1_C1_4 +#define HFGWTR_EL2 S3_4_C1_C1_5 +#define HFGITR_EL2 S3_4_C1_C1_6 +#define HDFGRTR_EL2 S3_4_C3_C1_4 +#define HDFGWTR_EL2 S3_4_C3_C1_5 + +/******************************************************************************* + * Armv8.6 - Enhanced Counter Virtualization Registers + ******************************************************************************/ +#define CNTPOFF_EL2 S3_4_C14_C0_6 + +/******************************************************************************* + * FEAT_HCX - Extended Hypervisor Configuration Register + ******************************************************************************/ +#define HCRX_EL2 S3_4_C1_C2_2 +#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) +#define HCRX_EL2_FnXS_BIT (UL(1) << 3) +#define HCRX_EL2_EnASR_BIT (UL(1) << 2) +#define HCRX_EL2_EnALS_BIT (UL(1) << 1) +#define HCRX_EL2_EnAS0_BIT (UL(1) << 0) + +/* Added for XLAT */ + +#define ID_AA64MMFR2_EL1_ST_WIDTH UL(4) +#define ID_AA64MMFR2_EL1_CNP_WIDTH UL(4) + +/* ID_AA64PFR0_EL1 definitions */ +#define ID_AA64PFR0_EL1_SVE_SHIFT UL(32) +#define ID_AA64PFR0_EL1_SVE_WIDTH UL(4) + +/* RNDR definitions */ +#define ID_AA64ISAR0_EL1_RNDR_SHIFT UL(60) +#define ID_AA64ISAR0_EL1_RNDR_WIDTH UL(4) + +/* ID_AA64MMFR1_EL1 definitions */ +#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT UL(4) +#define ID_AA64MMFR1_EL1_VMIDBits_WIDTH UL(4) +#define ID_AA64MMFR1_EL1_VMIDBits_8 UL(0) +#define ID_AA64MMFR1_EL1_VMIDBits_16 UL(2) + +#define ID_AA64MMFR0_EL1_TGRAN4_WIDTH UL(4) +#define ID_AA64MMFR0_EL1_TGRAN16_WIDTH UL(4) +#define ID_AA64MMFR0_EL1_TGRAN64_WIDTH UL(4) +#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT U(40) +#define ID_AA64MMFR0_EL1_TGRAN4_2_WIDTH U(4) +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 UL(0x1) +#define ID_AA64MMFR0_EL1_TGRAN4_2_LPA2 UL(0x3) +#define ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4 UL(0x0) + +#define ID_AA64DFR0_EL1_PMUVer_SHIFT UL(8) +#define ID_AA64DFR0_EL1_PMUVer_WIDTH UL(4) + +#define TCR_PS_BITS_4PB INPLACE(TCR_EL2_IPS, UL(6)) +#define SCTLR_ELx_M_BIT (UL(1) << 0) +#define MAIR_DEV_NGNRE UL(0x4) + +#define TCR_EL2_T0SZ_SHIFT UL(0) +#define TCR_EL2_T0SZ_WIDTH UL(6) + +#define TCR_EL2_T1SZ_SHIFT UL(16) +#define TCR_EL2_T1SZ_WIDTH UL(6) + +#define TCR_EL2_EPD0_BIT (UL(1) << 7) + +#define TCR_EL2_IRGN0_SHIFT UL(8) +#define TCR_EL2_IRGN0_WIDTH UL(2) +#define TCR_EL2_IRGN0_WBWA INPLACE(TCR_EL2_IRGN0, UL(1)) + +#define TCR_EL2_ORGN0_SHIFT UL(10) +#define TCR_EL2_ORGN0_WIDTH UL(2) +#define TCR_EL2_ORGN0_WBWA INPLACE(TCR_EL2_ORGN0, UL(1)) + +#define TCR_EL2_IRGN1_SHIFT UL(24) +#define TCR_EL2_IRGN1_WIDTH UL(2) +#define TCR_EL2_IRGN1_WBWA INPLACE(TCR_EL2_IRGN1, UL(1)) + +#define TCR_EL2_ORGN1_SHIFT UL(26) +#define TCR_EL2_ORGN1_WIDTH UL(2) +#define TCR_EL2_ORGN1_WBWA INPLACE(TCR_EL2_ORGN1, UL(1)) + +#define TCR_EL2_SH0_SHIFT UL(12) +#define TCR_EL2_SH0_WIDTH UL(2) +#define TCR_EL2_SH0_IS INPLACE(TCR_EL2_SH0, UL(3)) + +#define TCR_EL2_SH1_SHIFT UL(28) +#define TCR_EL2_SH1_WIDTH UL(2) +#define TCR_EL2_SH1_IS INPLACE(TCR_EL2_SH1, UL(3)) + +#define TCR_EL2_TG0_SHIFT UL(14) +#define TCR_EL2_TG0_WIDTH UL(2) +#define TCR_EL2_TG0_4K INPLACE(TCR_EL2_TG0, UL(0)) + +#define TCR_EL2_TG1_SHIFT UL(30) +#define TCR_EL2_TG1_WIDTH UL(2) +#define TCR_EL2_TG1_4K INPLACE(TCR_EL2_TG1, UL(2)) + +#define TCR_EL2_IPS_SHIFT UL(32) +#define TCR_EL2_IPS_WIDTH UL(3) + +#define TCR_EL2_DS_SHIFT UL(59) +#define TCR_EL2_DS_WIDTH UL(1) +#define TCR_EL2_DS_LPA2_EN INPLACE(TCR_EL2_DS, UL(1)) + +#define TCR_EL2_AS (UL(1) << 36) +#define TCR_EL2_HPD0 (UL(1) << 41) +#define TCR_EL2_HPD1 (UL(1) << 42) + +#define TTBRx_EL2_BADDR_SHIFT 1 +#define TTBRx_EL2_BADDR_WIDTH 47 + +#define PARANGE_0000_WIDTH U(32) +#define PARANGE_0001_WIDTH U(36) +#define PARANGE_0010_WIDTH U(40) +#define PARANGE_0011_WIDTH U(42) +#define PARANGE_0100_WIDTH U(44) +#define PARANGE_0101_WIDTH U(48) +#define PARANGE_0110_WIDTH U(52) + +#define ID_AA64MMFR0_EL1_PARANGE_WIDTH UL(4) + +#endif /* _ARCH_H_ */ diff --git a/val/xlat_tables_v2/include/arch_features.h b/val/xlat_tables_v2/include/arch_features.h new file mode 100644 index 00000000..13ef12ea --- /dev/null +++ b/val/xlat_tables_v2/include/arch_features.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef ARCH_FEATURES_H +#define ARCH_FEATURES_H + +#include +#include +#include + +static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void) +{ + return (EXTRACT(ID_AA64MMFR0_EL1_TGRAN64, + read_id_aa64mmfr0_el1())); +} +static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void) +{ + return (EXTRACT(ID_AA64MMFR0_EL1_TGRAN16, + read_id_aa64mmfr0_el1())); +} + +static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void) +{ + return (EXTRACT(ID_AA64MMFR0_EL1_TGRAN4, + read_id_aa64mmfr0_el1())); +} + +static inline bool is_armv8_4_ttst_present(void) +{ + return (EXTRACT(ID_AA64MMFR2_EL1_ST, + read_id_aa64mmfr2_el1()) == 1U); +} + +static inline bool is_armv8_2_ttcnp_present(void) +{ + return (EXTRACT(ID_AA64MMFR2_EL1_CNP, + read_id_aa64mmfr2_el1()) == 1U); +} + +/* + * Check if SVE is enabled + * ID_AA64PFR0_EL1.SVE, bits [35:32]: + * 0b0000 SVE architectural state and programmers' model are not implemented. + * 0b0001 SVE architectural state and programmers' model are implemented. + */ +static inline bool is_feat_sve_present(void) +{ + return (EXTRACT(ID_AA64PFR0_EL1_SVE, + read_id_aa64pfr0_el1()) != 0UL); +} + +/* + * Check if RNDR is available + */ +static inline bool is_feat_rng_present(void) +{ + return (EXTRACT(ID_AA64ISAR0_EL1_RNDR, + read_id_aa64isar0_el1()) != 0UL); +} + +/* + * Check if FEAT_VMID16 is implemented + * ID_AA64MMFR1_EL1.VMIDBits, bits [7:4]: + * 0b0000 8 bits. + * 0b0010 16 bits. + * All other values are reserved. + */ +static inline bool is_feat_vmid16_present(void) +{ + return (EXTRACT(ID_AA64MMFR1_EL1_VMIDBits, + read_id_aa64mmfr1_el1()) == ID_AA64MMFR1_EL1_VMIDBits_16); +} + +/* + * Check if FEAT_LPA2 is implemented for stage 1. + * 4KB granule at stage 1 supports 52-bit input and output addresses: + * ID_AA64MMFR0_EL1.TGran4 bits [31:28]: 0b0001 + */ +static inline bool is_feat_lpa2_4k_present(void) +{ + return (EXTRACT(ID_AA64MMFR0_EL1_TGRAN4, + read_id_aa64mmfr0_el1()) == ID_AA64MMFR0_EL1_TGRAN4_LPA2); +} + +/* + * Check if FEAT_LPA2 is implemented for stage 2. + * 4KB granule at stage 2 supports 52-bit input and output addresses: + * ID_AA64MMFR0_EL1.TGran4_2 bits [43:40]: 0b0011 || + * (ID_AA64MMFR0_EL1.TGran4_2 bits [43:40]: 0b0000 && + * ID_AA64MMFR0_EL1.TGran4 bits [31:28]: 0b0001 && + */ +static inline bool is_feat_lpa2_4k_2_present(void) +{ + u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); + + return ((EXTRACT(ID_AA64MMFR0_EL1_TGRAN4_2, id_aa64mmfr0_el1) == + ID_AA64MMFR0_EL1_TGRAN4_2_LPA2) || + ((EXTRACT(ID_AA64MMFR0_EL1_TGRAN4_2, id_aa64mmfr0_el1) == + ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4) && is_feat_lpa2_4k_present())); +} + +unsigned int arch_feat_get_pa_width(void); + +#endif /* ARCH_FEATURES_H */ diff --git a/val/xlat_tables_v2/include/arch_helpers.h b/val/xlat_tables_v2/include/arch_helpers.h new file mode 100644 index 00000000..c113eae7 --- /dev/null +++ b/val/xlat_tables_v2/include/arch_helpers.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef ARCH_HELPERS_H +#define ARCH_HELPERS_H + +#include +#include +#include +#include +#include + +typedef unsigned long u_register_t; + +#define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory") + +/********************************************************************** + * Macros which create inline functions to read or write CPU system + * registers + *********************************************************************/ + +#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(u_register_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ +} + +#define SYSREG_WRITE_CONST(reg_name, v) \ + __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) + +/* Define read function for system register */ +#define DEFINE_SYSREG_READ_FUNC(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) + +/* Define read & write function for system register */ +#define DEFINE_SYSREG_RW_FUNCS(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _name) + +/* Define read & write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + +/* Define read function for renamed system register */ +#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) + +/* Define write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + +/********************************************************************** + * Macros to create inline functions for system instructions + *********************************************************************/ + +/* Define function for simple system instruction */ +#define DEFINE_SYSOP_FUNC(_op) \ +static inline void _op(void) \ +{ \ + __asm__ (#_op); \ +} + +/* Define function for system instruction with type specifier */ +#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ +static inline void _op ## _type(void) \ +{ \ + __asm__ (#_op " " #_type); \ +} + +/* Define function for system instruction with register parameter */ +#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ +static inline void _op ## _type(uint64_t v) \ +{ \ + __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ +} + +/******************************************************************************* + * TLB maintenance accessor prototypes + ******************************************************************************/ + +#if ERRATA_A57_813419 +/* + * Define function for TLBI instruction with type specifier that implements + * the workaround for errata 813419 of Cortex-A57. + */ +#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ +static inline void tlbi ## _type(void) \ +{ \ + __asm__("tlbi " #_type "\n" \ + "dsb ish\n" \ + "tlbi " #_type); \ +} + +/* + * Define function for TLBI instruction with register parameter that implements + * the workaround for errata 813419 of Cortex-A57. + */ +#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ +static inline void tlbi ## _type(uint64_t v) \ +{ \ + __asm__("tlbi " #_type ", %0\n" \ + "dsb ish\n" \ + "tlbi " #_type ", %0" : : "r" (v)); \ +} +#endif /* ERRATA_A57_813419 */ + +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) +#if ERRATA_A57_813419 +DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) +DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) +#else +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) +#endif +DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) + +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) +#if ERRATA_A57_813419 +DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) +DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) +#else +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) +#endif + +/******************************************************************************* + * Cache maintenance accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) + +/******************************************************************************* + * Address translation accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) + +void flush_dcache_range(uintptr_t addr, size_t size); +void clean_dcache_range(uintptr_t addr, size_t size); +void inv_dcache_range(uintptr_t addr, size_t size); + +void dcsw_op_louis(u_register_t op_type); +void dcsw_op_all(u_register_t op_type); + +void disable_mmu(void); +void disable_mmu_icache(void); + +/******************************************************************************* + * Misc. accessor prototypes + ******************************************************************************/ + +#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) +#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) +DEFINE_SYSOP_FUNC(wfi) +DEFINE_SYSOP_FUNC(wfe) +DEFINE_SYSOP_FUNC(sev) +DEFINE_SYSOP_TYPE_FUNC(dsb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, st) +DEFINE_SYSOP_TYPE_FUNC(dmb, ld) +DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) +DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) +DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) +DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) +DEFINE_SYSOP_TYPE_FUNC(dmb, osh) +DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) +DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) +DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) +DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) +DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) +DEFINE_SYSOP_TYPE_FUNC(dmb, ish) +DEFINE_SYSOP_FUNC(isb) + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +DEFINE_SYSREG_READ_FUNC(midr_el1) +DEFINE_SYSREG_READ_FUNC(mpidr_el1) +DEFINE_SYSREG_RW_FUNCS(vpidr_el2) +DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) + +DEFINE_SYSREG_RW_FUNCS(par_el1) + +DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_afr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1) + +DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) + +DEFINE_SYSREG_READ_FUNC(CurrentEl) +DEFINE_SYSREG_READ_FUNC(ctr_el0) +DEFINE_SYSREG_RW_FUNCS(daif) +DEFINE_SYSREG_RW_FUNCS(nzcv) +DEFINE_SYSREG_READ_FUNC(spsel) + +DEFINE_SYSREG_RW_FUNCS(spsr_el1) +DEFINE_SYSREG_RW_FUNCS(spsr_el2) +DEFINE_SYSREG_RW_FUNCS(spsr_el3) + +DEFINE_SYSREG_RW_FUNCS(elr_el1) +DEFINE_SYSREG_RW_FUNCS(elr_el2) +DEFINE_SYSREG_RW_FUNCS(elr_el3) + +DEFINE_SYSREG_RW_FUNCS(scr_el3) +DEFINE_SYSREG_RW_FUNCS(hcr_el2) + +DEFINE_SYSREG_RW_FUNCS(vbar_el1) +DEFINE_SYSREG_RW_FUNCS(vbar_el2) +DEFINE_SYSREG_RW_FUNCS(vbar_el3) + +DEFINE_SYSREG_RW_FUNCS(sctlr_el1) +DEFINE_SYSREG_RW_FUNCS(sctlr_el2) +DEFINE_SYSREG_RW_FUNCS(sctlr_el3) + +DEFINE_SYSREG_RW_FUNCS(esr_el1) +DEFINE_SYSREG_RW_FUNCS(esr_el2) +DEFINE_SYSREG_RW_FUNCS(esr_el3) + +DEFINE_SYSREG_RW_FUNCS(far_el1) +DEFINE_SYSREG_RW_FUNCS(far_el2) +DEFINE_SYSREG_RW_FUNCS(far_el3) + +DEFINE_SYSREG_RW_FUNCS(mair_el1) +DEFINE_SYSREG_RW_FUNCS(mair_el2) +DEFINE_SYSREG_RW_FUNCS(mair_el3) + +DEFINE_SYSREG_RW_FUNCS(amair_el1) +DEFINE_SYSREG_RW_FUNCS(amair_el2) +DEFINE_SYSREG_RW_FUNCS(amair_el3) + +DEFINE_SYSREG_RW_FUNCS(tcr_el1) +DEFINE_SYSREG_RW_FUNCS(tcr_el2) +DEFINE_SYSREG_RW_FUNCS(tcr_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) +DEFINE_SYSREG_RW_FUNCS(vttbr_el2) + +DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR) +DEFINE_RENAME_SYSREG_RW_FUNCS(tpidr2_el0, TPIDR2_EL0) +DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el2, SMCR_EL2) + +/* Armv8.1 Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(pan, PAN) + +/* Armv8.2 Registers */ +DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) + +#define IS_IN_EL(x) \ + (GET_EL(read_CurrentEl()) == MODE_EL##x) + +#define IS_IN_EL1() IS_IN_EL(1) +#define IS_IN_EL2() IS_IN_EL(2) +#define IS_IN_EL3() IS_IN_EL(3) + +static inline unsigned int get_current_el(void) +{ + return GET_EL(read_CurrentEl()); +} + +/* + * Check if an EL is implemented from AA64PFR0 register fields. + */ +static inline uint64_t el_implemented(unsigned int el) +{ + if (el > 3U) { + return EL_IMPL_NONE; + } else { + unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; + + return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; + } +} + +#endif /* ARCH_HELPERS_H */ diff --git a/val/xlat_tables_v2/include/asm_macros.S b/val/xlat_tables_v2/include/asm_macros.S new file mode 100644 index 00000000..d1fc65c2 --- /dev/null +++ b/val/xlat_tables_v2/include/asm_macros.S @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef ASM_MACROS_S +#define ASM_MACROS_S + +#include +#include + +/* + * TLBI instruction with type specifier that implements the workaround for + * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76. + */ +#if ERRATA_A57_813419 || ERRATA_A76_1286807 +#define TLB_INVALIDATE(_type) \ + tlbi _type; \ + dsb ish; \ + tlbi _type +#else +#define TLB_INVALIDATE(_type) \ + tlbi _type +#endif + + + /* + * Create a stack frame at the start of an assembly function. Will also + * add all necessary call frame information (cfi) directives for a + * pretty stack trace. This is necessary as there is quite a bit of + * flexibility within a stack frame and the stack pointer can move + * around throughout the function. If the debugger isn't told where to + * find things, it gets lost, gives up and displays nothing. So inform + * the debugger of what's where. Anchor the Canonical Frame Address + * (CFA; the thing used to track what's where) to the frame pointer as + * that's not expected to change in the function body and no extra + * bookkeeping will be necessary, allowing free movement of the sp + * + * _frame_size: requested space for caller to use. Must be a mutliple + * of 16 for stack pointer alignment + */ + .macro func_prologue _frame_size=0 + .if \_frame_size & 0xf + .error "frame_size must have stack pointer alignment (multiple of 16)" + .endif + + /* put frame record at top of frame */ + stp x29, x30, [sp, #-0x10]! + mov x29,sp + .if \_frame_size + sub sp, sp, #\_frame_size + .endif + + /* point CFA to start of frame record, i.e. x29 + 0x10 */ + .cfi_def_cfa x29, 0x10 + /* inform it about x29, x30 locations */ + .cfi_offset x30, -0x8 + .cfi_offset x29, -0x10 + .endm + + /* + * Clear stack frame at the end of an assembly function. + * + * _frame_size: the value passed to func_prologue + */ + .macro func_epilogue _frame_size=0 + /* remove requested space */ + .if \_frame_size + add sp, sp, #\_frame_size + .endif + ldp x29, x30, [sp], #0x10 + .endm + + + .macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro smc_check label + mrs x0, esr_el3 + ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x0, #EC_AARCH64_SMC + b.ne $label + .endm + + /* + * Declare the exception vector table, enforcing it is aligned on a + * 2KB boundary, as required by the ARMv8 architecture. + * Use zero bytes as the fill value to be stored in the padding bytes + * so that it inserts illegal AArch64 instructions. This increases + * security, robustness and potentially facilitates debugging. + */ + .macro vector_base label, section_name=.vectors + .section \section_name, "ax" + .align 11, 0 + \label: + .endm + + /* + * Create an entry in the exception vector table, enforcing it is + * aligned on a 128-byte boundary, as required by the ARMv8 architecture. + * Use zero bytes as the fill value to be stored in the padding bytes + * so that it inserts illegal AArch64 instructions. This increases + * security, robustness and potentially facilitates debugging. + */ + .macro vector_entry label, section_name=.vectors + .cfi_sections .debug_frame + .section \section_name, "ax" + .align 7, 0 + .type \label, %function + .cfi_startproc + \label: + .endm + + /* + * Add the bytes until fill the full exception vector, whose size is always + * 32 instructions. If there are more than 32 instructions in the + * exception vector then an error is emitted. + */ + .macro end_vector_entry label + .cfi_endproc + .fill \label + (32 * 4) - . + .endm + + /* + * This macro calculates the base address of the current CPU's MP stack + * using the plat_my_core_pos() index, the name of the stack storage + * and the size of each stack + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_my_mp_stack _name, _size + bl plat_my_core_pos + adrp x2, (\_name + \_size) + add x2, x2, :lo12:(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm + + /* + * This macro calculates the base address of a UP stack using the + * name of the stack storage and the size of the stack + * Out: X0 = physical address of stack base + */ + .macro get_up_stack _name, _size + adrp x0, (\_name + \_size) + add x0, x0, :lo12:(\_name + \_size) + .endm + + /* + * Helper macro to generate the best mov/movk combinations according + * the value to be moved. The 16 bits from '_shift' are tested and + * if not zero, they are moved into '_reg' without affecting + * other bits. + */ + .macro _mov_imm16 _reg, _val, _shift + .if (\_val >> \_shift) & 0xffff + .if (\_val & (1 << \_shift - 1)) + movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift + .else + mov \_reg, \_val & (0xffff << \_shift) + .endif + .endif + .endm + + /* + * Helper macro to load arbitrary values into 32 or 64-bit registers + * which generates the best mov/movk combinations. Many base addresses + * are 64KB aligned the macro will eliminate updating bits 15:0 in + * that case + */ + .macro mov_imm _reg, _val + .if (\_val) == 0 + mov \_reg, #0 + .else + _mov_imm16 \_reg, (\_val), 0 + _mov_imm16 \_reg, (\_val), 16 + _mov_imm16 \_reg, (\_val), 32 + _mov_imm16 \_reg, (\_val), 48 + .endif + .endm + + /* + * Macro to mark instances where we're jumping to a function and don't + * expect a return. To provide the function being jumped to with + * additional information, we use 'bl' instruction to jump rather than + * 'b'. + * + * Debuggers infer the location of a call from where LR points to, which + * is usually the instruction after 'bl'. If this macro expansion + * happens to be the last location in a function, that'll cause the LR + * to point a location beyond the function, thereby misleading debugger + * back trace. We therefore insert a 'nop' after the function call for + * debug builds, unless 'skip_nop' parameter is non-zero. + */ + .macro no_ret _func:req, skip_nop=0 + bl \_func +#if DEBUG + .ifeq \skip_nop + nop + .endif +#endif + .endm + + /* + * Reserve space for a spin lock in assembly file. + */ + .macro define_asm_spinlock _name:req + .align SPINLOCK_ASM_ALIGN + \_name: + .space SPINLOCK_ASM_SIZE + .endm + + /* + * With RAS extension executes esb instruction, else NOP + */ + .macro esb + .inst 0xd503221f + .endm + + /* + * Helper macro to read system register value into x0 + */ + .macro read reg:req +#if ENABLE_BTI + bti j +#endif + mrs x0, \reg + ret + .endm + + /* + * Helper macro to write value from x1 to system register + */ + .macro write reg:req +#if ENABLE_BTI + bti j +#endif + msr \reg, x1 + ret + .endm + + /* + * The "sb" instruction was introduced later into the architecture, + * so not all toolchains understand it. Some deny its usage unless + * a supported processor is specified on the build command line. + * Use sb's system register encoding to work around this, we already + * guard the sb execution with a feature flag. + */ + + .macro sb_barrier_insn + msr SYSREG_SB, xzr + .endm + + /* + * Macro for using speculation barrier instruction introduced by + * FEAT_SB, if it's enabled. + */ + .macro speculation_barrier +#if ENABLE_FEAT_SB + sb_barrier_insn +#else + dsb sy + isb +#endif + .endm + + /* + * Macro for mitigating against speculative execution beyond ERET. Uses the + * speculation barrier instruction introduced by FEAT_SB, if it's enabled. + */ + .macro exception_return + eret +#if ENABLE_FEAT_SB + sb_barrier_insn +#else + dsb nsh + isb +#endif + .endm + +#endif /* ASM_MACROS_S */ diff --git a/val/xlat_tables_v2/include/asm_macros_common.S b/val/xlat_tables_v2/include/asm_macros_common.S new file mode 100644 index 00000000..f9dcada9 --- /dev/null +++ b/val/xlat_tables_v2/include/asm_macros_common.S @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef ASM_MACROS_COMMON_S +#define ASM_MACROS_COMMON_S + + /* + * This macro is used to create a function label and place the + * code into a separate text section based on the function name + * to enable elimination of unused code during linking. It also adds + * basic debug information to enable call stack printing most of the + * time. The optional _align parameter can be used to force a + * non-standard alignment (indicated in powers of 2). The default is + * _align=2 because both Aarch32 and Aarch64 instructions must be + * word aligned. Do *not* try to use a raw .align directive. Since func + * switches to a new section, this would not have the desired effect. + */ + .macro func _name, _align=2 + /* + * Add Call Frame Information entry in the .debug_frame section for + * debugger consumption. This enables callstack printing in debuggers. + * This does not use any space in the final loaded binary, only in the + * ELF file. + * Note that a function manipulating the CFA pointer location (i.e. the + * x29 frame pointer on AArch64) should declare it using the + * appropriate .cfi* directives, or be prepared to have a degraded + * debugging experience. + */ + .cfi_sections .debug_frame + .section .text.asm.\_name, "ax" + .type \_name, %function + /* + * .cfi_startproc and .cfi_endproc are needed to output entries in + * .debug_frame + */ + .cfi_startproc + .align \_align + \_name: +#if ENABLE_BTI + /* When Branch Target Identification is enabled, insert "bti jc" + * instruction to enable indirect calls and branches + */ + bti jc +#endif + .endm + + /* + * This macro is used to mark the end of a function. + */ + .macro endfunc _name + .cfi_endproc + .size \_name, . - \_name + .endm + + /* + * Theses macros are used to create function labels for deprecated + * APIs. If ERROR_DEPRECATED is non zero, the callers of these APIs + * will fail to link and cause build failure. + */ +#if ERROR_DEPRECATED + .macro func_deprecated _name + func deprecated\_name + .endm + + .macro endfunc_deprecated _name + endfunc deprecated\_name + .endm +#else + .macro func_deprecated _name + func \_name + .endm + + .macro endfunc_deprecated _name + endfunc \_name + .endm +#endif + + /* + * Helper assembler macro to count trailing zeros. The output is + * populated in the `TZ_COUNT` symbol. + */ + .macro count_tz _value, _tz_count + .if \_value + count_tz "(\_value >> 1)", "(\_tz_count + 1)" + .else + .equ TZ_COUNT, (\_tz_count - 1) + .endif + .endm + + /* + * This macro declares an array of 1 or more stacks, properly + * aligned and in the requested section + */ +#define DEFAULT_STACK_ALIGN (1 << 6) /* In case the caller doesnt provide alignment */ + + .macro declare_stack _name, _section, _size, _count, _align=DEFAULT_STACK_ALIGN + count_tz \_align, 0 + .if (\_align - (1 << TZ_COUNT)) + .error "Incorrect stack alignment specified (Must be a power of 2)." + .endif + .if ((\_size & ((1 << TZ_COUNT) - 1)) <> 0) + .error "Stack size not correctly aligned" + .endif + .section \_section, "aw", %nobits + .align TZ_COUNT + \_name: + .space ((\_count) * (\_size)), 0 + .endm + + +#endif /* ASM_MACROS_COMMON_S */ diff --git a/val/xlat_tables_v2/include/assert.h b/val/xlat_tables_v2/include/assert.h new file mode 100644 index 00000000..092b9664 --- /dev/null +++ b/val/xlat_tables_v2/include/assert.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include + +#define assert_func PLAT_ASSERT_FUNC + +extern void assert_func(const char *e, uint64_t line, const char *file); + +#define assert(e) ((e) ? (void)0 : assert_func(#e, __LINE__, __FILE__)) diff --git a/val/xlat_tables_v2/include/assert_macros.S b/val/xlat_tables_v2/include/assert_macros.S new file mode 100644 index 00000000..36f7fa83 --- /dev/null +++ b/val/xlat_tables_v2/include/assert_macros.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef ASSERT_MACROS_S +#define ASSERT_MACROS_S + + /* + * Assembler macro to enable asm_assert. Use this macro wherever + * assert is required in assembly. Please note that the macro makes + * use of label '300' to provide the logic and the caller + * should make sure that this label is not used to branch prior + * to calling this macro. + */ +#define ASM_ASSERT(_cc) \ +.ifndef .L_assert_filename ;\ + .pushsection .rodata.str1.1, "aS" ;\ + .L_assert_filename: ;\ + .string __FILE__ ;\ + .popsection ;\ +.endif ;\ + b._cc 300f ;\ + adr x0, .L_assert_filename ;\ + mov x1, __LINE__ ;\ + b asm_assert ;\ +300: + +#endif /* ASSERT_MACROS_S */ diff --git a/val/xlat_tables_v2/include/cdefs.h b/val/xlat_tables_v2/include/cdefs.h new file mode 100644 index 00000000..468b2bb6 --- /dev/null +++ b/val/xlat_tables_v2/include/cdefs.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _CDEFS_H +#define _CDEFS_H + +#define __dead2 __attribute__((__noreturn__)) +#define __deprecated __attribute__((__deprecated__)) +#define __packed __attribute__((__packed__)) +#define __used __attribute__((__used__)) +#define __unused __attribute__((__unused__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) + +#define __STRING(x) #x +#define __XSTRING(x) __STRING(x) + +/* + * For those constants to be shared between C and other sources, apply a 'U', + * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid + * undefined or unintended behaviour. + * + * The GNU assembler and linker do not support these suffixes (it causes the + * build process to fail) therefore the suffix is omitted when used in linker + * scripts and assembler files. +*/ +#if defined(__LINKER__) || defined(__ASSEMBLY__) +# define U(_x) (_x) +# define UL(_x) (_x) +# define ULL(_x) (_x) +# define L(_x) (_x) +# define LL(_x) (_x) +#else +# define U(_x) (_x##U) +# define UL(_x) (_x##UL) +# define ULL(_x) (_x##ULL) +# define L(_x) (_x##L) +# define LL(_x) (_x##LL) +#endif + +#define INPLACE(regfield, val) \ + (((val) + UL(0)) << (regfield##_SHIFT)) + +#define EXTRACT(regfield, reg) \ + (((reg) & MASK(regfield)) >> (regfield##_SHIFT)) + +#define MASK(regfield) \ + ((~0UL >> (64UL - (regfield##_WIDTH))) << (regfield##_SHIFT)) + +#define BIT_MASK_ULL(_msb, _lsb) \ + ((~ULL(0) >> (63UL - (_msb))) & (~ULL(0) << (_lsb))) + +#define ALIGNED(_size, _alignment) \ + (((unsigned long)(_size) % (_alignment)) == UL(0)) + +#define ARRAY_SIZE(a) \ + (sizeof(a) / sizeof((a)[0])) + +#define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory") + +#define IS_POWER_OF_TWO(x) \ + (((x) & ((x) - 1)) == 0) + +/* + * The round_up() macro rounds up a value to the given boundary in a + * type-agnostic yet type-safe manner. The boundary must be a power of two. + * In other words, it computes the smallest multiple of boundary which is + * greater than or equal to value. + * + * round_down() is similar but rounds the value down instead. + */ +#define round_boundary(value, boundary) \ + ((__typeof__(value))((boundary) - 1)) + +#define round_up(value, boundary) \ + ((((value) - 1) | round_boundary(value, boundary)) + 1) + +#define round_down(value, boundary) \ + ((value) & ~round_boundary(value, boundary)) + +#endif /* _CDEFS_H */ diff --git a/val/xlat_tables_v2/include/config.h b/val/xlat_tables_v2/include/config.h new file mode 100644 index 00000000..a0c4fff2 --- /dev/null +++ b/val/xlat_tables_v2/include/config.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#if defined(XLAT_CONFIG_FILE) +#include XLAT_CONFIG_FILE +#else +#error "Please include -DXLAT_CONFIG_FILE during compilation" +#endif diff --git a/val/xlat_tables_v2/include/debug.h b/val/xlat_tables_v2/include/debug.h new file mode 100644 index 00000000..6ed24fde --- /dev/null +++ b/val/xlat_tables_v2/include/debug.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include + +#define RSI_VERSION (0xC4000190) +#define RSI_REQ_VERSION ((1 << 16) | 0) + +typedef enum { + INFO = 1, + DBG = 2, + TEST = 3, + WARN = 4, + ERROR = 5, + ALWAYS = 9 +} print_verbosity_t; + +#define print_func PLAT_PRINT_FUNC +extern void print_func(print_verbosity_t verbosity, const char *fmt, ...); + +#ifdef PLAT_REALM_PRINT_FUNC +#define realm_print_func PLAT_REALM_PRINT_FUNC +extern void realm_print_func(print_verbosity_t verbosity, const char *fmt, ...); + +#define LOG(print_verbosity, fmt, ...) \ + do { \ + if (print_verbosity >= VERBOSITY) \ + { \ + if (in_realm()) \ + { \ + realm_print_func(print_verbosity, fmt, ##__VA_ARGS__); \ + if (print_verbosity == ERROR) \ + realm_print_func(ERROR, "Check failed at %s , line:%d", \ + __FILE__, __LINE__); \ + } \ + else \ + { \ + print_func(print_verbosity, fmt, ##__VA_ARGS__); \ + if (print_verbosity == ERROR) \ + print_func(ERROR, "Check failed at %s , line:%d", \ + __FILE__, __LINE__); \ + } \ + } \ + } while (0); + +static inline bool in_realm(void) +{ + struct smc_result smc_res; + + monitor_call_with_res(RSI_VERSION, RSI_REQ_VERSION, + 0UL, 0UL, 0UL, 0UL, 0UL, &smc_res); + + if (smc_res.x[0] != SMC_NOT_SUPPORTED) + { + return true; + } + + return false; +} + +#else +#define LOG(print_verbosity, fmt, ...) \ + do { \ + if (print_verbosity >= VERBOSITY) \ + { \ + print_func(print_verbosity, fmt, ##__VA_ARGS__); \ + if (print_verbosity == ERROR) \ + print_func(ERROR, "Check failed at %s , line:%d", \ + __FILE__, __LINE__); \ + } \ + } while (0); + +#endif diff --git a/val/xlat_tables_v2/include/def.h b/val/xlat_tables_v2/include/def.h new file mode 100644 index 00000000..2785ae35 --- /dev/null +++ b/val/xlat_tables_v2/include/def.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __DEF_H_ +#define __DEF_H_ + +#include "arch.h" + +#define VAL_TG0_4K 0x0 +#define VAL_TG0_64K 0x1 +#define VAL_TG0_16K 0x2 +#define PAGE_SIZE_4K 0x1000 +#define PAGE_SIZE_16K (4 * 0x1000) +#define PAGE_SIZE_64K (16 * 0x1000) +#define PAGE_BITS_4K 12 +#define PAGE_BITS_16K 14 +#define PAGE_BITS_64K 16 + +#define PLATFORM_PAGE_SIZE 0x1000 + +#if (PLATFORM_PAGE_SIZE == PAGE_SIZE_4K) + #define PAGE_ALIGNMENT PAGE_SIZE_4K + #define PAGE_SIZE PAGE_SIZE_4K + #define TCR_TG0 VAL_TG0_4K +#elif (PLATFORM_PAGE_SIZE == PAGE_SIZE_16K) + #define PAGE_ALIGNMENT PAGE_SIZE_16K + #define PAGE_SIZE PAGE_SIZE_16K + #define TCR_TG0 VAL_TG0_16K +#elif (PLATFORM_PAGE_SIZE == PAGE_SIZE_64K) + #define PAGE_ALIGNMENT PAGE_SIZE_64K + #define PAGE_SIZE PAGE_SIZE_64K + #define TCR_TG0 VAL_TG0_64K +#else + #error "Undefined value for PLATFORM_PAGE_SIZE" +#endif + +/******************************************************************************* + * Used to align variables on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* _VAL_DEF_H_ */ diff --git a/val/xlat_tables_v2/include/smc.h b/val/xlat_tables_v2/include/smc.h new file mode 100644 index 00000000..68e74e45 --- /dev/null +++ b/val/xlat_tables_v2/include/smc.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SMC_H +#define SMC_H + +/* SMCCC return codes */ +#define SMC_SUCCESS (unsigned long)(0) +#define SMC_NOT_SUPPORTED (unsigned long)(-1) +#define SMC_NOT_REQUIRED (unsigned long)(-2) +#define SMC_INVALID_PARAMETER (unsigned long)(-3) + +#define SMC_UNKNOWN (unsigned long)(-1) + +#ifndef __ASSEMBLER__ +unsigned long monitor_call(unsigned long id, + unsigned long arg0, + unsigned long arg1, + unsigned long arg2, + unsigned long arg3, + unsigned long arg4, + unsigned long arg5); + +/* Result registers X0-X4 */ +#define SMC_RESULT_REGS 5U + +struct smc_result { + unsigned long x[SMC_RESULT_REGS]; +}; + +void monitor_call_with_res(unsigned long id, + unsigned long arg0, + unsigned long arg1, + unsigned long arg2, + unsigned long arg3, + unsigned long arg4, + unsigned long arg5, + struct smc_result *res); + +#endif /* __ASSEMBLER__ */ + +#endif /* SMC_H */ diff --git a/val/xlat_tables_v2/include/xlat_mmu_helpers.h b/val/xlat_tables_v2/include/xlat_mmu_helpers.h new file mode 100644 index 00000000..6c2de42b --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_mmu_helpers.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_MMU_HELPERS_H +#define XLAT_MMU_HELPERS_H + +/* + * The following flags are passed to enable_mmu_xxx() to override the default + * values used to program system registers while enabling the MMU. + */ + +/* + * When this flag is used, all data access to Normal memory from this EL and all + * Normal memory accesses to the translation tables of this EL are non-cacheable + * for all levels of data and unified cache until the caches are enabled by + * setting the bit SCTLR_ELx.C. + */ +#define DISABLE_DCACHE (U(1) << 0) + +/* + * Mark the translation tables as non-cacheable for the MMU table walker, which + * is a different observer from the PE/CPU. If the flag is not specified, the + * tables are cacheable for the MMU table walker. + * + * Note that, as far as the PE/CPU observer is concerned, the attributes used + * are the ones specified in the translation tables themselves. The MAIR + * register specifies the cacheability through the field AttrIndx of the lower + * attributes of the translation tables. The shareability is specified in the SH + * field of the lower attributes. + * + * The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn + * and SHn of the TCR register to access the translation tables. + * + * The attributes specified in the TCR register and the tables can be different + * as there are no checks to prevent that. Special care must be taken to ensure + * that there aren't mismatches. The behaviour in that case is described in the + * sections 'Mismatched memory attributes' in the ARMv8 ARM. + */ +#define XLAT_TABLE_NC (U(1) << 1) + +/* + * Offsets into a mmu_cfg_params array generated by setup_mmu_cfg(). All + * parameters are 64 bits wide. + */ +#define MMU_CFG_MAIR 0 +#define MMU_CFG_TCR 1 +#define MMU_CFG_TTBR0 2 +#define MMU_CFG_PARAM_MAX 3 + +#ifndef __ASSEMBLER__ + +#include +#include +#include + + +/* + * Return the values that the MMU configuration registers must contain for the + * specified translation context. `params` must be a pointer to array of size + * MMU_CFG_PARAM_MAX. + */ +void setup_mmu_cfg(uint64_t *params, unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, + uintptr_t max_va, int xlat_regime); + +#ifdef __aarch64__ +/* AArch64 specific translation table APIs */ +void enable_mmu_el1(unsigned int flags); +void enable_mmu_el2(unsigned int flags); +void enable_mmu_el3(unsigned int flags); +void enable_mmu(unsigned int flags); + +void enable_mmu_direct_el1(unsigned int flags); +void enable_mmu_direct_el2(unsigned int flags); +void enable_mmu_direct_el3(unsigned int flags); +#else +/* AArch32 specific translation table API */ +void enable_mmu_svc_mon(unsigned int flags); +void enable_mmu_hyp(unsigned int flags); + +void enable_mmu_direct_svc_mon(unsigned int flags); +void enable_mmu_direct_hyp(unsigned int flags); +#endif /* __aarch64__ */ + +bool xlat_arch_is_granule_size_supported(size_t size); +size_t xlat_arch_get_max_supported_granule_size(void); + +#endif /* __ASSEMBLER__ */ + +#endif /* XLAT_MMU_HELPERS_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables.h b/val/xlat_tables_v2/include/xlat_tables.h new file mode 100644 index 00000000..35fa87c4 --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_H +#define XLAT_TABLES_H + +#include + +#ifndef __ASSEMBLER__ +#include +#include + +#include + +/* Helper macro to define entries for mmap_region_t. It creates + * identity mappings for each region. + */ +#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr) + +/* Helper macro to define entries for mmap_region_t. It allows to + * re-map address mappings from 'pa' to 'va' for each region. + */ +#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)} + +/* + * Shifts and masks to access fields of an mmap attribute + */ +#define MT_TYPE_MASK U(0x7) +#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) +/* Access permissions (RO/RW) */ +#define MT_PERM_SHIFT U(3) +/* Security state (SECURE/NS) */ +#define MT_SEC_SHIFT U(4) +/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ +#define MT_EXECUTE_SHIFT U(5) + +/* + * Memory mapping attributes + */ + +/* + * Memory types supported. + * These are organised so that, going down the list, the memory types are + * getting weaker; conversely going up the list the memory types are getting + * stronger. + */ +#define MT_DEVICE U(0) +#define MT_NON_CACHEABLE U(1) +#define MT_MEMORY U(2) +/* Values up to 7 are reserved to add new memory types in the future */ + +#define MT_RO (U(0) << MT_PERM_SHIFT) +#define MT_RW (U(1) << MT_PERM_SHIFT) + +#define MT_SECURE (U(0) << MT_SEC_SHIFT) +#define MT_NS (U(1) << MT_SEC_SHIFT) + +/* + * Access permissions for instruction execution are only relevant for normal + * read-only memory, i.e. MT_MEMORY | MT_RO. They are ignored (and potentially + * overridden) otherwise: + * - Device memory is always marked as execute-never. + * - Read-write normal memory is always marked as execute-never. + */ +#define MT_EXECUTE (U(0) << MT_EXECUTE_SHIFT) +#define MT_EXECUTE_NEVER (U(1) << MT_EXECUTE_SHIFT) + +/* Compound attributes for most common usages */ +#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) +#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) + +/* Memory type for EL3 regions */ +#if ENABLE_RME +#error FEAT_RME requires version 2 of the Translation Tables Library +#else +#define EL3_PAS MT_SECURE +#endif + +/* + * Structure for specifying a single region of memory. + */ +typedef struct mmap_region { + unsigned long long base_pa; + uintptr_t base_va; + size_t size; + unsigned int attr; +} mmap_region_t; + +/* Generic translation table APIs */ +void init_xlat_tables(void); +void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, + size_t size, unsigned int attr); +void mmap_add(const mmap_region_t *mm); + +#endif /*__ASSEMBLER__*/ +#endif /* XLAT_TABLES_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_aarch64.h b/val/xlat_tables_v2/include/xlat_tables_aarch64.h new file mode 100644 index 00000000..002ed933 --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_aarch64.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_AARCH64_H +#define XLAT_TABLES_AARCH64_H + +#include + +#if !defined(PAGE_SIZE) +#error "PAGE_SIZE is not defined." +#endif + +/* + * Encode a Physical Address Space size for its use in TCR_ELx. + */ +unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr); + +/* + * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page + * granularity. For 4KB granularity, a level 0 table descriptor doesn't support + * block translation. For 16KB, the same thing happens to levels 0 and 1. For + * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture + * Reference Manual (DDI 0487A.k) for more information. + * + * The define below specifies the first table level that allows block + * descriptors. + */ +#if PAGE_SIZE == PAGE_SIZE_4KB +# define MIN_LVL_BLOCK_DESC U(1) +#elif (PAGE_SIZE == PAGE_SIZE_16KB) || (PAGE_SIZE == PAGE_SIZE_64KB) +# define MIN_LVL_BLOCK_DESC U(2) +#endif + +#define XLAT_TABLE_LEVEL_MIN U(0) + +/* + * Define the architectural limits of the virtual address space in AArch64 + * state. + * + * TCR.TxSZ is calculated as 64 minus the width of said address space. + * The value of TCR.TxSZ must be in the range 16 to 39 [1] or 48 [2], + * depending on Small Translation Table Support which means that + * the virtual address space width must be in the range 48 to 25 or 16 bits. + * + * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information: + * Page 1730: 'Input address size', 'For all translation stages'. + * [2] See section 12.2.55 in the ARMv8-A Architecture Reference Manual + * (DDI 0487D.a) + */ +/* Maximum value of TCR_ELx.T(0,1)SZ is 39 */ +#define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MAX)) + +/* Maximum value of TCR_ELx.T(0,1)SZ is 48 */ +#define MIN_VIRT_ADDR_SPACE_SIZE_TTST \ + (ULL(1) << (U(64) - TCR_TxSZ_MAX_TTST)) +#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MIN)) + +/* + * Here we calculate the initial lookup level from the value of the given + * virtual address space size. For a 4 KB page size, + * - level 0 supports virtual address spaces of widths 48 to 40 bits; + * - level 1 from 39 to 31; + * - level 2 from 30 to 22. + * - level 3 from 21 to 16. + * + * Small Translation Table (Armv8.4-TTST) support allows the starting level + * of the translation table from 3 for 4KB granularity. See section 12.2.55 in + * the ARMv8-A Architecture Reference Manual (DDI 0487D.a). In Armv8.3 and below + * wider or narrower address spaces are not supported. As a result, level 3 + * cannot be used as initial lookup level with 4 KB granularity. See section + * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information. + * + * For example, for a 35-bit address space (i.e. virt_addr_space_size == + * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table + * D4-11 in the ARM ARM, the initial lookup level for an address space like that + * is 1. + * + * Note that this macro assumes that the given virtual address space size is + * valid. + */ +#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \ + (((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \ + ? 0U \ + : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \ + ? 1U \ + : (((_virt_addr_space_sz) > (ULL(1) << L2_XLAT_ADDRESS_SHIFT)) \ + ? 2U : 3U))) + +#endif /* XLAT_TABLES_AARCH64_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_arch.h b/val/xlat_tables_v2/include/xlat_tables_arch.h new file mode 100644 index 00000000..22f98090 --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_arch.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_ARCH_H +#define XLAT_TABLES_ARCH_H + +#ifdef __aarch64__ +#include "xlat_tables_aarch64.h" +#else +#include "xlat_tables_aarch32.h" +#endif + +/* + * Evaluates to 1 if the given physical address space size is a power of 2, + * or 0 if it's not. + */ +#define CHECK_PHY_ADDR_SPACE_SIZE(size) \ + (IS_POWER_OF_TWO(size)) + +/* + * Compute the number of entries required at the initial lookup level to address + * the whole virtual address space. + */ +#define GET_NUM_BASE_LEVEL_ENTRIES(addr_space_size) \ + ((addr_space_size) >> \ + XLAT_ADDR_SHIFT(GET_XLAT_TABLE_LEVEL_BASE(addr_space_size))) + +#endif /* XLAT_TABLES_ARCH_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_compat.h b/val/xlat_tables_v2/include/xlat_tables_compat.h new file mode 100644 index 00000000..28eabab5 --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_compat.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_COMPAT_H +#define XLAT_TABLES_COMPAT_H + +#if XLAT_TABLES_LIB_V2 +#include +#else +#include +#endif + +#endif /* XLAT_TABLES_COMPAT_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_defs.h b/val/xlat_tables_v2/include/xlat_tables_defs.h new file mode 100644 index 00000000..17e4bd53 --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_defs.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_DEFS_H +#define XLAT_TABLES_DEFS_H + +#include +#include +#include + +#include + +/* Miscellaneous MMU related constants */ +#define NUM_2MB_IN_GB (U(1) << 9) +#define NUM_4K_IN_2MB (U(1) << 9) +#define NUM_GB_IN_4GB (U(1) << 2) + +#define TWO_MB_SHIFT U(21) +#define ONE_GB_SHIFT U(30) +#define FOUR_KB_SHIFT U(12) + +#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) +#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) +#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) + +#define PAGE_SIZE_4KB U(4096) +#define PAGE_SIZE_16KB U(16384) +#define PAGE_SIZE_64KB U(65536) + +#define INVALID_DESC U(0x0) +/* + * A block descriptor points to a region of memory bigger than the granule size + * (e.g. a 2MB region when the granule size is 4KB). + */ +#define BLOCK_DESC U(0x1) /* Table levels 0-2 */ +/* A table descriptor points to the next level of translation table. */ +#define TABLE_DESC U(0x3) /* Table levels 0-2 */ +/* + * A page descriptor points to a page, i.e. a memory region whose size is the + * translation granule size (e.g. 4KB). + */ +#define PAGE_DESC U(0x3) /* Table level 3 */ + +#define DESC_MASK U(0x3) + +#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT +#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT +#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT + +/* XN: Translation regimes that support one VA range (EL2 and EL3). */ +#define XN (ULL(1) << 2) +/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */ +#define UXN (ULL(1) << 2) +#define PXN (ULL(1) << 1) +#define CONT_HINT (ULL(1) << 0) +#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) + +#define NON_GLOBAL (U(1) << 9) +#define ACCESS_FLAG (U(1) << 8) +#define NSH (U(0x0) << 6) +#define OSH (U(0x2) << 6) +#define ISH (U(0x3) << 6) + +#ifdef __aarch64__ +/* Guarded Page bit */ +#define GP (ULL(1) << 50) +#endif + +#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) + +/* + * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or + * 64KB. However, only 4KB are supported at the moment. + */ +#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT +//#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) +#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) + +#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING +#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */ +#else +#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */ +#endif +#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) + +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ +#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) + +#define XLAT_TABLE_LEVEL_MAX U(3) + +/* Values for number of entries in each MMU translation table */ +#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - U(1)) + +/* Values to convert a memory address to an index into a translation table */ +#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ + ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) + +#define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) +/* Mask to get the bits used to index inside a block of a certain level */ +#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) +/* Mask to get the address bits common to a block of a certain table level*/ +#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) +/* + * Extract from the given virtual address the index into the given lookup level. + * This macro assumes the system is using the 4KB translation granule. + */ +#define XLAT_TABLE_IDX(virtual_addr, level) \ + (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF)) + +/* + * The ARMv8 translation table descriptor format defines AP[2:1] as the Access + * Permissions bits, and does not define an AP[0] bit. + * + * AP[1] is valid only for a stage 1 translation that supports two VA ranges + * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1 + * when stage 1 translations can only support one VA range. + */ +#define AP2_SHIFT U(0x7) +#define AP2_RO ULL(0x1) +#define AP2_RW ULL(0x0) + +#define AP1_SHIFT U(0x6) +#define AP1_ACCESS_UNPRIVILEGED ULL(0x1) +#define AP1_NO_ACCESS_UNPRIVILEGED ULL(0x0) +#define AP1_RES1 ULL(0x1) + +/* + * The following definitions must all be passed to the LOWER_ATTRS() macro to + * get the right bitmask. + */ +#define AP_RO (AP2_RO << 5) +#define AP_RW (AP2_RW << 5) +#define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4) +#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4) +#define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4) +#define NS (U(0x1) << 3) +#define EL3_S1_NSE (U(0x1) << 9) +#define ATTR_NON_CACHEABLE_INDEX ULL(0x2) +#define ATTR_DEV_INDEX ULL(0x1) +#define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0) +#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) + +/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ +#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) +/* Device-nGnRE */ +#define ATTR_DEV MAIR_DEV_nGnRE +/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ +#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, \ + MAIR_NORM_WB_NTR_RWA) +#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) +#define ATTR_INDEX_MASK U(0x3) +#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) + +/* + * Shift values for the attributes fields in a block or page descriptor. + * See section D4.3.3 in the ARMv8-A ARM (issue B.a). + */ + +/* Memory attributes index field, AttrIndx[2:0]. */ +#define ATTR_INDEX_SHIFT 2 +/* Non-secure bit, NS. */ +#define NS_SHIFT 5 +/* Shareability field, SH[1:0] */ +#define SHAREABILITY_SHIFT 8 +/* The Access Flag, AF. */ +#define ACCESS_FLAG_SHIFT 10 +/* The not global bit, nG. */ +#define NOT_GLOBAL_SHIFT 11 +/* Contiguous hint bit. */ +#define CONT_HINT_SHIFT 52 +/* Execute-never bits, XN. */ +#define PXN_SHIFT 53 +#define XN_SHIFT 54 +#define UXN_SHIFT XN_SHIFT + +#endif /* XLAT_TABLES_DEFS_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_private.h b/val/xlat_tables_v2/include/xlat_tables_private.h new file mode 100644 index 00000000..aedc2b5c --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_private.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_PRIVATE_H +#define XLAT_TABLES_PRIVATE_H + +#include + + +#include + +#if PLAT_XLAT_TABLES_DYNAMIC +/* + * Private shifts and masks to access fields of an mmap attribute + */ +/* Dynamic or static */ +#define MT_DYN_SHIFT U(31) + +/* + * Memory mapping private attributes + * + * Private attributes not exposed in the public header. + */ + +/* + * Regions mapped before the MMU can't be unmapped dynamically (they are + * static) and regions mapped with MMU enabled can be unmapped. This + * behaviour can't be overridden. + * + * Static regions can overlap each other, dynamic regions can't. + */ +#define MT_STATIC (U(0) << MT_DYN_SHIFT) +#define MT_DYNAMIC (U(1) << MT_DYN_SHIFT) + +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + +/* Determine the physical address space encoded in the 'attr' parameter. */ +uint32_t xlat_arch_get_pas(uint32_t attr); + +/* + * Return the execute-never mask that will prevent instruction fetch at the + * given translation regime. + */ +uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime); + +/* + * Invalidate all TLB entries that match the given virtual address. This + * operation applies to all PEs in the same Inner Shareable domain as the PE + * that executes this function. This functions must be called for every + * translation table entry that is modified. It only affects the specified + * translation regime. + * + * Note, however, that it is architecturally UNDEFINED to invalidate TLB entries + * pertaining to a higher exception level, e.g. invalidating EL3 entries from + * S-EL1. + */ +void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime); + +/* + * This function has to be called at the end of any code that uses the function + * xlat_arch_tlbi_va(). + */ +void xlat_arch_tlbi_va_sync(void); + +/* Print VA, PA, size and attributes of all regions in the mmap array. */ +void xlat_mmap_print(const mmap_region_t *mmap); + +/* + * Print the current state of the translation tables by reading them from + * memory. + */ +void xlat_tables_print(xlat_ctx_t *ctx); + +/* + * Returns a block/page table descriptor for the given level and attributes. + */ +uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr, + unsigned long long addr_pa, unsigned int level); + +/* + * Architecture-specific initialization code. + */ + +/* Returns the current Exception Level. The returned EL must be 1 or higher. */ +unsigned int xlat_arch_current_el(void); + +/* + * Return the maximum physical address supported by the hardware. + * This value depends on the execution state (AArch32/AArch64). + */ +unsigned long long xlat_arch_get_max_supported_pa(void); + +/* + * Returns true if the MMU of the translation regime managed by the given + * xlat_ctx_t is enabled, false otherwise. + */ +bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx); + +/* + * Returns minimum virtual address space size supported by the architecture + */ +uintptr_t xlat_get_min_virt_addr_space_size(void); + +bool is_dcache_enabled(void); +#endif /* XLAT_TABLES_PRIVATE_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_v2.h b/val/xlat_tables_v2/include/xlat_tables_v2.h new file mode 100644 index 00000000..b4fbd36d --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_v2.h @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#ifndef XLAT_TABLES_V2_H +#define XLAT_TABLES_V2_H + +#include +#include + +#ifndef __ASSEMBLER__ +#include +#include + +#include + +/* + * Default granularity size for an mmap_region_t. + * Useful when no specific granularity is required. + * + * By default, choose the biggest possible block size allowed by the + * architectural state and granule size in order to minimize the number of page + * tables required for the mapping. + */ +#define REGION_DEFAULT_GRANULARITY XLAT_BLOCK_SIZE(MIN_LVL_BLOCK_DESC) + +/* Helper macro to define an mmap_region_t. */ +#define MAP_REGION(_pa, _va, _sz, _attr) \ + MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, REGION_DEFAULT_GRANULARITY) + +/* Helper macro to define an mmap_region_t with an identity mapping. */ +#define MAP_REGION_FLAT(_adr, _sz, _attr) \ + MAP_REGION(_adr, _adr, _sz, _attr) + +/* + * Helper macro to define entries for mmap_region_t. It allows to define 'pa' + * and sets 'va' to 0 for each region. To be used with mmap_add_alloc_va(). + */ +#define MAP_REGION_ALLOC_VA(pa, sz, attr) MAP_REGION(pa, 0, sz, attr) + +/* + * Helper macro to define an mmap_region_t to map with the desired granularity + * of translation tables. + * + * The granularity value passed to this macro must be a valid block or page + * size. When using a 4KB translation granule, this might be 4KB, 2MB or 1GB. + * Passing REGION_DEFAULT_GRANULARITY is also allowed and means that the library + * is free to choose the granularity for this region. In this case, it is + * equivalent to the MAP_REGION() macro. + */ +#define MAP_REGION2(_pa, _va, _sz, _attr, _gr) \ + MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr) + +/* + * Shifts and masks to access fields of an mmap attribute + */ +#define MT_TYPE_MASK U(0x7) +#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) +/* Access permissions (RO/RW) */ +#define MT_PERM_SHIFT U(3) + +/* Physical address space (SECURE/NS/Root/Realm) */ +#define MT_PAS_SHIFT U(4) +#define MT_PAS_MASK (U(3) << MT_PAS_SHIFT) +#define MT_PAS(_attr) ((_attr) & MT_PAS_MASK) + +/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ +#define MT_EXECUTE_SHIFT U(6) +/* In the EL1&0 translation regime, User (EL0) or Privileged (EL1). */ +#define MT_USER_SHIFT U(7) + +/* Shareability attribute for the memory region */ +#define MT_SHAREABILITY_SHIFT U(8) +#define MT_SHAREABILITY_MASK (U(3) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY(_attr) ((_attr) & MT_SHAREABILITY_MASK) + +#define MT_AF_SHIFT U(10) + +/* All other bits are reserved */ + +/* + * Memory mapping attributes + */ + +/* + * Memory types supported. + * These are organised so that, going down the list, the memory types are + * getting weaker; conversely going up the list the memory types are getting + * stronger. + */ +#define MT_DEVICE U(0) +#define MT_NON_CACHEABLE U(1) +#define MT_MEMORY U(2) +/* Values up to 7 are reserved to add new memory types in the future */ + +#define MT_RO (U(0) << MT_PERM_SHIFT) +#define MT_RW (U(1) << MT_PERM_SHIFT) + +#define MT_SECURE (U(0) << MT_PAS_SHIFT) +#define MT_NS (U(1) << MT_PAS_SHIFT) +#define MT_ROOT (U(2) << MT_PAS_SHIFT) +#define MT_REALM (U(3) << MT_PAS_SHIFT) + +/* + * Access permissions for instruction execution are only relevant for normal + * read-only memory, i.e. MT_MEMORY | MT_RO. They are ignored (and potentially + * overridden) otherwise: + * - Device memory is always marked as execute-never. + * - Read-write normal memory is always marked as execute-never. + */ +#define MT_EXECUTE (U(0) << MT_EXECUTE_SHIFT) +#define MT_EXECUTE_NEVER (U(1) << MT_EXECUTE_SHIFT) + +/* + * When mapping a region at EL0 or EL1, this attribute will be used to determine + * if a User mapping (EL0) will be created or a Privileged mapping (EL1). + */ +#define MT_USER (U(1) << MT_USER_SHIFT) +#define MT_PRIVILEGED (U(0) << MT_USER_SHIFT) +#define MT_AF_CLEAR (U(1) << MT_AF_SHIFT) +/* + * Shareability defines the visibility of any cache changes to + * all masters belonging to a shareable domain. + * + * MT_SHAREABILITY_ISH: For inner shareable domain + * MT_SHAREABILITY_OSH: For outer shareable domain + * MT_SHAREABILITY_NSH: For non shareable domain + */ +#define MT_SHAREABILITY_ISH (U(1) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_OSH (U(2) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_NSH (U(3) << MT_SHAREABILITY_SHIFT) + +/* Compound attributes for most common usages */ +#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) +#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) +#define MT_RW_DATA (MT_MEMORY | MT_RW | MT_EXECUTE_NEVER) +#define MT_DEVICE_RW (MT_DEVICE | MT_RW) + +/* + * Structure for specifying a single region of memory. + */ +typedef struct mmap_region { + unsigned long long base_pa; + uintptr_t base_va; + size_t size; + uint64_t attr; + /* Desired granularity. See the MAP_REGION2() macro for more details. */ + size_t granularity; +} mmap_region_t; + +/* + * Translation regimes supported by this library. EL_REGIME_INVALID tells the + * library to detect it at runtime. + */ +#define EL1_EL0_REGIME 1 +#define EL2_REGIME 2 +#define EL3_REGIME 3 +#define EL_REGIME_INVALID -1 + +/* Memory type for EL3 regions. With RME, EL3 is in ROOT PAS */ +#if ENABLE_RME +#define EL3_PAS MT_ROOT +#else +#define EL3_PAS MT_SECURE +#endif /* ENABLE_RME */ + +/* + * Declare the translation context type. + * Its definition is private. + */ +typedef struct xlat_ctx xlat_ctx_t; + +/* + * Statically allocate a translation context and associated structures. Also + * initialize them. + * + * _ctx_name: + * Prefix for the translation context variable. + * E.g. If _ctx_name is 'foo', the variable will be called 'foo_xlat_ctx'. + * Useful to distinguish multiple contexts from one another. + * + * _mmap_count: + * Number of mmap_region_t to allocate. + * Would typically be MAX_MMAP_REGIONS for the translation context describing + * the BL image currently executing. + * + * _xlat_tables_count: + * Number of sub-translation tables to allocate. + * Would typically be MAX_XLAT_TABLES for the translation context describing + * the BL image currently executing. + * Note that this is only for sub-tables ; at the initial lookup level, there + * is always a single table. + * + * _virt_addr_space_size, _phy_addr_space_size: + * Size (in bytes) of the virtual (resp. physical) address space. + * Would typically be PLAT_VIRT_ADDR_SPACE_SIZE + * (resp. PLAT_PHY_ADDR_SPACE_SIZE) for the translation context describing the + * BL image currently executing. + */ +#define REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \ + _virt_addr_space_size, _phy_addr_space_size) \ + REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \ + (_xlat_tables_count), \ + (_virt_addr_space_size), \ + (_phy_addr_space_size), \ + EL_REGIME_INVALID, \ + ".xlat_table", ".base_xlat_table") + +/* + * Same as REGISTER_XLAT_CONTEXT plus the additional parameters: + * + * _xlat_regime: + * Specify the translation regime managed by this xlat_ctx_t instance. The + * values are the one from the EL*_REGIME definitions. + * + * _section_name: + * Specify the name of the section where the translation tables have to be + * placed by the linker. + * + * _base_table_section_name: + * Specify the name of the section where the base translation tables have to + * be placed by the linker. + */ +#define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \ + _virt_addr_space_size, _phy_addr_space_size, \ + _xlat_regime, _section_name, _base_table_section_name) \ + REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \ + (_xlat_tables_count), \ + (_virt_addr_space_size), \ + (_phy_addr_space_size), \ + (_xlat_regime), \ + (_section_name), (_base_table_section_name) \ +) + +/****************************************************************************** + * Generic translation table APIs. + * Each API comes in 2 variants: + * - one that acts on the current translation context for this BL image + * - another that acts on the given translation context instead. This variant + * is named after the 1st version, with an additional '_ctx' suffix. + *****************************************************************************/ + +/* + * Initialize translation tables from the current list of mmap regions. Calling + * this function marks the transition point after which static regions can no + * longer be added. + */ +void init_xlat_tables(void); +void init_xlat_tables_ctx(xlat_ctx_t *ctx); + +/* + * Fill all fields of a dynamic translation tables context. It must be done + * either statically with REGISTER_XLAT_CONTEXT() or at runtime with this + * function. + */ +void xlat_setup_dynamic_ctx(xlat_ctx_t *ctx, unsigned long long pa_max, + uintptr_t va_max, struct mmap_region *mmap, + unsigned int mmap_num, uint64_t **tables, + unsigned int tables_num, uint64_t *base_table, + int xlat_regime, int *mapped_regions); + +/* + * Add a static region with defined base PA and base VA. This function can only + * be used before initializing the translation tables. The region cannot be + * removed afterwards. + */ +void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, + size_t size, unsigned int attr); +void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm); + +/* + * Add an array of static regions with defined base PA and base VA. This + * function can only be used before initializing the translation tables. The + * regions cannot be removed afterwards. + */ +void mmap_add(const mmap_region_t *mm); +void mmap_add_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm); + +/* + * Add a region with defined base PA. Returns base VA calculated using the + * highest existing region in the mmap array even if it fails to allocate the + * region. + */ +void mmap_add_region_alloc_va(unsigned long long base_pa, uintptr_t *base_va, + size_t size, unsigned int attr); +void mmap_add_region_alloc_va_ctx(xlat_ctx_t *ctx, mmap_region_t *mm); + +/* + * Add an array of static regions with defined base PA, and fill the base VA + * field on the array of structs. This function can only be used before + * initializing the translation tables. The regions cannot be removed afterwards. + */ +void mmap_add_alloc_va(mmap_region_t *mm); + +#if PLAT_XLAT_TABLES_DYNAMIC +/* + * Add a dynamic region with defined base PA and base VA. This type of region + * can be added and removed even after the translation tables are initialized. + * + * Returns: + * 0: Success. + * EINVAL: Invalid values were used as arguments. + * ERANGE: Memory limits were surpassed. + * ENOMEM: Not enough space in the mmap array or not enough free xlat tables. + * EPERM: It overlaps another region in an invalid way. + */ +int mmap_add_dynamic_region(unsigned long long base_pa, uintptr_t base_va, + size_t size, unsigned int attr); +int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm); + +/* + * Add a dynamic region with defined base PA. Returns base VA calculated using + * the highest existing region in the mmap array even if it fails to allocate + * the region. + * + * mmap_add_dynamic_region_alloc_va() returns the allocated VA in 'base_va'. + * mmap_add_dynamic_region_alloc_va_ctx() returns it in 'mm->base_va'. + * + * It returns the same error values as mmap_add_dynamic_region(). + */ +int mmap_add_dynamic_region_alloc_va(unsigned long long base_pa, + uintptr_t *base_va, + size_t size, unsigned int attr); +int mmap_add_dynamic_region_alloc_va_ctx(xlat_ctx_t *ctx, mmap_region_t *mm); + +/* + * Remove a region with the specified base VA and size. Only dynamic regions can + * be removed, and they can be removed even if the translation tables are + * initialized. + * + * Returns: + * 0: Success. + * EINVAL: The specified region wasn't found. + * EPERM: Trying to remove a static region. + */ +int mmap_remove_dynamic_region(uintptr_t base_va, size_t size); +int mmap_remove_dynamic_region_ctx(xlat_ctx_t *ctx, + uintptr_t base_va, + size_t size); + +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +/* + * Change the memory attributes of the memory region starting from a given + * virtual address in a set of translation tables. + * + * This function can only be used after the translation tables have been + * initialized. + * + * The base address of the memory region must be aligned on a page boundary. + * The size of this memory region must be a multiple of a page size. + * The memory region must be already mapped by the given translation tables + * and it must be mapped at the granularity of a page. + * + * Return 0 on success, a negative value on error. + * + * In case of error, the memory attributes remain unchanged and this function + * has no effect. + * + * ctx + * Translation context to work on. + * base_va: + * Virtual address of the 1st page to change the attributes of. + * size: + * Size in bytes of the memory region. + * attr: + * New attributes of the page tables. The attributes that can be changed are + * data access (MT_RO/MT_RW), instruction access (MT_EXECUTE_NEVER/MT_EXECUTE) + * and user/privileged access (MT_USER/MT_PRIVILEGED) in the case of contexts + * that are used in the EL1&0 translation regime. Also, note that this + * function doesn't allow to remap a region as RW and executable, or to remap + * device memory as executable. + * + * NOTE: The caller of this function must be able to write to the translation + * tables, i.e. the memory where they are stored must be mapped with read-write + * access permissions. This function assumes it is the case. If this is not + * the case then this function might trigger a data abort exception. + * + * NOTE2: The caller is responsible for making sure that the targeted + * translation tables are not modified by any other code while this function is + * executing. + */ +int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, + size_t size, uint32_t attr); +int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr); + +#if PLAT_RO_XLAT_TABLES +/* + * Change the memory attributes of the memory region encompassing the higher + * level translation tables to secure read-only data. + * + * Return 0 on success, a negative error code on error. + */ +int xlat_make_tables_readonly(void); +#endif + +/* + * Query the memory attributes of a memory page in a set of translation tables. + * + * Return 0 on success, a negative error code on error. + * On success, the attributes are stored into *attr. + * + * ctx + * Translation context to work on. + * base_va + * Virtual address of the page to get the attributes of. + * There are no alignment restrictions on this address. The attributes of the + * memory page it lies within are returned. + * attr + * Output parameter where to store the attributes of the targeted memory page. + */ +int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, + uint32_t *attr); +int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr); + +#endif /*__ASSEMBLER__*/ +#endif /* XLAT_TABLES_V2_H */ diff --git a/val/xlat_tables_v2/include/xlat_tables_v2_helpers.h b/val/xlat_tables_v2/include/xlat_tables_v2_helpers.h new file mode 100644 index 00000000..361ea5dd --- /dev/null +++ b/val/xlat_tables_v2/include/xlat_tables_v2_helpers.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +/* + * This header file contains internal definitions that are not supposed to be + * used outside of this library code. + */ + +#ifndef XLAT_TABLES_V2_HELPERS_H +#define XLAT_TABLES_V2_HELPERS_H + +#ifndef XLAT_TABLES_V2_H +#error "Do not include this header file directly. Include xlat_tables_v2.h instead." +#endif + +#ifndef __ASSEMBLER__ + +#include +#include + +//#include + +//#include +//#include +#include +#include +#include + +/* Forward declaration */ +struct mmap_region; + +/* + * Helper macro to define an mmap_region_t. This macro allows to specify all + * the fields of the structure but its parameter list is not guaranteed to + * remain stable as we add members to mmap_region_t. + */ +#define MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr) \ + { \ + .base_pa = (_pa), \ + .base_va = (_va), \ + .size = (_sz), \ + .attr = (_attr), \ + .granularity = (_gr), \ + } + +/* Struct that holds all information about the translation tables. */ +struct xlat_ctx { + /* + * Max allowed Virtual and Physical Addresses. + */ + unsigned long long pa_max_address; + uintptr_t va_max_address; + + /* + * Array of all memory regions stored in order of ascending end address + * and ascending size to simplify the code that allows overlapping + * regions. The list is terminated by the first entry with size == 0. + * The max size of the list is stored in `mmap_num`. `mmap` points to an + * array of mmap_num + 1 elements, so that there is space for the final + * null entry. + */ + struct mmap_region *mmap; + unsigned int mmap_num; + + /* + * Array of finer-grain translation tables. + * For example, if the initial lookup level is 1 then this array would + * contain both level-2 and level-3 entries. + */ + uint64_t (*tables)[XLAT_TABLE_ENTRIES]; + unsigned int tables_num; +#if PLAT_RO_XLAT_TABLES + bool readonly_tables; +#endif + /* + * Keep track of how many regions are mapped in each table. The base + * table can't be unmapped so it isn't needed to keep track of it. + */ +#if PLAT_XLAT_TABLES_DYNAMIC + int *tables_mapped_regions; +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + + int next_table; + + /* + * Base translation table. It doesn't need to have the same amount of + * entries as the ones used for other levels. + */ + uint64_t *base_table; + unsigned int base_table_entries; + + /* + * Max Physical and Virtual addresses currently in use by the + * translation tables. These might get updated as we map/unmap memory + * regions but they will never go beyond pa/va_max_address. + */ + unsigned long long max_pa; + uintptr_t max_va; + + /* Level of the base translation table. */ + unsigned int base_level; + + /* Set to true when the translation tables are initialized. */ + bool initialized; + + /* + * Translation regime managed by this xlat_ctx_t. It should be one of + * the EL*_REGIME defines. + */ + int xlat_regime; +}; + +#if PLAT_XLAT_TABLES_DYNAMIC +#define XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count) \ + static int _ctx_name##_mapped_regions[_xlat_tables_count]; + +#define XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name) \ + .tables_mapped_regions = _ctx_name##_mapped_regions, +#else +#define XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count) \ + /* do nothing */ + +#define XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name) \ + /* do nothing */ +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +#if PLAT_RO_XLAT_TABLES +#define XLAT_CTX_INIT_TABLE_ATTR() \ + .readonly_tables = false, +#else +#define XLAT_CTX_INIT_TABLE_ATTR() + /* do nothing */ +#endif + +#define REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, \ + _xlat_tables_count, _virt_addr_space_size, \ + _phy_addr_space_size, _xlat_regime, \ + _table_section, _base_table_section) \ + CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(_phy_addr_space_size), \ + assert_invalid_physical_addr_space_sizefor_##_ctx_name);\ + \ + static mmap_region_t _ctx_name##_mmap[XLAT_MAX_MMAP_REGIONS]; \ + \ + static uint64_t _ctx_name##_xlat_tables[_xlat_tables_count] \ + [XLAT_TABLE_ENTRIES] \ + __aligned(XLAT_TABLE_SIZE) __section(_table_section); \ + \ + static uint64_t _ctx_name##_base_xlat_table \ + [GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)] \ + __aligned(GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)\ + * sizeof(uint64_t)) \ + __section(_base_table_section); \ + \ + XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count) \ + \ + static xlat_ctx_t _ctx_name##_xlat_ctx = { \ + .pa_max_address = (_phy_addr_space_size) - 1ULL, \ + .va_max_address = (_virt_addr_space_size) - 1UL, \ + .mmap = _ctx_name##_mmap, \ + .mmap_num = (_mmap_count), \ + .tables = _ctx_name##_xlat_tables, \ + .tables_num = ARRAY_SIZE(_ctx_name##_xlat_tables), \ + XLAT_CTX_INIT_TABLE_ATTR() \ + XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name) \ + .next_table = 0, \ + .base_table = _ctx_name##_base_xlat_table, \ + .base_table_entries = \ + ARRAY_SIZE(_ctx_name##_base_xlat_table), \ + .max_pa = 0U, \ + .max_va = 0U, \ + .base_level = GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size),\ + .initialized = false, \ + .xlat_regime = (_xlat_regime) \ + } + +#endif /*__ASSEMBLER__*/ + +#endif /* XLAT_TABLES_V2_HELPERS_H */ diff --git a/val/xlat_tables_v2/src/cache_helpers.S b/val/xlat_tables_v2/src/cache_helpers.S new file mode 100644 index 00000000..7651a8d5 --- /dev/null +++ b/val/xlat_tables_v2/src/cache_helpers.S @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#include +#include "cdefs.h" +#include + + .globl flush_dcache_range + .globl flush_dcache_to_popa_range + .globl clean_dcache_range + .globl inv_dcache_range + .globl dcsw_op_louis + .globl dcsw_op_all + .globl dcsw_op_level1 + .globl dcsw_op_level2 + .globl dcsw_op_level3 + +/* + * This macro can be used for implementing various data cache operations `op` + */ +.macro do_dcache_maintenance_by_mva op + /* Exit early if size is zero */ + cbz x1, exit_loop_\op + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + dc \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy +exit_loop_\op: + ret +.endm + +.macro check_plat_can_cmo +#if CONDITIONAL_CMO + mov x3, x30 + mov x2, x0 + bl plat_can_cmo + mov x30, x3 + cbnz x0, 1f + ret +1: + mov x0, x2 +#endif +.endm + /* ------------------------------------------ + * Clean+Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func flush_dcache_range + check_plat_can_cmo + do_dcache_maintenance_by_mva civac +endfunc flush_dcache_range + + /* ------------------------------------------ + * Clean from base address till size. + * 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func clean_dcache_range + check_plat_can_cmo + do_dcache_maintenance_by_mva cvac +endfunc clean_dcache_range + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func inv_dcache_range + check_plat_can_cmo + do_dcache_maintenance_by_mva ivac +endfunc inv_dcache_range + + + /* + * On implementations with FEAT_MTE2, + * Root firmware must issue DC_CIGDPAPA instead of DC_CIPAPA , + * in order to additionally clean and invalidate Allocation Tags + * associated with the affected locations. + * + * ------------------------------------------ + * Clean+Invalidate by PA to POPA + * from base address till size. + * 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func flush_dcache_to_popa_range + /* Exit early if size is zero */ + cbz x1, exit_loop_dc_cipapa + check_plat_can_cmo + dcache_line_size x2, x3 + sub x3, x2, #1 + bic x0, x0, x3 + add x1, x1, x0 +loop_dc_cipapa: + sys #6, c7, c14, #1, x0 /* DC CIPAPA, */ + add x0, x0, x2 + cmp x0, x1 + b.lo loop_dc_cipapa + dsb osh +exit_loop_dc_cipapa: + ret +endfunc flush_dcache_to_popa_range + + /* --------------------------------------------------------------- + * Data cache operations by set/way to the level specified + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * x3: The last cache level to operate on + * x9: clidr_el1 + * x10: The cache level to begin operation from + * and will carry out the operation on each data cache from level 0 + * to the level in x3 in sequence + * + * The dcsw_op macro sets up the x3 and x9 parameters based on + * clidr_el1 cache information before invoking the main function + * --------------------------------------------------------------- + */ + + .macro dcsw_op shift, fw, ls + mrs x9, clidr_el1 + ubfx x3, x9, \shift, \fw + lsl x3, x3, \ls + mov x10, xzr + b do_dcsw_op + .endm + +func do_dcsw_op + cbz x3, exit + mrs x12, ID_AA64MMFR2_EL1 // stash FEAT_CCIDX identifier in x12 + ubfx x12, x12, #ID_AA64MMFR2_EL1_CCIDX_SHIFT, #ID_AA64MMFR2_EL1_CCIDX_LENGTH + adr x14, dcsw_loop_table // compute inner loop address + add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions +#if ENABLE_BTI + add x14, x14, x0, lsl #2 // inner loop is + "bti j" instruction +#endif + mov x0, x9 + mov w8, #1 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lo level_done // nothing to do if no cache or icache + + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + + cbz x12, 1f // check for FEAT_CCIDX for Associativity + ubfx x4, x1, #3, #21 // x4 = associativity CCSIDR_EL1[23:3] + b 2f +1: + ubfx x4, x1, #3, #10 // x4 = associativity CCSIDR_EL1[12:3] +2: + clz w5, w4 // bit position of way size increment + lsl w9, w4, w5 // w9 = aligned max way number + lsl w16, w8, w5 // w16 = way number loop decrement + orr w9, w10, w9 // w9 = combine way and cache number + + cbz x12, 3f // check for FEAT_CCIDX for NumSets + ubfx x6, x1, #32, #24 // x6 (w6) = numsets CCSIDR_EL1[55:32] + // ISA will not allow x->w ubfx + b 4f +3: + ubfx w6, w1, #13, #15 // w6 = numsets CCSIDR_EL1[27:13] +4: + lsl w17, w8, w2 // w17 = set number loop decrement + dsb sy // barrier before we start this level + br x14 // jump to DC operation specific loop + + .macro dcsw_loop _op +#if ENABLE_BTI + bti j +#endif +loop2_\_op: + lsl w7, w6, w2 // w7 = aligned max set number + +loop3_\_op: + orr w11, w9, w7 // combine cache, way and set number + dc \_op, x11 + subs w7, w7, w17 // decrement set number + b.hs loop3_\_op + + subs x9, x9, x16 // decrement way number + b.hs loop2_\_op + + b level_done + .endm + +level_done: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.hi loop1 + msr csselr_el1, xzr // select cache level 0 in csselr + dsb sy // barrier to complete final cache operation + isb +exit: + ret +endfunc do_dcsw_op + +dcsw_loop_table: + dcsw_loop isw + dcsw_loop cisw + dcsw_loop csw + + +func dcsw_op_louis + check_plat_can_cmo + dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_louis + + +func dcsw_op_all + check_plat_can_cmo + dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_all + + /* --------------------------------------------------------------- + * Helper macro for data cache operations by set/way for the + * level specified + * --------------------------------------------------------------- + */ + .macro dcsw_op_level level + mrs x9, clidr_el1 + mov x3, \level + sub x10, x3, #2 + b do_dcsw_op + .endm + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 1 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level1 + check_plat_can_cmo + dcsw_op_level #(1 << LEVEL_SHIFT) +endfunc dcsw_op_level1 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 2 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level2 + check_plat_can_cmo + dcsw_op_level #(2 << LEVEL_SHIFT) +endfunc dcsw_op_level2 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 3 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level3 + check_plat_can_cmo + dcsw_op_level #(3 << LEVEL_SHIFT) +endfunc dcsw_op_level3 diff --git a/val/xlat_tables_v2/src/enable_mmu.S b/val/xlat_tables_v2/src/enable_mmu.S new file mode 100644 index 00000000..0f3c6f0f --- /dev/null +++ b/val/xlat_tables_v2/src/enable_mmu.S @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ +#include +#include +#include + + .global enable_mmu_direct_el1 + .global enable_mmu_direct_el2 + .global enable_mmu_direct_el3 + + /* Macros to read and write to system register for a given EL. */ + .macro _msr reg_name, el, gp_reg + msr \reg_name\()_el\()\el, \gp_reg + .endm + + .macro _mrs gp_reg, reg_name, el + mrs \gp_reg, \reg_name\()_el\()\el + .endm + + .macro tlbi_invalidate_all el + .if \el == 1 + TLB_INVALIDATE(vmalle1) + .elseif \el == 2 + TLB_INVALIDATE(alle2) + .elseif \el == 3 + TLB_INVALIDATE(alle3) + .else + .error "EL must be 1, 2 or 3" + .endif + .endm + + /* void enable_mmu_direct_el(unsigned int flags) */ + .macro define_mmu_enable_func el + func enable_mmu_direct_\()el\el +#if ENABLE_ASSERTIONS + _mrs x1, sctlr, \el + tst x1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + /* Invalidate all TLB entries */ + tlbi_invalidate_all \el + + mov x7, x0 + adrp x0, mmu_cfg_params + add x0, x0, :lo12:mmu_cfg_params + + /* MAIR */ + ldr x1, [x0, #(MMU_CFG_MAIR << 3)] + _msr mair, \el, x1 + + /* TCR */ + ldr x2, [x0, #(MMU_CFG_TCR << 3)] + _msr tcr, \el, x2 + + /* TTBR */ + ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)] + _msr ttbr0, \el, x3 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Set and clear required fields of SCTLR */ + _mrs x4, sctlr, \el + mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT + orr x4, x4, x5 + + /* Additionally, amend SCTLR fields based on flags */ + bic x5, x4, #SCTLR_C_BIT + tst x7, #DISABLE_DCACHE + csel x4, x5, x4, ne + + _msr sctlr, \el, x4 + isb + + ret + endfunc enable_mmu_direct_\()el\el + .endm + + /* + * Define MMU-enabling functions for EL1, EL2 and EL3: + * + * enable_mmu_direct_el1 + * enable_mmu_direct_el2 + * enable_mmu_direct_el3 + */ + define_mmu_enable_func 1 + define_mmu_enable_func 2 + define_mmu_enable_func 3 diff --git a/val/xlat_tables_v2/src/smc.S b/val/xlat_tables_v2/src/smc.S new file mode 100644 index 00000000..14f0fd68 --- /dev/null +++ b/val/xlat_tables_v2/src/smc.S @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include + +.globl monitor_call +.globl monitor_call_with_res + +func monitor_call + /* As this is a function call, the arguments must already be in + * place in accordance to SMCCC. + */ + smc #0 + ret +endfunc monitor_call + +/* + * Issue an SMC call to EL3 monitor with the ability to return more than 1 + * result register. + * The arguments to this function are : + * x0 - x6 - SMC call arguments + * x7 - Reference to smc_result structure allocated by caller + * Return : + * x0 - x3 Return values from SMC + * The return args are also copied to smc_result data structure. + */ +func monitor_call_with_res + /* + * Push the value of x7 to the stack, as the SMC might change the + * content. (push two registers to maintain 16 bit aligned stack) + */ + stp x7, x8, [sp, #-16]! + /* Call SMC */ + smc #0 + /* Pop the saved values from stack */ + ldp x7, x8, [sp], #16 + /* Fill the smc_result structure */ + stp x0, x1, [x7, #0] + stp x2, x3, [x7, #16] + ret +endfunc monitor_call_with_res diff --git a/val/xlat_tables_v2/src/xlat_tables_arch.c b/val/xlat_tables_v2/src/xlat_tables_arch.c new file mode 100644 index 00000000..81445f36 --- /dev/null +++ b/val/xlat_tables_v2/src/xlat_tables_arch.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#include +#include + +#include "cdefs.h" +#include +#include +#include "assert.h" +#include "xlat_tables_private.h" + +/* + * Returns true if the provided granule size is supported, false otherwise. + */ +bool xlat_arch_is_granule_size_supported(size_t size) +{ + unsigned int tgranx; + + if (size == PAGE_SIZE_4KB) { + tgranx = read_id_aa64mmfr0_el0_tgran4_field(); + /* MSB of TGRAN4 field will be '1' for unsupported feature */ + return (tgranx < 8U); + } else if (size == PAGE_SIZE_16KB) { + tgranx = read_id_aa64mmfr0_el0_tgran16_field(); + return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED); + } else if (size == PAGE_SIZE_64KB) { + tgranx = read_id_aa64mmfr0_el0_tgran64_field(); + /* MSB of TGRAN64 field will be '1' for unsupported feature */ + return (tgranx < 8U); + } else { + return false; + } +} + +size_t xlat_arch_get_max_supported_granule_size(void) +{ + if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { + return PAGE_SIZE_64KB; + } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { + return PAGE_SIZE_16KB; + } else { + assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); + return PAGE_SIZE_4KB; + } +} + +/* + * Determine the physical address space encoded in the 'attr' parameter. + * + * The physical address will fall into one of four spaces; secure, + * nonsecure, root, or realm if RME is enabled, or one of two spaces; + * secure and nonsecure otherwise. + */ +uint32_t xlat_arch_get_pas(uint32_t attr) +{ + uint32_t pas = MT_PAS(attr); + + switch (pas) { + /* TTD.NSE = 1 and TTD.NS = 1 for Realm PAS */ + case MT_REALM: + return LOWER_ATTRS(EL3_S1_NSE | NS); + /* TTD.NSE = 1 and TTD.NS = 0 for Root PAS */ + case MT_ROOT: + return LOWER_ATTRS(EL3_S1_NSE); + case MT_NS: + return LOWER_ATTRS(NS); + default: /* MT_SECURE */ + return 0U; + } +} + +unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) +{ + /* Physical address can't exceed 48 bits */ + assert((max_addr & ADDR_MASK_48_TO_63) == 0U); + + /* 48 bits address */ + if ((max_addr & ADDR_MASK_44_TO_47) != 0U) + return TCR_PS_BITS_256TB; + + /* 44 bits address */ + if ((max_addr & ADDR_MASK_42_TO_43) != 0U) + return TCR_PS_BITS_16TB; + + /* 42 bits address */ + if ((max_addr & ADDR_MASK_40_TO_41) != 0U) + return TCR_PS_BITS_4TB; + + /* 40 bits address */ + if ((max_addr & ADDR_MASK_36_TO_39) != 0U) + return TCR_PS_BITS_1TB; + + /* 36 bits address */ + if ((max_addr & ADDR_MASK_32_TO_35) != 0U) + return TCR_PS_BITS_64GB; + + return TCR_PS_BITS_4GB; +} + +/* + * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is + * supported in ARMv8.2 onwards. + */ +static const unsigned int pa_range_bits_arr[] = { + PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, + PARANGE_0101, PARANGE_0110 +}; + +unsigned long long xlat_arch_get_max_supported_pa(void) +{ + u_register_t pa_range = read_id_aa64mmfr0_el1() & + ID_AA64MMFR0_EL1_PARANGE_MASK; + + /* All other values are reserved */ + assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); + + return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; +} + +/* + * Return minimum virtual address space size supported by the architecture + */ +uintptr_t xlat_get_min_virt_addr_space_size(void) +{ + uintptr_t ret; + + if (is_armv8_4_ttst_present()) + ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST; + else + ret = MIN_VIRT_ADDR_SPACE_SIZE; + + return ret; +} + +bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) +{ + if (ctx->xlat_regime == EL1_EL0_REGIME) { + assert(xlat_arch_current_el() >= 1U); + return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; + } else if (ctx->xlat_regime == EL2_REGIME) { + assert(xlat_arch_current_el() >= 2U); + return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; + } else { + assert(ctx->xlat_regime == EL3_REGIME); + assert(xlat_arch_current_el() >= 3U); + return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; + } +} + +bool is_dcache_enabled(void) +{ + unsigned int el = xlat_arch_current_el(); + + if (el == 1U) { + return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; + } else if (el == 2U) { + return (read_sctlr_el2() & SCTLR_C_BIT) != 0U; + } else { + return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; + } +} + +uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) +{ + if (xlat_regime == EL1_EL0_REGIME) { + return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); + } else { + assert((xlat_regime == EL2_REGIME) || + (xlat_regime == EL3_REGIME)); + return UPPER_ATTRS(XN); + } +} + +void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) +{ + /* + * Ensure the translation table write has drained into memory before + * invalidating the TLB entry. + */ + dsbishst(); + + /* + * This function only supports invalidation of TLB entries for the EL3 + * and EL1&0 translation regimes. + * + * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher + * exception level (see section D4.9.2 of the ARM ARM rev B.a). + */ + if (xlat_regime == EL1_EL0_REGIME) { + assert(xlat_arch_current_el() >= 1U); + tlbivaae1is(TLBI_ADDR(va)); + } else if (xlat_regime == EL2_REGIME) { + assert(xlat_arch_current_el() >= 2U); + tlbivae2is(TLBI_ADDR(va)); + } else { + assert(xlat_regime == EL3_REGIME); + assert(xlat_arch_current_el() >= 3U); + tlbivae3is(TLBI_ADDR(va)); + } +} + +void xlat_arch_tlbi_va_sync(void) +{ + /* + * A TLB maintenance instruction can complete at any time after + * it is issued, but is only guaranteed to be complete after the + * execution of DSB by the PE that executed the TLB maintenance + * instruction. After the TLB invalidate instruction is + * complete, no new memory accesses using the invalidated TLB + * entries will be observed by any observer of the system + * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph + * "Ordering and completion of TLB maintenance instructions". + */ + dsbish(); + + /* + * The effects of a completed TLB maintenance instruction are + * only guaranteed to be visible on the PE that executed the + * instruction after the execution of an ISB instruction by the + * PE that executed the TLB maintenance instruction. + */ + isb(); +} + +unsigned int xlat_arch_current_el(void) +{ + unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); + + assert(el > 0U); + + return el; +} + +void setup_mmu_cfg(uint64_t *params, unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, + uintptr_t max_va, int xlat_regime) +{ + uint64_t mair, ttbr0, tcr; + uintptr_t virtual_addr_space_size; + + /* Set attributes in the right indices of the MAIR. */ + mair = MAIR_ATTR_SET(ATTR_DEV, ATTR_DEV_INDEX); + mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); + mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); + + /* + * Limit the input address ranges and memory region sizes translated + * using TTBR0 to the given virtual address space size. + */ + assert(max_va < ((uint64_t)UINTPTR_MAX)); + + virtual_addr_space_size = (uintptr_t)max_va + 1U; + + assert(virtual_addr_space_size >= + xlat_get_min_virt_addr_space_size()); + assert(virtual_addr_space_size <= MAX_VIRT_ADDR_SPACE_SIZE); + assert(IS_POWER_OF_TWO(virtual_addr_space_size)); + + /* + * __builtin_ctzll(0) is undefined but here we are guaranteed that + * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. + */ + int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); + + tcr = (uint64_t)t0sz << TCR_T0SZ_SHIFT; + + /* + * Set the cacheability and shareability attributes for memory + * associated with translation table walks. + */ + if ((flags & XLAT_TABLE_NC) != 0U) { + /* Inner & outer non-cacheable non-shareable. */ + tcr |= TCR_SH_NON_SHAREABLE | + TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; + } else { + /* Inner & outer WBWA & shareable. */ + tcr |= TCR_SH_INNER_SHAREABLE | + TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; + } + + /* + * It is safer to restrict the max physical address accessible by the + * hardware as much as possible. + */ + unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); + + if (xlat_regime == EL1_EL0_REGIME) { + /* + * TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + } else if (xlat_regime == EL2_REGIME) { + tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT); + } else { + assert(xlat_regime == EL3_REGIME); + tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); + } + + /* Set TTBR bits as well */ + ttbr0 = (uint64_t) base_table; + + if (is_armv8_2_ttcnp_present()) { + /* Enable CnP bit so as to share page tables with all PEs. */ + ttbr0 |= TTBR_CNP_BIT; + } + + params[MMU_CFG_MAIR] = mair; + params[MMU_CFG_TCR] = tcr; + params[MMU_CFG_TTBR0] = ttbr0; +} diff --git a/val/xlat_tables_v2/src/xlat_tables_core.c b/val/xlat_tables_v2/src/xlat_tables_core.c new file mode 100644 index 00000000..831650cf --- /dev/null +++ b/val/xlat_tables_v2/src/xlat_tables_core.c @@ -0,0 +1,1236 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "xlat_tables_private.h" + +/* Helper function that cleans the data cache only if it is enabled. */ +static inline __attribute__((unused)) void xlat_clean_dcache_range(uintptr_t addr, size_t size) +{ + if (is_dcache_enabled()) + clean_dcache_range(addr, size); +} + +#if PLAT_XLAT_TABLES_DYNAMIC + +/* + * The following functions assume that they will be called using subtables only. + * The base table can't be unmapped, so it is not needed to do any special + * handling for it. + */ + +/* + * Returns the index of the array corresponding to the specified translation + * table. + */ +static int xlat_table_get_index(const xlat_ctx_t *ctx, const uint64_t *table) +{ + for (unsigned int i = 0; i < ctx->tables_num; i++) + if (ctx->tables[i] == table) + return (int)i; + + /* + * Maybe we were asked to get the index of the base level table, which + * should never happen. + */ + assert(false); + + return -1; +} + +/* Returns a pointer to an empty translation table. */ +static uint64_t *xlat_table_get_empty(const xlat_ctx_t *ctx) +{ + for (unsigned int i = 0; i < ctx->tables_num; i++) + if (ctx->tables_mapped_regions[i] == 0) + return ctx->tables[i]; + + return NULL; +} + +/* Increments region count for a given table. */ +static void xlat_table_inc_regions_count(const xlat_ctx_t *ctx, + const uint64_t *table) +{ + int idx = xlat_table_get_index(ctx, table); + + ctx->tables_mapped_regions[idx]++; +} + +/* Decrements region count for a given table. */ +static void xlat_table_dec_regions_count(const xlat_ctx_t *ctx, + const uint64_t *table) +{ + int idx = xlat_table_get_index(ctx, table); + + ctx->tables_mapped_regions[idx]--; +} + +/* Returns 0 if the specified table isn't empty, otherwise 1. */ +static bool xlat_table_is_empty(const xlat_ctx_t *ctx, const uint64_t *table) +{ + return ctx->tables_mapped_regions[xlat_table_get_index(ctx, table)] == 0; +} + +#else /* PLAT_XLAT_TABLES_DYNAMIC */ + +/* Returns a pointer to the first empty translation table. */ +static uint64_t *xlat_table_get_empty(xlat_ctx_t *ctx) +{ + assert(ctx->next_table < ctx->tables_num); + + return ctx->tables[ctx->next_table++]; +} + +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +/* + * Returns a block/page table descriptor for the given level and attributes. + */ +uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr, + unsigned long long addr_pa, unsigned int level) +{ + uint64_t desc; + uint32_t mem_type; + uint32_t shareability_type; + + /* Make sure that the granularity is fine enough to map this address. */ + assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U); + + desc = addr_pa; + /* + * There are different translation table descriptors for level 3 and the + * rest. + */ + desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; + + /* + * Clear Access flag if MT_AF_CLEAR is set otherwise Always set the access flag, as this + * library assumes access flag faults aren't managed. + */ + if ((attr & MT_AF_CLEAR) == 0U) + desc |= LOWER_ATTRS(ACCESS_FLAG); + + /* Determine the physical address space this region belongs to. */ + desc |= xlat_arch_get_pas(attr); + + /* + * Deduce other fields of the descriptor based on the MT_RW memory + * region attributes. + */ + desc |= ((attr & MT_RW) != 0U) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); + + /* + * Do not allow unprivileged access when the mapping is for a privileged + * EL. For translation regimes that do not have mappings for access for + * lower exception levels, set AP[2] to AP_NO_ACCESS_UNPRIVILEGED. + */ + if (ctx->xlat_regime == EL1_EL0_REGIME) { + if ((attr & MT_USER) != 0U) { + /* EL0 mapping requested, so we give User access */ + desc |= LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED); + } else { + /* EL1 mapping requested, no User access granted */ + desc |= LOWER_ATTRS(AP_NO_ACCESS_UNPRIVILEGED); + } + } else { + assert((ctx->xlat_regime == EL2_REGIME) || + (ctx->xlat_regime == EL3_REGIME)); + desc |= LOWER_ATTRS(AP_ONE_VA_RANGE_RES1); + } + + /* + * Deduce shareability domain and executability of the memory region + * from the memory type of the attributes (MT_TYPE). + * + * Data accesses to device memory and non-cacheable normal memory are + * coherent for all observers in the system, and correspondingly are + * always treated as being Outer Shareable. Therefore, for these 2 types + * of memory, it is not strictly needed to set the shareability field + * in the translation tables. + */ + mem_type = MT_TYPE(attr); + if (mem_type == MT_DEVICE) { + desc |= LOWER_ATTRS(ATTR_DEV_INDEX | OSH); + /* + * Always map device memory as execute-never. + * This is to avoid the possibility of a speculative instruction + * fetch, which could be an issue if this memory region + * corresponds to a read-sensitive peripheral. + */ + desc |= xlat_arch_regime_get_xn_desc(ctx->xlat_regime); + + } else { /* Normal memory */ + /* + * Always map read-write normal memory as execute-never. + * This library assumes that it is used by software that does + * not self-modify its code, therefore R/W memory is reserved + * for data storage, which must not be executable. + * + * Note that setting the XN bit here is for consistency only. + * The function that enables the MMU sets the SCTLR_ELx.WXN bit, + * which makes any writable memory region to be treated as + * execute-never, regardless of the value of the XN bit in the + * translation table. + * + * For read-only memory, rely on the MT_EXECUTE/MT_EXECUTE_NEVER + * attribute to figure out the value of the XN bit. The actual + * XN bit(s) to set in the descriptor depends on the context's + * translation regime and the policy applied in + * xlat_arch_regime_get_xn_desc(). + */ + if (((attr & MT_RW) != 0U) || ((attr & MT_EXECUTE_NEVER) != 0U)) { + desc |= xlat_arch_regime_get_xn_desc(ctx->xlat_regime); + } + + shareability_type = MT_SHAREABILITY(attr); + if (mem_type == MT_MEMORY) { + desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX); + if (shareability_type == MT_SHAREABILITY_NSH) { + desc |= LOWER_ATTRS(NSH); + } else if (shareability_type == MT_SHAREABILITY_OSH) { + desc |= LOWER_ATTRS(OSH); + } else { + desc |= LOWER_ATTRS(ISH); + } + + /* Check if Branch Target Identification is enabled */ +#if BTI_ENABLED + /* Set GP bit for block and page code entries + * if BTI mechanism is implemented. + */ + if (is_armv8_5_bti_present() && + ((attr & (MT_TYPE_MASK | MT_RW | + MT_EXECUTE_NEVER)) == MT_CODE)) { + desc |= GP; + } +#endif + } else { + assert(mem_type == MT_NON_CACHEABLE); + desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH); + } + } + + return desc; +} + +/* + * Enumeration of actions that can be made when mapping table entries depending + * on the previous value in that entry and information about the region being + * mapped. + */ +typedef enum { + + /* Do nothing */ + ACTION_NONE, + + /* Write a block (or page, if in level 3) entry. */ + ACTION_WRITE_BLOCK_ENTRY, + + /* + * Create a new table and write a table entry pointing to it. Recurse + * into it for further processing. + */ + ACTION_CREATE_NEW_TABLE, + + /* + * There is a table descriptor in this entry, read it and recurse into + * that table for further processing. + */ + ACTION_RECURSE_INTO_TABLE, + +} action_t; + +/* + * Function that returns the first VA of the table affected by the specified + * mmap region. + */ +static uintptr_t xlat_tables_find_start_va(mmap_region_t *mm, + const uintptr_t table_base_va, + const unsigned int level) +{ + uintptr_t table_idx_va; + + if (mm->base_va > table_base_va) { + /* Find the first index of the table affected by the region. */ + table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level); + } else { + /* Start from the beginning of the table. */ + table_idx_va = table_base_va; + } + + return table_idx_va; +} + +/* + * Function that returns table index for the given VA and level arguments. + */ +static inline unsigned int xlat_tables_va_to_index(const uintptr_t table_base_va, + const uintptr_t va, + const unsigned int level) +{ + return (unsigned int)((va - table_base_va) >> XLAT_ADDR_SHIFT(level)); +} + +#if PLAT_XLAT_TABLES_DYNAMIC + +/* + * From the given arguments, it decides which action to take when unmapping the + * specified region. + */ +static action_t xlat_tables_unmap_region_action(const mmap_region_t *mm, + const uintptr_t table_idx_va, const uintptr_t table_idx_end_va, + const unsigned int level, const uint64_t desc_type) +{ + action_t action; + uintptr_t region_end_va = mm->base_va + mm->size - 1U; + + if ((mm->base_va <= table_idx_va) && + (region_end_va >= table_idx_end_va)) { + /* Region covers all block */ + + if (level == 3U) { + /* + * Last level, only page descriptors allowed, + * erase it. + */ + assert(desc_type == PAGE_DESC); + + action = ACTION_WRITE_BLOCK_ENTRY; + } else { + /* + * Other levels can have table descriptors. If + * so, recurse into it and erase descriptors + * inside it as needed. If there is a block + * descriptor, just erase it. If an invalid + * descriptor is found, this table isn't + * actually mapped, which shouldn't happen. + */ + if (desc_type == TABLE_DESC) { + action = ACTION_RECURSE_INTO_TABLE; + } else { + assert(desc_type == BLOCK_DESC); + action = ACTION_WRITE_BLOCK_ENTRY; + } + } + + } else if ((mm->base_va <= table_idx_end_va) || + (region_end_va >= table_idx_va)) { + /* + * Region partially covers block. + * + * It can't happen in level 3. + * + * There must be a table descriptor here, if not there + * was a problem when mapping the region. + */ + assert(level < 3U); + assert(desc_type == TABLE_DESC); + + action = ACTION_RECURSE_INTO_TABLE; + } else { + /* The region doesn't cover the block at all */ + action = ACTION_NONE; + } + + return action; +} +/* + * Recursive function that writes to the translation tables and unmaps the + * specified region. + */ +static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm, + const uintptr_t table_base_va, + uint64_t *const table_base, + const unsigned int table_entries, + const unsigned int level) +{ + assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX)); + + uint64_t *subtable; + uint64_t desc; + + uintptr_t table_idx_va; + uintptr_t table_idx_end_va; /* End VA of this entry */ + + uintptr_t region_end_va = mm->base_va + mm->size - 1U; + + unsigned int table_idx; + + table_idx_va = xlat_tables_find_start_va(mm, table_base_va, level); + table_idx = xlat_tables_va_to_index(table_base_va, table_idx_va, level); + + while (table_idx < table_entries) { + + table_idx_end_va = table_idx_va + XLAT_BLOCK_SIZE(level) - 1U; + + desc = table_base[table_idx]; + uint64_t desc_type = desc & DESC_MASK; + + action_t action = xlat_tables_unmap_region_action(mm, + table_idx_va, table_idx_end_va, level, + desc_type); + + if (action == ACTION_WRITE_BLOCK_ENTRY) { + + table_base[table_idx] = INVALID_DESC; + xlat_arch_tlbi_va(table_idx_va, ctx->xlat_regime); + + } else if (action == ACTION_RECURSE_INTO_TABLE) { + + subtable = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK); + + /* Recurse to write into subtable */ + xlat_tables_unmap_region(ctx, mm, table_idx_va, + subtable, XLAT_TABLE_ENTRIES, + level + 1U); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)subtable, + XLAT_TABLE_ENTRIES * sizeof(uint64_t)); +#endif + /* + * If the subtable is now empty, remove its reference. + */ + if (xlat_table_is_empty(ctx, subtable)) { + table_base[table_idx] = INVALID_DESC; + xlat_arch_tlbi_va(table_idx_va, + ctx->xlat_regime); + } + + } else { + assert(action == ACTION_NONE); + } + + table_idx++; + table_idx_va += XLAT_BLOCK_SIZE(level); + + /* If reached the end of the region, exit */ + if (region_end_va <= table_idx_va) + break; + } + + if (level > ctx->base_level) + xlat_table_dec_regions_count(ctx, table_base); +} + +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +/* + * From the given arguments, it decides which action to take when mapping the + * specified region. + */ +static action_t xlat_tables_map_region_action(const mmap_region_t *mm, + unsigned int desc_type, unsigned long long dest_pa, + uintptr_t table_entry_base_va, unsigned int level) +{ + uintptr_t mm_end_va = mm->base_va + mm->size - 1U; + uintptr_t table_entry_end_va = + table_entry_base_va + XLAT_BLOCK_SIZE(level) - 1U; + + /* + * The descriptor types allowed depend on the current table level. + */ + + if ((mm->base_va <= table_entry_base_va) && + (mm_end_va >= table_entry_end_va)) { + + /* + * Table entry is covered by region + * -------------------------------- + * + * This means that this table entry can describe the whole + * translation with this granularity in principle. + */ + + if (level == 3U) { + /* + * Last level, only page descriptors are allowed. + */ + if (desc_type == PAGE_DESC) { + /* + * There's another region mapped here, don't + * overwrite. + */ + return ACTION_NONE; + } else { + assert(desc_type == INVALID_DESC); + return ACTION_WRITE_BLOCK_ENTRY; + } + + } else { + + /* + * Other levels. Table descriptors are allowed. Block + * descriptors too, but they have some limitations. + */ + + if (desc_type == TABLE_DESC) { + /* There's already a table, recurse into it. */ + return ACTION_RECURSE_INTO_TABLE; + + } else if (desc_type == INVALID_DESC) { + /* + * There's nothing mapped here, create a new + * entry. + * + * Check if the destination granularity allows + * us to use a block descriptor or we need a + * finer table for it. + * + * Also, check if the current level allows block + * descriptors. If not, create a table instead. + */ + if (((dest_pa & XLAT_BLOCK_MASK(level)) != 0U) + || (level < MIN_LVL_BLOCK_DESC) || + (mm->granularity < XLAT_BLOCK_SIZE(level))) + return ACTION_CREATE_NEW_TABLE; + else + return ACTION_WRITE_BLOCK_ENTRY; + + } else { + /* + * There's another region mapped here, don't + * overwrite. + */ + assert(desc_type == BLOCK_DESC); + + return ACTION_NONE; + } + } + + } else if ((mm->base_va <= table_entry_end_va) || + (mm_end_va >= table_entry_base_va)) { + + /* + * Region partially covers table entry + * ----------------------------------- + * + * This means that this table entry can't describe the whole + * translation, a finer table is needed. + + * There cannot be partial block overlaps in level 3. If that + * happens, some of the preliminary checks when adding the + * mmap region failed to detect that PA and VA must at least be + * aligned to PAGE_SIZE. + */ + assert(level < 3U); + + if (desc_type == INVALID_DESC) { + /* + * The block is not fully covered by the region. Create + * a new table, recurse into it and try to map the + * region with finer granularity. + */ + return ACTION_CREATE_NEW_TABLE; + + } else { + assert(desc_type == TABLE_DESC); + /* + * The block is not fully covered by the region, but + * there is already a table here. Recurse into it and + * try to map with finer granularity. + * + * PAGE_DESC for level 3 has the same value as + * TABLE_DESC, but this code can't run on a level 3 + * table because there can't be overlaps in level 3. + */ + return ACTION_RECURSE_INTO_TABLE; + } + } else { + + /* + * This table entry is outside of the region specified in the + * arguments, don't write anything to it. + */ + return ACTION_NONE; + } +} + +/* + * Recursive function that writes to the translation tables and maps the + * specified region. On success, it returns the VA of the last byte that was + * successfully mapped. On error, it returns the VA of the next entry that + * should have been mapped. + */ +static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm, + uintptr_t table_base_va, + uint64_t *const table_base, + unsigned int table_entries, + unsigned int level) +{ + assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX)); + + uintptr_t mm_end_va = mm->base_va + mm->size - 1U; + + uintptr_t table_idx_va; + unsigned long long table_idx_pa; + + uint64_t *subtable; + uint64_t desc; + + unsigned int table_idx; + + table_idx_va = xlat_tables_find_start_va(mm, table_base_va, level); + table_idx = xlat_tables_va_to_index(table_base_va, table_idx_va, level); + +#if PLAT_XLAT_TABLES_DYNAMIC + if (level > ctx->base_level) + xlat_table_inc_regions_count(ctx, table_base); +#endif + + while (table_idx < table_entries) { + + desc = table_base[table_idx]; + + table_idx_pa = mm->base_pa + table_idx_va - mm->base_va; + + action_t action = xlat_tables_map_region_action(mm, + (uint32_t)(desc & DESC_MASK), table_idx_pa, + table_idx_va, level); + + if (action == ACTION_WRITE_BLOCK_ENTRY) { + + table_base[table_idx] = + xlat_desc(ctx, (uint32_t)mm->attr, table_idx_pa, + level); + + } else if (action == ACTION_CREATE_NEW_TABLE) { + uintptr_t end_va; + + subtable = xlat_table_get_empty(ctx); + if (subtable == NULL) { + /* Not enough free tables to map this region */ + return table_idx_va; + } + + /* Point to new subtable from this one. */ + table_base[table_idx] = + TABLE_DESC | (uintptr_t)subtable; + + /* Recurse to write into subtable */ + end_va = xlat_tables_map_region(ctx, mm, table_idx_va, + subtable, XLAT_TABLE_ENTRIES, + level + 1U); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)subtable, + XLAT_TABLE_ENTRIES * sizeof(uint64_t)); +#endif + if (end_va != + (table_idx_va + XLAT_BLOCK_SIZE(level) - 1U)) + return end_va; + + } else if (action == ACTION_RECURSE_INTO_TABLE) { + uintptr_t end_va; + + subtable = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK); + /* Recurse to write into subtable */ + end_va = xlat_tables_map_region(ctx, mm, table_idx_va, + subtable, XLAT_TABLE_ENTRIES, + level + 1U); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)subtable, + XLAT_TABLE_ENTRIES * sizeof(uint64_t)); +#endif + if (end_va != + (table_idx_va + XLAT_BLOCK_SIZE(level) - 1U)) + return end_va; + + } else { + + assert(action == ACTION_NONE); + + } + + table_idx++; + table_idx_va += XLAT_BLOCK_SIZE(level); + + /* If reached the end of the region, exit */ + if (mm_end_va <= table_idx_va) + break; + } + + return table_idx_va - 1U; +} + +/* + * Function that verifies that a region can be mapped. + * Returns: + * 0: Success, the mapping is allowed. + * EINVAL: Invalid values were used as arguments. + * ERANGE: The memory limits were surpassed. + * ENOMEM: There is not enough memory in the mmap array. + * EPERM: Region overlaps another one in an invalid way. + */ +static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm) +{ + unsigned long long base_pa = mm->base_pa; + uintptr_t base_va = mm->base_va; + size_t size = mm->size; + size_t granularity = mm->granularity; + + unsigned long long end_pa = base_pa + size - 1U; + uintptr_t end_va = base_va + size - 1U; + + if (!IS_PAGE_ALIGNED(base_pa) || !IS_PAGE_ALIGNED(base_va) || + !IS_PAGE_ALIGNED(size)) + return -EINVAL; + + if ((granularity != XLAT_BLOCK_SIZE(1U)) && + (granularity != XLAT_BLOCK_SIZE(2U)) && + (granularity != XLAT_BLOCK_SIZE(3U))) { + return -EINVAL; + } + + /* Check for overflows */ + if ((base_pa > end_pa) || (base_va > end_va)) + return -ERANGE; + + if (end_va > ctx->va_max_address) + return -ERANGE; + + if (end_pa > ctx->pa_max_address) + return -ERANGE; + + /* Check that there is space in the ctx->mmap array */ + if (ctx->mmap[ctx->mmap_num - 1].size != 0U) + return -ENOMEM; + + /* Check for PAs and VAs overlaps with all other regions */ + for (const mmap_region_t *mm_cursor = ctx->mmap; + mm_cursor->size != 0U; ++mm_cursor) { + + uintptr_t mm_cursor_end_va = mm_cursor->base_va + + mm_cursor->size - 1U; + + /* + * Check if one of the regions is completely inside the other + * one. + */ + bool fully_overlapped_va = + ((base_va >= mm_cursor->base_va) && + (end_va <= mm_cursor_end_va)) || + ((mm_cursor->base_va >= base_va) && + (mm_cursor_end_va <= end_va)); + + /* + * Full VA overlaps are only allowed if both regions are + * identity mapped (zero offset) or have the same VA to PA + * offset. Also, make sure that it's not the exact same area. + * This can only be done with static regions. + */ + if (fully_overlapped_va) { + +#if PLAT_XLAT_TABLES_DYNAMIC + if (((mm->attr & MT_DYNAMIC) != 0U) || + ((mm_cursor->attr & MT_DYNAMIC) != 0U)) + return -EPERM; +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + if ((mm_cursor->base_va - mm_cursor->base_pa) != + (base_va - base_pa)) + return -EPERM; + + if ((base_va == mm_cursor->base_va) && + (size == mm_cursor->size)) + return -EPERM; + + } else { + /* + * If the regions do not have fully overlapping VAs, + * then they must have fully separated VAs and PAs. + * Partial overlaps are not allowed + */ + + unsigned long long mm_cursor_end_pa = + mm_cursor->base_pa + mm_cursor->size - 1U; + + bool separated_pa = (end_pa < mm_cursor->base_pa) || + (base_pa > mm_cursor_end_pa); + bool separated_va = (end_va < mm_cursor->base_va) || + (base_va > mm_cursor_end_va); + + if (!separated_va || !separated_pa) + return -EPERM; + } + } + + return 0; +} + +void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm) +{ + mmap_region_t *mm_cursor = ctx->mmap, *mm_destination; + const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num; + const mmap_region_t *mm_last; + unsigned long long end_pa = mm->base_pa + mm->size - 1U; + uintptr_t end_va = mm->base_va + mm->size - 1U; + int ret; + + /* Ignore empty regions */ + if (mm->size == 0U) + return; + + ret = mmap_add_region_check(ctx, mm); + if (ret != 0) { + //ERROR("mmap_add_region_check() failed. error %d\n", ret); + assert(false); + return; + } + + /* + * Find correct place in mmap to insert new region. + * + * 1 - Lower region VA end first. + * 2 - Smaller region size first. + * + * VA 0 0xFF + * + * 1st |------| + * 2nd |------------| + * 3rd |------| + * 4th |---| + * 5th |---| + * 6th |----------| + * 7th |-------------------------------------| + * + * This is required for overlapping regions only. It simplifies adding + * regions with the loop in xlat_tables_init_internal because the outer + * ones won't overwrite block or page descriptors of regions added + * previously. + * + * Overlapping is only allowed for static regions. + */ + + while (((mm_cursor->base_va + mm_cursor->size - 1U) < end_va) + && (mm_cursor->size != 0U)) { + ++mm_cursor; + } + + while (((mm_cursor->base_va + mm_cursor->size - 1U) == end_va) && + (mm_cursor->size != 0U) && (mm_cursor->size < mm->size)) { + ++mm_cursor; + } + + /* + * Find the last entry marker in the mmap + */ + mm_last = ctx->mmap; + while ((mm_last->size != 0U) && (mm_last < mm_end)) { + ++mm_last; + } + + /* + * Check if we have enough space in the memory mapping table. + * This shouldn't happen as we have checked in mmap_add_region_check + * that there is free space. + */ + assert(mm_last->size == 0U); + + /* Make room for new region by moving other regions up by one place */ + mm_destination = mm_cursor + 1; + (void)memmove(mm_destination, mm_cursor, + (uintptr_t)mm_last - (uintptr_t)mm_cursor); + + /* + * Check we haven't lost the empty sentinel from the end of the array. + * This shouldn't happen as we have checked in mmap_add_region_check + * that there is free space. + */ + assert(mm_end->size == 0U); + + *mm_cursor = *mm; + + if (end_pa > ctx->max_pa) + ctx->max_pa = end_pa; + if (end_va > ctx->max_va) + ctx->max_va = end_va; +} + +/* + * Determine the table level closest to the initial lookup level that + * can describe this translation. Then, align base VA to the next block + * at the determined level. + */ +static void mmap_alloc_va_align_ctx(xlat_ctx_t *ctx, mmap_region_t *mm) +{ + /* + * By or'ing the size and base PA the alignment will be the one + * corresponding to the smallest boundary of the two of them. + * + * There are three different cases. For example (for 4 KiB page size): + * + * +--------------+------------------++--------------+ + * | PA alignment | Size multiple of || VA alignment | + * +--------------+------------------++--------------+ + * | 2 MiB | 2 MiB || 2 MiB | (1) + * | 2 MiB | 4 KiB || 4 KiB | (2) + * | 4 KiB | 2 MiB || 4 KiB | (3) + * +--------------+------------------++--------------+ + * + * - In (1), it is possible to take advantage of the alignment of the PA + * and the size of the region to use a level 2 translation table + * instead of a level 3 one. + * + * - In (2), the size is smaller than a block entry of level 2, so it is + * needed to use a level 3 table to describe the region or the library + * will map more memory than the desired one. + * + * - In (3), even though the region has the size of one level 2 block + * entry, it isn't possible to describe the translation with a level 2 + * block entry because of the alignment of the base PA. + * + * Only bits 47:21 of a level 2 block descriptor are used by the MMU, + * bits 20:0 of the resulting address are 0 in this case. Because of + * this, the PA generated as result of this translation is aligned to + * 2 MiB. The PA that was requested to be mapped is aligned to 4 KiB, + * though, which means that the resulting translation is incorrect. + * The only way to prevent this is by using a finer granularity. + */ + unsigned long long align_check; + + align_check = mm->base_pa | (unsigned long long)mm->size; + + /* + * Assume it is always aligned to level 3. There's no need to check that + * level because its block size is PAGE_SIZE. The checks to verify that + * the addresses and size are aligned to PAGE_SIZE are inside + * mmap_add_region. + */ + for (unsigned int level = ctx->base_level; level <= 2U; ++level) { + + if ((align_check & XLAT_BLOCK_MASK(level)) != 0U) + continue; + + mm->base_va = round_up(mm->base_va, XLAT_BLOCK_SIZE(level)); + return; + } +} + +void mmap_add_region_alloc_va_ctx(xlat_ctx_t *ctx, mmap_region_t *mm) +{ + mm->base_va = ctx->max_va + 1UL; + + assert(mm->size > 0U); + + mmap_alloc_va_align_ctx(ctx, mm); + + /* Detect overflows. More checks are done in mmap_add_region_check(). */ + assert(mm->base_va > ctx->max_va); + + mmap_add_region_ctx(ctx, mm); +} + +void mmap_add_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm) +{ + const mmap_region_t *mm_cursor = mm; + + while (mm_cursor->granularity != 0U) { + mmap_add_region_ctx(ctx, mm_cursor); + mm_cursor++; + } +} + +#if PLAT_XLAT_TABLES_DYNAMIC + +int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm) +{ + mmap_region_t *mm_cursor = ctx->mmap; + const mmap_region_t *mm_last = mm_cursor + ctx->mmap_num; + unsigned long long end_pa = mm->base_pa + mm->size - 1U; + uintptr_t end_va = mm->base_va + mm->size - 1U; + int ret; + + /* Nothing to do */ + if (mm->size == 0U) + return 0; + + /* Now this region is a dynamic one */ + mm->attr |= MT_DYNAMIC; + + ret = mmap_add_region_check(ctx, mm); + if (ret != 0) + return ret; + + /* + * Find the adequate entry in the mmap array in the same way done for + * static regions in mmap_add_region_ctx(). + */ + + while (((mm_cursor->base_va + mm_cursor->size - 1U) < end_va) + && (mm_cursor->size != 0U)) { + ++mm_cursor; + } + + while (((mm_cursor->base_va + mm_cursor->size - 1U) == end_va) && + (mm_cursor->size != 0U) && (mm_cursor->size < mm->size)) { + ++mm_cursor; + } + + /* Make room for new region by moving other regions up by one place */ + (void)memmove(mm_cursor + 1U, mm_cursor, + (uintptr_t)mm_last - (uintptr_t)mm_cursor); + + /* + * Check we haven't lost the empty sentinel from the end of the array. + * This shouldn't happen as we have checked in mmap_add_region_check + * that there is free space. + */ + assert(mm_last->size == 0U); + + *mm_cursor = *mm; + + /* + * Update the translation tables if the xlat tables are initialized. If + * not, this region will be mapped when they are initialized. + */ + if (ctx->initialized) { + end_va = xlat_tables_map_region(ctx, mm_cursor, + 0U, ctx->base_table, ctx->base_table_entries, + ctx->base_level); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)ctx->base_table, + ctx->base_table_entries * sizeof(uint64_t)); +#endif + /* Failed to map, remove mmap entry, unmap and return error. */ + if (end_va != (mm_cursor->base_va + mm_cursor->size - 1U)) { + (void)memmove(mm_cursor, mm_cursor + 1U, + (uintptr_t)mm_last - (uintptr_t)mm_cursor); + + /* + * Check if the mapping function actually managed to map + * anything. If not, just return now. + */ + if (mm->base_va >= end_va) + return -ENOMEM; + + /* + * Something went wrong after mapping some table + * entries, undo every change done up to this point. + */ + mmap_region_t unmap_mm = { + .base_pa = 0U, + .base_va = mm->base_va, + .size = end_va - mm->base_va, + .attr = 0U + }; + xlat_tables_unmap_region(ctx, &unmap_mm, 0U, + ctx->base_table, ctx->base_table_entries, + ctx->base_level); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)ctx->base_table, + ctx->base_table_entries * sizeof(uint64_t)); +#endif + return -ENOMEM; + } + + /* + * Make sure that all entries are written to the memory. There + * is no need to invalidate entries when mapping dynamic regions + * because new table/block/page descriptors only replace old + * invalid descriptors, that aren't TLB cached. + */ + dsbishst(); + } + + if (end_pa > ctx->max_pa) + ctx->max_pa = end_pa; + if (end_va > ctx->max_va) + ctx->max_va = end_va; + + return 0; +} + +int mmap_add_dynamic_region_alloc_va_ctx(xlat_ctx_t *ctx, mmap_region_t *mm) +{ + mm->base_va = ctx->max_va + 1UL; + + if (mm->size == 0U) + return 0; + + mmap_alloc_va_align_ctx(ctx, mm); + + /* Detect overflows. More checks are done in mmap_add_region_check(). */ + if (mm->base_va < ctx->max_va) { + return -ENOMEM; + } + + return mmap_add_dynamic_region_ctx(ctx, mm); +} + +/* + * Removes the region with given base Virtual Address and size from the given + * context. + * + * Returns: + * 0: Success. + * EINVAL: Invalid values were used as arguments (region not found). + * EPERM: Tried to remove a static region. + */ +int mmap_remove_dynamic_region_ctx(xlat_ctx_t *ctx, uintptr_t base_va, + size_t size) +{ + mmap_region_t *mm = ctx->mmap; + const mmap_region_t *mm_last = mm + ctx->mmap_num; + int update_max_va_needed = 0; + int update_max_pa_needed = 0; + + /* Check sanity of mmap array. */ + assert(mm[ctx->mmap_num].size == 0U); + + while (mm->size != 0U) { + if ((mm->base_va == base_va) && (mm->size == size)) + break; + ++mm; + } + + /* Check that the region was found */ + if (mm->size == 0U) + return -EINVAL; + + /* If the region is static it can't be removed */ + if ((mm->attr & MT_DYNAMIC) == 0U) + return -EPERM; + + /* Check if this region is using the top VAs or PAs. */ + if ((mm->base_va + mm->size - 1U) == ctx->max_va) + update_max_va_needed = 1; + if ((mm->base_pa + mm->size - 1U) == ctx->max_pa) + update_max_pa_needed = 1; + + /* Update the translation tables if needed */ + if (ctx->initialized) { + xlat_tables_unmap_region(ctx, mm, 0U, ctx->base_table, + ctx->base_table_entries, + ctx->base_level); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)ctx->base_table, + ctx->base_table_entries * sizeof(uint64_t)); +#endif + xlat_arch_tlbi_va_sync(); + } + + /* Remove this region by moving the rest down by one place. */ + (void)memmove(mm, mm + 1U, (uintptr_t)mm_last - (uintptr_t)mm); + + /* Check if we need to update the max VAs and PAs */ + if (update_max_va_needed == 1) { + ctx->max_va = 0U; + mm = ctx->mmap; + while (mm->size != 0U) { + if ((mm->base_va + mm->size - 1U) > ctx->max_va) + ctx->max_va = mm->base_va + mm->size - 1U; + ++mm; + } + } + + if (update_max_pa_needed == 1) { + ctx->max_pa = 0U; + mm = ctx->mmap; + while (mm->size != 0U) { + if ((mm->base_pa + mm->size - 1U) > ctx->max_pa) + ctx->max_pa = mm->base_pa + mm->size - 1U; + ++mm; + } + } + + return 0; +} + +void xlat_setup_dynamic_ctx(xlat_ctx_t *ctx, unsigned long long pa_max, + uintptr_t va_max, struct mmap_region *mmap, + unsigned int mmap_num, uint64_t **tables, + unsigned int tables_num, uint64_t *base_table, + int xlat_regime, int *mapped_regions) +{ + ctx->xlat_regime = xlat_regime; + + ctx->pa_max_address = pa_max; + ctx->va_max_address = va_max; + + ctx->mmap = mmap; + ctx->mmap_num = mmap_num; + memset(ctx->mmap, 0, sizeof(struct mmap_region) * mmap_num); + + ctx->tables = (void *) tables; + ctx->tables_num = tables_num; + + uintptr_t va_space_size = va_max + 1; + ctx->base_level = GET_XLAT_TABLE_LEVEL_BASE(va_space_size); + ctx->base_table = base_table; + ctx->base_table_entries = (unsigned int)GET_NUM_BASE_LEVEL_ENTRIES(va_space_size); + + ctx->tables_mapped_regions = mapped_regions; + + ctx->max_pa = 0; + ctx->max_va = 0; + ctx->initialized = 0; +} + +#endif /* PLAT_XLAT_TABLES_DYNAMIC */ + +void init_xlat_tables_ctx(xlat_ctx_t *ctx) +{ + assert(ctx != NULL); + assert((ctx->xlat_regime == EL3_REGIME) || + (ctx->xlat_regime == EL2_REGIME) || + (ctx->xlat_regime == EL1_EL0_REGIME)); + assert(!is_mmu_enabled_ctx(ctx)); + + mmap_region_t *mm = ctx->mmap; + + assert(ctx->va_max_address >= + (xlat_get_min_virt_addr_space_size() - 1U)); + assert(ctx->va_max_address <= (MAX_VIRT_ADDR_SPACE_SIZE - 1U)); + assert(IS_POWER_OF_TWO(ctx->va_max_address + 1U)); + + xlat_mmap_print(mm); + + /* All tables must be zeroed before mapping any region. */ + + for (unsigned int i = 0U; i < ctx->base_table_entries; i++) + ctx->base_table[i] = INVALID_DESC; + + for (unsigned int j = 0; j < ctx->tables_num; j++) { +#if PLAT_XLAT_TABLES_DYNAMIC + ctx->tables_mapped_regions[j] = 0; +#endif + for (unsigned int i = 0U; i < XLAT_TABLE_ENTRIES; i++) + ctx->tables[j][i] = INVALID_DESC; + } + + while (mm->size != 0U) { + uintptr_t end_va = xlat_tables_map_region(ctx, mm, 0U, + ctx->base_table, ctx->base_table_entries, + ctx->base_level); +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) + xlat_clean_dcache_range((uintptr_t)ctx->base_table, + ctx->base_table_entries * sizeof(uint64_t)); +#endif + if (end_va != (mm->base_va + mm->size - 1U)) { + assert(end_va == (mm->base_va + mm->size - 1U)); + } + mm++; + } + + assert(ctx->pa_max_address <= xlat_arch_get_max_supported_pa()); + assert(ctx->max_va <= ctx->va_max_address); + assert(ctx->max_pa <= ctx->pa_max_address); + + ctx->initialized = true; + + xlat_tables_print(ctx); +} diff --git a/val/xlat_tables_v2/src/xlat_tables_utils.c b/val/xlat_tables_v2/src/xlat_tables_utils.c new file mode 100644 index 00000000..ba7d617f --- /dev/null +++ b/val/xlat_tables_v2/src/xlat_tables_utils.c @@ -0,0 +1,574 @@ +/* + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file is derived from xlat_table_v2 library in TF-A project */ + +#include +#include +#include +#include +#include + +#include +#include +#include "xlat_tables_private.h" +#include "arch_helpers.h" +#include "debug.h" +#include "assert.h" + +#if LOG_LEVEL < LOG_LEVEL_VERBOSE + +void xlat_mmap_print(__unused const mmap_region_t *mmap) +{ + /* Empty */ +} + +void xlat_tables_print(__unused xlat_ctx_t *ctx) +{ + /* Empty */ +} + +#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */ + +void xlat_mmap_print(const mmap_region_t *mmap) +{ + LOG(DBG, "mmap:\n"); + const mmap_region_t *mm = mmap; + + while (mm->size != 0U) { + LOG(DBG, " VA:0x%lx PA:0x%lx size:0x%lx attr:0x%x granularity:0x%lx\n", + mm->base_va, mm->base_pa, mm->size, mm->attr, mm->granularity); + ++mm; + }; + LOG(DBG, "\n"); +} + +/* Print the attributes of the specified block descriptor. */ +static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc) +{ + uint64_t mem_type_index = ATTR_INDEX_GET(desc); + int xlat_regime = ctx->xlat_regime; + + if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) { + LOG(DBG, "MEM"); + } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) { + LOG(DBG, "NC"); + } else { + assert(mem_type_index == ATTR_DEV_INDEX); + LOG(DBG, "DEV"); + } + + if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) { + /* For EL3 and EL2 only check the AP[2] and XN bits. */ + LOG(DBG, ((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW"); + LOG(DBG, ((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC"); + } else { + assert(xlat_regime == EL1_EL0_REGIME); + /* + * For EL0 and EL1: + * - In AArch64 PXN and UXN can be set independently but in + * AArch32 there is no UXN (XN affects both privilege levels). + * For consistency, we set them simultaneously in both cases. + * - RO and RW permissions must be the same in EL1 and EL0. If + * EL0 can access that memory region, so can EL1, with the + * same permissions. + */ + uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME); + uint64_t xn_perm = desc & xn_mask; + + assert((xn_perm == xn_mask) || (xn_perm == 0ULL)); + LOG(DBG, ((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW"); + /* Only check one of PXN and UXN, the other one is the same. */ + LOG(DBG, ((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC"); + /* + * Privileged regions can only be accessed from EL1, user + * regions can be accessed from EL1 and EL0. + */ + LOG(DBG, ((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL) + ? "-USER" : "-PRIV"); + } + + switch (desc & LOWER_ATTRS(EL3_S1_NSE | NS)) { + case 0ULL: + LOG(DBG, "-S"); + break; + case LOWER_ATTRS(NS): + LOG(DBG, "-NS"); + break; + case LOWER_ATTRS(EL3_S1_NSE): + LOG(DBG, "-RT"); + break; + default: /* LOWER_ATTRS(EL3_S1_NSE | NS) */ + LOG(DBG, "-RL"); + } + +#ifdef __aarch64__ + /* Check Guarded Page bit */ + if ((desc & GP) != 0ULL) { + LOG(DBG, "-GP"); + } +#endif +} + +static const char * const level_spacers[] = { + "[LV0] ", + " [LV1] ", + " [LV2] ", + " [LV3] " +}; + +static const char *invalid_descriptors_ommited = + "%s(%d invalid descriptors omitted)\n"; + +/* + * Recursive function that reads the translation tables passed as an argument + * and prints their status. + */ +static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va, + const uint64_t *table_base, unsigned int table_entries, + unsigned int level) +{ + assert(level <= XLAT_TABLE_LEVEL_MAX); + + uint64_t desc; + uintptr_t table_idx_va = table_base_va; + unsigned int table_idx = 0U; + size_t level_size = XLAT_BLOCK_SIZE(level); + + /* + * Keep track of how many invalid descriptors are counted in a row. + * Whenever multiple invalid descriptors are found, only the first one + * is printed, and a line is added to inform about how many descriptors + * have been omitted. + */ + uint64_t invalid_row_count = 0; + + while (table_idx < table_entries) { + + desc = table_base[table_idx]; + + if ((desc & DESC_MASK) == INVALID_DESC) { + + if (invalid_row_count == 0) { + LOG(DBG, "%sVA:0x%lx size:0x%lx \n", + level_spacers[level], + table_idx_va, level_size); + } + invalid_row_count++; + + } else { + + if (invalid_row_count > 1) { + LOG(DBG, invalid_descriptors_ommited, + level_spacers[level], + invalid_row_count - 1); + } + invalid_row_count = 0; + + /* + * Check if this is a table or a block. Tables are only + * allowed in levels other than 3, but DESC_PAGE has the + * same value as DESC_TABLE, so we need to check. + */ + if (((desc & DESC_MASK) == TABLE_DESC) && + (level < XLAT_TABLE_LEVEL_MAX)) { + /* + * Do not print any PA for a table descriptor, + * as it doesn't directly map physical memory + * but instead points to the next translation + * table in the translation table walk. + */ + LOG(DBG, "%sVA:0x%lx size:0x%lx \n", + level_spacers[level], + table_idx_va, level_size); + + uintptr_t addr_inner = desc & TABLE_ADDR_MASK; + + xlat_tables_print_internal(ctx, table_idx_va, + (uint64_t *)addr_inner, + XLAT_TABLE_ENTRIES, level + 1U); + } else { + LOG(DBG, "%sVA:0x%lx PA:0x%lx size:0x%lx ", + level_spacers[level], table_idx_va, + (uint64_t)(desc & TABLE_ADDR_MASK), level_size); + xlat_desc_print(ctx, desc); + LOG(DBG, "\n"); + } + } + + table_idx++; + table_idx_va += level_size; + } + + if (invalid_row_count > 1) { + LOG(DBG, level_spacers[level], + invalid_descriptors_ommited, + invalid_row_count - 1); + } +} + +void xlat_tables_print(xlat_ctx_t *ctx) +{ + const char *xlat_regime_str; + uint64_t used_page_tables; + + if (ctx->xlat_regime == EL1_EL0_REGIME) { + xlat_regime_str = "1&0"; + } else if (ctx->xlat_regime == EL2_REGIME) { + xlat_regime_str = "2"; + } else { + assert(ctx->xlat_regime == EL3_REGIME); + xlat_regime_str = "3"; + } + LOG(DBG, "Translation tables state:\n"); + LOG(DBG, " Xlat regime: EL %s\n", xlat_regime_str); + LOG(DBG, " Max allowed PA: 0x%lx\n", ctx->pa_max_address); + LOG(DBG, " Max allowed VA: 0x%lx\n", ctx->va_max_address); + LOG(DBG, " Max mapped PA: 0x%lx\n", ctx->max_pa); + LOG(DBG, " Max mapped VA: 0x%lx\n", ctx->max_va); + + LOG(DBG, " Initial lookup level: 0x%x\n", ctx->base_level); + LOG(DBG, " Entries @initial lookup level: 0x%x\n", ctx->base_table_entries); + +#if PLAT_XLAT_TABLES_DYNAMIC + used_page_tables = 0; + for (unsigned int i = 0; i < ctx->tables_num; ++i) { + if (ctx->tables_mapped_regions[i] != 0) + ++used_page_tables; + } +#else + used_page_tables = ctx->next_table; +#endif + LOG(DBG, " Used %d sub-tables out of %d\n", used_page_tables, (uint64_t)ctx->tables_num); + LOG(DBG, "(spare: %d)\n", (uint64_t)ctx->tables_num - used_page_tables); + + xlat_tables_print_internal(ctx, 0U, ctx->base_table, + ctx->base_table_entries, ctx->base_level); +} + +#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */ + +/* + * Do a translation table walk to find the block or page descriptor that maps + * virtual_addr. + * + * On success, return the address of the descriptor within the translation + * table. Its lookup level is stored in '*out_level'. + * On error, return NULL. + * + * xlat_table_base + * Base address for the initial lookup level. + * xlat_table_base_entries + * Number of entries in the translation table for the initial lookup level. + * virt_addr_space_size + * Size in bytes of the virtual address space. + */ +static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr, + void *xlat_table_base, + unsigned int xlat_table_base_entries, + unsigned long long virt_addr_space_size, + unsigned int *out_level) +{ + unsigned int start_level; + uint64_t *table; + unsigned int entries; + + start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size); + + table = xlat_table_base; + entries = xlat_table_base_entries; + + for (unsigned int level = start_level; + level <= XLAT_TABLE_LEVEL_MAX; + ++level) { + uint64_t idx, desc, desc_type; + + idx = XLAT_TABLE_IDX(virtual_addr, level); + if (idx >= entries) { + LOG(ERROR, "Missing xlat table entry at address 0x%lx\n", virtual_addr); + return NULL; + } + + desc = table[idx]; + desc_type = desc & DESC_MASK; + + if (desc_type == INVALID_DESC) { + LOG(DBG, "Invalid entry (memory not mapped)\n"); + return NULL; + } + + if (level == XLAT_TABLE_LEVEL_MAX) { + /* + * Only page descriptors allowed at the final lookup + * level. + */ + assert(desc_type == PAGE_DESC); + *out_level = level; + return &table[idx]; + } + + if (desc_type == BLOCK_DESC) { + *out_level = level; + return &table[idx]; + } + + assert(desc_type == TABLE_DESC); + table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK); + entries = XLAT_TABLE_ENTRIES; + } + + /* + * This shouldn't be reached, the translation table walk should end at + * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop. + */ + assert(false); + + return NULL; +} + + +static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx, + uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry, + unsigned long long *addr_pa, unsigned int *table_level) +{ + uint64_t *entry; + uint64_t desc; + unsigned int level; + unsigned long long virt_addr_space_size; + + /* + * Sanity-check arguments. + */ + assert(ctx != NULL); + assert(ctx->initialized); + assert((ctx->xlat_regime == EL1_EL0_REGIME) || + (ctx->xlat_regime == EL2_REGIME) || + (ctx->xlat_regime == EL3_REGIME)); + + virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL; + assert(virt_addr_space_size > 0U); + + entry = find_xlat_table_entry(base_va, + ctx->base_table, + ctx->base_table_entries, + virt_addr_space_size, + &level); + if (entry == NULL) { + LOG(ERROR, "Address 0x%lx is not mapped.\n", base_va); + return -EINVAL; + } + + if (addr_pa != NULL) { + *addr_pa = *entry & TABLE_ADDR_MASK; + } + + if (table_entry != NULL) { + *table_entry = entry; + } + + if (table_level != NULL) { + *table_level = level; + } + + desc = *entry; + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + LOG(DBG, "Attributes: \n"); + xlat_desc_print(ctx, desc); + LOG(DBG, "\n"); +#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */ + + assert(attributes != NULL); + *attributes = 0U; + + uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK; + + if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) { + *attributes |= MT_MEMORY; + } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) { + *attributes |= MT_NON_CACHEABLE; + } else { + assert(attr_index == ATTR_DEV_INDEX); + *attributes |= MT_DEVICE; + } + + uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U; + + if (ap2_bit == AP2_RW) + *attributes |= MT_RW; + + if (ctx->xlat_regime == EL1_EL0_REGIME) { + uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U; + + if (ap1_bit == AP1_ACCESS_UNPRIVILEGED) + *attributes |= MT_USER; + } + + uint64_t ns_bit = (desc >> NS_SHIFT) & 1U; + + if (ns_bit == 1U) + *attributes |= MT_NS; + + uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime); + + if ((desc & xn_mask) == xn_mask) { + *attributes |= MT_EXECUTE_NEVER; + } else { + assert((desc & xn_mask) == 0U); + } + + /* Set MT_AF_CLEAR bit if Access flag is set */ + if (desc >> ACCESS_FLAG_SHIFT & 1U) + *attributes |= MT_AF_CLEAR; + + return 0; +} + + +int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, + uint32_t *attr) +{ + return xlat_get_mem_attributes_internal(ctx, base_va, attr, + NULL, NULL, NULL); +} + + +int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, + size_t size, uint32_t attr) +{ + /* Note: This implementation isn't optimized. */ + + assert(ctx != NULL); + assert(ctx->initialized); + + unsigned long long virt_addr_space_size = + (unsigned long long)ctx->va_max_address + 1U; + assert(virt_addr_space_size > 0U); + + if (!IS_PAGE_ALIGNED(base_va)) { + LOG(DBG, __func__); + LOG(ERROR, " Address 0x%lx is not aligned on a page boundary.\n", base_va); + return -EINVAL; + } + + if (size == 0U) { + LOG(DBG, __func__); + LOG(ERROR, " Size is 0\n"); + return -EINVAL; + } + + if ((size % PAGE_SIZE) != 0U) { + LOG(DBG, __func__); + LOG(ERROR, " Sixe 0x%lx is not a multiple of page size.\n", size); + return -EINVAL; + } + + if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) { + LOG(DBG, __func__); + LOG(ERROR, " Mapping memory as read-write and executable not allowed.\n"); + return -EINVAL; + } + + size_t pages_count = size / PAGE_SIZE; + + LOG(DBG, "Changing memory attributes of 0x%x pages starting from address 0x%lx...\n", + pages_count, base_va); + + uintptr_t base_va_original = base_va; + + /* + * Sanity checks. + */ + for (unsigned int i = 0U; i < pages_count; ++i) { + const uint64_t *entry; + uint64_t desc, attr_index; + unsigned int level; + + entry = find_xlat_table_entry(base_va, + ctx->base_table, + ctx->base_table_entries, + virt_addr_space_size, + &level); + if (entry == NULL) { + LOG(ERROR, "Address 0x%lx is not mapped.\n", base_va); + return -EINVAL; + } + + desc = *entry; + + /* + * Check that all the required pages are mapped at page + * granularity. + */ + if (((desc & DESC_MASK) != PAGE_DESC) || + (level != XLAT_TABLE_LEVEL_MAX)) { + LOG(ALWAYS, "Address 0x%lx is not mapped at the right granularity.\n", + base_va); + LOG(ERROR, "Granularity is 0x%lx, should be 0x%lx.\n", + XLAT_BLOCK_SIZE(level), PAGE_SIZE); + return -EINVAL; + } + + /* + * If the region type is device, it shouldn't be executable. + */ + attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK; + if (attr_index == ATTR_DEV_INDEX) { + if ((attr & MT_EXECUTE_NEVER) == 0U) { + LOG(ERROR, "Setting device memory as executable at address 0x%lx.\n", + base_va); + return -EINVAL; + } + } + + base_va += PAGE_SIZE; + } + + /* Restore original value. */ + base_va = base_va_original; + + for (unsigned int i = 0U; i < pages_count; ++i) { + + uint32_t old_attr = 0U, new_attr; + uint64_t *entry = NULL; + unsigned int level = 0U; + unsigned long long addr_pa = 0ULL; + + (void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr, + &entry, &addr_pa, &level); + + /* Ignore old attributes. Rewrite the descriptor with new attributs */ + new_attr = attr; + + /* + * The break-before-make sequence requires writing an invalid + * descriptor and making sure that the system sees the change + * before writing the new descriptor. + */ + *entry = INVALID_DESC; +#if !HW_ASSISTED_COHERENCY + dccvac((uintptr_t)entry); +#endif + /* Invalidate any cached copy of this mapping in the TLBs. */ + xlat_arch_tlbi_va(base_va, ctx->xlat_regime); + + /* Ensure completion of the invalidation. */ + xlat_arch_tlbi_va_sync(); + + /* Write new descriptor */ + *entry = xlat_desc(ctx, new_attr, addr_pa, level); +#if !HW_ASSISTED_COHERENCY + dccvac((uintptr_t)entry); +#endif + base_va += PAGE_SIZE; + } + + /* Ensure that the last descriptor written is seen by the system. */ + dsbish(); + + return 0; +} From 3052e9cc3e00cf7e1c54612517608cbf34acf24c Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Fri, 20 Feb 2026 03:40:44 +0000 Subject: [PATCH 06/13] Implement Unified VAL Status Reporting - Added val_status.h and val_status.h for status reporting - Design changes only patchset(review feedback incorporated) Signed-off-by: Shruti Ghadge Change-Id: If614cff14863a21c54405380569f854acc3d114b --- val/include/val_status.h | 108 +++++++++++++++++++++++++++++++++++ val/src/val_status.c | 120 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 val/include/val_status.h create mode 100644 val/src/val_status.c diff --git a/val/include/val_status.h b/val/include/val_status.h new file mode 100644 index 00000000..bf19de90 --- /dev/null +++ b/val/include/val_status.h @@ -0,0 +1,108 @@ +/** @file + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef VAL_STATUS_H +#define VAL_STATUS_H + +#ifndef TARGET_UEFI +#include +#endif + +#include "pal_interface.h" + +/* Structure to capture test state */ +typedef struct { + uint32_t index; + uint8_t state; + uint16_t status_code; +} val_test_status_t; + +/* ========================================================= + * TEST STATES + * ========================================================= */ +#define TEST_START 0x1u //Test execution has started +#define TEST_END 0x2u //Test execution is completed +#define TEST_PASS 0x4u //Test is passed +#define TEST_PARTIAL_COVERED 0x5u //Test is Partially covered +#define TEST_WARNING 0x6u //Test executed with warnings +#define TEST_SKIP 0x7u //Test is Skipped +#define TEST_FAIL 0x8u //Test reported Failure +#define TEST_NOT_IMPLEMENTED 0x9u //Test is not implemented +#define TEST_PAL_NOT_SUPPORTED 0xAu //Test has no PAL support +#define TEST_SUPPORTED 0x0u //Test is supported for a particular platform/rules +#define TEST_STATE_UNKNOWN 0xFu //Test state not applicable/unknown + +/* ========================================================= + * STATUS / RESULT CODES + * ========================================================= */ +#define STATUS_SUCCESS 0x0u //ACS reported success +#define STATUS_ERROR 0x1u //ACS reported error +#define STATUS_SKIP 0x2u //ACS reported Skipped +#define ERROR_POINT(n) ((uint16_t)(n)) //Checkpoint for FAIL/WARN/SKIP +#define STATUS_UNKNOWN 0xFFFFu // status code not applicable/unknown + +/* ========================================================= + * PACKING FORMAT (32-bit) + * [31:28] state (4 bits) | [15:0] status/code (16 bits) + * ========================================================= */ +#define VAL_TEST_STATE_SHIFT 28u +#define VAL_RESULT_CODE_SHIFT 0u +#define VAL_TEST_STATE_MASK 0xFu +#define VAL_RESULT_CODE_MASK 0xFFFFu + +#define GENERATE_TEST_RESULT(state, code) \ + ((uint32_t)((((uint32_t)(state) & VAL_TEST_STATE_MASK) << VAL_TEST_STATE_SHIFT) | \ + ((uint32_t)(code) & VAL_RESULT_CODE_MASK))) + +#define GET_CODE(RESULT) \ + ((uint16_t)(((uint32_t)(RESULT) >> VAL_RESULT_CODE_SHIFT) & VAL_RESULT_CODE_MASK)) + +#define GET_STATE(RESULT) \ + ((uint8_t)((((uint32_t)(RESULT) >> VAL_TEST_STATE_SHIFT) & VAL_TEST_STATE_MASK))) + +/* ========================================================= + * RESULT_* MACROS (combine state + status) + * ========================================================= */ +#define RESULT_PASS GENERATE_TEST_RESULT(TEST_PASS, STATUS_SUCCESS) +#define RESULT_PARTIAL_COVERED GENERATE_TEST_RESULT(TEST_PARTIAL_COVERED, STATUS_SUCCESS) +#define RESULT_WARNING(n) GENERATE_TEST_RESULT(TEST_WARNING, ERROR_POINT(n)) +#define RESULT_FAIL(n) GENERATE_TEST_RESULT(TEST_FAIL, ERROR_POINT(n)) +#define RESULT_SKIP(n) GENERATE_TEST_RESULT(TEST_SKIP, ERROR_POINT(n)) +#define RESULT_NOT_IMPLEMENTED GENERATE_TEST_RESULT(TEST_NOT_IMPLEMENTED, STATUS_UNKNOWN) +#define RESULT_PAL_NOT_SUPPORTED GENERATE_TEST_RESULT(TEST_PAL_NOT_SUPPORTED, STATUS_UNKNOWN) +#define RESULT_UNKNOWN GENERATE_TEST_RESULT(TEST_STATE_UNKNOWN, STATUS_UNKNOWN) + +/* ========================================================= + * IS_TEST_* MACROS (check STATE from packed status) + * ========================================================= */ +#define IS_TEST_PASS(p) (GET_STATE(p) == TEST_PASS) +#define IS_TEST_PARTIAL_COVERED(p) (GET_STATE(p) == TEST_PARTIAL_COVERED) +#define IS_TEST_WARNING(p) (GET_STATE(p) == TEST_WARNING) +#define IS_TEST_SKIP(p) (GET_STATE(p) == TEST_SKIP) +#define IS_TEST_FAIL(p) (GET_STATE(p) == TEST_FAIL) +#define IS_TEST_NOT_IMPLEMENTED(p) (GET_STATE(p) == TEST_NOT_IMPLEMENTED) +#define IS_TEST_PAL_NOT_SUPPORTED(p) (GET_STATE(p) == TEST_PAL_NOT_SUPPORTED) + +/* ========================================================= + * APIs + * ========================================================= */ +void val_data_cache_ops_by_va(addr_t addr, uint32_t type); +void val_set_status(uint32_t index, uint32_t status); +uint32_t val_get_status(uint32_t index); +void test_report_status(uint32_t status); + +#endif /* VAL_STATUS_H */ + diff --git a/val/src/val_status.c b/val/src/val_status.c new file mode 100644 index 00000000..30914a77 --- /dev/null +++ b/val/src/val_status.c @@ -0,0 +1,120 @@ +/** @file + * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/val_interface.h" +#include "include/val_status.h" +#include "val_logger.h" + +/* Map shared memory as an array of status records */ +static inline volatile val_test_status_t *val_get_shared_address(void) +{ + return (volatile val_test_status_t *)val_get_status_region_base(); +} + +/** + * @brief Stores encoded test result for a PE into shared memory. + * + * Extracts state and status code from test_res and updates + * the entry corresponding to the given PE index. + * + * @param index index of PE reporting the test result. + * @param test_res Encoded test result (state + status code). + */ +void val_set_status(uint32_t index, uint32_t test_res) +{ + volatile val_test_status_t *mem = val_get_shared_address(); + + if (index >= val_pe_get_num()) { + val_print(ERROR, "val_set_status: invalid PE index %u\n", + (unsigned int)index); + return; + } + mem[index].index = index; + mem[index].state = (uint8_t)GET_STATE(test_res); + mem[index].status_code = (uint16_t)GET_CODE(test_res); + val_data_cache_ops_by_va((addr_t)&mem[index], CLEAN_AND_INVALIDATE); +} + +/** + * @brief Retrieves encoded test result for a PE. + * + * Reads state and status code for the given PE index + * and generates the combined test result. + * + * @param index PE (Processing Element) index. + * + * @return Encoded test result (state + status code). + */ +uint32_t val_get_status(uint32_t index) +{ + volatile val_test_status_t *mem = val_get_shared_address(); + + if (index >= val_pe_get_num()) { + val_print(ERROR, "val_get_status: invalid PE index %u\n", + (unsigned int)index); + return RESULT_UNKNOWN; + } + val_data_cache_ops_by_va((addr_t)&mem[index], INVALIDATE); + return GENERATE_TEST_RESULT(mem[index].state, mem[index].status_code); +} + +/** + * @brief Prints test result. + * + * Decodes the test result and prints PASS/FAIL/SKIP/WARN + * along with checkpoint information when applicable. + * + * @param test_res Encoded test result (state + status code). + */ +void test_report_status(uint32_t test_res) +{ + uint8_t state = (uint8_t)GET_STATE(test_res); + + switch (state) { + + case TEST_SKIP: + val_print(INFO, "SKIPPED"); + break; + + case TEST_FAIL: + val_print(INFO, "FAILED"); + break; + + case TEST_WARNING: + val_print(INFO, "WARNING"); + break; + + case TEST_PASS: + val_print(INFO, "PASSED"); + break; + + case TEST_PARTIAL_COVERED: + val_print(INFO, "PASSED(*PARTIAL)"); + break; + + case TEST_NOT_IMPLEMENTED: + val_print(INFO, "NOT TESTED (TEST NOT IMPLEMENTED)"); + break; + + case TEST_PAL_NOT_SUPPORTED: + val_print(INFO, "NOT TESTED (PAL NOT SUPPORTED)"); + break; + + default: + val_print(INFO, "STATUS:0x%08x", (unsigned int)test_res); + break; + } +} From 4311423c0d4a386e8517b4b0fca223c717590d99 Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Thu, 2 Apr 2026 07:27:01 +0000 Subject: [PATCH 07/13] Integrate Unified VAL Status Reporting across tests and infra - Align test pool and infra to updated status report design Signed-off-by: Shruti Ghadge Change-Id: I7c880574a04d52270ba6dbbd6202ef05ade9d98d --- test_pool/cxl/cxl001.c | 6 +-- test_pool/cxl/cxl002.c | 8 ++-- test_pool/cxl/cxl003.c | 6 +-- test_pool/cxl/cxl004.c | 6 +-- test_pool/cxl/cxl010.c | 8 ++-- test_pool/cxl/cxl011.c | 20 +++++----- test_pool/cxl/cxl013.c | 18 ++++----- test_pool/drtm/dl001.c | 26 ++++++------- test_pool/drtm/dl002.c | 16 ++++---- test_pool/drtm/dl003.c | 24 ++++++------ test_pool/drtm/dl004.c | 16 ++++---- test_pool/drtm/dl005.c | 44 ++++++++++----------- test_pool/drtm/dl006.c | 14 +++---- test_pool/drtm/dl007.c | 12 +++--- test_pool/drtm/dl008.c | 22 +++++------ test_pool/drtm/dl009.c | 10 ++--- test_pool/drtm/dl010.c | 16 ++++---- test_pool/drtm/dl011.c | 24 ++++++------ test_pool/drtm/dl012.c | 16 ++++---- test_pool/drtm/interface001.c | 8 ++-- test_pool/drtm/interface002.c | 4 +- test_pool/drtm/interface003.c | 10 ++--- test_pool/drtm/interface004.c | 8 ++-- test_pool/drtm/interface005.c | 10 ++--- test_pool/drtm/interface006.c | 8 ++-- test_pool/drtm/interface007.c | 6 +-- test_pool/drtm/interface008.c | 4 +- test_pool/drtm/interface009.c | 4 +- test_pool/drtm/interface010.c | 14 +++---- test_pool/drtm/interface011.c | 10 ++--- test_pool/drtm/interface012.c | 6 +-- test_pool/drtm/interface013.c | 12 +++--- test_pool/drtm/interface014.c | 16 ++++---- test_pool/drtm/interface015.c | 8 ++-- test_pool/ete/ete001.c | 4 +- test_pool/ete/ete002.c | 6 +-- test_pool/ete/ete003.c | 16 ++++---- test_pool/ete/ete004.c | 14 +++---- test_pool/ete/ete005.c | 4 +- test_pool/ete/ete006.c | 6 +-- test_pool/ete/ete007.c | 6 +-- test_pool/ete/ete008.c | 6 +-- test_pool/exerciser/e001.c | 10 ++--- test_pool/exerciser/e002.c | 10 ++--- test_pool/exerciser/e003.c | 12 +++--- test_pool/exerciser/e004.c | 18 ++++----- test_pool/exerciser/e006.c | 14 +++---- test_pool/exerciser/e007.c | 12 +++--- test_pool/exerciser/e008.c | 14 +++---- test_pool/exerciser/e010.c | 10 ++--- test_pool/exerciser/e011.c | 12 +++--- test_pool/exerciser/e012.c | 16 ++++---- test_pool/exerciser/e013.c | 18 ++++----- test_pool/exerciser/e014.c | 10 ++--- test_pool/exerciser/e015.c | 8 ++-- test_pool/exerciser/e016.c | 14 +++---- test_pool/exerciser/e017.c | 16 ++++---- test_pool/exerciser/e019.c | 12 +++--- test_pool/exerciser/e020.c | 12 +++--- test_pool/exerciser/e021.c | 10 ++--- test_pool/exerciser/e022.c | 8 ++-- test_pool/exerciser/e023.c | 22 +++++------ test_pool/exerciser/e024.c | 18 ++++----- test_pool/exerciser/e025.c | 10 ++--- test_pool/exerciser/e026.c | 14 +++---- test_pool/exerciser/e027.c | 18 ++++----- test_pool/exerciser/e028.c | 8 ++-- test_pool/exerciser/e029.c | 18 ++++----- test_pool/exerciser/e030.c | 10 ++--- test_pool/exerciser/e033.c | 18 ++++----- test_pool/exerciser/e035.c | 16 ++++---- test_pool/exerciser/e036.c | 14 +++---- test_pool/exerciser/e039.c | 14 +++---- test_pool/exerciser/e040.c | 12 +++--- test_pool/exerciser/e041.c | 10 ++--- test_pool/exerciser/e043.c | 14 +++---- test_pool/exerciser/e044.c | 10 ++--- test_pool/exerciser/e045.c | 14 +++---- test_pool/gic/g001.c | 4 +- test_pool/gic/g002.c | 6 +-- test_pool/gic/g003.c | 8 ++-- test_pool/gic/g004.c | 6 +-- test_pool/gic/g005.c | 12 +++--- test_pool/gic/g006.c | 6 +-- test_pool/gic/g007.c | 6 +-- test_pool/gic/g008.c | 12 +++--- test_pool/gic/g009.c | 12 +++--- test_pool/gic/g010.c | 10 ++--- test_pool/gic/g011.c | 10 ++--- test_pool/gic/g012.c | 4 +- test_pool/gic/g013.c | 14 +++---- test_pool/gic/g014.c | 16 ++++---- test_pool/gic/g015.c | 6 +-- test_pool/gic/g016.c | 4 +- test_pool/gic/its001.c | 10 ++--- test_pool/gic/its002.c | 14 +++---- test_pool/gic/its003.c | 18 ++++----- test_pool/gic/its004.c | 10 ++--- test_pool/gic/its005.c | 10 ++--- test_pool/gic/v2m001.c | 10 ++--- test_pool/gic/v2m002.c | 6 +-- test_pool/gic/v2m003.c | 10 ++--- test_pool/gic/v2m004.c | 10 ++--- test_pool/memory_map/m001.c | 6 +-- test_pool/memory_map/m002.c | 6 +-- test_pool/memory_map/m003.c | 6 +-- test_pool/memory_map/m004.c | 22 +++++------ test_pool/memory_map/m005.c | 12 +++--- test_pool/mpam/error001.c | 8 ++-- test_pool/mpam/error002.c | 8 ++-- test_pool/mpam/error003.c | 8 ++-- test_pool/mpam/error004.c | 8 ++-- test_pool/mpam/error005.c | 8 ++-- test_pool/mpam/error006.c | 8 ++-- test_pool/mpam/error007.c | 8 ++-- test_pool/mpam/error008.c | 8 ++-- test_pool/mpam/error009.c | 8 ++-- test_pool/mpam/error010.c | 8 ++-- test_pool/mpam/error011.c | 8 ++-- test_pool/mpam/error012.c | 10 ++--- test_pool/mpam/error013.c | 8 ++-- test_pool/mpam/error014.c | 8 ++-- test_pool/mpam/feat001.c | 18 ++++----- test_pool/mpam/intr001.c | 14 +++---- test_pool/mpam/intr002.c | 14 +++---- test_pool/mpam/intr003.c | 14 +++---- test_pool/mpam/intr004.c | 14 +++---- test_pool/mpam/intr005.c | 14 +++---- test_pool/mpam/intr006.c | 12 +++--- test_pool/mpam/mem001.c | 14 +++---- test_pool/mpam/mem002.c | 18 ++++----- test_pool/mpam/mem003.c | 14 +++---- test_pool/mpam/monitor001.c | 12 +++--- test_pool/mpam/monitor002.c | 12 +++--- test_pool/mpam/monitor003.c | 13 ++++--- test_pool/mpam/monitor004.c | 13 ++++--- test_pool/mpam/monitor005.c | 14 +++---- test_pool/mpam/monitor006.c | 6 +-- test_pool/mpam/monitor007.c | 6 +-- test_pool/mpam/monitor008.c | 6 +-- test_pool/mpam/mpam001.c | 14 +++---- test_pool/mpam/mpam002.c | 32 ++++++++++++--- test_pool/mpam/mpam003.c | 14 +++---- test_pool/mpam/mpam004.c | 12 +++--- test_pool/mpam/mpam005.c | 6 +-- test_pool/mpam/mpam006.c | 12 +++--- test_pool/mpam/mpam007.c | 16 ++++---- test_pool/mpam/partition001.c | 13 ++++--- test_pool/mpam/partition002.c | 12 +++--- test_pool/mpam/partition003.c | 12 +++--- test_pool/mpam/partition004.c | 19 +++++---- test_pool/mpam/partition005.c | 14 +++---- test_pool/mpam/partition006.c | 14 +++---- test_pool/mpam/reg001.c | 8 ++-- test_pool/mpam/reg002.c | 4 +- test_pool/mpam/reg003.c | 6 +-- test_pool/mpam/reg004.c | 12 +++--- test_pool/mpam/reg005.c | 6 +-- test_pool/mpam/reg006.c | 4 +- test_pool/nist_sts/test_n001.c | 12 +++--- test_pool/pcie/p001.c | 6 +-- test_pool/pcie/p002.c | 20 +++++----- test_pool/pcie/p003.c | 6 +-- test_pool/pcie/p004.c | 14 +++---- test_pool/pcie/p005.c | 14 +++---- test_pool/pcie/p006.c | 12 +++--- test_pool/pcie/p007.c | 6 +-- test_pool/pcie/p008.c | 14 +++---- test_pool/pcie/p009.c | 6 +-- test_pool/pcie/p010.c | 6 +-- test_pool/pcie/p011.c | 6 +-- test_pool/pcie/p017.c | 12 +++--- test_pool/pcie/p018.c | 10 ++--- test_pool/pcie/p019.c | 8 ++-- test_pool/pcie/p020.c | 6 +-- test_pool/pcie/p021.c | 8 ++-- test_pool/pcie/p022.c | 6 +-- test_pool/pcie/p023.c | 16 ++++---- test_pool/pcie/p024.c | 6 +-- test_pool/pcie/p025.c | 6 +-- test_pool/pcie/p026.c | 6 +-- test_pool/pcie/p030.c | 12 +++--- test_pool/pcie/p031.c | 6 +-- test_pool/pcie/p032.c | 6 +-- test_pool/pcie/p033.c | 6 +-- test_pool/pcie/p035.c | 10 ++--- test_pool/pcie/p036.c | 6 +-- test_pool/pcie/p037.c | 6 +-- test_pool/pcie/p038.c | 6 +-- test_pool/pcie/p039.c | 6 +-- test_pool/pcie/p042.c | 6 +-- test_pool/pcie/p045.c | 18 ++++----- test_pool/pcie/p046.c | 10 ++--- test_pool/pcie/p047.c | 8 ++-- test_pool/pcie/p048.c | 6 +-- test_pool/pcie/p049.c | 6 +-- test_pool/pcie/p050.c | 6 +-- test_pool/pcie/p051.c | 6 +-- test_pool/pcie/p052.c | 6 +-- test_pool/pcie/p053.c | 6 +-- test_pool/pcie/p054.c | 6 +-- test_pool/pcie/p056.c | 6 +-- test_pool/pcie/p057.c | 6 +-- test_pool/pcie/p058.c | 12 +++--- test_pool/pcie/p061.c | 6 +-- test_pool/pcie/p062.c | 6 +-- test_pool/pcie/p063.c | 10 ++--- test_pool/pcie/p064.c | 6 +-- test_pool/pcie/p065.c | 6 +-- test_pool/pcie/p066.c | 8 ++-- test_pool/pcie/p067.c | 6 +-- test_pool/pcie/p068.c | 6 +-- test_pool/pcie/p069.c | 6 +-- test_pool/pcie/p070.c | 8 ++-- test_pool/pcie/p071.c | 6 +-- test_pool/pcie/p072.c | 6 +-- test_pool/pcie/p078.c | 20 +++++----- test_pool/pcie/p079.c | 14 +++---- test_pool/pcie/p080.c | 8 ++-- test_pool/pcie/p081.c | 10 ++--- test_pool/pcie/p082.c | 16 ++++---- test_pool/pcie/p083.c | 6 +-- test_pool/pcie/p084.c | 6 +-- test_pool/pcie/p085.c | 6 +-- test_pool/pcie/p086.c | 14 +++---- test_pool/pcie/p087.c | 8 ++-- test_pool/pcie/p088.c | 6 +-- test_pool/pcie/p089.c | 6 +-- test_pool/pcie/p090.c | 6 +-- test_pool/pcie/p091.c | 6 +-- test_pool/pcie/p092.c | 8 ++-- test_pool/pcie/p093.c | 8 ++-- test_pool/pcie/p094.c | 18 ++++----- test_pool/pcie/p095.c | 10 ++--- test_pool/pcie/p096.c | 12 +++--- test_pool/pcie/p097.c | 8 ++-- test_pool/pcie/p100.c | 6 +-- test_pool/pcie/p105.c | 10 ++--- test_pool/pe/pe001.c | 14 +++---- test_pool/pe/pe002.c | 4 +- test_pool/pe/pe003.c | 4 +- test_pool/pe/pe004.c | 4 +- test_pool/pe/pe006.c | 6 +-- test_pool/pe/pe007.c | 4 +- test_pool/pe/pe008.c | 4 +- test_pool/pe/pe009.c | 12 +++--- test_pool/pe/pe010.c | 12 +++--- test_pool/pe/pe011.c | 6 +-- test_pool/pe/pe012.c | 4 +- test_pool/pe/pe013.c | 4 +- test_pool/pe/pe014.c | 6 +-- test_pool/pe/pe015.c | 4 +- test_pool/pe/pe016.c | 12 +++--- test_pool/pe/pe017.c | 4 +- test_pool/pe/pe018.c | 4 +- test_pool/pe/pe019.c | 18 ++++----- test_pool/pe/pe020.c | 6 +-- test_pool/pe/pe021.c | 4 +- test_pool/pe/pe022.c | 8 ++-- test_pool/pe/pe023.c | 8 ++-- test_pool/pe/pe024.c | 4 +- test_pool/pe/pe025.c | 4 +- test_pool/pe/pe026.c | 8 ++-- test_pool/pe/pe027.c | 4 +- test_pool/pe/pe028.c | 6 +-- test_pool/pe/pe029.c | 4 +- test_pool/pe/pe030.c | 4 +- test_pool/pe/pe031.c | 4 +- test_pool/pe/pe032.c | 4 +- test_pool/pe/pe033.c | 4 +- test_pool/pe/pe034.c | 10 ++--- test_pool/pe/pe035.c | 4 +- test_pool/pe/pe036.c | 6 +-- test_pool/pe/pe037.c | 8 ++-- test_pool/pe/pe038.c | 4 +- test_pool/pe/pe039.c | 4 +- test_pool/pe/pe040.c | 8 ++-- test_pool/pe/pe041.c | 4 +- test_pool/pe/pe042.c | 4 +- test_pool/pe/pe043.c | 4 +- test_pool/pe/pe044.c | 4 +- test_pool/pe/pe045.c | 4 +- test_pool/pe/pe046.c | 4 +- test_pool/pe/pe047.c | 4 +- test_pool/pe/pe048.c | 4 +- test_pool/pe/pe049.c | 4 +- test_pool/pe/pe051.c | 4 +- test_pool/pe/pe052.c | 4 +- test_pool/pe/pe053.c | 4 +- test_pool/pe/pe054.c | 6 +-- test_pool/pe/pe055.c | 4 +- test_pool/pe/pe056.c | 4 +- test_pool/pe/pe057.c | 4 +- test_pool/pe/pe058.c | 4 +- test_pool/pe/pe059.c | 4 +- test_pool/pe/pe060.c | 4 +- test_pool/pe/pe061.c | 6 +-- test_pool/pe/pe062.c | 16 ++++---- test_pool/pe/pe065.c | 4 +- test_pool/pe/pe066.c | 8 ++-- test_pool/pe/pe068.c | 4 +- test_pool/peripherals/d001.c | 22 +++++------ test_pool/peripherals/d002.c | 10 ++--- test_pool/peripherals/d003.c | 32 +++++++-------- test_pool/peripherals/d004.c | 20 +++++----- test_pool/pfdi/pfdi001.c | 12 +++--- test_pool/pfdi/pfdi002.c | 10 ++--- test_pool/pfdi/pfdi003.c | 10 ++--- test_pool/pfdi/pfdi004.c | 10 ++--- test_pool/pfdi/pfdi005.c | 10 ++--- test_pool/pfdi/pfdi006.c | 8 ++-- test_pool/pfdi/pfdi007.c | 14 +++---- test_pool/pfdi/pfdi008.c | 10 ++--- test_pool/pfdi/pfdi009.c | 10 ++--- test_pool/pfdi/pfdi010.c | 10 ++--- test_pool/pfdi/pfdi011.c | 4 +- test_pool/pfdi/pfdi012.c | 22 +++++------ test_pool/pfdi/pfdi013.c | 10 ++--- test_pool/pfdi/pfdi014.c | 14 +++---- test_pool/pfdi/pfdi016.c | 10 ++--- test_pool/pfdi/pfdi017.c | 10 ++--- test_pool/pfdi/pfdi018.c | 14 +++---- test_pool/pfdi/pfdi019.c | 10 ++--- test_pool/pfdi/pfdi020.c | 14 +++---- test_pool/pfdi/pfdi021.c | 10 ++--- test_pool/pfdi/pfdi022.c | 10 ++--- test_pool/pfdi/pfdi023.c | 10 ++--- test_pool/pfdi/pfdi024.c | 10 ++--- test_pool/pfdi/pfdi025.c | 10 ++--- test_pool/pfdi/pfdi026.c | 10 ++--- test_pool/pfdi/pfdi027.c | 12 +++--- test_pool/pfdi/pfdi028.c | 14 +++---- test_pool/pfdi/pfdi029.c | 10 ++--- test_pool/pfdi/pfdi030.c | 10 ++--- test_pool/pfdi/pfdi031.c | 10 ++--- test_pool/pmu/pmu001.c | 6 +-- test_pool/pmu/pmu002.c | 4 +- test_pool/pmu/pmu003.c | 4 +- test_pool/pmu/pmu004.c | 12 +++--- test_pool/pmu/pmu005.c | 14 +++---- test_pool/pmu/pmu006.c | 6 +-- test_pool/pmu/pmu008.c | 28 ++++++------- test_pool/pmu/pmu009.c | 22 +++++------ test_pool/power_wakeup/u001.c | 6 +-- test_pool/power_wakeup/u002.c | 9 +++-- test_pool/power_wakeup/u003.c | 9 +++-- test_pool/power_wakeup/u004.c | 15 +++---- test_pool/power_wakeup/u005.c | 19 ++++----- test_pool/power_wakeup/u006.c | 22 +++++------ test_pool/ras/ras001.c | 6 +-- test_pool/ras/ras002.c | 6 +-- test_pool/ras/ras003.c | 10 ++--- test_pool/ras/ras004.c | 10 ++--- test_pool/ras/ras005.c | 10 ++--- test_pool/ras/ras006.c | 12 +++--- test_pool/ras/ras007.c | 8 ++-- test_pool/ras/ras008.c | 8 ++-- test_pool/ras/ras009.c | 16 ++++---- test_pool/ras/ras010.c | 6 +-- test_pool/ras/ras011.c | 36 ++++++++--------- test_pool/ras/ras012.c | 14 +++---- test_pool/ras/ras013.c | 8 ++-- test_pool/ras/ras014.c | 6 +-- test_pool/ras/ras016.c | 8 ++-- test_pool/ras/ras017.c | 8 ++-- test_pool/ras/ras018.c | 18 ++++----- test_pool/smmu/i001.c | 6 +-- test_pool/smmu/i002.c | 14 +++---- test_pool/smmu/i003.c | 8 ++-- test_pool/smmu/i004.c | 14 +++---- test_pool/smmu/i005.c | 12 +++--- test_pool/smmu/i006.c | 8 ++-- test_pool/smmu/i007.c | 10 ++--- test_pool/smmu/i008.c | 18 ++++----- test_pool/smmu/i009.c | 18 ++++----- test_pool/smmu/i010.c | 12 +++--- test_pool/smmu/i011.c | 12 +++--- test_pool/smmu/i012.c | 12 +++--- test_pool/smmu/i013.c | 8 ++-- test_pool/smmu/i014.c | 8 ++-- test_pool/smmu/i015.c | 8 ++-- test_pool/smmu/i016.c | 10 ++--- test_pool/smmu/i017.c | 10 ++--- test_pool/smmu/i018.c | 8 ++-- test_pool/smmu/i019.c | 10 ++--- test_pool/smmu/i020.c | 8 ++-- test_pool/smmu/i021.c | 12 +++--- test_pool/smmu/i022.c | 6 +-- test_pool/smmu/i023.c | 12 +++--- test_pool/smmu/i024.c | 8 ++-- test_pool/smmu/i025.c | 8 ++-- test_pool/timer/t001.c | 8 ++-- test_pool/timer/t002.c | 6 +-- test_pool/timer/t003.c | 26 ++++++------- test_pool/timer/t004.c | 16 ++++---- test_pool/timer/t005.c | 12 +++--- test_pool/timer/t006.c | 4 +- test_pool/timer/t008.c | 4 +- test_pool/tpm/tpm001.c | 6 +-- test_pool/tpm/tpm002.c | 12 +++--- test_pool/watchdog/w001.c | 17 ++++---- test_pool/watchdog/w002.c | 23 +++++------ test_pool/watchdog/w003.c | 8 ++-- val/ValLib.inf | 1 + val/ValLibRB.inf | 1 + val/include/acs_common.h | 52 +++---------------------- val/include/acs_pmu.h | 2 +- val/include/acs_val.h | 8 +--- val/include/pal_interface.h | 4 +- val/include/val_interface.h | 13 ++++--- val/src/acs_gic_support.c | 4 +- val/src/acs_mpam.c | 4 +- val/src/acs_pe.c | 10 ++--- val/src/acs_pe_infra.c | 12 +++--- val/src/acs_pmu.c | 6 +-- val/src/acs_status.c | 46 +--------------------- val/src/acs_test_infra.c | 54 ++++++++++++++++++-------- val/src/rule_based_execution_helpers.c | 31 +++++++-------- val/src/rule_based_orchestrator.c | 41 +++++++++---------- val/src/test_wrappers.c | 33 +++++++++------- 420 files changed, 2164 insertions(+), 2202 deletions(-) diff --git a/test_pool/cxl/cxl001.c b/test_pool/cxl/cxl001.c index 05c29cb7..29d862f7 100644 --- a/test_pool/cxl/cxl001.c +++ b/test_pool/cxl/cxl001.c @@ -40,7 +40,7 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { val_print(DEBUG, "\n No CXL devices discovered"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -74,9 +74,9 @@ payload(void) } if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/cxl/cxl002.c b/test_pool/cxl/cxl002.c index c0d7f607..14250c7b 100644 --- a/test_pool/cxl/cxl002.c +++ b/test_pool/cxl/cxl002.c @@ -49,7 +49,7 @@ payload(void) comp_count = val_cxl_get_component_info(CXL_COMPONENT_INFO_COUNT, 0); if (comp_count == 0) { val_print(TRACE, "\n No CXL components discovered"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -90,11 +90,11 @@ payload(void) if (test_skip == 0) { val_print(TRACE, "\n No CXL Type1/Type2 components discovered"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); } else if (test_fail) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); } else { - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } } diff --git a/test_pool/cxl/cxl003.c b/test_pool/cxl/cxl003.c index 3682e95b..b7258b66 100644 --- a/test_pool/cxl/cxl003.c +++ b/test_pool/cxl/cxl003.c @@ -34,7 +34,7 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { val_print(DEBUG, "\n No CXL devices discovered"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -48,9 +48,9 @@ payload(void) } if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/cxl/cxl004.c b/test_pool/cxl/cxl004.c index e224faf6..7be460c9 100644 --- a/test_pool/cxl/cxl004.c +++ b/test_pool/cxl/cxl004.c @@ -81,7 +81,7 @@ payload(void) if (num_cxl_hb == 0) { val_print(TRACE, "\n No CXL Host Bridges discovered via CEDT"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -109,9 +109,9 @@ payload(void) } if (test_fail) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); } else { - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } } diff --git a/test_pool/cxl/cxl010.c b/test_pool/cxl/cxl010.c index 126db377..c5f8da53 100644 --- a/test_pool/cxl/cxl010.c +++ b/test_pool/cxl/cxl010.c @@ -39,14 +39,14 @@ payload(void) num_cxl_hb = val_cxl_get_info(CXL_INFO_NUM_DEVICES, 0); if (num_cxl_hb == 0) { val_print(DEBUG, "\n No CXL devices discovered"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } for (index = 0; index < num_cxl_hb; index++) { if (val_cxl_check_persistent_memory(index)) { val_print(DEBUG, "\n No Persistent memory supported"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); return; } } @@ -54,10 +54,10 @@ payload(void) dpb_field = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 0, 3); if ((dpb_field == 0x1) || (dpb_field == 0x2)) { - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } else { val_print(ERROR, "\n ID_AA64ISAR1_EL1.DPB does not indicate PCMO support"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); } } diff --git a/test_pool/cxl/cxl011.c b/test_pool/cxl/cxl011.c index 67416dc6..98617f64 100644 --- a/test_pool/cxl/cxl011.c +++ b/test_pool/cxl/cxl011.c @@ -54,7 +54,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received exception type: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); } static @@ -172,7 +172,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { val_print(ERROR, "\n Failed to install exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -182,13 +182,13 @@ payload(void) val_print(TRACE, "\n DPB %x", dpb_field); if ((dpb_field != 0x1) && (dpb_field != 0x2)) { val_print(TRACE, "\n DC CVAP/CVADP not supported by this PE"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } if (find_cxl_mem_target(&target)) { val_print(TRACE, "\n No CXL Type 3 mem-capable target found"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); return; } @@ -210,13 +210,13 @@ payload(void) if (get_aer_status(target.rp_bdf, &aer_ori)) { val_print(ERROR, "\n AER capability not found on root port 0x%x", target.rp_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } status = val_cxl_map_hdm_address(cfmws_base, SIZE_4KB, &mapped); if (status != ACS_STATUS_PASS) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); return; } @@ -227,13 +227,13 @@ payload(void) if (get_aer_status(target.rp_bdf, &aer_updated)) { val_print(ERROR, "\n Failed to read AER status after PCMO sequence"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); return; } if (compare_aer_status(&aer_ori, &aer_updated)) { val_print(ERROR, "\n AER errors detected after PCMO sequence"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(pe_index, RESULT_FAIL(5)); return; } @@ -246,11 +246,11 @@ payload(void) if (read_back != CXL_TEST_PATTERN) { val_print(ERROR, "\n Readback mismatch: expected 0x%llx", CXL_TEST_PATTERN); val_print(ERROR, " observed 0x%llx", read_back); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(pe_index, RESULT_FAIL(6)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/cxl/cxl013.c b/test_pool/cxl/cxl013.c index 6117ab94..8d32e601 100644 --- a/test_pool/cxl/cxl013.c +++ b/test_pool/cxl/cxl013.c @@ -46,7 +46,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received exception type: %d", interrupt_type); exception = 1; - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); } static @@ -208,7 +208,7 @@ payload(void) if (atomic_feat < 0x2) { val_print(ERROR, "\n FEAT_LSE not supported (ID_AA64ISAR0_EL1.Atomic = 0x%x)", atomic_feat); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -217,7 +217,7 @@ payload(void) if (lse2_feat == 0) { val_print(ERROR, "\n FEAT_LSE2 not supported (ID_AA64MMFR2_EL1.AT = 0x%x)", lse2_feat); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -225,7 +225,7 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { val_print(ERROR, "\n Failed to install exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); return; } branch_to_test = &&exception_return; @@ -233,21 +233,21 @@ payload(void) if (find_cxl_type3_target(&target) != ACS_STATUS_PASS) { val_print(TRACE, "\n No CXL Type-3 memory target found"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } status = val_cxl_get_cfmws_window(target.host_index, &cfmws_base, &cfmws_size); if ((status != ACS_STATUS_PASS) || (cfmws_base == 0) || (cfmws_size < SIZE_4KB)) { val_print(ERROR, "\n Failed to locate usable CFMWS window"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); return; } status = val_cxl_map_hdm_address(cfmws_base, SIZE_4KB, &mapped); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Failed to map CXL Type-3 memory region"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); return; } @@ -259,7 +259,7 @@ payload(void) if ((status != ACS_STATUS_PASS) || exception) { val_print(ERROR, "\n Atomic sequence failed on CXL memory"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(pe_index, RESULT_FAIL(5)); return; } @@ -294,7 +294,7 @@ payload(void) if (mec_feat == 0) val_print(WARN, "\n Optional feature FEAT_MEC is not supported"); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/dl001.c b/test_pool/drtm/dl001.c index 4a1d5b23..7f6716c1 100644 --- a/test_pool/drtm/dl001.c +++ b/test_pool/drtm/dl001.c @@ -42,14 +42,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -60,12 +60,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(3)); + val_set_status(index, RESULT_FAIL(4)); } } goto free_dlme_region; @@ -77,13 +77,13 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); drtm_params->dlme_region_address = drtm_params->dlme_region_address - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); } } goto free_dlme_region; @@ -96,13 +96,13 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); drtm_params->dlme_image_start = drtm_params->dlme_image_start - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(8)); } } goto free_dlme_region; @@ -115,13 +115,13 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); + val_set_status(index, RESULT_FAIL(9)); drtm_params->dlme_data_offset = drtm_params->dlme_data_offset - 0x4; if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); + val_set_status(index, RESULT_FAIL(10)); } } goto free_dlme_region; @@ -138,7 +138,7 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); + val_set_status(index, RESULT_FAIL(11)); temp = drtm_params->dlme_image_start; drtm_params->dlme_image_start = drtm_params->dlme_data_offset; drtm_params->dlme_data_offset = temp; @@ -146,7 +146,7 @@ payload(uint32_t num_pe) status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 12)); + val_set_status(index, RESULT_FAIL(12)); } } goto free_dlme_region; @@ -156,7 +156,7 @@ payload(uint32_t num_pe) drtm_params->dlme_image_start = drtm_params->dlme_data_offset; drtm_params->dlme_data_offset = temp; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl002.c b/test_pool/drtm/dl002.c index 6367e310..9e88609c 100644 --- a/test_pool/drtm/dl002.c +++ b/test_pool/drtm/dl002.c @@ -42,14 +42,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -58,14 +58,14 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Dynamic Launch failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -74,7 +74,7 @@ payload(uint32_t num_pe) drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM check DL result failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_dlme_region; } @@ -82,7 +82,7 @@ payload(uint32_t num_pe) status = val_drtm_get_error(&feat1); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Get Error failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); goto free_dlme_region; } val_print(TRACE, "\n Get Error code 0x%x\n", feat1); @@ -92,11 +92,11 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_DENIED) { val_print(ERROR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); val_print(ERROR, ", Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl003.c b/test_pool/drtm/dl003.c index 0be36922..c080a843 100644 --- a/test_pool/drtm/dl003.c +++ b/test_pool/drtm/dl003.c @@ -42,14 +42,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -59,7 +59,7 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Dynamic Launch failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } @@ -68,7 +68,7 @@ payload(uint32_t num_pe) drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM check DL result failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -76,7 +76,7 @@ payload(uint32_t num_pe) status = val_drtm_get_error(&feat1); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Get Error failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_dlme_region; } @@ -86,12 +86,12 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_DENIED) { val_print(ERROR, "\n Error Code Mismatch, Expected = %d", DRTM_ACS_DENIED); val_print(ERROR, ", Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(6)); + val_set_status(index, RESULT_FAIL(7)); } } goto free_dlme_region; @@ -101,7 +101,7 @@ payload(uint32_t num_pe) status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(8)); goto free_dlme_region; } @@ -110,7 +110,7 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Dynamic Launch failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); + val_set_status(index, RESULT_FAIL(9)); goto free_dlme_region; } @@ -118,7 +118,7 @@ payload(uint32_t num_pe) status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); + val_set_status(index, RESULT_FAIL(10)); goto free_dlme_region; } @@ -127,11 +127,11 @@ payload(uint32_t num_pe) drtm_params->dlme_data_offset); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM check DL result failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); + val_set_status(index, RESULT_FAIL(11)); goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl004.c b/test_pool/drtm/dl004.c index b6b60820..91dd2440 100644 --- a/test_pool/drtm/dl004.c +++ b/test_pool/drtm/dl004.c @@ -39,14 +39,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -55,14 +55,14 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -71,7 +71,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Unexpected Status for close locality %d", status); val_print(ERROR, " Expected %d,", DRTM_ACS_INVALID_PARAMETERS); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_dlme_region; } @@ -82,7 +82,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Close Locality 2 failed err=%d", status); val_print(ERROR, " Expected %d,", DRTM_ACS_SUCCESS); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); goto free_dlme_region; } @@ -92,11 +92,11 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_ALREADY_CLOSED) { val_print(ERROR, "\n DRTM Close Locality 2 failed err=%d", status); val_print(ERROR, " Expected %d,", DRTM_ACS_ALREADY_CLOSED); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl005.c b/test_pool/drtm/dl005.c index 1c86087d..9e232c1f 100644 --- a/test_pool/drtm/dl005.c +++ b/test_pool/drtm/dl005.c @@ -173,14 +173,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -189,14 +189,14 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Dynamic Launch failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -205,7 +205,7 @@ payload(uint32_t num_pe) drtm_params->dlme_data_offset); if (status == ACS_STATUS_FAIL) { val_print(ERROR, "\n DRTM check DL result failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_dlme_region; } @@ -218,26 +218,26 @@ payload(uint32_t num_pe) if ((dlme_data_address + dlme_data_header->dlme_data_size) > (drtm_params->dlme_region_address + drtm_params->dlme_region_size)) { val_print(ERROR, "\n DLME Data Header outside DLME Region"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); goto free_dlme_region; } /* R314060 : Check if Protected Region size is not zero */ if (dlme_data_header->protected_regions_size == 0) { val_print(ERROR, "\n DLME Data Protected Region Size is 0"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); goto free_dlme_region; } /* R314060 : Check if Address Map size is not zero */ if (dlme_data_header->address_map_size == 0) { val_print(ERROR, "\n DLME Data Address Map Size is 0"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(8)); goto free_dlme_region; } /* R314060 : Check if Event Log size is not zero */ if (dlme_data_header->drtm_event_log_size <= 0) { val_print(ERROR, "\n DLME Data Event Log Size is incorrect"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); + val_set_status(index, RESULT_FAIL(9)); goto free_dlme_region; } @@ -245,7 +245,7 @@ payload(uint32_t num_pe) if ((dlme_data_header->dlme_data_size) > (drtm_params->dlme_region_address + drtm_params->dlme_region_size - dlme_data_address)) { val_print(ERROR, "\n DLME Data Header exceeds DLME Data"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); + val_set_status(index, RESULT_FAIL(10)); goto free_dlme_region; } @@ -253,7 +253,7 @@ payload(uint32_t num_pe) /* Do revision check and num of regions check */ if ((prot_region->header.revision != 1) || (prot_region->header.num_regions == 0)) { val_print(ERROR, "\n Protected region not populated"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 11)); + val_set_status(index, RESULT_FAIL(11)); goto free_dlme_region; } @@ -262,7 +262,7 @@ payload(uint32_t num_pe) if ((prot_region->header.num_regions != 1) || (prot_region->regions[0].start_addr != 0)) { val_print(ERROR, "\n Protected region wrongly populated"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 12)); + val_set_status(index, RESULT_FAIL(12)); goto free_dlme_region; } } @@ -271,7 +271,7 @@ payload(uint32_t num_pe) /* Do revision check and num of regions check */ if ((addr_map->header.revision != 1) || (addr_map->header.num_regions == 0)) { val_print(ERROR, "\n Address Map not populated"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 13)); + val_set_status(index, RESULT_FAIL(13)); goto free_dlme_region; } @@ -281,7 +281,7 @@ payload(uint32_t num_pe) for (uint32_t i = 0; i < prot_region->header.num_regions; i++) { if (!(DRTM_IS_4KB_ALIGNED(prot_region->regions[i].start_addr))) { val_print(ERROR, "\n Protected Memory Regions Not 4KB Aligned"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 14)); + val_set_status(index, RESULT_FAIL(14)); test_fails++; } @@ -290,7 +290,7 @@ payload(uint32_t num_pe) if (prot_region->regions[i].start_addr < prot_region->regions[i-1].start_addr) { val_print(ERROR, "\n Protected Regions Memory Regions Not Sorted"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 15)); + val_set_status(index, RESULT_FAIL(15)); test_fails++; } } @@ -298,7 +298,7 @@ payload(uint32_t num_pe) for (uint32_t i = 0; i < addr_map->header.num_regions; i++) { if (!(DRTM_IS_4KB_ALIGNED(addr_map->regions[i].start_addr))) { val_print(ERROR, "\n Address Map Memory Regions Not 4KB Aligned"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 16)); + val_set_status(index, RESULT_FAIL(16)); test_fails++; } @@ -307,7 +307,7 @@ payload(uint32_t num_pe) if (addr_map->regions[i].start_addr < addr_map->regions[i-1].start_addr) { val_print(ERROR, "\n Address Map Memory Regions Not Sorted"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 17)); + val_set_status(index, RESULT_FAIL(17)); test_fails++; } } @@ -318,14 +318,14 @@ payload(uint32_t num_pe) if ((tcb_hash_table->header.revision != 1) || (tcb_hash_table->header.num_hashes == 0)) { /* Fail The test */ val_print(ERROR, "\n TCB_HASH_TABLE Not Correctly Formatted"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 18)); + val_set_status(index, RESULT_FAIL(18)); goto free_dlme_region; } /* R315040 In Success Case. Check if Maximum number of entries is greator than num_hashes */ if (tcb_hash_table->header.num_hashes > VAL_EXTRACT_BITS(g_drtm_features.tcb_hash_features.value, 0, 7)) { val_print(ERROR, "\n Number of hashes exceeds maximum allowed value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 19)); + val_set_status(index, RESULT_FAIL(19)); test_fails++; } } @@ -337,7 +337,7 @@ payload(uint32_t num_pe) if ((uint32_t)(*((uint64_t *)acpi_region_address)) != ACS_ACPI_SIGNATURE('X', 'S', 'D', 'T')) { val_print(ERROR, "\n ACPI XSDT Table Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 20)); + val_set_status(index, RESULT_FAIL(20)); test_fails++; } } @@ -346,12 +346,12 @@ payload(uint32_t num_pe) if ((dlme_data_header->tcb_hash_table_size != 0) && (dlme_data_header->acpi_table_region_size != 0)) { val_print(ERROR, "\n TCB Hash Table & ACPI Table Region Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 21)); + val_set_status(index, RESULT_FAIL(21)); test_fails++; } if (test_fails == 0) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl006.c b/test_pool/drtm/dl006.c index 9cecc63a..941e8b53 100644 --- a/test_pool/drtm/dl006.c +++ b/test_pool/drtm/dl006.c @@ -176,14 +176,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -192,7 +192,7 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } @@ -200,7 +200,7 @@ payload(uint32_t num_pe) status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -219,7 +219,7 @@ payload(uint32_t num_pe) status = print_tcg_event_header(event_log_head); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Event Log Header Checks failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_dlme_region; } @@ -228,7 +228,7 @@ payload(uint32_t num_pe) status = print_event_spec(event_spec); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Event Log signature check failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); goto free_dlme_region; } @@ -287,7 +287,7 @@ payload(uint32_t num_pe) event = event2; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl007.c b/test_pool/drtm/dl007.c index 16548b05..532fe72b 100644 --- a/test_pool/drtm/dl007.c +++ b/test_pool/drtm/dl007.c @@ -55,7 +55,7 @@ payload(uint32_t num_pe) if (num_of_pe < 2) { /* Skip the test as there is no secondary PE */ val_print(ERROR, "\n No secondary PE Present. Skipping"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -71,14 +71,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -94,18 +94,18 @@ payload(uint32_t num_pe) val_print(ERROR, "\n DRTM Dynamic Launch failed, Expected = %d", DRTM_ACS_SECONDARY_PE_NOT_OFF); val_print(ERROR, " Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(3)); + val_set_status(index, RESULT_FAIL(4)); } } goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl008.c b/test_pool/drtm/dl008.c index c784056c..a82912bd 100644 --- a/test_pool/drtm/dl008.c +++ b/test_pool/drtm/dl008.c @@ -43,14 +43,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -79,12 +79,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(3)); + val_set_status(index, RESULT_FAIL(4)); } } goto free_dlme_region; @@ -113,12 +113,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(5)); + val_set_status(index, RESULT_FAIL(6)); } } goto free_dlme_region; @@ -138,12 +138,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(7)); + val_set_status(index, RESULT_FAIL(8)); } } goto free_dlme_region; @@ -170,12 +170,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 9)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 10)); + val_set_status(index, RESULT_FAIL(9)); + val_set_status(index, RESULT_FAIL(10)); } } goto free_dlme_region; @@ -187,7 +187,7 @@ payload(uint32_t num_pe) "\n DRTM implementation supports TPM based hashing, skip check"); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl009.c b/test_pool/drtm/dl009.c index 800cde17..13f3dacd 100644 --- a/test_pool/drtm/dl009.c +++ b/test_pool/drtm/dl009.c @@ -41,14 +41,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -64,12 +64,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n Incorrect Status. Expected = -2 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(3)); + val_set_status(index, RESULT_FAIL(4)); } } goto free_dlme_region; @@ -77,7 +77,7 @@ payload(uint32_t num_pe) drtm_params->launch_features = 0; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl010.c b/test_pool/drtm/dl010.c index 6f88f557..67016c0b 100644 --- a/test_pool/drtm/dl010.c +++ b/test_pool/drtm/dl010.c @@ -36,7 +36,7 @@ void secondary_pe_payload(void) dl_status = val_drtm_dynamic_launch(drtm_params_buffer); val_data_cache_ops_by_va((addr_t)&dl_status, CLEAN_AND_INVALIDATE); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } static @@ -60,7 +60,7 @@ payload(uint32_t num_pe) if (num_of_pe < 2) { /* Skip the test as there is no secondary PE */ val_print(ERROR, "\n No secondary PE Present. Skipping"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -76,14 +76,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -101,7 +101,7 @@ payload(uint32_t num_pe) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", sec_pe_index); val_print(ERROR, " Found = %d", dl_status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } @@ -110,18 +110,18 @@ payload(uint32_t num_pe) val_print(ERROR, "\n DRTM Dynamic Launch failed, Expected = %d", DRTM_ACS_DENIED); val_print(ERROR, " Found = %d", dl_status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(4)); + val_set_status(index, RESULT_FAIL(5)); } } goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/dl011.c b/test_pool/drtm/dl011.c index cd388947..5a98e55b 100644 --- a/test_pool/drtm/dl011.c +++ b/test_pool/drtm/dl011.c @@ -49,7 +49,7 @@ payload(uint32_t num_pe) dma_protection_support = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7); if (dma_protection_support != DRTM_DMA_FEATURES_DMA_PROTECTION_REGION) { val_print(ERROR, "\n Not valid for complete DMA protection. Skipping"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -58,7 +58,7 @@ payload(uint32_t num_pe) max_mem_regions = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 8, 23); if (max_mem_regions == 0) { val_print(ERROR, "\n No regions in DRTM_PARAMETERS allowed. Skipping"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -66,14 +66,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -85,7 +85,7 @@ payload(uint32_t num_pe) ((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, mem_desc_table_size)); if (!mem_desc_table) { val_print(ERROR, "\n Failed to allocate memory for Memory Descriptor Table"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_drtm_params; } @@ -97,7 +97,7 @@ payload(uint32_t num_pe) ((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, region_size)); if (!region_address) { val_print(ERROR, "\n Failed to allocate memory for Memory Regions"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_mem_desc_table; } @@ -119,12 +119,12 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_MEM_PROTECT_INVALID) { val_print(ERROR, "\n Incorrect Status. Expected = -6 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(5)); + val_set_status(index, RESULT_FAIL(6)); } } goto free_memory_region; @@ -135,7 +135,7 @@ payload(uint32_t num_pe) max_mem_regions = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 8, 23); if (max_mem_regions > 1) { val_print(ERROR, "\n Only one memory region is allowed. Skipping R313020"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); goto free_memory_region; } @@ -160,18 +160,18 @@ payload(uint32_t num_pe) /* This will return invalid parameter */ if (status != DRTM_ACS_MEM_PROTECT_INVALID) { val_print(ERROR, "\n Incorrect Status. Expected = -6 Found = %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); if (status == DRTM_ACS_SUCCESS) { status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(7)); + val_set_status(index, RESULT_FAIL(8)); } } goto free_memory_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_memory_region: val_memory_free_aligned((void *)region_address); diff --git a/test_pool/drtm/dl012.c b/test_pool/drtm/dl012.c index 5f87cfe7..1c6eecd0 100644 --- a/test_pool/drtm/dl012.c +++ b/test_pool/drtm/dl012.c @@ -66,7 +66,7 @@ payload(uint32_t num_pe) if (drtm_feature != DRTM_DLME_IMG_FEAT_DLME_IMG_AUTH_SUPP) { val_print(DEBUG, "\n DRTM implementation does not support DLME Img Auth, skip check"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -74,14 +74,14 @@ payload(uint32_t num_pe) drtm_params = (DRTM_PARAMETERS *)((uint64_t)val_aligned_alloc(DRTM_SIZE_4K, drtm_params_size)); if (!drtm_params) { val_print(ERROR, "\n Failed to allocate memory for DRTM Params"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } status = val_drtm_init_drtm_params(drtm_params); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n DRTM Init Params failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_drtm_params; } @@ -95,7 +95,7 @@ payload(uint32_t num_pe) /* This will return only in fail*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Dynamic Launch failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_dlme_region; } @@ -103,7 +103,7 @@ payload(uint32_t num_pe) status = val_drtm_unprotect_memory(); if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n Unprotect Memory failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_dlme_region; } @@ -121,7 +121,7 @@ payload(uint32_t num_pe) status = check_event_spec_signature(event_spec); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Event Log signature check failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); goto free_dlme_region; } @@ -170,11 +170,11 @@ payload(uint32_t num_pe) if (dlme_image_auth != ACS_STATUS_PASS) { val_print(ERROR, "\n DLME IMG AUTH not found in Event Log"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); goto free_dlme_region; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_dlme_region: val_memory_free_aligned((void *)drtm_params->dlme_region_address); diff --git a/test_pool/drtm/interface001.c b/test_pool/drtm/interface001.c index 89e38b83..499455a2 100644 --- a/test_pool/drtm/interface001.c +++ b/test_pool/drtm/interface001.c @@ -32,25 +32,25 @@ payload(uint32_t num_pe) if (status >> 31) { val_print(ERROR, "\n DRTM get version failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } major = DRTM_VERSION_GET_MAJOR(g_drtm_features.version.value); if (major != 1) { val_print(INFO, "\n Major Version not as expected, Current version =%d", major); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } minor = DRTM_VERSION_GET_MINOR(g_drtm_features.version.value); if (minor != 1) { val_print(INFO, "\n Minor Version not as expected, Current version =%d", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface002.c b/test_pool/drtm/interface002.c index 04bc80a6..bcef21bd 100644 --- a/test_pool/drtm/interface002.c +++ b/test_pool/drtm/interface002.c @@ -35,7 +35,7 @@ static void payload(void) status = val_drtm_features(invalid_fid, &feat1, &feat2); if (status != DRTM_ACS_NOT_SUPPORTED) { val_print(ERROR, "\n Invalid function ID test failed, status=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -55,7 +55,7 @@ static void payload(void) "\n Function ID Rsvd Bits:[62:32] not zero, status=%d", status); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t interface002_entry(uint32_t num_pe) diff --git a/test_pool/drtm/interface003.c b/test_pool/drtm/interface003.c index d7d37ae4..8a1e9b41 100644 --- a/test_pool/drtm/interface003.c +++ b/test_pool/drtm/interface003.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query unprotect memory func check failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -41,25 +41,25 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query close locality func check failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } status = g_drtm_features.get_error; if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query get error func check failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } status = g_drtm_features.set_error; if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query set error func check failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface004.c b/test_pool/drtm/interface004.c index 34b731a7..194d8b13 100644 --- a/test_pool/drtm/interface004.c +++ b/test_pool/drtm/interface004.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) /*Status value lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query TCB hash feature failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -41,15 +41,15 @@ payload(uint32_t num_pe) if (status > DRTM_ACS_SUCCESS) { if (val_drtm_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(features_tcb_hashes, 8, 63)) != ACS_STATUS_PASS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } else { val_print(ERROR, "\n TCB hash feature value not available in return value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface005.c b/test_pool/drtm/interface005.c index 8925adb9..6cefe440 100644 --- a/test_pool/drtm/interface005.c +++ b/test_pool/drtm/interface005.c @@ -34,7 +34,7 @@ payload(uint32_t num_pe) /*Status value less than zero are error case*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query DMA protection feature failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -42,24 +42,24 @@ payload(uint32_t num_pe) if (status > DRTM_ACS_SUCCESS) { if (val_drtm_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(features_dma_prot, 24, 63)) != ACS_STATUS_PASS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } /* Check atleast 1 DMA Protection is supported */ dma_prot_support = VAL_EXTRACT_BITS(g_drtm_features.dma_prot_features.value, 0, 7); if (dma_prot_support == 0) { val_print(ERROR, "\n DMA Protection Not Supported"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); return; } } else { val_print(ERROR, "\n DMA protection feature value not available in return value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(3)); + val_set_status(index, RESULT_FAIL(4)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface006.c b/test_pool/drtm/interface006.c index 5739542d..828861c5 100644 --- a/test_pool/drtm/interface006.c +++ b/test_pool/drtm/interface006.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) /*Statu value lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query TPM feature failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -42,16 +42,16 @@ payload(uint32_t num_pe) if ((val_drtm_reserved_bits_check_is_zero(VAL_EXTRACT_BITS(features_tpm, 16, 31)) != ACS_STATUS_PASS) && (val_drtm_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(features_tpm, 37, 63)) != ACS_STATUS_PASS)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } else { val_print(ERROR, "\n TPM feature value not available in return value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface007.c b/test_pool/drtm/interface007.c index c22af04f..d2abdddc 100644 --- a/test_pool/drtm/interface007.c +++ b/test_pool/drtm/interface007.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) /*Status lessthan zero are error case*/ if (status < DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM query Min memory req feature failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -46,9 +46,9 @@ payload(uint32_t num_pe) } else { val_print(ERROR, "\n Min memory requirement feature value not available in return value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface008.c b/test_pool/drtm/interface008.c index 50cc4230..b088758e 100644 --- a/test_pool/drtm/interface008.c +++ b/test_pool/drtm/interface008.c @@ -34,11 +34,11 @@ payload(uint32_t num_pe) { val_print(ERROR, "\n Version not as expected, Current version =%d", psci_major_ver); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface009.c b/test_pool/drtm/interface009.c index f45e083a..bcade0ba 100644 --- a/test_pool/drtm/interface009.c +++ b/test_pool/drtm/interface009.c @@ -34,11 +34,11 @@ payload(uint32_t num_pe) { val_print(ERROR, "\n Version not as expected, Current version =%d", smccc_major_ver); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface010.c b/test_pool/drtm/interface010.c index 3b178922..4ef9777e 100644 --- a/test_pool/drtm/interface010.c +++ b/test_pool/drtm/interface010.c @@ -46,7 +46,7 @@ payload(uint32_t num_pe) if (pe_rdbase == 0) { val_print(ERROR, "\n Could not get RD Base Address"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -58,14 +58,14 @@ payload(uint32_t num_pe) if ((VAL_EXTRACT_BITS(gicr_ctrl_value, 0, 0) != 0) || (VAL_EXTRACT_BITS(gicr_ctrl_value, 3, 3) != 0)) { val_print(ERROR, "\n LPI is not disabled"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } num_its = val_gic_get_info(GIC_INFO_NUM_ITS); if (num_its == 0) { val_print(DEBUG, "\n No ITS, Skipping Test."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -74,7 +74,7 @@ payload(uint32_t num_pe) if (val_gic_its_get_base(its_id, &its_base)) { val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -84,11 +84,11 @@ payload(uint32_t num_pe) if ((VAL_EXTRACT_BITS(gits_ctrl_value, 0, 0) != 0) || (VAL_EXTRACT_BITS(gits_ctrl_value, 31, 31) != 1)) { val_print(ERROR, "\n ITS is not disabled"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t @@ -102,7 +102,7 @@ interface010_entry(uint32_t num_pe) if (status != ACS_STATUS_SKIP) { if (val_gic_its_configure() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; /* execute payload, which will execute relevant functions on current and other PEs */ payload(num_pe); } diff --git a/test_pool/drtm/interface011.c b/test_pool/drtm/interface011.c index 450e1b0e..b25c6499 100644 --- a/test_pool/drtm/interface011.c +++ b/test_pool/drtm/interface011.c @@ -45,7 +45,7 @@ payload(uint32_t num_pe) if (pe_rdbase == 0) { val_print(ERROR, "\n Could not get RD Base Address"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -57,7 +57,7 @@ payload(uint32_t num_pe) if ((VAL_EXTRACT_BITS(gicr_ctrl_value, 0, 0) == 0) && (VAL_EXTRACT_BITS(gicr_ctrl_value, 3, 3) == 0)) { val_print(ERROR, "\n LPI is disabled"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -73,11 +73,11 @@ payload(uint32_t num_pe) new_gicr_pendbaser = val_mmio_read(pe_rdbase + ARM_GICR_PENDBASER); if (gicr_pendbaser != new_gicr_pendbaser) { val_print(ERROR, "\n GICR_PENDBASER value is changed when LPI is enable"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t @@ -91,7 +91,7 @@ interface011_entry(uint32_t num_pe) if (status != ACS_STATUS_SKIP) { if (val_gic_its_configure() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; /* execute payload, which will execute relevant functions on current and other PEs */ payload(num_pe); } diff --git a/test_pool/drtm/interface012.c b/test_pool/drtm/interface012.c index 0bd45c2f..ea0421d6 100644 --- a/test_pool/drtm/interface012.c +++ b/test_pool/drtm/interface012.c @@ -33,7 +33,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -42,11 +42,11 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/drtm/interface013.c b/test_pool/drtm/interface013.c index fc6bb036..8749456c 100644 --- a/test_pool/drtm/interface013.c +++ b/test_pool/drtm/interface013.c @@ -62,7 +62,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -71,14 +71,14 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } /* num_hashes value zero indicates that hashes cannot be recorded with DRTM_SET_TCB_HASH */ if (!num_hashes) { val_print(ERROR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); } /* Max number of hashes can be recorded plus one */ @@ -88,7 +88,7 @@ payload(uint32_t num_pe) ((sizeof(uint32_t) + (sizeof(uint8_t) * SHA_256_DIGEST_SIZE_BYTES)) * num_hashes)); if (!drtm_hash_table) { val_print(ERROR, "\n Failed to allocate tcb hash table"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -97,11 +97,11 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_OUT_OF_RESOURCE) { val_print(ERROR, "\n DRTM set invalid num of Hashes failed %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_tcb_hash; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_tcb_hash: val_memory_free(drtm_hash_table); diff --git a/test_pool/drtm/interface014.c b/test_pool/drtm/interface014.c index 26f77545..d0ae1393 100644 --- a/test_pool/drtm/interface014.c +++ b/test_pool/drtm/interface014.c @@ -59,7 +59,7 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(DEBUG, "\n DRTM_SET_TCB_HASH function not supported err=%d", status); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -68,21 +68,21 @@ payload(uint32_t num_pe) if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM_LOCK_TCB_HASHES function not supported err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } /* num_hashes value zero indicates that hashes cannot be recorded with DRTM_SET_TCB_HASH */ if (!num_hashes) { val_print(ERROR, "\n Max Hashes can be recorded with DRTM_SET_TCB_HASH is 0"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); } drtm_hash_table = (DRTM_TCB_HASH_TABLE *)val_memory_alloc(sizeof(DRTM_TCB_HASH_TABLE_HDR) + ((sizeof(uint32_t) + (sizeof(uint8_t) * SHA_256_DIGEST_SIZE_BYTES)) * NUM_OF_HASHES)); if (!drtm_hash_table) { val_print(ERROR, "\n Failed to allocate tcb hash table"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -92,7 +92,7 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_INVALID_PARAMETERS) { val_print(ERROR, "\n DRTM set invalid parameters failed %d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); goto free_tcb_hash; } @@ -100,7 +100,7 @@ payload(uint32_t num_pe) status = val_drtm_lock_tcb_hashes(); if (status != DRTM_ACS_SUCCESS) { val_print(ERROR, "\n DRTM Lock Hashes failed err=%d", status); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); goto free_tcb_hash; } /* Refill the hash table with revision as 1 */ @@ -109,12 +109,12 @@ payload(uint32_t num_pe) status = val_drtm_set_tcb_hash((uint64_t)drtm_hash_table); if (status != DRTM_ACS_DENIED) { val_print(ERROR, "\n DRTM set Hash denied failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); goto free_tcb_hash; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); free_tcb_hash: val_memory_free(drtm_hash_table); diff --git a/test_pool/drtm/interface015.c b/test_pool/drtm/interface015.c index a266a9c2..3553f73f 100644 --- a/test_pool/drtm/interface015.c +++ b/test_pool/drtm/interface015.c @@ -34,7 +34,7 @@ payload(uint32_t num_pe) if (status < DRTM_ACS_SUCCESS) { val_print(DEBUG, "\n DRTM query DLME Image Authentication feature not supported err=%d", status); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -42,16 +42,16 @@ payload(uint32_t num_pe) if (status > DRTM_ACS_SUCCESS) { if (val_drtm_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(features_dlme_img_auth, 1, 63)) != ACS_STATUS_PASS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } else { val_print(ERROR, "\n DLME Image Authentication feature value not available in return value"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ete/ete001.c b/test_pool/ete/ete001.c index 82409231..4d91a95f 100644 --- a/test_pool/ete/ete001.c +++ b/test_pool/ete/ete001.c @@ -36,11 +36,11 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ete001_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete002.c b/test_pool/ete/ete002.c index bb0b51e3..869e84fa 100644 --- a/test_pool/ete/ete002.c +++ b/test_pool/ete/ete002.c @@ -39,7 +39,7 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -144,9 +144,9 @@ static void payload(void) } if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ete002_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete003.c b/test_pool/ete/ete003.c index 45904430..6042d173 100644 --- a/test_pool/ete/ete003.c +++ b/test_pool/ete/ete003.c @@ -83,9 +83,9 @@ void check_timestamp(uint32_t num_pe) "\n Primary PE start_timestamp : 0x%llx", start_timestamp[index]); val_print(TRACE, "\n Primary PE end_timestamp : 0x%llx", end_timestamp[index]); - val_set_status(index, RESULT_FAIL(0, 06)); + val_set_status(index, RESULT_FAIL(06)); } else - val_set_status(index, RESULT_PASS(0, 02)); + val_set_status(index, RESULT_PASS); } static void payload(void) @@ -102,7 +102,7 @@ static void payload(void) if (data == 0) { test_fail = 1; val_print_primary_pe(ERROR, "\n FEAT_TRBE not supported", 0, index); - val_set_status(index, RESULT_FAIL(0, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -111,7 +111,7 @@ static void payload(void) if (data == 0) { test_fail = 1; val_print_primary_pe(ERROR, "\n FEAT_TRF not supported", 0, index); - val_set_status(index, RESULT_FAIL(0, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -147,7 +147,7 @@ static void payload(void) test_fail = 1; val_data_cache_ops_by_va((addr_t)(&test_fail), CLEAN_AND_INVALIDATE); val_print_primary_pe(ERROR, "\n Trace Generation Failed", 0, index); - val_set_status(index, RESULT_FAIL(0, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -156,19 +156,19 @@ static void payload(void) test_fail = 1; val_data_cache_ops_by_va((addr_t)(&test_fail), CLEAN_AND_INVALIDATE); val_print_primary_pe(ERROR, "\n Traced Timestamp is 0", 0, index); - val_set_status(index, RESULT_FAIL(0, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } if ((start_timestamp[index] <= traced_timestamp) && (traced_timestamp <= end_timestamp[index])) { - val_set_status(index, RESULT_PASS(0, 01)); + val_set_status(index, RESULT_PASS); return; } test_fail = 1; val_data_cache_ops_by_va((addr_t)(&test_fail), CLEAN_AND_INVALIDATE); - val_set_status(index, RESULT_FAIL(0, 05)); + val_set_status(index, RESULT_FAIL(05)); } /* ETE_04 - This test verifies that all the trace units diff --git a/test_pool/ete/ete004.c b/test_pool/ete/ete004.c index 6d12151e..09a57f66 100644 --- a/test_pool/ete/ete004.c +++ b/test_pool/ete/ete004.c @@ -44,7 +44,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(dfr0_value, 44, 47); if (data == 0) { val_print_primary_pe(ERROR, "\n FEAT_TRBE not supported", 0, index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -52,7 +52,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(dfr0_value, 40, 43); if (data == 0) { val_print_primary_pe(ERROR, "\n FEAT_TRF not supported", 0, index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -60,7 +60,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(dfr0_value, 56, 59); if (data == 0) { val_print_primary_pe(ERROR, "\n FEAT_TRBE_EXT not supported", 0, index); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -95,23 +95,23 @@ static void payload(void) (traced_timestamp_2 == ACS_STATUS_FAIL) || (traced_timestamp_3 == ACS_STATUS_FAIL)) { val_print_primary_pe(ERROR, "\n Trace Generation Failed", 0, index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } if ((traced_timestamp_1 == 0) || (traced_timestamp_2 == 0) || (traced_timestamp_3 == 0)) { val_print_primary_pe(ERROR, "\n Traced Timestamp is 0", 0, index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } /* Check Traced Timestamp is increasing */ if ((traced_timestamp_1 < traced_timestamp_2) && (traced_timestamp_2 < traced_timestamp_3)) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(index, RESULT_FAIL(05)); } uint32_t ete004_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete005.c b/test_pool/ete/ete005.c index 8d95cafa..4e8bebeb 100644 --- a/test_pool/ete/ete005.c +++ b/test_pool/ete/ete005.c @@ -35,11 +35,11 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ete005_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete006.c b/test_pool/ete/ete006.c index 6e17fd1a..69ed92e9 100644 --- a/test_pool/ete/ete006.c +++ b/test_pool/ete/ete006.c @@ -38,7 +38,7 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -49,11 +49,11 @@ static void payload(void) if (index == primary_index) primary_pe_flag_updates = data; else if (primary_pe_flag_updates != data) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ete006_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete007.c b/test_pool/ete/ete007.c index 9ca92981..db51c4f3 100644 --- a/test_pool/ete/ete007.c +++ b/test_pool/ete/ete007.c @@ -38,7 +38,7 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -49,11 +49,11 @@ static void payload(void) if (index == primary_index) min_trace_alignment = data; else if (min_trace_alignment != data) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ete007_entry(uint32_t num_pe) diff --git a/test_pool/ete/ete008.c b/test_pool/ete/ete008.c index aeed951a..f8bb0141 100644 --- a/test_pool/ete/ete008.c +++ b/test_pool/ete/ete008.c @@ -36,16 +36,16 @@ static void payload(void) if (int_id == 1) { val_print_primary_pe(DEBUG, "\n GICC TRBE interrupt field needs at least 6.5 ACPI table", 0, index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } val_print_primary_pe(DEBUG, "\n GICC TRBE INTERRUPT GISV = %d", int_id, index); if (val_gic_is_valid_ppi(int_id)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); } diff --git a/test_pool/exerciser/e001.c b/test_pool/exerciser/e001.c index 86c24bdc..c50369ed 100644 --- a/test_pool/exerciser/e001.c +++ b/test_pool/exerciser/e001.c @@ -235,7 +235,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P. */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -314,11 +314,11 @@ payload(void) val_pcie_write_acsctrl(acsctrl_default); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; @@ -335,7 +335,7 @@ e001_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e002.c b/test_pool/exerciser/e002.c index c2f0919b..6e993d6e 100644 --- a/test_pool/exerciser/e002.c +++ b/test_pool/exerciser/e002.c @@ -362,7 +362,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P. */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -474,11 +474,11 @@ payload(void) val_pcie_write_acsctrl(acsctrl_default); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; @@ -495,7 +495,7 @@ e002_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e003.c b/test_pool/exerciser/e003.c index 5673c386..cb04b6c7 100644 --- a/test_pool/exerciser/e003.c +++ b/test_pool/exerciser/e003.c @@ -364,7 +364,7 @@ payload(void) returning SKIP if called for BSA */ /* TODO revisit could be warning for BSA, since we can't deduce if condition of BSA rule */ if (g_build_sbsa == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -372,13 +372,13 @@ payload(void) barspace_transactions_order_check(); if (warn_cnt) - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); else if (!run_flag) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -394,7 +394,7 @@ e003_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e004.c b/test_pool/exerciser/e004.c index 971763e8..31da6896 100644 --- a/test_pool/exerciser/e004.c +++ b/test_pool/exerciser/e004.c @@ -68,7 +68,7 @@ payload (void) if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { val_print(DEBUG, "\n No ITS, Skipping Test.\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -107,7 +107,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -115,7 +115,7 @@ payload (void) if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -124,7 +124,7 @@ payload (void) if (status) { val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -135,7 +135,7 @@ payload (void) if (val_gic_its_get_base(its_id, &its_base)) { val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -151,7 +151,7 @@ payload (void) if (irq_pending == 0) { val_print(ERROR, "\n Interrupt triggered from PE for bdf : 0x%x, ", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); return; } @@ -160,12 +160,12 @@ payload (void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -181,7 +181,7 @@ e004_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e006.c b/test_pool/exerciser/e006.c index bad08a64..d20b8f0d 100644 --- a/test_pool/exerciser/e006.c +++ b/test_pool/exerciser/e006.c @@ -85,7 +85,7 @@ payload (void) e_intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!e_intr_map) { val_print(ERROR, "\n Memory allocation error", 00); - val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -131,7 +131,7 @@ payload (void) if (ret_val) { val_print (ERROR, "\n Installing ISR failed for IRQ: %x", e_intr_line); - val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -184,13 +184,13 @@ payload (void) } if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); else if (warn_cnt) - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); val_memory_free_aligned(e_intr_map); @@ -209,7 +209,7 @@ e006_entry(uint32_t num_pe) status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload (TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e007.c b/test_pool/exerciser/e007.c index b3089363..be1a16fc 100644 --- a/test_pool/exerciser/e007.c +++ b/test_pool/exerciser/e007.c @@ -155,7 +155,7 @@ payload (void) returning SKIP if called for BSA */ /* TODO revisit could be warning for BSA, since we can't deduce if condition of BSA rule */ if (g_build_sbsa == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -186,7 +186,7 @@ payload (void) if (smmu_index != ACS_INVALID_INDEX) { if (val_smmu_disable(smmu_index)) { val_print(ERROR, "\n Exerciser %x smmu disable error", instance); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } } @@ -195,7 +195,7 @@ payload (void) dram_buf1_virt = val_memory_alloc_cacheable(e_bdf, TEST_DATA_BLK_SIZE, &dram_buf1_phys); if (!dram_buf1_virt) { val_print(ERROR, "\n WB and OSH mem alloc failure %x", 2); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -217,11 +217,11 @@ payload (void) } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 0)); + val_set_status(pe_index, RESULT_PASS); return; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); return; } @@ -237,7 +237,7 @@ e007_entry(uint32_t num_pe) status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload (TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e008.c b/test_pool/exerciser/e008.c index 6d49b708..572c7afc 100644 --- a/test_pool/exerciser/e008.c +++ b/test_pool/exerciser/e008.c @@ -196,7 +196,7 @@ payload (void *arg) if (smmu_index != ACS_INVALID_INDEX) { if (val_smmu_disable(smmu_index)) { val_print(ERROR, "\n Exerciser %x smmu disable error", instance); - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } } @@ -207,7 +207,7 @@ payload (void *arg) if (!dram_buf1_virt) { val_print(ERROR, "\n WB and OSH mem alloc failure %x", 2); - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -230,13 +230,13 @@ payload (void *arg) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else - val_set_status(pe_index, RESULT_PASS(test_data->test_num, 1)); + val_set_status(pe_index, RESULT_PASS); return; test_fail: - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); return; } @@ -254,7 +254,7 @@ e008_entry(uint32_t num_pe) status = val_initialize_test(test_entries[0].test_num, test_entries[0].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } @@ -278,7 +278,7 @@ e038_entry(uint32_t num_pe) status = val_initialize_test(test_entries[1].test_num, test_entries[1].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } diff --git a/test_pool/exerciser/e010.c b/test_pool/exerciser/e010.c index bb620c53..71e3bd29 100644 --- a/test_pool/exerciser/e010.c +++ b/test_pool/exerciser/e010.c @@ -72,7 +72,7 @@ payload(void) if (status == PCIE_CAP_NOT_FOUND) { val_print(DEBUG, "\n Unable to start transaction monitoring"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -81,7 +81,7 @@ payload(void) if (status == PCIE_CAP_NOT_FOUND) { val_print(DEBUG, "\n Unable to stop transaction monitoring"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } @@ -96,9 +96,9 @@ payload(void) } if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; @@ -115,7 +115,7 @@ e010_entry(uint32_t num_pe) status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload (TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e011.c b/test_pool/exerciser/e011.c index c57f84b5..2acdbfb1 100644 --- a/test_pool/exerciser/e011.c +++ b/test_pool/exerciser/e011.c @@ -46,7 +46,7 @@ payload (void) if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { val_print(DEBUG, "\n Skipping Test as GIC ITS not available"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -84,7 +84,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -92,15 +92,15 @@ payload (void) status = val_iovirt_get_its_info(ITS_GET_GRP_INDEX_FOR_ID, 0, its_id, &grp_id); if (status) { val_print(ERROR, "\n Invalid ITS ID, Failed on BDF 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -116,7 +116,7 @@ e011_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e012.c b/test_pool/exerciser/e012.c index 55327eca..12ff589c 100644 --- a/test_pool/exerciser/e012.c +++ b/test_pool/exerciser/e012.c @@ -66,7 +66,7 @@ payload (void) status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status || (num_group < 2)) { val_print(DEBUG, "\n Number of ITS Group < 2, Skipping Test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -105,7 +105,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -129,7 +129,7 @@ payload (void) if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -138,7 +138,7 @@ payload (void) if (status) { val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", base_lpi_id + instance); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -159,7 +159,7 @@ payload (void) "\n Interrupt triggered for int_id : 0x%x, ", base_lpi_id + instance); val_print(ERROR, "BDF : 0x%x ", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); val_gic_free_msi(e_bdf, device_id, get_value, base_lpi_id + instance, msi_index); return; } @@ -170,12 +170,12 @@ payload (void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -191,7 +191,7 @@ e012_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e013.c b/test_pool/exerciser/e013.c index dde83446..9e39508a 100644 --- a/test_pool/exerciser/e013.c +++ b/test_pool/exerciser/e013.c @@ -70,7 +70,7 @@ get_exerciser_in_its_group(uint32_t its_id, uint32_t *req_instance) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return 1; } @@ -109,7 +109,7 @@ payload (void) if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { val_print(DEBUG, "\n No ITS, Skipping Test.\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -146,7 +146,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -169,7 +169,7 @@ payload (void) if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", req_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -178,7 +178,7 @@ payload (void) if (status) { val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -197,7 +197,7 @@ payload (void) if (irq_pending == 0) { val_print(ERROR, "\n Interrupt triggered from diff exerciser : 0x%x, ", req_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); val_gic_free_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index); return; } @@ -208,12 +208,12 @@ payload (void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -229,7 +229,7 @@ e013_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e014.c b/test_pool/exerciser/e014.c index a8baa880..e2775600 100644 --- a/test_pool/exerciser/e014.c +++ b/test_pool/exerciser/e014.c @@ -129,7 +129,7 @@ payload(void) if (!val_pcie_p2p_support()) { val_print(DEBUG, "\n P2P is supported, Skipping Test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -159,7 +159,7 @@ payload(void) status = check_p2p_transaction(instance, bar_base); if (status) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -169,12 +169,12 @@ payload(void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t @@ -189,7 +189,7 @@ e014_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e015.c b/test_pool/exerciser/e015.c index dbaae132..69c92978 100644 --- a/test_pool/exerciser/e015.c +++ b/test_pool/exerciser/e015.c @@ -191,11 +191,11 @@ payload(void) test_result: if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; @@ -212,7 +212,7 @@ e015_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e016.c b/test_pool/exerciser/e016.c index cc1fcb4e..e5997f9a 100644 --- a/test_pool/exerciser/e016.c +++ b/test_pool/exerciser/e016.c @@ -44,7 +44,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } static @@ -68,7 +68,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -125,7 +125,7 @@ payload(void) if ((old_value != new_value && new_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { val_print(ERROR, "\n Memory access check failed for BDF 0x%x", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); val_pcie_clear_urd(bdf); return; } @@ -135,16 +135,16 @@ payload(void) } } -val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); +val_set_status(pe_index, RESULT_PASS); return; test_warn_unimplemented: val_memory_unmap(baseptr); - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -160,7 +160,7 @@ e016_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e017.c b/test_pool/exerciser/e017.c index b6348ae5..92e5da80 100644 --- a/test_pool/exerciser/e017.c +++ b/test_pool/exerciser/e017.c @@ -89,7 +89,7 @@ payload(void *arg) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -102,7 +102,7 @@ payload(void *arg) { val_print(ERROR, "\n Unable to allocate memory for buffer of %x pages", TEST_DATA_NUM_PAGES); - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -210,11 +210,11 @@ payload(void *arg) val_memory_free_pages(dram_buf_virt, TEST_DATA_NUM_PAGES); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_PASS); return; test_skip_unimplemented: @@ -222,7 +222,7 @@ payload(void *arg) val_pcie_enable_bme(erp_bdf); /* Return the buffer to the heap manager */ val_memory_free_pages(dram_buf_virt, TEST_DATA_NUM_PAGES); - val_set_status(pe_index, RESULT_WARN(test_data->test_num, 02)); + val_set_status(pe_index, RESULT_WARNING(02)); } uint32_t @@ -238,7 +238,7 @@ e017_entry(uint32_t num_pe) status = val_initialize_test(data.test_num, test_entries[0].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } @@ -263,7 +263,7 @@ e034_entry(uint32_t num_pe) status = val_initialize_test(data.test_num, test_entries[1].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } diff --git a/test_pool/exerciser/e019.c b/test_pool/exerciser/e019.c index 720ca9b3..07a8c116 100644 --- a/test_pool/exerciser/e019.c +++ b/test_pool/exerciser/e019.c @@ -108,7 +108,7 @@ payload(void) pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { val_print(ERROR, "\n mem alloc failure %x", 03); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -119,7 +119,7 @@ payload(void) if (!dram_buf_in_virt) { val_print(ERROR, "\n Cacheable mem alloc failure %x", 02); val_memory_free_aligned(pgt_base_array); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -283,15 +283,15 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RCiEP/iEP type devicefound, Skipping the test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); goto test_clean; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); goto test_clean; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); test_clean: /* Return the pages to the heap manager */ @@ -334,7 +334,7 @@ e019_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e020.c b/test_pool/exerciser/e020.c index 8608ef7d..73ec1012 100644 --- a/test_pool/exerciser/e020.c +++ b/test_pool/exerciser/e020.c @@ -113,7 +113,7 @@ payload(void) pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { val_print(ERROR, "\n mem alloc failure"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -124,7 +124,7 @@ payload(void) if (!dram_buf_in_virt) { val_print(ERROR, "\n Cacheable mem alloc failure"); val_memory_free_aligned(pgt_base_array); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -337,14 +337,14 @@ payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); goto test_clean; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); test_clean: /* Return the pages to the heap manager */ @@ -397,7 +397,7 @@ e020_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e021.c b/test_pool/exerciser/e021.c index 5e7691c8..4e1d6d8e 100644 --- a/test_pool/exerciser/e021.c +++ b/test_pool/exerciser/e021.c @@ -436,17 +436,17 @@ payload(void) barspace_transactions_order_check(); if (warn_cnt) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } else if (!run_flag) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -460,7 +460,7 @@ e021_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(0); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e022.c b/test_pool/exerciser/e022.c index 4ec25e24..bc77b912 100644 --- a/test_pool/exerciser/e022.c +++ b/test_pool/exerciser/e022.c @@ -208,14 +208,14 @@ payload(void) barspace_transactions_order_check(); if (!run_flag) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -229,7 +229,7 @@ e022_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e023.c b/test_pool/exerciser/e023.c index 97bfaf68..8ea62f9f 100644 --- a/test_pool/exerciser/e023.c +++ b/test_pool/exerciser/e023.c @@ -318,7 +318,7 @@ payload(void) if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { val_print(ERROR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -327,7 +327,7 @@ payload(void) if (status == PCIE_CAP_NOT_FOUND) { val_print(ERROR, "\n ECID_DPC not found"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -356,7 +356,7 @@ payload(void) if (status) { val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -364,7 +364,7 @@ payload(void) status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -372,7 +372,7 @@ payload(void) if (status) { val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -387,7 +387,7 @@ payload(void) clear_status_bits(e_bdf, aer_offset, 0, 0); if (inject_error(e_bdf, instance, aer_offset)) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -396,7 +396,7 @@ payload(void) clear_status_bits(e_bdf, aer_offset, AER_ERROR_MASK, 0); if (inject_error(e_bdf, instance, aer_offset)) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); return; } mask_value = 0; @@ -405,7 +405,7 @@ payload(void) clear_status_bits(e_bdf, aer_offset, 0, AER_UNCORR_SEVR_FATAL); if (inject_error(e_bdf, instance, aer_offset)) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(pe_index, RESULT_FAIL(05)); return; } @@ -425,9 +425,9 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; @@ -444,7 +444,7 @@ e023_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e024.c b/test_pool/exerciser/e024.c index 3c12dafc..5284382a 100644 --- a/test_pool/exerciser/e024.c +++ b/test_pool/exerciser/e024.c @@ -124,7 +124,7 @@ save_config_space(uint32_t rp_bdf) if (cfg_space_buf[tbl_index] == NULL) { val_print(ERROR, "\n Memory allocation failed."); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return 1; } @@ -218,7 +218,7 @@ payload(void) if (status) { val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -226,7 +226,7 @@ payload(void) status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -234,7 +234,7 @@ payload(void) if (status) { val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -367,7 +367,7 @@ payload(void) val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", erp_bdf); val_memory_free_aligned(cfg_space_buf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -407,11 +407,11 @@ payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; @@ -428,7 +428,7 @@ e024_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e025.c b/test_pool/exerciser/e025.c index 8a0ee080..58d5ec96 100644 --- a/test_pool/exerciser/e025.c +++ b/test_pool/exerciser/e025.c @@ -174,7 +174,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P. */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; } @@ -228,11 +228,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; @@ -249,7 +249,7 @@ e025_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e026.c b/test_pool/exerciser/e026.c index 1ba0dee4..d281974f 100644 --- a/test_pool/exerciser/e026.c +++ b/test_pool/exerciser/e026.c @@ -87,14 +87,14 @@ payload(void *arg) pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { val_print(ERROR, "\n mem alloc failure for pgt_base_array"); - val_set_status(pe_index, RESULT_FAIL(payload_data->test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } pgt_base = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base) { val_print(ERROR, "\n mem alloc failure for pgt_base"); - val_set_status(pe_index, RESULT_FAIL(payload_data->test_num, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); val_memory_free_aligned(pgt_base_array); return; } @@ -223,14 +223,14 @@ payload(void *arg) } test_pass: - val_set_status(pe_index, RESULT_PASS(payload_data->test_num, 01)); + val_set_status(pe_index, RESULT_PASS); goto test_clean; if (test_skip) - val_set_status(pe_index, RESULT_SKIP(payload_data->test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); test_fail: - val_set_status(pe_index, RESULT_FAIL(payload_data->test_num, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); test_clean: val_memory_free_aligned(pgt_base_array); val_memory_free_aligned(pgt_base); @@ -250,7 +250,7 @@ e026_entry(uint32_t num_pe) status = val_initialize_test(test_entries[0].test_num, test_entries[0].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } @@ -275,7 +275,7 @@ e032_entry(uint32_t num_pe) status = val_initialize_test(test_entries[1].test_num, test_entries[1].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_configurable_payload(&data, payload); } diff --git a/test_pool/exerciser/e027.c b/test_pool/exerciser/e027.c index 3f90d3cd..2ed25545 100644 --- a/test_pool/exerciser/e027.c +++ b/test_pool/exerciser/e027.c @@ -123,7 +123,7 @@ save_config_space(uint32_t rp_bdf) if (cfg_space_buf[tbl_index] == NULL) { val_print(ERROR, "\n Memory allocation failed."); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return 1; } @@ -226,7 +226,7 @@ payload(void) if (status) { val_print(ERROR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -234,7 +234,7 @@ payload(void) status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -242,7 +242,7 @@ payload(void) if (status) { val_print(ERROR, "\n Intr handler registration failed: 0x%x", lpi_int_id); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -331,7 +331,7 @@ payload(void) val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", erp_bdf); val_memory_free_aligned(cfg_space_buf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -369,11 +369,11 @@ payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; @@ -390,7 +390,7 @@ e027_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e028.c b/test_pool/exerciser/e028.c index ca23c167..8c9808f7 100644 --- a/test_pool/exerciser/e028.c +++ b/test_pool/exerciser/e028.c @@ -171,11 +171,11 @@ payload() } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -191,7 +191,7 @@ e028_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e029.c b/test_pool/exerciser/e029.c index 70ef3791..2059a017 100644 --- a/test_pool/exerciser/e029.c +++ b/test_pool/exerciser/e029.c @@ -70,7 +70,7 @@ payload() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -96,7 +96,7 @@ payload() if (status == NOT_IMPLEMENTED) { val_print(DEBUG, "\n System doesn't trigger an external abort"); val_print(DEBUG, "\n Skipping for bdf %x", e_bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -104,7 +104,7 @@ payload() if (ras_node == NOT_IMPLEMENTED) { val_print(DEBUG, "\n No RAS compliant node to record PCIe Error"); val_print(DEBUG, "\n Skippping RAS check for BDF - 0x%x", e_bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } @@ -127,7 +127,7 @@ payload() val_pcie_disable_msa(e_bdf); /* Set test status as FAIL, update to PASS in exception handler */ - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); /* Test runs for atleast one endpoint */ test_skip = 0; @@ -143,7 +143,7 @@ payload() val_print(DEBUG, " bar_data %x ", bar_data); if (!(exception)) { val_print(ERROR, "\n External Abort isnt recieved, BDF %x", e_bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); } /* Get the RAS Error Status register value of the RAS node implemented*/ @@ -192,11 +192,11 @@ payload() } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_SKIP(03)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -212,7 +212,7 @@ e029_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e030.c b/test_pool/exerciser/e030.c index f605a2a4..16b13ac4 100644 --- a/test_pool/exerciser/e030.c +++ b/test_pool/exerciser/e030.c @@ -64,7 +64,7 @@ payload(void) pgt_base_array = val_aligned_alloc(MEM_ALIGN_4K, sizeof(uint64_t) * num_exercisers); if (!pgt_base_array) { val_print(ERROR, "\n mem alloc failure %x", 03); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -177,16 +177,16 @@ payload(void) } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); goto test_clean; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); test_clean: if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); /* Remove all address mappings for each exerciser */ for (instance = 0; instance < num_exercisers; ++instance) @@ -225,7 +225,7 @@ e030_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e033.c b/test_pool/exerciser/e033.c index 14c8d97f..fecc496e 100644 --- a/test_pool/exerciser/e033.c +++ b/test_pool/exerciser/e033.c @@ -65,7 +65,7 @@ payload (void) if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) { val_print(DEBUG, "\n No ITS, Skipping Test.\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -104,7 +104,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -112,7 +112,7 @@ payload (void) if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -121,7 +121,7 @@ payload (void) if (status) { val_print(ERROR, "\n Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -132,7 +132,7 @@ payload (void) if (val_gic_its_get_base(its_id, &its_base)) { val_print(ERROR, "\n Could not find ITS Base for its_id : 0x%x", its_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -149,7 +149,7 @@ payload (void) "\n Interrupt trigger failed for : 0x%x, ", lpi_int_id + instance); val_print(ERROR, "BDF : 0x%x ", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index); return; } @@ -159,12 +159,12 @@ payload (void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -179,7 +179,7 @@ e033_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e035.c b/test_pool/exerciser/e035.c index d5f21f11..ba97605f 100644 --- a/test_pool/exerciser/e035.c +++ b/test_pool/exerciser/e035.c @@ -64,7 +64,7 @@ payload (void) if (val_gic_get_info(GIC_INFO_NUM_ITS) < 2) { val_print(DEBUG, "\n Skipping Test as multiple ITS not available"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -101,7 +101,7 @@ payload (void) if (status) { val_print(ERROR, "\n Could not get device info for BDF : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -135,7 +135,7 @@ payload (void) if (status) { val_print(ERROR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -144,7 +144,7 @@ payload (void) if (status) { val_print(ERROR, "\n Intr handler registration fail, Interrupt : 0x%x", base_lpi_id + instance); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -167,7 +167,7 @@ payload (void) "\n BDF : 0x%x, ", e_bdf); val_print(ERROR, "its_id : 0x%x", its_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); val_gic_free_msi(e_bdf, device_id, its_id, base_lpi_id + instance, msi_index); return; } @@ -179,12 +179,12 @@ payload (void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } /* Pass Test */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } @@ -200,7 +200,7 @@ e035_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e036.c b/test_pool/exerciser/e036.c index 6cbaf103..c00409ac 100644 --- a/test_pool/exerciser/e036.c +++ b/test_pool/exerciser/e036.c @@ -120,7 +120,7 @@ payload(void) dram_buf_base_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES * 2); if (!dram_buf_base_virt) { val_print(ERROR, "\n Cacheable mem alloc failure %x", 2); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -139,13 +139,13 @@ payload(void) if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { val_print(ERROR, "\n TCR read failure %x", 3); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); return; } if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { val_print(ERROR, "\n TTBR0 read failure %x", 4); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); return; } @@ -393,14 +393,14 @@ payload(void) } if (e_valid_cnt) - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); else - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); goto test_clean; test_fail: - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); test_clean: val_memory_free_pages(dram_buf_base_virt, TEST_DATA_NUM_PAGES * 2); @@ -420,7 +420,7 @@ e036_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return RESULT_SKIP(1); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e039.c b/test_pool/exerciser/e039.c index aa69cbf9..40974687 100644 --- a/test_pool/exerciser/e039.c +++ b/test_pool/exerciser/e039.c @@ -43,7 +43,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); } static @@ -67,7 +67,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -136,21 +136,21 @@ payload(void) if (test_skip) { val_print(DEBUG, "\n No exerciser with prefetchable mmio space, Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; test_warn_unimplemented: val_memory_unmap(baseptr); - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; test_fail: val_memory_unmap(baseptr); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -167,7 +167,7 @@ e039_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e040.c b/test_pool/exerciser/e040.c index 66ef8137..ecf65877 100644 --- a/test_pool/exerciser/e040.c +++ b/test_pool/exerciser/e040.c @@ -278,13 +278,13 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); if (val_exerciser_test_init() != ACS_STATUS_PASS) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } comp_count = val_cxl_get_component_info(CXL_COMPONENT_INFO_COUNT, 0); if (comp_count == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } @@ -310,11 +310,11 @@ payload(void) } if (test_skip == 0) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_SKIP(03)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -328,7 +328,7 @@ e040_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e041.c b/test_pool/exerciser/e041.c index b1ce9986..a917ffe6 100644 --- a/test_pool/exerciser/e041.c +++ b/test_pool/exerciser/e041.c @@ -167,7 +167,7 @@ payload(void) comp_count = val_cxl_get_component_info(CXL_COMPONENT_INFO_COUNT, 0); if (comp_count == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -211,16 +211,16 @@ payload(void) status = cache_sequence(instance, e_bdf); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n CXL.cache exerciser sequence failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -234,7 +234,7 @@ e041_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e043.c b/test_pool/exerciser/e043.c index 52003e8a..2f36135f 100644 --- a/test_pool/exerciser/e043.c +++ b/test_pool/exerciser/e043.c @@ -76,7 +76,7 @@ payload() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -130,13 +130,13 @@ payload() val_print(TRACE, "\n host_index: %llx", host_index); status = val_cxl_get_cfmws_window(host_index, &cfmws_base, &cfmws_size); if (status != ACS_STATUS_PASS) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } status = val_cxl_map_hdm_address(cfmws_base, SIZE_4KB, &mapped); if (status != ACS_STATUS_PASS) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -164,11 +164,11 @@ payload() } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -184,7 +184,7 @@ e043_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e044.c b/test_pool/exerciser/e044.c index 01f9d678..f7d06485 100644 --- a/test_pool/exerciser/e044.c +++ b/test_pool/exerciser/e044.c @@ -81,7 +81,7 @@ payload(void) num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS); if (num_instances == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -133,11 +133,11 @@ payload(void) } if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -151,7 +151,7 @@ e044_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e045.c b/test_pool/exerciser/e045.c index 89b9564c..3badf824 100644 --- a/test_pool/exerciser/e045.c +++ b/test_pool/exerciser/e045.c @@ -79,19 +79,19 @@ payload(void) status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } status = val_exerciser_check_firmware_handle_support(); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Firmware first handling not supported"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -133,11 +133,11 @@ payload(void) } if (test_skip) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (fail_count) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_count)); + val_set_status(pe_index, RESULT_FAIL(fail_count)); } else { - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } } @@ -152,7 +152,7 @@ e045_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP_VAL; + return TEST_SKIP; val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/gic/g001.c b/test_pool/gic/g001.c index 75e95b3c..8282fbc1 100644 --- a/test_pool/gic/g001.c +++ b/test_pool/gic/g001.c @@ -36,11 +36,11 @@ payload() if (gic_version < 2) { val_print(ERROR, "\n GIC version is %x ", gic_version); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/gic/g002.c b/test_pool/gic/g002.c index 539897a2..75557a72 100644 --- a/test_pool/gic/g002.c +++ b/test_pool/gic/g002.c @@ -48,15 +48,15 @@ payload() if (gic_version < 3) { if ((num_ecam > 0) && (num_msi_frame == 0)) { val_print(ERROR, "\n GICv2 with PCIe : Invalid Configuration"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } else { - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/g003.c b/test_pool/gic/g003.c index 2413eb3c..abb92a94 100644 --- a/test_pool/gic/g003.c +++ b/test_pool/gic/g003.c @@ -43,7 +43,7 @@ payload() if (data == 0) { val_print(ERROR, "\n GICv3 and PCIe : ITS Not Present"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -51,17 +51,17 @@ payload() if (data == 0) { val_print(ERROR, "\n GICv3 and PCIe : LPI Not Supported"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } /* If PCIe is not present or Gic version is older then GICv3, just Skip the test */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); } uint32_t diff --git a/test_pool/gic/g004.c b/test_pool/gic/g004.c index d0476a19..8f6bca4f 100644 --- a/test_pool/gic/g004.c +++ b/test_pool/gic/g004.c @@ -33,17 +33,17 @@ payload() gic_version = val_gic_get_info(GIC_INFO_VERSION); if (gic_version < 3) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } data = val_gic_get_info(GIC_INFO_SEC_STATES); if (data != 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/g005.c b/test_pool/gic/g005.c index 65bbbb73..cdf72953 100644 --- a/test_pool/gic/g005.c +++ b/test_pool/gic/g005.c @@ -56,7 +56,7 @@ payload() // Distributor must forward NS Group 1 interrupt if (!enable_grp1ns) { val_print(ERROR, "\n Non-secure SGIs not forwarded"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } else { @@ -65,7 +65,7 @@ payload() pe_rdbase = val_gic_get_pe_rdbase(mpid); val_print(DEBUG, "\n PE RD base address %llx", pe_rdbase); if (pe_rdbase == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } /* Read the current value of GICR_ISENABLER0 and set the lower 8 bits to 1 */ @@ -78,7 +78,7 @@ payload() val_print(DEBUG, " data 0x%x", data); data = VAL_EXTRACT_BITS(data, 0, 7); if (data == 0xFF) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } else { @@ -86,7 +86,7 @@ payload() "\n GICR_ISENABLER0: %X\n ", data); val_print(ERROR, "\n INTID 0 - 7 not implemented as non-secure SGIs"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } @@ -96,7 +96,7 @@ payload() val_mmio_write((val_get_gicd_base() + GICD_ISENABLER), data); data = VAL_EXTRACT_BITS(val_gic_get_info(GIC_INFO_SGI_NON_SECURE_LEGACY), 0, 7); if (data == 0xFF) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } else { @@ -104,7 +104,7 @@ payload() "\n GICD_IENABLER: %X\n ", data); val_print(ERROR, "\n INTID 0 - 7 not implemented as non-secure SGIs"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } } diff --git a/test_pool/gic/g006.c b/test_pool/gic/g006.c index e530a43e..dee3b6f5 100644 --- a/test_pool/gic/g006.c +++ b/test_pool/gic/g006.c @@ -32,7 +32,7 @@ isr_phy() { val_timer_set_phy_el1(0); val_print(TRACE, "\n Received phy el1 interrupt "); - val_set_status(0, RESULT_PASS(TEST_NUM, 1)); + val_set_status(0, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -54,7 +54,7 @@ payload() if (val_gic_install_isr(intid, isr_phy)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -67,7 +67,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n EL0-Phy timer interrupt not received on INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } diff --git a/test_pool/gic/g007.c b/test_pool/gic/g007.c index 8a59068f..e70adc1b 100644 --- a/test_pool/gic/g007.c +++ b/test_pool/gic/g007.c @@ -31,7 +31,7 @@ isr_vir() { val_timer_set_vir_el1(0); val_print(TRACE, "\n Received virt el1 interrupt "); - val_set_status(0, RESULT_PASS(TEST_NUM, 1)); + val_set_status(0, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -58,7 +58,7 @@ payload() if (val_gic_install_isr(intid, isr_vir)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -71,7 +71,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n EL0-Virtual timer interrupt not received on INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } diff --git a/test_pool/gic/g008.c b/test_pool/gic/g008.c index f9a48f37..4ea02d69 100644 --- a/test_pool/gic/g008.c +++ b/test_pool/gic/g008.c @@ -37,7 +37,7 @@ payload() if (intid != 25) { val_print(ERROR, "\n GIC Maintenance interrupt not mapped to PPI ID 25, id %d", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -47,7 +47,7 @@ payload() if (intid != 26) { val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI id 26, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -57,7 +57,7 @@ payload() if (intid != 27) { val_print(ERROR, "\n EL0-Virtual timer not mapped to PPI ID 27, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -67,7 +67,7 @@ payload() if (intid != 28) { val_print(ERROR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -77,11 +77,11 @@ payload() if (intid != 30) { val_print(ERROR, "\n EL0-Phy timer not mapped to PPI ID 30, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/g009.c b/test_pool/gic/g009.c index 590ba467..c2ba9894 100644 --- a/test_pool/gic/g009.c +++ b/test_pool/gic/g009.c @@ -37,7 +37,7 @@ isr_vir() /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_vir_el2(0); val_print(TRACE, "\n Received vir el2 interrupt "); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -55,7 +55,7 @@ payload() if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { val_print(DEBUG, "\n Skipping. Test accesses EL2" " Registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -69,7 +69,7 @@ payload() * ID_AA64MMFR1_EL1 VH, bits [11:8] must be 0x1 */ if (!((data >> 8) & 0xF)) { val_print(DEBUG, "\n v8.1 VHE not supported on this PE "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -81,13 +81,13 @@ payload() val_print(DEBUG, "\n NS EL2 virtual timer not mapped to PPI base range, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } if (val_gic_install_isr(intid, isr_vir)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -99,7 +99,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n NS EL2 Virtual timer interrupt %d not received", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); } return; } diff --git a/test_pool/gic/g010.c b/test_pool/gic/g010.c index 931e65b8..491b35d4 100644 --- a/test_pool/gic/g010.c +++ b/test_pool/gic/g010.c @@ -37,7 +37,7 @@ isr_phy() /* We received our interrupt, so disable timer from generating further interrupts */ val_timer_set_phy_el2(0); val_print(TRACE, "\n Received phy el2 interrupt "); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -54,7 +54,7 @@ payload() if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { val_print(DEBUG, "\n Skipping. Test accesses EL2" " Registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -67,13 +67,13 @@ payload() if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) { val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI base range, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } if (val_gic_install_isr(intid, isr_phy)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -85,7 +85,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n EL2-Phy timer interrupt not received on INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); } return; } diff --git a/test_pool/gic/g011.c b/test_pool/gic/g011.c index be4679a5..e36bd083 100644 --- a/test_pool/gic/g011.c +++ b/test_pool/gic/g011.c @@ -43,8 +43,8 @@ isr_mnt() data &= ~0x7; val_gic_reg_write(ICH_HCR_EL2, data); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); val_print(TRACE, "\n Received GIC maintenance interrupt "); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -61,7 +61,7 @@ payload() if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { val_print(DEBUG, "\n Skipping. Test accesses EL2" " Registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -75,13 +75,13 @@ payload() val_print(DEBUG, "\n GIC Maintenance interrupt not mapped to PPI base range," "\n INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } if (val_gic_install_isr(intid, isr_mnt)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -97,7 +97,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n Interrupt not received within timeout"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } return; diff --git a/test_pool/gic/g012.c b/test_pool/gic/g012.c index 3a720905..e4b54e40 100644 --- a/test_pool/gic/g012.c +++ b/test_pool/gic/g012.c @@ -42,11 +42,11 @@ payload(void) val_print(ERROR, "\n GIC version is %3x, expected GICv3 or higher version", gic_version); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/gic/g013.c b/test_pool/gic/g013.c index b36175e5..e0280874 100644 --- a/test_pool/gic/g013.c +++ b/test_pool/gic/g013.c @@ -42,8 +42,8 @@ payload() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -51,8 +51,8 @@ payload() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(02)); return; } } @@ -60,8 +60,8 @@ payload() intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -69,8 +69,8 @@ payload() intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(04)); return; } @@ -78,8 +78,8 @@ payload() intid = val_pe_get_gmain_gsiv(index); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(05)); return; } @@ -87,12 +87,12 @@ payload() intid = val_pe_get_pmu_gsiv(index); if (IS_PPI_RESERVED(intid)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 06)); val_print(ERROR, "\n Interrupt ID is reserved for future SBSA usage "); + val_set_status(index, RESULT_FAIL(06)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/gic/g014.c b/test_pool/gic/g014.c index bdd6a1e9..285a46bf 100644 --- a/test_pool/gic/g014.c +++ b/test_pool/gic/g014.c @@ -42,7 +42,7 @@ static void payload(void) if (intid != 30) { val_print(ERROR, "\n EL0-Phy timer not mapped to PPI ID 30, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -51,7 +51,7 @@ static void payload(void) if (intid != 27) { val_print(ERROR, "\n EL0-Virtual timer not mapped to PPI ID 27, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -59,7 +59,7 @@ static void payload(void) if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { val_print(DEBUG, "\n Skipping. Test accesses EL2" " Registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -70,7 +70,7 @@ static void payload(void) * ID_AA64MMFR1_EL1 VH, bits [11:8] must be 0x1 */ if (!((data >> 8) & 0xF)) { val_print(DEBUG, "\n v8.1 VHE not supported on this PE "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -81,7 +81,7 @@ static void payload(void) if (intid != 28) { val_print(ERROR, "\n NS EL2 virtual timer not mapped to PPI ID 28, id %d", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -92,7 +92,7 @@ static void payload(void) if (intid != 26) { val_print(DEBUG, "\n NS EL2 physical timer not mapped to PPI id 26, INTID: %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -103,11 +103,11 @@ static void payload(void) if (intid != 25) { val_print(ERROR, "\n GIC Maintenance interrupt not mapped to PPI ID 25, id %d", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/gic/g015.c b/test_pool/gic/g015.c index a8e85df9..275f5215 100644 --- a/test_pool/gic/g015.c +++ b/test_pool/gic/g015.c @@ -44,7 +44,7 @@ payload(void) if (gic_version < 4) { val_print(ERROR, "\n Expected GICv4 or higher major version", gic_version); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -66,12 +66,12 @@ payload(void) { val_print(TRACE, "\n Interrupt controller is compliant with Gicv4.1 or higher"); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } } - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } diff --git a/test_pool/gic/g016.c b/test_pool/gic/g016.c index eb64f9f6..e61292a3 100644 --- a/test_pool/gic/g016.c +++ b/test_pool/gic/g016.c @@ -36,11 +36,11 @@ payload(void) val_print(DEBUG, "\n Non GIC Interrupt count: %d", num_non_gic); if (num_non_gic > 0) { val_print(ERROR, "\n Non GIC Interrupt found"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/gic/its001.c b/test_pool/gic/its001.c index aa3d2661..ffd860c8 100644 --- a/test_pool/gic/its001.c +++ b/test_pool/gic/its001.c @@ -32,13 +32,13 @@ payload() status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status) { val_print(ERROR, "\n ITS get group number failed "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } if (!num_group) { val_print(DEBUG, "\n No ITS group found "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } val_print(DEBUG, "\n Number of ITS groups = %d", num_group); @@ -46,18 +46,18 @@ payload() status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks); if (status) { val_print(ERROR, "\n ITS get number of blocks failed "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); return; } if (!num_blocks) { val_print(ERROR, "\n No valid ITS Blocks found in group %d ", i); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(2)); + val_set_status(index, RESULT_FAIL(3)); return; } val_print(DEBUG, "\n Number of ITS Blocks = %d " " ", num_blocks); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/its002.c b/test_pool/gic/its002.c index b87b1697..81613c28 100644 --- a/test_pool/gic/its002.c +++ b/test_pool/gic/its002.c @@ -33,12 +33,12 @@ payload() status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group); if (status) { val_print(ERROR, "\n ITS get group number failed "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); return; } if (!num_group) { val_print(DEBUG, "\n No ITS group found "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -48,13 +48,13 @@ payload() status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks); if (status) { val_print(ERROR, "\n ITS get number of blocks failed "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } if (!num_blocks) { val_print(ERROR, "\n No valid ITS Blocks found in group %d ", i); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } val_print(DEBUG, "\n ITS group index = %d", i); @@ -64,7 +64,7 @@ payload() status = val_iovirt_get_its_info(ITS_GET_ID_FOR_BLK_INDEX, i, j, &its_id); if (status) { val_print(ERROR, "\n ITS get id failed "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -76,13 +76,13 @@ payload() if (status != ACS_INVALID_INDEX) { val_print(ERROR, "\n ITS ID (%d) repeated in multiple groups", its_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/its003.c b/test_pool/gic/its003.c index 10d8114d..d91dbbf6 100644 --- a/test_pool/gic/its003.c +++ b/test_pool/gic/its003.c @@ -49,13 +49,13 @@ payload() if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { val_print(DEBUG, "\n No entries in BDF table"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } if (val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0) == 0) { val_print(DEBUG, "\n No SMMU, Skipping Test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); return; } @@ -63,7 +63,7 @@ payload() streamID = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!streamID) { val_print(DEBUG, "\n Stream ID memory allocation failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -71,7 +71,7 @@ payload() smmu_index = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!smmu_index) { val_print(DEBUG, "\n Smmu index memory allocation failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -79,7 +79,7 @@ payload() dev_bdf = val_aligned_alloc(MEM_ALIGN_4K, bdf_tbl_ptr->num_entries * sizeof(uint32_t)); if (!dev_bdf) { val_print(DEBUG, "\n Dev BDF memory allocation failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); return; } @@ -111,7 +111,7 @@ payload() if (status) { val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); /* Free allocated memory before return*/ val_memory_free_aligned(streamID); val_memory_free_aligned(smmu_index); @@ -172,11 +172,11 @@ payload() val_memory_free_aligned(dev_bdf); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_SKIP(3)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(pe_index, RESULT_FAIL(5)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/its004.c b/test_pool/gic/its004.c index b9d14566..740b9021 100644 --- a/test_pool/gic/its004.c +++ b/test_pool/gic/its004.c @@ -46,7 +46,7 @@ payload() bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { val_print(DEBUG, "\n No entries in BDF table"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -69,7 +69,7 @@ payload() &stream_id, &its_id); if (status) { val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -121,11 +121,11 @@ payload() } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/its005.c b/test_pool/gic/its005.c index 2eae2c34..0d4f73be 100644 --- a/test_pool/gic/its005.c +++ b/test_pool/gic/its005.c @@ -46,7 +46,7 @@ payload() bdf_tbl_ptr = val_pcie_bdf_table_ptr(); if ((!bdf_tbl_ptr) || (!bdf_tbl_ptr->num_entries)) { val_print(DEBUG, "\n No entries in BDF table"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -69,7 +69,7 @@ payload() &stream_id, &its_id); if (status) { val_print(DEBUG, "\n Could not get device info for BDF : 0x%x", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -104,11 +104,11 @@ payload() } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/v2m001.c b/test_pool/gic/v2m001.c index 1e62ff8f..f832432f 100644 --- a/test_pool/gic/v2m001.c +++ b/test_pool/gic/v2m001.c @@ -39,7 +39,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { val_print(DEBUG, "\n No MSI frame, Skipping "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -58,7 +58,7 @@ payload() /* Read GICD_ICFGR register to Check for Level/Edge Sensitive. */ status = val_gic_get_intr_trigger_type(spi_id, &trigger_type); if (status) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -71,17 +71,17 @@ payload() if (test_skip) { val_print(WARN, "\n No SPI Information Found. Skipping "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } if (fail_cnt) { val_print(ERROR, "\n SPI Trigger Type Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/v2m002.c b/test_pool/gic/v2m002.c index de5a7a2a..77d14fa5 100644 --- a/test_pool/gic/v2m002.c +++ b/test_pool/gic/v2m002.c @@ -38,7 +38,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { val_print(DEBUG, "\n No MSI frame, Skipping "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -84,11 +84,11 @@ payload() if (fail_cnt) { val_print(ERROR, "\n MSI_TYPER Register Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/gic/v2m003.c b/test_pool/gic/v2m003.c index 33219fa8..2e140ffd 100644 --- a/test_pool/gic/v2m003.c +++ b/test_pool/gic/v2m003.c @@ -32,7 +32,7 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_print(TRACE, "\n Received SPI "); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(int_id); return; @@ -53,7 +53,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { val_print(DEBUG, "\n No MSI frame, Skipping "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -68,7 +68,7 @@ payload() /* Register an interrupt handler to verify */ if (val_gic_install_isr(int_id, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -82,7 +82,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n Interrupt not received within timeout"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -96,7 +96,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n Interrupt not received within timeout"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } diff --git a/test_pool/gic/v2m004.c b/test_pool/gic/v2m004.c index 2f2c9e05..baaef433 100644 --- a/test_pool/gic/v2m004.c +++ b/test_pool/gic/v2m004.c @@ -32,7 +32,7 @@ isr() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_print(TRACE, "\n Received SPI "); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(int_id); return; @@ -55,7 +55,7 @@ payload() msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME); if (msi_frame == 0) { val_print(DEBUG, "\n No MSI frame, Skipping "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -70,7 +70,7 @@ payload() /* Register an interrupt handler to verify */ if (val_gic_install_isr(int_id, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -91,7 +91,7 @@ payload() /* If the Status is changed that means interrupt handler is called & test is failed. */ if (timeout != 0) { val_print(ERROR, "\n Interrupt generated by GICD registers"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -105,7 +105,7 @@ payload() if (timeout == 0) { val_print(ERROR, "\n Interrupt not received within timeout"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } diff --git a/test_pool/memory_map/m001.c b/test_pool/memory_map/m001.c index 2c293bb2..3998e523 100644 --- a/test_pool/memory_map/m001.c +++ b/test_pool/memory_map/m001.c @@ -43,7 +43,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(TRACE, "\n Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } static @@ -61,7 +61,7 @@ payload() val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); /* If we don't find a single un-populated address, mark this test as skipped */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); while (loop_var) { /* Get the base address of unpopulated region */ @@ -81,7 +81,7 @@ payload() if (val_memory_get_info(addr, &attr) == MEM_TYPE_NOT_POPULATED) { /* default value of FAIL, Pass is set in the exception handler */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); branch_to_test = &&exception_taken; diff --git a/test_pool/memory_map/m002.c b/test_pool/memory_map/m002.c index 1b177bcb..49957820 100644 --- a/test_pool/memory_map/m002.c +++ b/test_pool/memory_map/m002.c @@ -56,7 +56,7 @@ payload() val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); if (g_el1skiptrap_mask & EL1SKIPTRAP_DEVMEM) { val_print(DEBUG, @@ -83,7 +83,7 @@ payload() {}; exception_taken_d: - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); loop_var--; instance++; } @@ -109,7 +109,7 @@ payload() {}; exception_taken_n: - val_set_status(index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(index, RESULT_PASS); loop_var--; instance++; } diff --git a/test_pool/memory_map/m003.c b/test_pool/memory_map/m003.c index 7241589b..acf55822 100644 --- a/test_pool/memory_map/m003.c +++ b/test_pool/memory_map/m003.c @@ -46,7 +46,7 @@ static uint64_t check_number_of_bits(uint32_t index, uint64_t data) return ((uint64_t)0x1 << (int)52); else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return 0; } } @@ -68,11 +68,11 @@ payload() if (addr < value) { /* PE can access the Non-Secure address space*/ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } diff --git a/test_pool/memory_map/m004.c b/test_pool/memory_map/m004.c index 1873d68e..990f8e59 100644 --- a/test_pool/memory_map/m004.c +++ b/test_pool/memory_map/m004.c @@ -45,7 +45,7 @@ check_peripheral_dma_capability (void) if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { val_print(DEBUG, "\n Skip as no peripherals detected "); - val_set_status(index, RESULT_SKIP (TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -63,9 +63,9 @@ check_peripheral_dma_capability (void) } if (fail_cnt) { - val_set_status (index, RESULT_FAIL (TEST_NUM, 01)); + val_set_status (index, RESULT_FAIL(01)); } else { - val_set_status (index, RESULT_PASS (TEST_NUM, 01)); + val_set_status (index, RESULT_PASS); } } @@ -85,7 +85,7 @@ payload_check_dev_dma_if_behind_smmu (void) if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { val_print(DEBUG, "\n Skip as no peripherals detected "); - val_set_status(index, RESULT_SKIP (TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -105,11 +105,11 @@ payload_check_dev_dma_if_behind_smmu (void) } if (!test_run) { - val_set_status (index, RESULT_SKIP (TEST_NUM1, 02)); + val_set_status (index, RESULT_SKIP(02)); } else if (fail_cnt) { - val_set_status (index, RESULT_FAIL (TEST_NUM1, 01)); + val_set_status (index, RESULT_FAIL(01)); } else { - val_set_status (index, RESULT_PASS (TEST_NUM1, 01)); + val_set_status (index, RESULT_PASS); } } @@ -128,7 +128,7 @@ payload_check_if_non_dma_dev_behind_smmu (void) if (pcie_peripherals_bdf_list == NULL || pcie_peripherals_bdf_list->count == 0) { val_print(DEBUG, "\n Skip as no peripherals detected "); - val_set_status(index, RESULT_SKIP (TEST_NUM2, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -150,11 +150,11 @@ payload_check_if_non_dma_dev_behind_smmu (void) } if (!test_run) { - val_set_status (index, RESULT_SKIP (TEST_NUM2, 02)); + val_set_status (index, RESULT_SKIP(02)); } else if (fail_cnt) { - val_set_status (index, RESULT_FAIL (TEST_NUM2, 01)); + val_set_status (index, RESULT_FAIL(01)); } else { - val_set_status (index, RESULT_PASS (TEST_NUM2, 01)); + val_set_status (index, RESULT_PASS); } } diff --git a/test_pool/memory_map/m005.c b/test_pool/memory_map/m005.c index 21d05ca1..88e5215e 100644 --- a/test_pool/memory_map/m005.c +++ b/test_pool/memory_map/m005.c @@ -46,7 +46,7 @@ static void payload_check_s2_64kb_granule_support(void) if (data == 0) { val_print(DEBUG, "\n EL2 not implemented, Skipping the test."); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -56,11 +56,11 @@ static void payload_check_s2_64kb_granule_support(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 36, 39); if (data != 0x2) { val_print(ERROR, "\n 64KB granule not supported at stage 2."); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -78,7 +78,7 @@ static void payload_check_peripheral_addr_64kb_apart(void) if (peri_count < 2) { val_print(DEBUG, "\n No or one peripherals reported by the system."); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM1, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -107,9 +107,9 @@ static void payload_check_peripheral_addr_64kb_apart(void) } if (fail_cnt) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } else { - val_set_status(pe_index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(pe_index, RESULT_PASS); } } diff --git a/test_pool/mpam/error001.c b/test_pool/mpam/error001.c index 502f1e46..365fb21d 100644 --- a/test_pool/mpam/error001.c +++ b/test_pool/mpam/error001.c @@ -51,7 +51,7 @@ static void payload(void) status = val_mpam_msc_reset_errcode(index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -83,11 +83,11 @@ static void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error002.c b/test_pool/mpam/error002.c index 3df10fb0..d9cc7cd0 100644 --- a/test_pool/mpam/error002.c +++ b/test_pool/mpam/error002.c @@ -57,7 +57,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -95,11 +95,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error003.c b/test_pool/mpam/error003.c index 122b9b43..50067450 100644 --- a/test_pool/mpam/error003.c +++ b/test_pool/mpam/error003.c @@ -54,7 +54,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -102,11 +102,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error004.c b/test_pool/mpam/error004.c index 6a97e432..a4ca9d1a 100644 --- a/test_pool/mpam/error004.c +++ b/test_pool/mpam/error004.c @@ -57,7 +57,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -95,11 +95,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error005.c b/test_pool/mpam/error005.c index 323e09e9..88d2e1a2 100644 --- a/test_pool/mpam/error005.c +++ b/test_pool/mpam/error005.c @@ -79,7 +79,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -108,11 +108,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error006.c b/test_pool/mpam/error006.c index 293f9b0c..af0711e7 100644 --- a/test_pool/mpam/error006.c +++ b/test_pool/mpam/error006.c @@ -62,7 +62,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -104,11 +104,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error007.c b/test_pool/mpam/error007.c index 4769664d..174b5ab0 100644 --- a/test_pool/mpam/error007.c +++ b/test_pool/mpam/error007.c @@ -62,7 +62,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -102,11 +102,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error008.c b/test_pool/mpam/error008.c index 51acca89..625881e1 100644 --- a/test_pool/mpam/error008.c +++ b/test_pool/mpam/error008.c @@ -88,7 +88,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -132,11 +132,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error009.c b/test_pool/mpam/error009.c index aa4548e9..e00cc05e 100644 --- a/test_pool/mpam/error009.c +++ b/test_pool/mpam/error009.c @@ -152,7 +152,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -182,11 +182,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error010.c b/test_pool/mpam/error010.c index a8fb769e..7309e1a8 100644 --- a/test_pool/mpam/error010.c +++ b/test_pool/mpam/error010.c @@ -94,7 +94,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -137,11 +137,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error011.c b/test_pool/mpam/error011.c index 15787730..2920017f 100644 --- a/test_pool/mpam/error011.c +++ b/test_pool/mpam/error011.c @@ -147,7 +147,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -177,11 +177,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error012.c b/test_pool/mpam/error012.c index c25e4404..e08fc852 100644 --- a/test_pool/mpam/error012.c +++ b/test_pool/mpam/error012.c @@ -66,7 +66,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { val_print(DEBUG, "\n Error Code Reset Failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -93,7 +93,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { val_print(DEBUG, "\n Error Code Reset Failed after RIS"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -122,11 +122,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/error013.c b/test_pool/mpam/error013.c index 078aa5d0..964c83b2 100644 --- a/test_pool/mpam/error013.c +++ b/test_pool/mpam/error013.c @@ -67,7 +67,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -164,11 +164,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t error013_entry(void) diff --git a/test_pool/mpam/error014.c b/test_pool/mpam/error014.c index 5c8bdd68..941ef925 100644 --- a/test_pool/mpam/error014.c +++ b/test_pool/mpam/error014.c @@ -57,7 +57,7 @@ payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -147,11 +147,11 @@ payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/feat001.c b/test_pool/mpam/feat001.c index cc10c0f9..95e54146 100644 --- a/test_pool/mpam/feat001.c +++ b/test_pool/mpam/feat001.c @@ -78,7 +78,7 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n LLC not present, Skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -86,7 +86,7 @@ payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { val_print(DEBUG, "\n Invalid LLC ID, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -172,7 +172,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_aligned(dest_buf); if (src_buf != NULL) @@ -210,7 +210,7 @@ payload(void) /* Free the buffers to the heap manager */ val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -270,7 +270,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -331,7 +331,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } @@ -384,11 +384,11 @@ payload(void) } if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); else if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/intr001.c b/test_pool/mpam/intr001.c index ec00fae7..4884870d 100644 --- a/test_pool/mpam/intr001.c +++ b/test_pool/mpam/intr001.c @@ -41,7 +41,7 @@ esr(uint64_t exception_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(WARN, "\n Received Exception of type %d", exception_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); } static void intr_handler(void) @@ -49,7 +49,7 @@ static void intr_handler(void) uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); val_print(DEBUG, "\n Received MSC Err interrupt %d", intr_num); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); /* Restore Error Control Register original settings */ val_mpam_mmr_write(msc_index, REG_MPAMF_ECR, mpamf_ecr_saved); @@ -100,7 +100,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -118,7 +118,7 @@ void payload(void) /* Register the interrupt handler */ if (val_gic_install_isr(intr_num, intr_handler)) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -140,18 +140,18 @@ void payload(void) val_mpam_mmr_write(msc_index, REG_MPAMF_ECR, mpamf_ecr_saved); if (timeout == 0) { val_print(ERROR, "\n MSC Err Interrupt not received on %d", intr_num); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } } /* Set the test status to Skip as none of the MPAM nodes implemented error interrupts */ if (intr_count == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_PASS); return; exception_taken: diff --git a/test_pool/mpam/intr002.c b/test_pool/mpam/intr002.c index 3c879c61..9ae86900 100644 --- a/test_pool/mpam/intr002.c +++ b/test_pool/mpam/intr002.c @@ -40,7 +40,7 @@ esr(uint64_t exception_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(WARN, "\n Received Exception of type %d", exception_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(index, RESULT_FAIL(05)); } static void intr_handler(void) @@ -48,7 +48,7 @@ static void intr_handler(void) uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); val_print(ERROR, "\n Received unexpected edge-trigger interrupt %d", intr_num); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); /* Write 0b0000 into MPAMF_ESR.ERRCODE to clear the interrupt */ val_mpam_msc_reset_errcode(msc_index); @@ -97,7 +97,7 @@ void payload(void) status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -115,7 +115,7 @@ void payload(void) /* Register the interrupt handler */ if (val_gic_install_isr(intr_num, intr_handler) == ACS_STATUS_ERR) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -137,18 +137,18 @@ void payload(void) val_mpam_mmr_write(msc_index, REG_MPAMF_ECR, mpamf_ecr); if (timeout && (!IS_RESULT_PENDING(val_get_status(pe_index)))) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } } /* Set the test status to Skip as none of the MPAM nodes implemented error interrupts */ if (intr_count == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; exception_taken: diff --git a/test_pool/mpam/intr003.c b/test_pool/mpam/intr003.c index 9ffa7210..44b17689 100644 --- a/test_pool/mpam/intr003.c +++ b/test_pool/mpam/intr003.c @@ -37,7 +37,7 @@ void intr_handler(void) uint32_t ctl; val_print(DEBUG, "\n Received Oflow error interrupt %d ", intr_num); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); ctl = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); ctl &= ~(((uint32_t)1 << MBWU_CTL_OFLOW_STATUS_BIT_SHIFT) | @@ -129,7 +129,7 @@ void payload(void) /* Register the interrupt handler */ status = val_gic_install_isr(intr_num, intr_handler); if (status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -150,7 +150,7 @@ void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation for buffers failed", 0x0); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -193,7 +193,7 @@ void payload(void) if (isr_completion_flag == 0) { val_print(ERROR, "\n MSC MSMON Oflow Err Interrupt not received on %d", intr_num); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -205,7 +205,7 @@ void payload(void) (((esr_value >> ESR_OVRWR_SHIFT) & ESR_OVRWR_MASK) != 0)) { val_print(ERROR, "\n MPAMF_ESR.ERRCODE/OVRWR is not cleared by ISR for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -217,11 +217,11 @@ void payload(void) /* Set the test status to Skip if none of the MPAM nodes implement error interrupts */ if (intr_count == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/intr004.c b/test_pool/mpam/intr004.c index 26a504e3..4117985c 100644 --- a/test_pool/mpam/intr004.c +++ b/test_pool/mpam/intr004.c @@ -121,16 +121,16 @@ void intr_handler(void) if (!status_l_asserted) { val_print(ERROR, "\n OFLOW_STATUS_L not set on overflow interrupt for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); } else { val_print(DEBUG, "\n OFLOW_STATUS_L observed set on interrupt for MSC %d", msc_index); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); if (val_mpam_mbwu_clear_overflow_status(msc_index)) { val_print(ERROR, "\n Failed to clear overflow status via helper for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); } } @@ -246,7 +246,7 @@ void payload(void) if (status) { val_print(ERROR, "\n Failed to configure overflow interrupt for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); test_fail++; goto monitor_cleanup; } @@ -310,11 +310,11 @@ void payload(void) val_mpam_reg_write(MPAM2_EL2, mpam2_el2_saved); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail || !intr_enabled) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_PASS); } uint32_t intr004_entry(void) diff --git a/test_pool/mpam/intr005.c b/test_pool/mpam/intr005.c index 8453ec20..860ef616 100644 --- a/test_pool/mpam/intr005.c +++ b/test_pool/mpam/intr005.c @@ -107,16 +107,16 @@ void intr_handler(void) if (!status_asserted) { val_print(ERROR, "\n OFLOW_STATUS not set on overflow MSI for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); } else { val_print(DEBUG, "\n OFLOW_STATUS observed set on MSI for MSC %d", msc_index); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); if (val_mpam_mbwu_clear_overflow_status(msc_index)) { val_print(ERROR, "\n Failed to clear overflow status via helper for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 07)); + val_set_status(pe_index, RESULT_FAIL(07)); } } @@ -263,7 +263,7 @@ void payload(void) if (status) { val_print(ERROR, "\n Failed to configure overflow MSI for MSC %d", msc_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 06)); + val_set_status(pe_index, RESULT_FAIL(06)); test_fail++; goto monitor_cleanup; } @@ -325,11 +325,11 @@ void payload(void) val_mpam_reg_write(MPAM2_EL2, mpam2_el2_saved); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail || !intr_enabled) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t intr005_entry(void) diff --git a/test_pool/mpam/intr006.c b/test_pool/mpam/intr006.c index b4cef9bf..2f5c5db1 100644 --- a/test_pool/mpam/intr006.c +++ b/test_pool/mpam/intr006.c @@ -77,10 +77,10 @@ void intr_handler(void) "\n Expected errcode: %d", ESR_ERRCODE_UNDEF_RIS_MON_SEL); val_print(ERROR, "\n Actual errcode: %d", errcode); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); } else { errcode_valid = 1; - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } /* Stop further ERR_MSI assertions once handled */ @@ -179,7 +179,7 @@ void payload(void) /* Ensure a clean error state before injecting a new error. */ status = val_mpam_msc_reset_errcode(msc_index); if (!status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); test_fail++; break; } @@ -252,11 +252,11 @@ void payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t intr006_entry(void) diff --git a/test_pool/mpam/mem001.c b/test_pool/mpam/mem001.c index 3e3d92af..6c45481f 100644 --- a/test_pool/mpam/mem001.c +++ b/test_pool/mpam/mem001.c @@ -140,7 +140,7 @@ void payload(void) /* Skip this test if no MBWPBM supported MSC present in the system */ if (mbwpbm_node_cnt == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -236,14 +236,14 @@ void payload(void) buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * buf_size)) { /* src and dst buffer size */ val_print(ERROR, "\n No SRAT mem range info found"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -255,7 +255,7 @@ void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Memory allocation of buffers failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -265,7 +265,7 @@ void payload(void) if (!val_mpam_get_mbwumon_count(msc_index)) { val_print(INFO, "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_SKIP(03)); return; } @@ -336,7 +336,7 @@ void payload(void) > counter[index-1][msc_index][rsrc_index]) { val_print(ERROR, "\n Failed for msc_index : %d", msc_index); val_print(ERROR, "\n cfg_index : %d", index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } } @@ -344,7 +344,7 @@ void payload(void) } } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/mem002.c b/test_pool/mpam/mem002.c index 1947a668..8d406322 100644 --- a/test_pool/mpam/mem002.c +++ b/test_pool/mpam/mem002.c @@ -46,7 +46,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } @@ -159,7 +159,7 @@ void static payload_secondary() dest_buf = src_buf + buf_size; if ((src_buf == NULL) || (dest_buf == NULL)) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2); @@ -176,7 +176,7 @@ void static payload_secondary() /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } @@ -261,7 +261,7 @@ payload_primary(void) if (mbwmin_node_cnt == 0) { val_print(INFO, "\n %d MSC Memory Nodes support MBW Min Limit Partitioning", mbwmin_node_cnt); - val_set_status(primary_pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(primary_pe_index, RESULT_SKIP(01)); return; } @@ -278,7 +278,7 @@ payload_primary(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(primary_pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(primary_pe_index, RESULT_FAIL(03)); return; } @@ -319,7 +319,7 @@ payload_primary(void) num_pe_cont); if (alloc_status == 0) { - val_set_status(primary_pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(primary_pe_index, RESULT_FAIL(04)); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); return; } @@ -352,7 +352,7 @@ payload_primary(void) if (!val_mpam_get_mbwumon_count(msc_index)) { val_print(INFO, "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); contend_flag = 0; return; } @@ -478,7 +478,7 @@ payload_primary(void) if (counter[msc_index][rsrc_index][scenario_cnt] < counter[msc_index][rsrc_index][scenario_cnt + 1]) { val_print(ERROR, "\n Failed for msc_index : %d", msc_index); - val_set_status(primary_pe_index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(primary_pe_index, RESULT_FAIL(05)); return; } } @@ -486,7 +486,7 @@ payload_primary(void) } /* Set the test status to pass */ - val_set_status(primary_pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(primary_pe_index, RESULT_PASS); return; diff --git a/test_pool/mpam/mem003.c b/test_pool/mpam/mem003.c index 0e349b85..f3704b1c 100644 --- a/test_pool/mpam/mem003.c +++ b/test_pool/mpam/mem003.c @@ -139,7 +139,7 @@ void payload(void) /* Skip this test if no MBWMAX supported MSC present in the system */ if (mbwmax_node_cnt == 0) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -235,14 +235,14 @@ void payload(void) buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * buf_size)) { /* src and dst buffer size */ val_print(ERROR, "\n No SRAT mem range info found"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -254,7 +254,7 @@ void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Memory allocation of buffers failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -264,7 +264,7 @@ void payload(void) if (!val_mpam_get_mbwumon_count(msc_index)) { val_print(INFO, "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_SKIP(03)); return; } @@ -335,7 +335,7 @@ void payload(void) > counter[index-1][msc_index][rsrc_index]) { val_print(ERROR, "\n Failed for msc_index : %d", msc_index); val_print(ERROR, "\n cfg_index : %d", index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } } @@ -343,7 +343,7 @@ void payload(void) } } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor001.c b/test_pool/mpam/monitor001.c index 97ae13ed..f737be93 100644 --- a/test_pool/mpam/monitor001.c +++ b/test_pool/mpam/monitor001.c @@ -62,7 +62,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -70,7 +70,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -114,7 +114,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if (csumon_count == 0 || cpor_nodes == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -188,7 +188,7 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -256,7 +256,7 @@ static void payload(void) /* Test fails if storage_value1 is zero or storage_value2 is non zero */ if (!storage_value1 || storage_value2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); /*Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -293,7 +293,7 @@ static void payload(void) } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor002.c b/test_pool/mpam/monitor002.c index ae10514f..3ce84c5f 100644 --- a/test_pool/mpam/monitor002.c +++ b/test_pool/mpam/monitor002.c @@ -62,7 +62,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -70,7 +70,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -114,7 +114,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if (csumon_count == 0 || ccap_nodes == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -188,7 +188,7 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (src_buf != NULL) val_pe_cache_invalidate_range((uint64_t)src_buf, buf_size); if (src_buf != NULL) @@ -264,7 +264,7 @@ static void payload(void) /* Test fails if storage_value1 is zero or storage_value2 is non zero */ if (!storage_value1 || storage_value2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); /*Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -301,7 +301,7 @@ static void payload(void) } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor003.c b/test_pool/mpam/monitor003.c index 3817faa8..23cd5b9e 100644 --- a/test_pool/mpam/monitor003.c +++ b/test_pool/mpam/monitor003.c @@ -61,7 +61,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -69,7 +69,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -108,7 +108,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if (csumon_count == 0 || cpor_nodes == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -182,12 +182,13 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); return; + } /* Configure CSU monitors with partid1 */ @@ -250,7 +251,7 @@ static void payload(void) /* Test fails if storage_value1 is zero or storage_value2 is non zero */ if (!storage_value1 || storage_value2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); /*Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -287,7 +288,7 @@ static void payload(void) } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor004.c b/test_pool/mpam/monitor004.c index 060e73ee..a9df6e7e 100644 --- a/test_pool/mpam/monitor004.c +++ b/test_pool/mpam/monitor004.c @@ -60,7 +60,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -68,7 +68,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -107,7 +107,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if (csumon_count == 0 || ccap_nodes == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -182,12 +182,13 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); return; + } /* Configure CSU monitors with partid1 */ @@ -250,7 +251,7 @@ static void payload(void) /* Test fails if storage_value1 is zero or storage_value2 is non zero */ if (!storage_value1 || storage_value2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); /*Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -287,7 +288,7 @@ static void payload(void) } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor005.c b/test_pool/mpam/monitor005.c index 2bf668ec..3d02b866 100644 --- a/test_pool/mpam/monitor005.c +++ b/test_pool/mpam/monitor005.c @@ -56,7 +56,7 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n No LLC found, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -64,7 +64,7 @@ payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { val_print(DEBUG, "\n Invalid LLC ID, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -131,7 +131,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); if (dest_buf != NULL) @@ -163,7 +163,7 @@ payload(void) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -226,11 +226,11 @@ payload(void) } if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); else if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor006.c b/test_pool/mpam/monitor006.c index 78be64cd..423d5bbe 100644 --- a/test_pool/mpam/monitor006.c +++ b/test_pool/mpam/monitor006.c @@ -183,11 +183,11 @@ payload(void) val_mem_free_at_address((uint64_t)dest_buf, buf_size); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor007.c b/test_pool/mpam/monitor007.c index 7d596dfc..5e5b6280 100644 --- a/test_pool/mpam/monitor007.c +++ b/test_pool/mpam/monitor007.c @@ -269,11 +269,11 @@ payload(void) val_mem_free_at_address((uint64_t)dest_buf, buf_size); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/monitor008.c b/test_pool/mpam/monitor008.c index 348548c3..43292e16 100644 --- a/test_pool/mpam/monitor008.c +++ b/test_pool/mpam/monitor008.c @@ -276,11 +276,11 @@ payload(void) val_mem_free_at_address((uint64_t)src_buf, buf_size); if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/mpam001.c b/test_pool/mpam/mpam001.c index 3fd3ce00..664e509b 100644 --- a/test_pool/mpam/mpam001.c +++ b/test_pool/mpam/mpam001.c @@ -48,11 +48,11 @@ static void payload_check_mpam_ext_support(void) /* PEs must implement FEAT_MPAM */ if (!is_feat_mpam_implemented()) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } static void payload_check_mpam_part_id_count(void) @@ -65,7 +65,7 @@ static void payload_check_mpam_part_id_count(void) /* Initial check: FEAT_MPAM must be implemented before accessing MPAMIDR_EL1 */ if (!is_feat_mpam_implemented()) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -76,14 +76,14 @@ static void payload_check_mpam_part_id_count(void) must be >= 16 */ data = VAL_EXTRACT_BITS(mpamidr_val, 0, 15); if (data < 16) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM1, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } /* check support for MPAM virtulization support indicated by MPAMIDR_EL1.HAS_HCR bit */ data = VAL_EXTRACT_BITS(mpamidr_val, 17, 17); if (data == 0) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM1, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } @@ -91,11 +91,11 @@ static void payload_check_mpam_part_id_count(void) MPAMIDR_EL1.VPMR_MAX must be > 0 */ data = VAL_EXTRACT_BITS(mpamidr_val, 18, 20); if (data < 1) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM1, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t mpam001_entry(uint32_t num_pe) diff --git a/test_pool/mpam/mpam002.c b/test_pool/mpam/mpam002.c index c6cdad4b..4e60d297 100644 --- a/test_pool/mpam/mpam002.c +++ b/test_pool/mpam/mpam002.c @@ -111,23 +111,33 @@ static void payload_check_mpam_llc_csu_support(void) uint32_t llc_msc_index; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + /* Check if PE implements FEAT_MPAM */ + /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0 + indicates implementation of MPAM extension */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(01)); + val_print(DEBUG, "\n FEAT_MPAM not supported by PE"); + return; + } + /* Get MPAM msc_index of LLC cache */ llc_msc_index = get_llc_msc_index(); /* Check if msc_index in valid, else mark test as FAIL */ if (llc_msc_index == LLC_MSC_INDEX_UNKNOWN) { val_print(ERROR, "\n MSC on LLC not found "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } /* Check if LLC supports CSU monitor */ if (!val_mpam_supports_csumon(llc_msc_index)) { val_print(ERROR, "\n CSU MON unsupported by LLC"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } @@ -139,13 +149,23 @@ static void payload_check_llc_csu_mon_count(void) uint32_t csumon_count; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + /* Check if PE implements FEAT_MPAM */ + /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0 + indicates implementation of MPAM extension */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(01)); + val_print(DEBUG, "\n FEAT_MPAM not supported by PE"); + return; + } + /* Get MPAM msc_index of LLC cache */ llc_msc_index = get_llc_msc_index(); /* Check if msc_index in valid, else mark test as FAIL */ if (llc_msc_index == LLC_MSC_INDEX_UNKNOWN) { val_print(ERROR, "\n MSC on LLC not found "); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -153,10 +173,10 @@ static void payload_check_llc_csu_mon_count(void) csumon_count = val_mpam_get_csumon_count(llc_msc_index); if (csumon_count < 16) { val_print(ERROR, "\n CSU MON %d less than 16", csumon_count); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } else { - val_set_status(index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(index, RESULT_PASS); return; } } diff --git a/test_pool/mpam/mpam003.c b/test_pool/mpam/mpam003.c index 2222c5e3..573bd561 100644 --- a/test_pool/mpam/mpam003.c +++ b/test_pool/mpam/mpam003.c @@ -51,7 +51,7 @@ static void payload(void) /* Check if PE implements FEAT_MPAM */ if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -61,7 +61,7 @@ static void payload(void) val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (!msc_node_cnt) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -112,7 +112,7 @@ static void payload(void) if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || (addr_len <= 2 * BUFFER_SIZE)) { /* src and dst buffer size */ val_print(ERROR, "\n No SRAT mem range info found"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -125,7 +125,7 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Memory allocation of buffers failed"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -180,11 +180,11 @@ static void payload(void) val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(pe_index, RESULT_FAIL(05)); else if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/mpam004.c b/test_pool/mpam/mpam004.c index a7beac5d..32de3034 100644 --- a/test_pool/mpam/mpam004.c +++ b/test_pool/mpam/mpam004.c @@ -44,7 +44,7 @@ static void payload(void) /* Check if PE implements FEAT_MPAM */ if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } @@ -53,7 +53,7 @@ static void payload(void) val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (!msc_node_cnt) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -96,7 +96,7 @@ static void payload(void) if (mbwu_bw == HMAT_INVALID_INFO) { val_print(ERROR, "\n No HMAT info "); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } if ((val_mpam_mbwu_supports_lwd(msc_index) == MBWU_COUNTER_44BIT) @@ -110,11 +110,11 @@ static void payload(void) } if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); else if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_SKIP(03)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/mpam005.c b/test_pool/mpam/mpam005.c index 9e7def2b..7252abb8 100644 --- a/test_pool/mpam/mpam005.c +++ b/test_pool/mpam/mpam005.c @@ -44,7 +44,7 @@ static void payload(void) val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -105,9 +105,9 @@ static void payload(void) } if (test_fails) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t mpam005_entry(uint32_t num_pe) diff --git a/test_pool/mpam/mpam006.c b/test_pool/mpam/mpam006.c index bb705fdf..667e67cc 100644 --- a/test_pool/mpam/mpam006.c +++ b/test_pool/mpam/mpam006.c @@ -227,7 +227,7 @@ payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -235,7 +235,7 @@ payload(void) llc_identifier = val_cache_get_info(CACHE_ID, llc_index); if (llc_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -244,7 +244,7 @@ payload(void) val_print(DEBUG, "\n MSC count = %d", msc_node_cnt); if (msc_node_cnt == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -254,7 +254,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); if (dest_buf != NULL) val_memory_free_aligned(dest_buf); if (src_buf != NULL) @@ -332,7 +332,7 @@ payload(void) /* Test fails if storage_value1 is non zero or storage_value2 is zero */ if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(index, RESULT_FAIL(05)); /*Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); @@ -351,7 +351,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/mpam007.c b/test_pool/mpam/mpam007.c index 9154bedd..0f464068 100644 --- a/test_pool/mpam/mpam007.c +++ b/test_pool/mpam/mpam007.c @@ -53,7 +53,7 @@ static void payload(void) /* If PE not implements FEAT_MPAM, FAIL the test */ if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -64,7 +64,7 @@ static void payload(void) if (msc_node_cnt == 0) { val_print(ERROR, "\n MSC count is 0"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -190,27 +190,27 @@ static void payload(void) if (g_sys_last_lvl_cache == SLC_TYPE_UNKNOWN) { val_print(ERROR, "\n PPTT and memside LLC MSC found, Please provide" "System Last-Level cache info via -slc cmdline option \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } else if (g_sys_last_lvl_cache == SLC_TYPE_PPTT_CACHE && pptt_llc_cpor_supported) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } else if (g_sys_last_lvl_cache == SLC_TYPE_MEMSIDE_CACHE && memside_llc_cpor_supported) { - val_set_status(index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(index, RESULT_PASS); return; } else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); val_print(ERROR, "\n CPOR unsupported by System last-level cache"); + val_set_status(index, RESULT_FAIL(04)); return; } } /* if either of PPTT LLC or mem-side LLC supports cache portioning (CPOR) pass the test */ if (pptt_llc_cpor_supported || memside_llc_cpor_supported) { - val_set_status(index, RESULT_PASS(TEST_NUM, 03)); + val_set_status(index, RESULT_PASS); } else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(index, RESULT_FAIL(05)); } return; diff --git a/test_pool/mpam/partition001.c b/test_pool/mpam/partition001.c index b2ac9799..130a5f87 100644 --- a/test_pool/mpam/partition001.c +++ b/test_pool/mpam/partition001.c @@ -74,7 +74,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -82,7 +82,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -118,7 +118,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if ((cpor_nodes == 0) || (csumon_count == 0)) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -188,12 +188,13 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) val_memory_free_pages(src_buf, num_pages); return; + } /* Configure CSU Monitor */ @@ -260,9 +261,9 @@ static void payload(void) } if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/partition002.c b/test_pool/mpam/partition002.c index d80a7554..e533ede9 100644 --- a/test_pool/mpam/partition002.c +++ b/test_pool/mpam/partition002.c @@ -74,7 +74,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -82,7 +82,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -118,7 +118,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting Cache Portion Partitoning are 0 */ if ((ccap_nodes == 0) || (csumon_count == 0)) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -190,7 +190,7 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -262,9 +262,9 @@ static void payload(void) } if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/partition003.c b/test_pool/mpam/partition003.c index c2c8813d..b33d97df 100644 --- a/test_pool/mpam/partition003.c +++ b/test_pool/mpam/partition003.c @@ -75,7 +75,7 @@ static void payload(void) llc_index = val_cache_get_llc_index(); if (llc_index == CACHE_TABLE_EMPTY) { val_print(ERROR, "\n Cache info table empty"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -83,7 +83,7 @@ static void payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(ERROR, "\n LLC invalid in PPTT"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -119,7 +119,7 @@ static void payload(void) /* Skip the test if CSU monitors/ nodes supporting CCAP & CPOR are 0 */ if ((ccap_cpor_nodes == 0) || (csumon_count == 0)) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -195,7 +195,7 @@ static void payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -267,9 +267,9 @@ static void payload(void) } if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/partition004.c b/test_pool/mpam/partition004.c index 230c24ec..8397d7ca 100644 --- a/test_pool/mpam/partition004.c +++ b/test_pool/mpam/partition004.c @@ -14,7 +14,6 @@ * See the License for the specific language governing permissions and * limitations under the License. **/ - #include "acs_val.h" #include "acs_pe.h" #include "acs_mpam.h" @@ -81,15 +80,15 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n No LLC found, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; + val_set_status(index, RESULT_SKIP(1)); } /* Get the LLC Cache ID */ cache_identifier = val_cache_get_info(CACHE_ID, llc_idx); if (cache_identifier == INVALID_CACHE_INFO) { val_print(DEBUG, "\n Invalid LLC ID, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -172,7 +171,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -215,7 +214,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -276,7 +275,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -337,7 +336,7 @@ payload(void) val_memory_free_aligned(src_buf); val_memory_free_aligned(dest_buf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } @@ -389,11 +388,11 @@ payload(void) } if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); else if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/mpam/partition005.c b/test_pool/mpam/partition005.c index d2e3a367..deb11c0c 100644 --- a/test_pool/mpam/partition005.c +++ b/test_pool/mpam/partition005.c @@ -83,7 +83,7 @@ payload(void) /* Check if LLC is valid */ if (llc_index == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n No LLC found, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -91,7 +91,7 @@ payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(DEBUG, "\n Invalid LLC ID, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -162,7 +162,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -320,11 +320,11 @@ payload(void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); } else if (test_fail) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } return; @@ -348,7 +348,7 @@ payload(void) /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, saved_el2); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } diff --git a/test_pool/mpam/partition006.c b/test_pool/mpam/partition006.c index 3d9df4b4..b25aa17a 100644 --- a/test_pool/mpam/partition006.c +++ b/test_pool/mpam/partition006.c @@ -90,7 +90,7 @@ payload(void) /* Check if LLC is valid */ if (llc_index == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n No LLC found, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -98,7 +98,7 @@ payload(void) cache_identifier = val_cache_get_info(CACHE_ID, llc_index); if (cache_identifier == INVALID_CACHE_INFO) { val_print(DEBUG, "\n Invalid LLC ID, skipping test"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -160,7 +160,7 @@ payload(void) if ((src_buf == NULL) || (dest_buf == NULL)) { val_print(ERROR, "\n Mem allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); if (dest_buf != NULL) val_memory_free_pages(dest_buf, num_pages); if (src_buf != NULL) @@ -354,11 +354,11 @@ payload(void) } if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); } else if (test_fail) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } return; @@ -389,7 +389,7 @@ payload(void) /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, saved_el2); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } diff --git a/test_pool/mpam/reg001.c b/test_pool/mpam/reg001.c index f34e0278..f5c2ab14 100644 --- a/test_pool/mpam/reg001.c +++ b/test_pool/mpam/reg001.c @@ -50,7 +50,7 @@ static void payload(void) if (ext != 0) { /* Fail the test */ val_print(ERROR, "\n MPAMF_IDR.EXT value is not 0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } } @@ -60,7 +60,7 @@ static void payload(void) if (ext != 1) { /* Fail the test */ val_print(ERROR, "\n MPAMF_IDR.EXT value is not 1"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } } @@ -68,12 +68,12 @@ static void payload(void) /* Invalid */ /* TODO : Check for v0.1 */ val_print(ERROR, "\n MSC Version not valid"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/reg002.c b/test_pool/mpam/reg002.c index 8180fb2a..e6eb4583 100644 --- a/test_pool/mpam/reg002.c +++ b/test_pool/mpam/reg002.c @@ -49,13 +49,13 @@ static void payload(void) if (BITFIELD_READ(IDR_HAS_EXTD_ESR, idr_value) == 0) { /* Fail The Test */ val_print(ERROR, "\n MPAMF_IDR.HAS_EXTD_ESR value is 0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } } } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/reg003.c b/test_pool/mpam/reg003.c index ed98e36c..9437f8ff 100644 --- a/test_pool/mpam/reg003.c +++ b/test_pool/mpam/reg003.c @@ -237,15 +237,15 @@ static void payload(void) } else { /* Invalid */ val_print(ERROR, "\n MSC Version not valid"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } } if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/reg004.c b/test_pool/mpam/reg004.c index 510d3bbd..bfbd967b 100644 --- a/test_pool/mpam/reg004.c +++ b/test_pool/mpam/reg004.c @@ -46,7 +46,7 @@ static void payload(void) { /* Skip the test */ val_print_primary_pe(TRACE, "\n PE Does not Support RME", 0, pe_index); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -54,7 +54,7 @@ static void payload(void) { /* Skip the test */ val_print_primary_pe(TRACE, "\n PE Does not Support MPAM", 0, pe_index); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); return; } @@ -62,7 +62,7 @@ static void payload(void) if ((mpam_major < 1) || ((mpam_major == 1) && (mpam_minor < 1))) { val_print_primary_pe(ERROR, "\n PE Does not Support MPAMv1.1", 0, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -71,18 +71,18 @@ static void payload(void) if (VAL_EXTRACT_BITS(mpamidr_val, MPAMIDR_SP4, MPAMIDR_SP4) == 0) { val_print_primary_pe(ERROR, "\n PE Does not Support 4 PARTID Spaces", 0, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } /* Check alternative space, ALTSP feature */ if (VAL_EXTRACT_BITS(mpamidr_val, MPAMIDR_HAS_ALTSP, MPAMIDR_HAS_ALTSP) == 0) { val_print_primary_pe(ERROR, "\n PE Does not Support ALTSP", 0, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/reg005.c b/test_pool/mpam/reg005.c index 6c76c292..051b8c62 100644 --- a/test_pool/mpam/reg005.c +++ b/test_pool/mpam/reg005.c @@ -41,7 +41,7 @@ static void payload(void) { /* Skip the test */ val_print(TRACE, "\n PE Does not Support MPAM for RME"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -60,11 +60,11 @@ static void payload(void) if (num_sp4 == 0) { /* Fail The Test */ val_print(ERROR, "\n Four Space Region Number is 0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/mpam/reg006.c b/test_pool/mpam/reg006.c index 3b38b6fd..f3f7320c 100644 --- a/test_pool/mpam/reg006.c +++ b/test_pool/mpam/reg006.c @@ -58,11 +58,11 @@ static void payload(void) if (nfu_bit != 0) { /* Fail The Test */ - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c index 077269d7..ef5addbe 100644 --- a/test_pool/nist_sts/test_n001.c +++ b/test_pool/nist_sts/test_n001.c @@ -193,7 +193,7 @@ payload() /* Generate a Random file with binary ASCII values */ status = create_random_file(); if (status != ACS_STATUS_PASS) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -233,7 +233,7 @@ payload() status |= mkdir(dirname, 0777); if (status != ACS_STATUS_PASS) { val_print(ERROR, "\n Directory not created"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } else @@ -247,9 +247,9 @@ payload() test_select = test_list[i]; status = main(argc, argv); // NIST STS if (status == ACS_STATUS_NIST_PASS) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } else { - val_set_status(index, RESULT_SKIP(TEST_NUM, 04)); + val_set_status(index, RESULT_SKIP(04)); return; } } @@ -260,9 +260,9 @@ payload() */ status = main(argc, argv); // NIST STS if (status == ACS_STATUS_NIST_PASS) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } else { - val_set_status(index, RESULT_SKIP(TEST_NUM, 05)); + val_set_status(index, RESULT_SKIP(05)); return; } } diff --git a/test_pool/pcie/p001.c b/test_pool/pcie/p001.c index 17299328..44d73369 100644 --- a/test_pool/pcie/p001.c +++ b/test_pool/pcie/p001.c @@ -35,12 +35,12 @@ payload(void) if (num_ecam == 0) { val_print(ERROR, "\n No ECAMs discovered "); if (g_build_sbsa) - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pcie/p002.c b/test_pool/pcie/p002.c index a94983a9..3fd658ce 100644 --- a/test_pool/pcie/p002.c +++ b/test_pool/pcie/p002.c @@ -43,7 +43,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(TRACE, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } /* @@ -117,7 +117,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -127,7 +127,7 @@ payload(void) if (num_ecam == 0) { val_print(DEBUG, "\n No ECAM in MCFG. Skipping test "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -136,7 +136,7 @@ payload(void) ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, num_ecam); if (ecam_base == 0) { val_print(ERROR, "\n ECAM Base in MCFG is 0 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } segment = val_pcie_get_info(PCIE_INFO_SEGMENT, num_ecam); @@ -155,7 +155,7 @@ payload(void) if (ret == PCIE_NO_MAPPING || (data == 0)) { val_print(ERROR, "\n Incorrect data at ECAM Base %4x ", data); val_print(ERROR, "\n BDF is %x ", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -191,7 +191,7 @@ payload(void) val_print(ERROR, "\n Invalid data read from ECAP offset 0x%x", next_offset); val_memory_set(skip_rid_list, sizeof(uint32_t) * MAX_VFS, 0); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } @@ -221,8 +221,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, - (bus_index << PCIE_BUS_SHIFT)|dev_index)); + val_set_status(index, RESULT_FAIL((bus_index << PCIE_BUS_SHIFT)|dev_index)); return; } @@ -231,8 +230,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, - (bus_index << PCIE_BUS_SHIFT)|dev_index)); + val_set_status(index, RESULT_FAIL((bus_index << PCIE_BUS_SHIFT)|dev_index)); return; } @@ -243,7 +241,7 @@ payload(void) val_memory_set(skip_rid_list, sizeof(uint32_t) * MAX_VFS, 0); } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); exception_return: return; diff --git a/test_pool/pcie/p003.c b/test_pool/pcie/p003.c index dbf3e325..8d840754 100644 --- a/test_pool/pcie/p003.c +++ b/test_pool/pcie/p003.c @@ -124,13 +124,13 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No EP/ DP/ UP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p004.c b/test_pool/pcie/p004.c index e006f91f..494d8e27 100644 --- a/test_pool/pcie/p004.c +++ b/test_pool/pcie/p004.c @@ -39,7 +39,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } static @@ -118,7 +118,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -179,7 +179,7 @@ payload(void) val_print(ERROR, "\n Memory offset + base 0x%llx", mem_base + mem_offset); val_print(ERROR, " exceeds the memory limit 0x%llx", mem_lim); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -200,7 +200,7 @@ payload(void) val_print(DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); val_print(DEBUG, "\n Value in memory after write - 0x%x", read_value); val_print(ERROR, "\n Memory access check failed for BDF 0x%x", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); val_pcie_clear_urd(bdf); return; } @@ -237,7 +237,7 @@ payload(void) val_print(ERROR, " is 0x%x", read_value); val_print(ERROR, "\n Out of range 0x%x", (new_mem_lim + MEM_OFFSET_SMALL)); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); } } @@ -266,10 +266,10 @@ payload(void) val_print(DEBUG, "\n No RP/iEP_RP type device found with valid Memory Base/Limit Reg." " Skipping the test."); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p005.c b/test_pool/pcie/p005.c index bb129f2a..af2fee46 100644 --- a/test_pool/pcie/p005.c +++ b/test_pool/pcie/p005.c @@ -39,7 +39,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } static @@ -118,7 +118,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -192,7 +192,7 @@ payload(void) val_print(ERROR, "\n Memory offset + base 0x%llx", mem_base + mem_offset); val_print(ERROR, " exceeds the memory limit 0x%llx", mem_lim); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -213,7 +213,7 @@ payload(void) val_print(DEBUG, "\n Value written into memory - 0x%x", KNOWN_DATA); val_print(DEBUG, "\n Value in memory after write - 0x%x", read_value); val_print(ERROR, "\n Memory access check failed for BDF 0x%x\n", bdf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); val_pcie_clear_urd(bdf); return; } @@ -271,7 +271,7 @@ payload(void) val_print(ERROR, " 0x%llx", updated_mem_lim); val_print(ERROR, "\n Out of range 0x%llx", (new_mem_lim + MEM_OFFSET_SMALL)); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); } } @@ -299,10 +299,10 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP/iEP_RP type device found with valid Memory Base/Limit Reg."); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p006.c b/test_pool/pcie/p006.c index dad82257..25db2c2e 100644 --- a/test_pool/pcie/p006.c +++ b/test_pool/pcie/p006.c @@ -46,7 +46,7 @@ payload(void) intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { val_print(ERROR, "\n Memory allocation error"); - val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -75,12 +75,12 @@ payload(void) if (status) { // Report warn if the Legacy IRQ map does not exist if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } else { val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); continue; } } @@ -98,7 +98,7 @@ payload(void) } else { val_print(ERROR, "\n Int id %d is not SPI", intr_line); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); return; } } @@ -106,9 +106,9 @@ payload(void) val_memory_free_aligned(intr_map); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p007.c b/test_pool/pcie/p007.c index 815669d1..d678870f 100644 --- a/test_pool/pcie/p007.c +++ b/test_pool/pcie/p007.c @@ -65,12 +65,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p008.c b/test_pool/pcie/p008.c index 76c9b9d9..71f3f804 100644 --- a/test_pool/pcie/p008.c +++ b/test_pool/pcie/p008.c @@ -38,7 +38,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(TRACE, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } static @@ -64,7 +64,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -74,7 +74,7 @@ payload(void) if (num_ecam == 0) { val_print(DEBUG, "\n No ECAM in MCFG. Skipping test "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -96,8 +96,7 @@ payload(void) if (ret == PCIE_NO_MAPPING || (data == 0)) { val_print(ERROR, "\n Incorrect data at ECAM Base %4x ", data); val_print(ERROR, "\n BDF is %x ", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, - (bus_index << PCIE_BUS_SHIFT)|dev_index)); + val_set_status(index, RESULT_FAIL((bus_index << PCIE_BUS_SHIFT)|dev_index)); return; } @@ -110,8 +109,7 @@ payload(void) /* Returned data must be FF's, otherwise the test must fail */ if (data != PCIE_UNKNOWN_RESPONSE) { val_print(ERROR, "\n Incorrect data for Bdf 0x%x ", bdf); - val_set_status(index, RESULT_FAIL(TEST_NUM, - (bus_index << PCIE_BUS_SHIFT)|dev_index)); + val_set_status(index, RESULT_FAIL((bus_index << PCIE_BUS_SHIFT)|dev_index)); return; } } @@ -120,7 +118,7 @@ payload(void) } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); exception_return: return; diff --git a/test_pool/pcie/p009.c b/test_pool/pcie/p009.c index 77ed06c7..fb44e6d9 100644 --- a/test_pool/pcie/p009.c +++ b/test_pool/pcie/p009.c @@ -114,11 +114,11 @@ payload(void) } if (test_skip) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fail)); + val_set_status(pe_index, RESULT_FAIL(test_fail)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/pcie/p010.c b/test_pool/pcie/p010.c index 87962c54..663227cb 100644 --- a/test_pool/pcie/p010.c +++ b/test_pool/pcie/p010.c @@ -65,12 +65,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p011.c b/test_pool/pcie/p011.c index 86a7224e..885a2c10 100644 --- a/test_pool/pcie/p011.c +++ b/test_pool/pcie/p011.c @@ -132,12 +132,12 @@ payload(void) if (test_skip) { val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p017.c b/test_pool/pcie/p017.c index 9c429ebb..3f746edd 100644 --- a/test_pool/pcie/p017.c +++ b/test_pool/pcie/p017.c @@ -49,7 +49,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -62,7 +62,7 @@ payload(void) /* Get the number of Root Complex in the system */ if (!num_pcie_rc) { val_print(DEBUG, "\n Skip because no PCIe RC detected "); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -95,7 +95,7 @@ payload(void) /* Check If RP supports P2P with other RP's. */ status = val_pcie_dev_p2p_support(bdf); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } if (status) @@ -128,12 +128,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP type device found with P2P and ATS Support. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p018.c b/test_pool/pcie/p018.c index 715f4e21..45055c05 100644 --- a/test_pool/pcie/p018.c +++ b/test_pool/pcie/p018.c @@ -43,7 +43,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -62,7 +62,7 @@ payload(void) /* Check If RP supports P2P with other RP's. */ status = val_pcie_dev_p2p_support(bdf); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } if (status) @@ -89,12 +89,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p019.c b/test_pool/pcie/p019.c index 734abd01..f61354ea 100644 --- a/test_pool/pcie/p019.c +++ b/test_pool/pcie/p019.c @@ -44,7 +44,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -121,12 +121,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP type device found. Skipping device"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p020.c b/test_pool/pcie/p020.c index a40195ea..7379e4f4 100644 --- a/test_pool/pcie/p020.c +++ b/test_pool/pcie/p020.c @@ -38,11 +38,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table20, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p021.c b/test_pool/pcie/p021.c index 913430d0..75972bbe 100644 --- a/test_pool/pcie/p021.c +++ b/test_pool/pcie/p021.c @@ -36,7 +36,7 @@ payload(void) if (val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0) == 0) { val_print(DEBUG, "\n No ECAMs discovered, Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -44,11 +44,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table21, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p022.c b/test_pool/pcie/p022.c index b915d2d0..66999b4b 100644 --- a/test_pool/pcie/p022.c +++ b/test_pool/pcie/p022.c @@ -37,11 +37,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table22, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p023.c b/test_pool/pcie/p023.c index 46ce4c2f..5845ad05 100644 --- a/test_pool/pcie/p023.c +++ b/test_pool/pcie/p023.c @@ -48,7 +48,7 @@ payload(void) intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { val_print(ERROR, "\n Memory allocation error"); - val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -77,12 +77,12 @@ payload(void) if (status) { // Report warn if the Legacy IRQ map does not exist if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } else { val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); continue; } } @@ -100,7 +100,7 @@ payload(void) } else { val_print(ERROR, "\n Int id %d is not SPI", intr_line); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_SKIP(3)); return; } @@ -111,14 +111,14 @@ payload(void) status = val_gic_get_espi_intr_trigger_type(intr_line, &trigger_type); if (status) { - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(pe_index, RESULT_FAIL(4)); return; } if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) { val_print(ERROR, "\n Legacy interrupt programmed with incorrect trigger type"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(pe_index, RESULT_FAIL(5)); return; } } @@ -126,9 +126,9 @@ payload(void) val_memory_free_aligned(intr_map); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p024.c b/test_pool/pcie/p024.c index be4de20f..7ade35cd 100644 --- a/test_pool/pcie/p024.c +++ b/test_pool/pcie/p024.c @@ -37,11 +37,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table24, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p025.c b/test_pool/pcie/p025.c index b138078c..4279f2a2 100644 --- a/test_pool/pcie/p025.c +++ b/test_pool/pcie/p025.c @@ -37,11 +37,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table25, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p026.c b/test_pool/pcie/p026.c index 3e8978ee..b17465d2 100644 --- a/test_pool/pcie/p026.c +++ b/test_pool/pcie/p026.c @@ -37,11 +37,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table26, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p030.c b/test_pool/pcie/p030.c index bee28c8f..043a514d 100644 --- a/test_pool/pcie/p030.c +++ b/test_pool/pcie/p030.c @@ -38,7 +38,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(TRACE, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } /* @@ -123,7 +123,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -194,7 +194,7 @@ payload(void) val_pcie_disable_msa(bdf); /* Set test status as FAIL, update to PASS in exception handler */ - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -231,11 +231,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p031.c b/test_pool/pcie/p031.c index f37628c0..5d42951f 100644 --- a/test_pool/pcie/p031.c +++ b/test_pool/pcie/p031.c @@ -77,11 +77,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p032.c b/test_pool/pcie/p032.c index 7a9836ae..52417391 100644 --- a/test_pool/pcie/p032.c +++ b/test_pool/pcie/p032.c @@ -74,11 +74,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p033.c b/test_pool/pcie/p033.c index 3888c4f5..97a07198 100644 --- a/test_pool/pcie/p033.c +++ b/test_pool/pcie/p033.c @@ -81,11 +81,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p035.c b/test_pool/pcie/p035.c index 1b691ef4..dca1e4da 100644 --- a/test_pool/pcie/p035.c +++ b/test_pool/pcie/p035.c @@ -129,7 +129,7 @@ payload(void) if (func_config_space == NULL) { val_print(ERROR, "\n Memory allocation fail"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); return; } @@ -153,7 +153,7 @@ payload(void) { val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(func_config_space); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -210,12 +210,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No EP type device found with PCIe Express Cap support. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p036.c b/test_pool/pcie/p036.c index 8a0852ff..71b03392 100644 --- a/test_pool/pcie/p036.c +++ b/test_pool/pcie/p036.c @@ -142,11 +142,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p037.c b/test_pool/pcie/p037.c index 3254ec60..6b2d8ffc 100644 --- a/test_pool/pcie/p037.c +++ b/test_pool/pcie/p037.c @@ -88,12 +88,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP/iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p038.c b/test_pool/pcie/p038.c index 19057d64..ee6b2b2d 100644 --- a/test_pool/pcie/p038.c +++ b/test_pool/pcie/p038.c @@ -96,12 +96,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RP or iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fail) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fail)); + val_set_status(pe_index, RESULT_FAIL(test_fail)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p039.c b/test_pool/pcie/p039.c index d58c09ee..bbd84810 100644 --- a/test_pool/pcie/p039.c +++ b/test_pool/pcie/p039.c @@ -79,11 +79,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p042.c b/test_pool/pcie/p042.c index 74369dda..944ddfbd 100644 --- a/test_pool/pcie/p042.c +++ b/test_pool/pcie/p042.c @@ -96,11 +96,11 @@ static void payload(void) /* Report the status of test */ if (skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 0)); + val_set_status(index, RESULT_SKIP(0)); else if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 0)); + val_set_status(index, RESULT_FAIL(0)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 0)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p045.c b/test_pool/pcie/p045.c index c1d11f93..19320ce1 100644 --- a/test_pool/pcie/p045.c +++ b/test_pool/pcie/p045.c @@ -46,7 +46,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received Exception %d", interrupt_type); - val_set_status(index, RESULT_FAIL(test_num, 02)); + val_set_status(index, RESULT_FAIL(02)); } static @@ -79,7 +79,7 @@ payload(void) uint32_t msa_en = 0; uint32_t reg_value, base_cc; - val_set_status(index, RESULT_SKIP(test_num, 0)); + val_set_status(index, RESULT_SKIP(0)); /* Install exception handlers */ status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); @@ -87,7 +87,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed to install exception handler"); - val_set_status(index, RESULT_FAIL(test_num, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -224,7 +224,7 @@ payload(void) else if (status) { val_print(ERROR, "\n Failed in ioremap with status %x", status); test_fail++; - val_set_status(index, RESULT_FAIL(test_num, test_fail)); + val_set_status(index, RESULT_FAIL(test_fail)); goto next_bar; } @@ -243,7 +243,7 @@ payload(void) /* Setting the status to Pass to enable test for next BDF. * Failure has been recorded with test_fail. */ - val_set_status(index, RESULT_PASS(test_num, 02)); + val_set_status(index, RESULT_PASS); test_fail++; } @@ -263,14 +263,14 @@ payload(void) } if (test_warn) { - val_set_status(index, RESULT_WARN(test_num, 0)); + val_set_status(index, RESULT_WARNING(0)); return; } else if (test_skip) - val_set_status(index, RESULT_SKIP(test_num, 1)); + val_set_status(index, RESULT_SKIP(1)); else if (test_fail) - val_set_status(index, RESULT_FAIL(test_num, test_fail)); + val_set_status(index, RESULT_FAIL(test_fail)); else - val_set_status(index, RESULT_PASS(test_num, 0)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pcie/p046.c b/test_pool/pcie/p046.c index aa6c4613..7fcea517 100644 --- a/test_pool/pcie/p046.c +++ b/test_pool/pcie/p046.c @@ -87,7 +87,7 @@ payload (void) uint32_t ret; if(!count) { - val_set_status (index, RESULT_SKIP (TEST_NUM, 2)); + val_set_status (index, RESULT_SKIP(2)); return; } @@ -119,7 +119,7 @@ payload (void) if(mvec->vector.vector_irq_base < LPI_BASE) { val_print(ERROR, " MSI vector irq %llx is not an LPI\n", mvec->vector.vector_irq_base); - val_set_status (index, RESULT_FAIL (TEST_NUM, mvec->vector.vector_irq_base)); + val_set_status (index, RESULT_FAIL(mvec->vector.vector_irq_base)); status = 1; }else { val_print(DEBUG, @@ -138,14 +138,14 @@ payload (void) if (test_skip) { val_print(DEBUG, "\n No MSI vectors found "); - val_set_status (index, RESULT_SKIP(TEST_NUM, 0)); + val_set_status (index, RESULT_SKIP(0)); } else if (!status) { - val_set_status (index, RESULT_PASS(TEST_NUM, 0)); + val_set_status (index, RESULT_PASS); } return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); } uint32_t diff --git a/test_pool/pcie/p047.c b/test_pool/pcie/p047.c index acf1039a..8e9dd76e 100644 --- a/test_pool/pcie/p047.c +++ b/test_pool/pcie/p047.c @@ -70,7 +70,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(bar_data, 1, 2); if (data != 0) { val_print(ERROR, "\n NP type-1 pcie is not 32-bit mem type"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); status = 2; break; } @@ -80,7 +80,7 @@ static void payload(void) if (ret) { val_print(ERROR, "\n NP type-1 pcie bridge end device" "is not 32-bit mem type"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); status = 2; break; } @@ -96,10 +96,10 @@ static void payload(void) if (!status) { val_print(DEBUG, "\n No Type1 Non Prefetcable BAR Detected. Skipping test"); - val_set_status(index, RESULT_SKIP (TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); } else if (status == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t p047_entry(uint32_t num_pe) diff --git a/test_pool/pcie/p048.c b/test_pool/pcie/p048.c index 210332a2..5c5e397c 100644 --- a/test_pool/pcie/p048.c +++ b/test_pool/pcie/p048.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table48, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p049.c b/test_pool/pcie/p049.c index ad5e76fa..fc26b7f9 100644 --- a/test_pool/pcie/p049.c +++ b/test_pool/pcie/p049.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table49, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p050.c b/test_pool/pcie/p050.c index a51750ac..d6a3db66 100644 --- a/test_pool/pcie/p050.c +++ b/test_pool/pcie/p050.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table50, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p051.c b/test_pool/pcie/p051.c index d6c79f22..55382405 100644 --- a/test_pool/pcie/p051.c +++ b/test_pool/pcie/p051.c @@ -39,13 +39,13 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table51, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) { val_print(ERROR, "\nCheck failed - Slot Implemented[8] PCI Express Capabilities"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); } else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p052.c b/test_pool/pcie/p052.c index 50f1561d..04663394 100644 --- a/test_pool/pcie/p052.c +++ b/test_pool/pcie/p052.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table52, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p053.c b/test_pool/pcie/p053.c index 7b98c0b2..8eac326c 100644 --- a/test_pool/pcie/p053.c +++ b/test_pool/pcie/p053.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table53, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p054.c b/test_pool/pcie/p054.c index 2de3a938..9f475641 100644 --- a/test_pool/pcie/p054.c +++ b/test_pool/pcie/p054.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table54, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p056.c b/test_pool/pcie/p056.c index eea66476..0a965349 100644 --- a/test_pool/pcie/p056.c +++ b/test_pool/pcie/p056.c @@ -40,11 +40,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table56, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p057.c b/test_pool/pcie/p057.c index eb890543..01ffcfa6 100644 --- a/test_pool/pcie/p057.c +++ b/test_pool/pcie/p057.c @@ -39,11 +39,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table57, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p058.c b/test_pool/pcie/p058.c index 15571927..402ea95a 100644 --- a/test_pool/pcie/p058.c +++ b/test_pool/pcie/p058.c @@ -50,7 +50,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(DEBUG, "\n Received exception of type: %d", interrupt_type); - val_set_status(pe_index, RESULT_PASS(test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } @@ -137,7 +137,7 @@ payload(void *arg) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -233,7 +233,7 @@ payload(void *arg) val_pcie_disable_msa(bdf); /* Set test status as FAIL, update to PASS in exception handler */ - val_set_status(pe_index, RESULT_FAIL(test_num, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); /* If test runs for atleast an endpoint */ test_skip = 0; @@ -272,12 +272,12 @@ payload(void *arg) if (test_skip == 1) { val_print(DEBUG, "\n Found no target device type with MMIO BAR. Skipping test."); - val_set_status(pe_index, RESULT_SKIP(test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(test_num, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p061.c b/test_pool/pcie/p061.c index ed61c4d8..07e05e82 100644 --- a/test_pool/pcie/p061.c +++ b/test_pool/pcie/p061.c @@ -91,11 +91,11 @@ payload(void *arg) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p062.c b/test_pool/pcie/p062.c index c8449f74..5d0c5eff 100644 --- a/test_pool/pcie/p062.c +++ b/test_pool/pcie/p062.c @@ -107,11 +107,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p063.c b/test_pool/pcie/p063.c index cf618db2..e7423b55 100644 --- a/test_pool/pcie/p063.c +++ b/test_pool/pcie/p063.c @@ -124,7 +124,7 @@ payload(void) if (func_config_space == NULL) { val_print(ERROR, "\n Memory allocation fail"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); return; } @@ -149,7 +149,7 @@ payload(void) { val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(func_config_space); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -206,12 +206,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No target device type with FLR Cap found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p064.c b/test_pool/pcie/p064.c index a9a7ebf8..262af4d9 100644 --- a/test_pool/pcie/p064.c +++ b/test_pool/pcie/p064.c @@ -85,12 +85,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No iEP_EP found with ARI Capability Support. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p065.c b/test_pool/pcie/p065.c index 75cb6f70..ded7cf87 100644 --- a/test_pool/pcie/p065.c +++ b/test_pool/pcie/p065.c @@ -90,12 +90,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p066.c b/test_pool/pcie/p066.c index a32de49f..a91b3d87 100644 --- a/test_pool/pcie/p066.c +++ b/test_pool/pcie/p066.c @@ -91,16 +91,16 @@ payload(void) /* Skip the test if no iEP_RP found */ if (iep_rp_found == 0) { val_print(DEBUG, "\n No iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p067.c b/test_pool/pcie/p067.c index 3e65b858..a1b9cbf6 100644 --- a/test_pool/pcie/p067.c +++ b/test_pool/pcie/p067.c @@ -104,12 +104,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p068.c b/test_pool/pcie/p068.c index ddeeaa39..f1502487 100644 --- a/test_pool/pcie/p068.c +++ b/test_pool/pcie/p068.c @@ -35,7 +35,7 @@ payload(void) if (!num_pcie_rc) { val_print(DEBUG, "\n Skip because no PCIe RC detected "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -44,11 +44,11 @@ payload(void) mem_attr = val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, num_pcie_rc); if (mem_attr == INNER_SHAREABLE) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else { val_print(ERROR, "\n Failed mem attribute check for PCIe RC %d", num_pcie_rc); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } diff --git a/test_pool/pcie/p069.c b/test_pool/pcie/p069.c index 685fa6d9..2458be7c 100644 --- a/test_pool/pcie/p069.c +++ b/test_pool/pcie/p069.c @@ -86,12 +86,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No target device type found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p070.c b/test_pool/pcie/p070.c index c79b5397..e873cde7 100644 --- a/test_pool/pcie/p070.c +++ b/test_pool/pcie/p070.c @@ -70,12 +70,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No target device type found. Skipping test", bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -95,4 +95,4 @@ p070_entry(uint32_t num_pe) val_report_status(0, ACS_END(TEST_NUM), NULL); return status; -} \ No newline at end of file +} diff --git a/test_pool/pcie/p071.c b/test_pool/pcie/p071.c index 2e3f729d..6b716245 100644 --- a/test_pool/pcie/p071.c +++ b/test_pool/pcie/p071.c @@ -144,13 +144,13 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No DP/ iEP_RP type device found.Skipping test", bdf); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p072.c b/test_pool/pcie/p072.c index 25b1c602..b0094a04 100644 --- a/test_pool/pcie/p072.c +++ b/test_pool/pcie/p072.c @@ -124,12 +124,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No iEP_EP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p078.c b/test_pool/pcie/p078.c index f8dfe0d0..ae9641fd 100644 --- a/test_pool/pcie/p078.c +++ b/test_pool/pcie/p078.c @@ -55,7 +55,7 @@ payload_primary(void) intr_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!intr_map) { val_print (ERROR, "\n Memory allocation error"); - val_set_status(pe_index, RESULT_FAIL (test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -84,14 +84,14 @@ payload_primary(void) if (status) { /* Report warn if the Legacy IRQ map does not exist */ if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(test_num, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); val_memory_free_aligned(intr_map); return; } else { val_print (DEBUG, "\n PCIe Legacy IRQs unmapped. Skipping BDF %llx", bdf); - val_set_status(pe_index, RESULT_SKIP(test_num, 2)); + val_set_status(pe_index, RESULT_SKIP(2)); continue; } } @@ -109,7 +109,7 @@ payload_primary(void) else { val_print(ERROR, "\n Int id %d is not SPI", intr_line); val_memory_free_aligned(intr_map); - val_set_status(pe_index, RESULT_FAIL(test_num, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } } @@ -117,9 +117,9 @@ payload_primary(void) val_memory_free_aligned(intr_map); if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } /* Payload for the rule PCI_LI_03 */ @@ -161,22 +161,22 @@ payload_secondary(void) status = val_gic_get_espi_intr_trigger_type(intr_line, &trigger_type); if (status) { - val_set_status(pe_index, RESULT_FAIL(test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) { val_print(ERROR, "\n Legacy interrupt programmed with incorrect trigger type"); - val_set_status(pe_index, RESULT_FAIL(test_num, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else - val_set_status(pe_index, RESULT_PASS(test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p079.c b/test_pool/pcie/p079.c index 60625633..3a82eb44 100644 --- a/test_pool/pcie/p079.c +++ b/test_pool/pcie/p079.c @@ -136,7 +136,7 @@ payload(void) iep_bdf = get_iep_bdf_under_rp(bdf); if (iep_bdf == 0x0) { val_print(ERROR, "\n Could Not Find iEP_EP under iEP_RP."); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -146,7 +146,7 @@ payload(void) if (cfg_space_buf == NULL) { val_print(ERROR, "\n Memory allocation failed."); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -173,7 +173,7 @@ payload(void) { val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(cfg_space_buf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -188,7 +188,7 @@ payload(void) { val_print(ERROR, "\n Failed to time delay for BDF 0x%x ", bdf); val_memory_free_aligned(cfg_space_buf); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } @@ -222,12 +222,12 @@ payload(void) /* Skip the test if no iEP_RP found */ if (iep_rp_found == 0) { val_print(DEBUG, "\n No iEP_RP type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p080.c b/test_pool/pcie/p080.c index 66ed7d45..ab996901 100644 --- a/test_pool/pcie/p080.c +++ b/test_pool/pcie/p080.c @@ -86,16 +86,16 @@ payload(void) } if (warn_cnt) - val_set_status(pe_index, RESULT_WARN(TEST_NUM, warn_cnt)); + val_set_status(pe_index, RESULT_WARNING(warn_cnt)); else if (test_skip) { val_print(DEBUG, "\n No target device type found with ATC available. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p081.c b/test_pool/pcie/p081.c index 2b5e6c54..b94fc34c 100644 --- a/test_pool/pcie/p081.c +++ b/test_pool/pcie/p081.c @@ -48,7 +48,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; } @@ -68,7 +68,7 @@ payload(void) /* Check If iEP_EP supports P2P with others. */ status = val_pcie_dev_p2p_support(bdf); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; } if (status) @@ -156,12 +156,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No iEP_EP type device found with P2P support. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p082.c b/test_pool/pcie/p082.c index a252c2d3..6e912bf9 100644 --- a/test_pool/pcie/p082.c +++ b/test_pool/pcie/p082.c @@ -80,7 +80,7 @@ payload(void *arg) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; } @@ -106,7 +106,7 @@ payload(void *arg) /* Check If Endpoint supports P2P with other Functions. */ status = val_pcie_dev_p2p_support(bdf); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_WARNING(01)); return; } if (status) @@ -170,12 +170,12 @@ payload(void *arg) if (test_skip == 1) { val_print(DEBUG, "\n No target device type with Multifunction and P2P support.Skipping test"); - val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails + aer_cap_fail) - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -235,11 +235,11 @@ p016_entry(uint32_t num_pe) if (status != ACS_STATUS_SKIP) { if (g_aer_cap_status == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(test_entries[2].test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (g_aer_cap_status == ACS_STATUS_FAIL) - val_set_status(pe_index, RESULT_FAIL(test_entries[2].test_num, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); else - val_set_status(pe_index, RESULT_PASS(test_entries[2].test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } /* get the result from all PE and check for failure */ diff --git a/test_pool/pcie/p083.c b/test_pool/pcie/p083.c index 1fb187d4..7f763e16 100644 --- a/test_pool/pcie/p083.c +++ b/test_pool/pcie/p083.c @@ -146,12 +146,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No target device type found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p084.c b/test_pool/pcie/p084.c index 00156351..558a32b2 100644 --- a/test_pool/pcie/p084.c +++ b/test_pool/pcie/p084.c @@ -80,12 +80,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RCEC type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p085.c b/test_pool/pcie/p085.c index dc8df26e..ae5005e0 100644 --- a/test_pool/pcie/p085.c +++ b/test_pool/pcie/p085.c @@ -74,12 +74,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No RCiEP/ RCEC type device found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (fail_cnt) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt)); + val_set_status(pe_index, RESULT_FAIL(fail_cnt)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p086.c b/test_pool/pcie/p086.c index 2b9a240a..583e0a22 100644 --- a/test_pool/pcie/p086.c +++ b/test_pool/pcie/p086.c @@ -42,7 +42,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(TRACE, "\n Received exception of type in test 861: %d", interrupt_type); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); } static uint32_t test_sequence_1B(uint8_t *addr) @@ -59,7 +59,7 @@ static uint32_t test_sequence_1B(uint8_t *addr) if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { val_print(ERROR, "\n Error in read and write 1B"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return 1; } @@ -84,7 +84,7 @@ uint32_t test_sequence_2B(uint16_t *addr) if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { val_print(ERROR, "\n Error in read and write 2B"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return 1; } @@ -115,7 +115,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -177,12 +177,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No MMIO BARs detected. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p087.c b/test_pool/pcie/p087.c index d2dd6883..c16d6a69 100644 --- a/test_pool/pcie/p087.c +++ b/test_pool/pcie/p087.c @@ -59,7 +59,7 @@ payload(void) if (num_ecam == 0) { val_print(ERROR, "\n No ECAMs discovered "); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -116,12 +116,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n Found no Endpoint with PCIe Capability. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p088.c b/test_pool/pcie/p088.c index c83c0e97..7608813b 100644 --- a/test_pool/pcie/p088.c +++ b/test_pool/pcie/p088.c @@ -38,11 +38,11 @@ payload(void) ret = val_pcie_register_bitfields_check((void *)&bf_info_table88, table_entries); if (ret == ACS_STATUS_SKIP) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (ret) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret)); + val_set_status(pe_index, RESULT_FAIL(ret)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } diff --git a/test_pool/pcie/p089.c b/test_pool/pcie/p089.c index d729cad7..7f7dcb2d 100644 --- a/test_pool/pcie/p089.c +++ b/test_pool/pcie/p089.c @@ -42,7 +42,7 @@ static void payload(void) /* Get the number of Root Complex in the system */ if (!num_pcie_rc) { val_print(DEBUG, "\n Skip because no PCIe RC detected "); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); return; } @@ -63,9 +63,9 @@ static void payload(void) } if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t p089_entry(uint32_t num_pe) diff --git a/test_pool/pcie/p090.c b/test_pool/pcie/p090.c index 8c80d227..5355ba53 100644 --- a/test_pool/pcie/p090.c +++ b/test_pool/pcie/p090.c @@ -91,12 +91,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n Found no RP with DPC Capability. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(02)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p091.c b/test_pool/pcie/p091.c index 72661041..c7cd12d3 100644 --- a/test_pool/pcie/p091.c +++ b/test_pool/pcie/p091.c @@ -37,14 +37,14 @@ payload(void) if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(index, RESULT_WARN(TEST_NUM, 0)); + val_set_status(index, RESULT_WARNING(1)); } else if (status == 0) { val_print(ERROR, "\n STE tag value should not be 0\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } else - val_set_status(index, RESULT_PASS(TEST_NUM, 0)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pcie/p092.c b/test_pool/pcie/p092.c index 4db12a32..33dc8d8e 100644 --- a/test_pool/pcie/p092.c +++ b/test_pool/pcie/p092.c @@ -168,12 +168,12 @@ payload(void *arg) if (test_skip == 1) { val_print(DEBUG, "\n No target device type with required extended cap found. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(test_data->test_num, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t @@ -257,4 +257,4 @@ p014_entry(uint32_t num_pe) val_report_status(0, ACS_END(test_entries[3].test_num), test_entries[3].rule); return status; -} \ No newline at end of file +} diff --git a/test_pool/pcie/p093.c b/test_pool/pcie/p093.c index 5bc12470..1eea2687 100644 --- a/test_pool/pcie/p093.c +++ b/test_pool/pcie/p093.c @@ -46,7 +46,7 @@ payload(void) /* Check If PCIe Hierarchy supports P2P */ if (val_pcie_p2p_support() == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(pe_index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_WARNING(1)); return; } @@ -135,12 +135,12 @@ payload(void) if (test_skip == 1) { val_print(DEBUG, "\n No Downstream Port of Switch found. Skipping device"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_SKIP(1)); } else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails)); + val_set_status(pe_index, RESULT_FAIL(test_fails)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p094.c b/test_pool/pcie/p094.c index adf233a2..8cf79109 100644 --- a/test_pool/pcie/p094.c +++ b/test_pool/pcie/p094.c @@ -46,7 +46,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(test_num, 02)); + val_set_status(index, RESULT_FAIL(02)); } static @@ -79,7 +79,7 @@ payload(void) uint32_t msa_en = 0; uint32_t reg_value, base_cc; - val_set_status(index, RESULT_SKIP(test_num, 0)); + val_set_status(index, RESULT_SKIP(0)); /* Install exception handlers */ status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); @@ -87,7 +87,7 @@ payload(void) if (status) { val_print(ERROR, "\n Failed to install exception handler"); - val_set_status(index, RESULT_FAIL(test_num, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -226,7 +226,7 @@ payload(void) test_fail++; val_print(ERROR, "\n pal_memory_ioremap failed, status: 0x%x", status); - val_set_status(index, RESULT_FAIL(test_num, test_fail)); + val_set_status(index, RESULT_FAIL(test_fail)); goto next_bar; } @@ -249,7 +249,7 @@ payload(void) /* Setting the status to Pass to enable next check for current BDF. * Failure has been recorded with test_fail. */ - val_set_status(index, RESULT_PASS(test_num, 01)); + val_set_status(index, RESULT_PASS); test_fail++; } @@ -269,14 +269,14 @@ payload(void) } if (test_warn) { - val_set_status(index, RESULT_WARN(test_num, 0)); + val_set_status(index, RESULT_WARNING(1)); return; } else if (test_skip) - val_set_status(index, RESULT_FAIL(test_num, 1)); + val_set_status(index, RESULT_FAIL(1)); else if (test_fail) - val_set_status(index, RESULT_FAIL(test_num, test_fail)); + val_set_status(index, RESULT_FAIL(test_fail)); else - val_set_status(index, RESULT_PASS(test_num, 0)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pcie/p095.c b/test_pool/pcie/p095.c index fcf58ed3..9bb2dc0e 100644 --- a/test_pool/pcie/p095.c +++ b/test_pool/pcie/p095.c @@ -44,7 +44,7 @@ payload(void) if (!target_dev_index) { val_print(DEBUG, "\n No DMA controllers detected... "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -68,20 +68,20 @@ payload(void) } val_print(ERROR, "\n The DMA address %lx used by device ", dma_addr); val_print(ERROR, "\n is not present in the SMMU IOVA table\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index)); + val_set_status(index, RESULT_FAIL(target_dev_index)); return; } } } if (iommu_flag) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); } diff --git a/test_pool/pcie/p096.c b/test_pool/pcie/p096.c index 5085b5c8..a90d898a 100644 --- a/test_pool/pcie/p096.c +++ b/test_pool/pcie/p096.c @@ -52,14 +52,14 @@ payload (void) count = val_peripheral_get_info (NUM_ALL, 0); if (!count) { - val_set_status(index, RESULT_SKIP (TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } irq_map = val_aligned_alloc(MEM_ALIGN_4K, sizeof(PERIPHERAL_IRQ_MAP)); if (!irq_map) { val_print(ERROR, "\n Memory allocation error"); - val_set_status(index, RESULT_FAIL (TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -149,13 +149,13 @@ payload (void) val_memory_free_aligned(irq_map); if (warn_cnt) - val_set_status(index, RESULT_WARN (TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING (1)); else if (test_skip) - val_set_status(index, RESULT_SKIP (TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP (2)); else if (!status) - val_set_status(index, RESULT_PASS (TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL (TEST_NUM, status)); + val_set_status(index, RESULT_FAIL (status)); return; } diff --git a/test_pool/pcie/p097.c b/test_pool/pcie/p097.c index 9eb78489..97a1bafd 100644 --- a/test_pool/pcie/p097.c +++ b/test_pool/pcie/p097.c @@ -228,7 +228,7 @@ payload (void) if (check_list_duplicates (current_dev_mvec, next_dev_mvec)) { val_print (ACS_STATUS_ERR, "\n Allocated MSIs are not unique", 0); - val_set_status (index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status (index, RESULT_FAIL(01)); status = 1; } @@ -249,14 +249,14 @@ payload (void) if (test_skip) { val_print(ERROR, "\n No MSI vectors found ");; - val_set_status (index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status (index, RESULT_SKIP(01)); } else if (!status) { - val_set_status (index, RESULT_PASS(TEST_NUM, 01)); + val_set_status (index, RESULT_PASS); } return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); } uint32_t diff --git a/test_pool/pcie/p100.c b/test_pool/pcie/p100.c index 152f18fc..cbe2caef 100644 --- a/test_pool/pcie/p100.c +++ b/test_pool/pcie/p100.c @@ -80,11 +80,11 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); else if (test_fails) - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); else - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); } uint32_t diff --git a/test_pool/pcie/p105.c b/test_pool/pcie/p105.c index 6a10b000..1a763830 100644 --- a/test_pool/pcie/p105.c +++ b/test_pool/pcie/p105.c @@ -43,7 +43,7 @@ payload(void) if (!target_dev_index) { val_print(DEBUG, "\n No DMA controllers detected... "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -67,7 +67,7 @@ payload(void) val_print(ERROR, "\n The DMA addr allocated to device %d ", target_dev_index); val_print(ERROR, "\n is not present in the SMMU IOVA table\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index)); + val_set_status(index, RESULT_FAIL(target_dev_index)); return; } /* Free the allocated memory here */ @@ -76,13 +76,13 @@ payload(void) } if (iommu_flag) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); } diff --git a/test_pool/pe/pe001.c b/test_pool/pe/pe001.c index 98ab5f8a..9e48f90e 100644 --- a/test_pool/pe/pe001.c +++ b/test_pool/pe/pe001.c @@ -221,9 +221,9 @@ id_regs_check(void) } if (check == 1) - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -243,7 +243,7 @@ payload(uint32_t num_pe) if (num_pe == 1) { val_print(DEBUG, "\n Skipping as num of PE is 1 "); - val_set_status(my_index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(my_index, RESULT_SKIP(1)); return; } @@ -284,7 +284,7 @@ payload(uint32_t num_pe) if (g_pe_reg_info == NULL) { val_print(ERROR, "\n Allocation for secondary PE Registers Failed \n"); - val_set_status(my_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(my_index, RESULT_FAIL(1)); return; } @@ -296,7 +296,7 @@ payload(uint32_t num_pe) if(timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); return; } } @@ -400,10 +400,10 @@ payload(uint32_t num_pe) if (total_fail) { val_print(ERROR, "\n\n Total Register and cache fail for all PE %d \n", total_fail); - val_set_status(my_index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(my_index, RESULT_FAIL(4)); } else - val_set_status(my_index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(my_index, RESULT_PASS); val_memory_free((void *) g_pe_reg_info); return; diff --git a/test_pool/pe/pe002.c b/test_pool/pe/pe002.c index be5eb5c5..819731e8 100644 --- a/test_pool/pe/pe002.c +++ b/test_pool/pe/pe002.c @@ -36,14 +36,14 @@ payload() /* For Gic v2 number of max PE 8, for GIC v3 and higher number of max PE 2^28 */ if (((gic_version == 2) && (num_of_pe <= 8)) || ((gic_version >= 3) && (num_of_pe <= (2 << 27)))) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } val_print(DEBUG, "\n Number of PE is %d", num_of_pe); val_print(DEBUG, "\n Gic version is %d", gic_version); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } diff --git a/test_pool/pe/pe003.c b/test_pool/pe/pe003.c index a75d4794..b5662f15 100644 --- a/test_pool/pe/pe003.c +++ b/test_pool/pe/pe003.c @@ -33,9 +33,9 @@ payload() data = (data & 0xF00000) >> 20; if ((data == 0x0) || (data == 0x1)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe004.c b/test_pool/pe/pe004.c index 25bc907c..ef6ffa58 100644 --- a/test_pool/pe/pe004.c +++ b/test_pool/pe/pe004.c @@ -44,9 +44,9 @@ payload() * must be 1 if LPA2 is implemented, 4KB granule supports 52 bit input and output addresses. */ if ((tgran4 == 0x0) || (tgran4 == 0x1)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } uint32_t diff --git a/test_pool/pe/pe006.c b/test_pool/pe/pe006.c index 7028e7e0..d7ffb0cc 100644 --- a/test_pool/pe/pe006.c +++ b/test_pool/pe/pe006.c @@ -32,7 +32,7 @@ payload() if (!g_crypto_support) { val_print_primary_pe(DEBUG, "\n Crypto extension not supported", 0, index); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -40,9 +40,9 @@ payload() //bits 7:4, 11:8, 15:12 must be non-zero if (((data >> 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe007.c b/test_pool/pe/pe007.c index 6476db07..e2e954bd 100644 --- a/test_pool/pe/pe007.c +++ b/test_pool/pe/pe007.c @@ -37,9 +37,9 @@ payload() } if (((data >> 25) & 1) == 0) //Bit 25 must be 0 - val_set_status(index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } diff --git a/test_pool/pe/pe008.c b/test_pool/pe/pe008.c index c98f2b84..7ec8c799 100644 --- a/test_pool/pe/pe008.c +++ b/test_pool/pe/pe008.c @@ -32,9 +32,9 @@ payload() data = val_pe_reg_read(ID_AA64PFR0_EL1); if ((data & 0x3) && (data & 0x30)) //bits 1:0 and 5:4 must not be zero - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe009.c b/test_pool/pe/pe009.c index 1b0d54bf..d0d34db8 100644 --- a/test_pool/pe/pe009.c +++ b/test_pool/pe/pe009.c @@ -52,16 +52,16 @@ payload() /* PMCR_EL0 Bits 15:11 for Number of counters. */ data = VAL_EXTRACT_BITS(val_pe_reg_read(PMCR_EL0), 11, 15); if (data > 3) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else { if (index == primary_pe_idx) { val_print(ERROR, "\n Number of PMU counters reported: %d, expected >= 4", data); } - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } } else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } return; @@ -79,13 +79,13 @@ payload_check_for_pmuv3() /* Check for PMUv3 */ data = fetch_pmu_version(); if (data == 0x0 || data == 0xF) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_print_primary_pe(ERROR, "\n PMUv3 not implemented, ID_AA64DFR0_EL1 PMUVer: 0x%lx", data, primary_pe_idx); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -128,4 +128,4 @@ pe067_entry(uint32_t num_pe) val_report_status(0, ACS_END(TEST_NUM_VBSA), NULL); return status; -} \ No newline at end of file +} diff --git a/test_pool/pe/pe010.c b/test_pool/pe/pe010.c index e8f5a649..95e56514 100644 --- a/test_pool/pe/pe010.c +++ b/test_pool/pe/pe010.c @@ -36,7 +36,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(ERROR, "\n Error : Received Exception of type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } static @@ -67,7 +67,7 @@ isr() /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ val_pe_reg_write(PMOVSCLR_EL0, 0x1); val_print(TRACE, "\n Received PMUIRQ "); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(int_id); return; @@ -87,20 +87,20 @@ payload() data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11); if ((data == 0x0) || (data == 0xF)) { /* PMUver not implemented, Skipping. */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } int_id = val_pe_get_pmu_gsiv(index); if (int_id == 0) { /* PMU interrupt number not updated */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } if (val_gic_install_isr(int_id, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -118,7 +118,7 @@ payload() exception_taken: if (timeout == 0) { val_print(ERROR, "\n Interrupt not recieved within timeout"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } } diff --git a/test_pool/pe/pe011.c b/test_pool/pe/pe011.c index 13b7f167..814bb480 100644 --- a/test_pool/pe/pe011.c +++ b/test_pool/pe/pe011.c @@ -41,21 +41,21 @@ payload() val_print(ERROR, "\n Number of PE breakpoints reported: %d, expected >= 6", breakpointcount); } - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } /*bits [31:28] Number of breakpoints that are context-aware, minus 1*/ context_aware_breakpoints = VAL_EXTRACT_BITS(data, 28, 31) + 1; if (context_aware_breakpoints > 1) - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); else { if (pe_index == primary_pe_idx) { val_print(ERROR, "\n Number of PE context-aware breakpoints reported: %d, expected > 1", context_aware_breakpoints); } - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); } return; diff --git a/test_pool/pe/pe012.c b/test_pool/pe/pe012.c index 88d9e1ec..9afea3cd 100644 --- a/test_pool/pe/pe012.c +++ b/test_pool/pe/pe012.c @@ -35,13 +35,13 @@ payload() data = ((data >> 20) & 0xF) + 1; /* number of synchronous watchpoints */ if (data > 3) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else { if (index == primary_pe_idx) { val_print(ERROR, "\n Number of synchronous watchpoints reported: %d, expected > 3", data); } - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } return; diff --git a/test_pool/pe/pe013.c b/test_pool/pe/pe013.c index 2398c11f..d542d3c4 100644 --- a/test_pool/pe/pe013.c +++ b/test_pool/pe/pe013.c @@ -32,9 +32,9 @@ payload() data = val_pe_reg_read(ID_AA64ISAR0_EL1); if ((data >> 16) & 0xF) //bits 19:16 are CRC32 and must not be zero - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe014.c b/test_pool/pe/pe014.c index 2deb3c2d..67cf6c3a 100644 --- a/test_pool/pe/pe014.c +++ b/test_pool/pe/pe014.c @@ -33,9 +33,9 @@ static void check_pauth_algorithm(uint32_t index, uint64_t data1, uint32_t data2 if (((VAL_EXTRACT_BITS(data1, 4, 7) != 0) && (VAL_EXTRACT_BITS(data1, 24, 27) != 0)) || ((VAL_EXTRACT_BITS(data2, 8, 11) != 0) && (VAL_EXTRACT_BITS(data2, 12, 15) != 0))) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } static @@ -71,7 +71,7 @@ payload() (VAL_EXTRACT_BITS(data1, 8, 11) == 0) && (VAL_EXTRACT_BITS(data1, 28, 31) == 0)) { /* Pointer signing not implemented, Skip the test */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } diff --git a/test_pool/pe/pe015.c b/test_pool/pe/pe015.c index 9e0c3870..ac672aae 100644 --- a/test_pool/pe/pe015.c +++ b/test_pool/pe/pe015.c @@ -37,9 +37,9 @@ payload() /* Must support LSE as indicated by ID_AA64ISAR0_EL1.Atomic = 0b0010 or 0b0011 */ if ((data == 0x2) || (data == 0x3)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe016.c b/test_pool/pe/pe016.c index 0fd7cbff..ff6d546f 100644 --- a/test_pool/pe/pe016.c +++ b/test_pool/pe/pe016.c @@ -53,7 +53,7 @@ payload() /* If PE implements SVE2, it's a pass. No need to check architecture family, as * BSA mandates SVE2 from v9 */ if (VAL_EXTRACT_BITS(data, 0, 3) > 0) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); tmp_reg_data->status = ACS_STATUS_PASS; return; } @@ -63,20 +63,20 @@ payload() /* SVE2 not implemented, SMBIOS info missing, cannot confirm if PE is v9. Skipping the test */ if (pe_family == ACS_STATUS_ERR) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); tmp_reg_data->status = ACS_STATUS_ERR; return; } /* SVE2 not implemented, SMBIOS does not report Armv9, skipping the test */ if (pe_family != PROCESSOR_FAMILY_ARMV9) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); tmp_reg_data->status = ACS_STATUS_SKIP; return; } /* SVE2 not implemented, SMBIOS reports Armv9, failing the test */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); tmp_reg_data->status = ACS_STATUS_FAIL; } @@ -95,14 +95,14 @@ pe016_entry(uint32_t num_pe) if (smbios_slots == 0) { val_print(WARN, "\n SMBIOS Table Not Found, Skipping the test\n"); status = ACS_STATUS_SKIP; - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); /* get the result from all PE and check for failure */ status = val_check_for_error(TEST_NUM, 1, TEST_RULE); } /* This check is when user is forcing us to skip this test */ - if (status != TEST_SKIP_VAL) { + if (GET_STATE(status) != TEST_SKIP) { g_sve_reg_info = (sve_reg_details *) val_memory_calloc(num_pe, sizeof(sve_reg_details)); if (g_sve_reg_info == NULL) { val_print(ERROR, "\n Memory Allocation for SVE Register data Failed"); diff --git a/test_pool/pe/pe017.c b/test_pool/pe/pe017.c index b23a2d7a..8934859b 100644 --- a/test_pool/pe/pe017.c +++ b/test_pool/pe/pe017.c @@ -32,9 +32,9 @@ payload() data = val_pe_reg_read(ID_AA64PFR0_EL1); if (data & 0x0F00) //bits 11:8 for EL2 support - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; diff --git a/test_pool/pe/pe018.c b/test_pool/pe/pe018.c index 9f83c3d5..cb229626 100644 --- a/test_pool/pe/pe018.c +++ b/test_pool/pe/pe018.c @@ -41,9 +41,9 @@ payload() */ if ((VAL_EXTRACT_BITS(data, 40, 43) != 0x1)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } uint32_t diff --git a/test_pool/pe/pe019.c b/test_pool/pe/pe019.c index 7f2da9a9..e0202371 100644 --- a/test_pool/pe/pe019.c +++ b/test_pool/pe/pe019.c @@ -41,19 +41,19 @@ payload() if ((Gran4_2 == 0x1) && (Gran4 != 0xF)) { /* 4KB granule not supported at stage 2 & supported at stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } if ((Gran4_2 == 0x2) && (Gran4 != 0x0)) { /* 4KB granule size with 48-bit addresses supported at stage 2, but not stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } if ((Gran4_2 == 0x3) && (Gran4 != 0x1)) { /* 4KB granule size with 52-bit addresses supported at stage 2, but not stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -64,19 +64,19 @@ payload() if ((Gran16_2 == 0x1) && (Gran16 != 0x0)) { /* Stage 2 not supported 16KB granules & but stage 1 support */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } if ((Gran16_2 == 0x2) && (Gran16 != 0x1)) { /* 16KB granule size with 48-bit addresses supported at stage 2, but not stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } if ((Gran16_2 == 0x3) && (Gran16 != 0x2)) { /* 16KB granule size with 52-bit addresses supported at stage 2, but not stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); return; } @@ -87,17 +87,17 @@ payload() if ((Gran64_2 == 0x1) && (Gran64 != 0xF)) { /* Stage 2 not supported 64KB granules & but stage 1 support */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); return; } if ((Gran64_2 == 0x2) && (Gran64 != 0x0)) { /* 64KB granule size supported at stage 2, but not stage 1*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(8)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/pe/pe020.c b/test_pool/pe/pe020.c index f52ab656..3ea10592 100644 --- a/test_pool/pe/pe020.c +++ b/test_pool/pe/pe020.c @@ -37,16 +37,16 @@ payload() /* PMCR_EL0 Bits 15:11 for Number of counters. */ data = VAL_EXTRACT_BITS(val_pe_reg_read(PMCR_EL0), 11, 15); if (data > 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else { if (index == primary_pe_idx) { val_print(ERROR, "\n Number of PMU counters reported: %d, expected > 1", data); } - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } } else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } return; diff --git a/test_pool/pe/pe021.c b/test_pool/pe/pe021.c index b8ae8069..eaf29546 100644 --- a/test_pool/pe/pe021.c +++ b/test_pool/pe/pe021.c @@ -35,9 +35,9 @@ payload() /*bits [31:28] Number of breakpoints that are context-aware, minus 1*/ context_aware_breakpoints = VAL_EXTRACT_BITS(data, 28, 31) + 1; if (context_aware_breakpoints > 1) - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); else - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } diff --git a/test_pool/pe/pe022.c b/test_pool/pe/pe022.c index 4cb7c590..3172aa0a 100644 --- a/test_pool/pe/pe022.c +++ b/test_pool/pe/pe022.c @@ -39,9 +39,9 @@ payload_check_el3_support() /* Check if PE implements EL3 AArch64 execution state, ID_AA64PFR0_EL1[15:12] should be non-zero value */ if (feat_el3) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -65,10 +65,10 @@ payload_check_secure_state_support() /* Pass the test if Secure state is implemented via EL3 or SEL2 */ if (feat_sel2 || feat_el3) { - val_set_status(index, RESULT_PASS(TEST_NUM1, 1)); + val_set_status(index, RESULT_PASS); return; } else { - val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } diff --git a/test_pool/pe/pe023.c b/test_pool/pe/pe023.c index f00a7426..765366c7 100644 --- a/test_pool/pe/pe023.c +++ b/test_pool/pe/pe023.c @@ -44,17 +44,17 @@ payload(void) if (VAL_EXTRACT_BITS(data, 36, 43) == 0) { /* Implementation before Arm v8.5 */ if (VAL_EXTRACT_BITS(data, 24, 31) == 0) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } else { /* Implementation after Arm v8.5 */ if (((VAL_EXTRACT_BITS(data, 24, 31) == 0) || (VAL_EXTRACT_BITS(data, 24, 31) == 0x10)) && ((VAL_EXTRACT_BITS(data, 36, 43) == 0x22) || (VAL_EXTRACT_BITS(data, 36, 43) == 0x32))) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } } diff --git a/test_pool/pe/pe024.c b/test_pool/pe/pe024.c index 0b216477..3b747b19 100644 --- a/test_pool/pe/pe024.c +++ b/test_pool/pe/pe024.c @@ -36,9 +36,9 @@ payload(void) data = val_pe_reg_read(ID_AA64MMFR0_EL1); if (data & 0x0020) //bits 7:4 == 0010 - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; diff --git a/test_pool/pe/pe025.c b/test_pool/pe/pe025.c index 58655497..f1749574 100644 --- a/test_pool/pe/pe025.c +++ b/test_pool/pe/pe025.c @@ -37,9 +37,9 @@ payload(void) /* bits 1:0, 5:4, 9:8 and 13:12 must not be zero */ if ((data & 0x3) && (data & 0x30) && (data & 0x300) && (data & 0x3000)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; diff --git a/test_pool/pe/pe026.c b/test_pool/pe/pe026.c index 2c5ea92a..00e941e1 100644 --- a/test_pool/pe/pe026.c +++ b/test_pool/pe/pe026.c @@ -55,7 +55,7 @@ static void payload(void) if (VAL_EXTRACT_BITS(data2, 20, 23) == 0x2 || VAL_EXTRACT_BITS(data2, 28, 31) == 0x1) { val_print(TRACE, "\n System supports both FEAT_LPA & FEAT_LPA2 "); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } @@ -68,17 +68,17 @@ static void payload(void) /* If the base address is greater than 48 bits it is outside 256TB memory map */ if (IS_ADDR_EXCEEDS_48BITS(peri_base)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } peri_count--; } - val_set_status(index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(index, RESULT_PASS); } else { - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); } } diff --git a/test_pool/pe/pe027.c b/test_pool/pe/pe027.c index 34ad3e74..c04c060d 100644 --- a/test_pool/pe/pe027.c +++ b/test_pool/pe/pe027.c @@ -34,9 +34,9 @@ void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 28, 31); if (data == 0x0) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe027_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe028.c b/test_pool/pe/pe028.c index 9bdd19f7..1cb93c01 100644 --- a/test_pool/pe/pe028.c +++ b/test_pool/pe/pe028.c @@ -38,12 +38,12 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 0, 3); if (data == 0b0001 || data == 0b0010) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else { if (val_memory_check_for_persistent_mem()) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); } } diff --git a/test_pool/pe/pe029.c b/test_pool/pe/pe029.c index 03907bf1..4c1e5ef0 100644 --- a/test_pool/pe/pe029.c +++ b/test_pool/pe/pe029.c @@ -36,9 +36,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 4, 7); if (data == 0x2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe029_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe030.c b/test_pool/pe/pe030.c index dd6c8466..dd8f1157 100644 --- a/test_pool/pe/pe030.c +++ b/test_pool/pe/pe030.c @@ -36,9 +36,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 8, 11); if (data == 0x1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe030_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe031.c b/test_pool/pe/pe031.c index f1b80459..aa69d990 100644 --- a/test_pool/pe/pe031.c +++ b/test_pool/pe/pe031.c @@ -33,9 +33,9 @@ static void payload(void) */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 52, 55); if ((data == 0x1) || (data == 0x2)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe031_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe032.c b/test_pool/pe/pe032.c index e1010e4b..d30090f3 100644 --- a/test_pool/pe/pe032.c +++ b/test_pool/pe/pe032.c @@ -40,9 +40,9 @@ static void payload(void) * address authentication support using QARMA5 and QARMA3. */ if ((VAL_EXTRACT_BITS(data1, 4, 7) != 0) || (VAL_EXTRACT_BITS(data2, 12, 15) != 0)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe032_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe033.c b/test_pool/pe/pe033.c index 99b909ff..a4c404f8 100644 --- a/test_pool/pe/pe033.c +++ b/test_pool/pe/pe033.c @@ -34,9 +34,9 @@ static void payload(void) val_print_primary_pe(DEBUG, "\n ID_AA64PFR0_EL1.AMU[47:44] = %llx", data, index); if (data != 0) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe033_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe034.c b/test_pool/pe/pe034.c index 874b681f..2ccaae77 100644 --- a/test_pool/pe/pe034.c +++ b/test_pool/pe/pe034.c @@ -31,25 +31,25 @@ static void payload(void) if (!g_crypto_support) { val_print_primary_pe(DEBUG, "\n Crypto extension not supported", 0, index); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } /* Read ID_AA64ISAR0_EL1.SHA3[35:32] for cryptography support for SHA3 */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 32, 35); if (data == 0x1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } /* Read ID_AA64ISAR0_EL1.SHA3[15:12] for cryptography support for SHA512 */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 12, 15); if (data == 0x2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe034_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe035.c b/test_pool/pe/pe035.c index 72cf6b53..87e833ba 100644 --- a/test_pool/pe/pe035.c +++ b/test_pool/pe/pe035.c @@ -31,9 +31,9 @@ static void payload(void) /* Read ID_AA64MMFR2_EL1.FWB[43:40] for stage 2 control of memory types and cacheability */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 40, 43); if (data == 0x1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe035_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe036.c b/test_pool/pe/pe036.c index a0077168..eebf6ab0 100644 --- a/test_pool/pe/pe036.c +++ b/test_pool/pe/pe036.c @@ -40,11 +40,11 @@ static void payload(void) * Value 0 indicates nested virtualization not supported */ if (data == 0) - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); else if (data == 0x2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe036_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe037.c b/test_pool/pe/pe037.c index 4035aa5a..0b012530 100644 --- a/test_pool/pe/pe037.c +++ b/test_pool/pe/pe037.c @@ -38,7 +38,7 @@ void payload(void) if (data == 0) { /* SVE Not Implemented Skip the test */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -49,12 +49,12 @@ void payload(void) if (data == 0) /* SPE Not Implemented Skip the test */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); if (data == 1) /* SPE Implemented but SPEv1p1 not implemented. Fail the test*/ - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pe/pe038.c b/test_pool/pe/pe038.c index 4e6910a5..8f9205e5 100644 --- a/test_pool/pe/pe038.c +++ b/test_pool/pe/pe038.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 0, 3); if (data != 1) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe038_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe039.c b/test_pool/pe/pe039.c index 6f5e3b68..3b1b80b9 100644 --- a/test_pool/pe/pe039.c +++ b/test_pool/pe/pe039.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 60, 63); if (data != 1) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe039_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe040.c b/test_pool/pe/pe040.c index 2d004754..1e97e44b 100644 --- a/test_pool/pe/pe040.c +++ b/test_pool/pe/pe040.c @@ -41,9 +41,9 @@ static void payload_check_if_pmuv3_5(void) /* Read ID_AA64DFR0_EL1.PMUVer[11:8] >= 0b0110 and != 0xF for PMU v3.5 or higher support */ if ((data < PE_PMUv3p5) || (data == 0xF)) /* 0xF is PMUv3 not supported */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } static void payload_check_if_pmuv3_7(void) @@ -57,9 +57,9 @@ static void payload_check_if_pmuv3_7(void) /* Read ID_AA64DFR0_EL1.PMUVer[11:8] >= 0b0111 and != 0xF for PMU v3.7 or higher support */ if ((data < PE_PMUv3p7) || (data == 0xF)) - val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe040_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe041.c b/test_pool/pe/pe041.c index 413c4c9e..6e0e932f 100644 --- a/test_pool/pe/pe041.c +++ b/test_pool/pe/pe041.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 0, 3); if (data < 2) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe041_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe042.c b/test_pool/pe/pe042.c index ee4cf1de..a51368d0 100644 --- a/test_pool/pe/pe042.c +++ b/test_pool/pe/pe042.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 56, 59); if (data != 2) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe042_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe043.c b/test_pool/pe/pe043.c index 95f7ecef..902c9281 100644 --- a/test_pool/pe/pe043.c +++ b/test_pool/pe/pe043.c @@ -40,9 +40,9 @@ static void payload(void) val_print_primary_pe(DEBUG, "\n ID_AA64PFR0_EL1.CSV3 = %llx", data_csv3, index); if (((data_csv2 == 2) || (data_csv2 == 3)) && (data_csv3 == 1)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe043_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe044.c b/test_pool/pe/pe044.c index 8ade2061..1ecc0de1 100644 --- a/test_pool/pe/pe044.c +++ b/test_pool/pe/pe044.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7); if (data != 2) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe044_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe045.c b/test_pool/pe/pe045.c index 0df3a845..192567ed 100644 --- a/test_pool/pe/pe045.c +++ b/test_pool/pe/pe045.c @@ -34,9 +34,9 @@ payload() data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7); if (data == 0) - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/pe/pe046.c b/test_pool/pe/pe046.c index f574710d..1c3444e6 100644 --- a/test_pool/pe/pe046.c +++ b/test_pool/pe/pe046.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 36, 39); if (data != 1) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe046_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe047.c b/test_pool/pe/pe047.c index 8cdce498..c1e11f61 100644 --- a/test_pool/pe/pe047.c +++ b/test_pool/pe/pe047.c @@ -34,9 +34,9 @@ static void payload(void) val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.SPECRES = %llx", data, index); if (data != 1 && data != 2) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pe047_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe048.c b/test_pool/pe/pe048.c index 00ca727f..04b7c6db 100644 --- a/test_pool/pe/pe048.c +++ b/test_pool/pe/pe048.c @@ -34,9 +34,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 56, 59); if ((data != 1) && (data != 2)) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/pe/pe049.c b/test_pool/pe/pe049.c index 08d5f1f1..ceb370ba 100644 --- a/test_pool/pe/pe049.c +++ b/test_pool/pe/pe049.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 60, 63); if (data == 2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe049_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe051.c b/test_pool/pe/pe051.c index 786e3578..1752cf44 100644 --- a/test_pool/pe/pe051.c +++ b/test_pool/pe/pe051.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 52, 55); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe051_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe052.c b/test_pool/pe/pe052.c index 98bd6982..3f8cd11c 100644 --- a/test_pool/pe/pe052.c +++ b/test_pool/pe/pe052.c @@ -35,9 +35,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 44, 47); if ((data == 1) || (data == 2)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe052_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe053.c b/test_pool/pe/pe053.c index 66f8c94b..b90a1059 100644 --- a/test_pool/pe/pe053.c +++ b/test_pool/pe/pe053.c @@ -40,9 +40,9 @@ static void payload(void) */ if (((VAL_EXTRACT_BITS(data1, 4, 7) == 5) || (VAL_EXTRACT_BITS(data1, 4, 7) == 6)) || ((VAL_EXTRACT_BITS(data2, 12, 15) == 5) || (VAL_EXTRACT_BITS(data2, 12, 15) == 6))) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe053_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe054.c b/test_pool/pe/pe054.c index 1c34350a..b3b4a6b9 100644 --- a/test_pool/pe/pe054.c +++ b/test_pool/pe/pe054.c @@ -33,7 +33,7 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 32, 35); if (data == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -41,9 +41,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ZFR0_EL1), 44, 47); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe054_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe055.c b/test_pool/pe/pe055.c index 25bc2db2..7aaaa37b 100644 --- a/test_pool/pe/pe055.c +++ b/test_pool/pe/pe055.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 48, 51); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t c035_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe056.c b/test_pool/pe/pe056.c index dced153c..5c2e5fca 100644 --- a/test_pool/pe/pe056.c +++ b/test_pool/pe/pe056.c @@ -37,12 +37,12 @@ static void payload(void) val_print(DEBUG, "\n ID_AA64MMFR1_EL1.TWED = %llx", data); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else { if (index == primary_pe_idx) val_print(WARN, "\n Recommended WFE fine-tuning delay feature not implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); } } diff --git a/test_pool/pe/pe057.c b/test_pool/pe/pe057.c index 42b6fc1b..355e9919 100644 --- a/test_pool/pe/pe057.c +++ b/test_pool/pe/pe057.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 20, 23); if (data == 3) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe057_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe058.c b/test_pool/pe/pe058.c index 1048a711..d45f6ed5 100644 --- a/test_pool/pe/pe058.c +++ b/test_pool/pe/pe058.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 56, 59); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe058_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe059.c b/test_pool/pe/pe059.c index 2ea417e1..d64ff399 100644 --- a/test_pool/pe/pe059.c +++ b/test_pool/pe/pe059.c @@ -33,9 +33,9 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR2_EL1), 0, 3); if (data == 2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe059_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe060.c b/test_pool/pe/pe060.c index ae8c4460..547b93e9 100644 --- a/test_pool/pe/pe060.c +++ b/test_pool/pe/pe060.c @@ -34,9 +34,9 @@ static void payload(void) val_print_primary_pe(DEBUG, "\n ID_AA64ISAR1_EL1.LS64 = %llx", data, index); if (data >= 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe060_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe061.c b/test_pool/pe/pe061.c index 020c704a..41be9c54 100644 --- a/test_pool/pe/pe061.c +++ b/test_pool/pe/pe061.c @@ -35,7 +35,7 @@ static void payload(void) data, index); if (data == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -45,9 +45,9 @@ static void payload(void) data, index); if (data == 0x20 || data == 0x40) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe061_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe062.c b/test_pool/pe/pe062.c index d3fa4cf4..ff8dea18 100644 --- a/test_pool/pe/pe062.c +++ b/test_pool/pe/pe062.c @@ -39,15 +39,15 @@ static void payload(void) /* If FEAT_HPDS2 is not supported then PBHA bits cannot be enabled */ if (data != 2) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } else { /* Read CurrentEL which indicates the current exception level */ el = val_pe_reg_read(CurrentEL); if (el != AARCH64_EL1 && el != AARCH64_EL2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); val_print_primary_pe(DEBUG, "\n Current EL = %llx", el, index); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -83,7 +83,7 @@ static void payload(void) VAL_EXTRACT_BITS(data, 41, 41), index); val_print_primary_pe(DEBUG, "\n TCR_ELx.HWU0nn = %llx", VAL_EXTRACT_BITS(data, 43, 46), index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } } @@ -97,7 +97,7 @@ static void payload(void) VAL_EXTRACT_BITS(data, 42, 42), index); val_print_primary_pe(DEBUG, "\n TCR_ELx.HWU1nn = %llx", VAL_EXTRACT_BITS(data, 47, 50), index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } } @@ -113,7 +113,7 @@ static void payload(void) VAL_EXTRACT_BITS(data, 24, 24), index); val_print_primary_pe(DEBUG, "\n TCR_EL2.HWUnn = %llx", VAL_EXTRACT_BITS(data, 25, 28), index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } } @@ -122,7 +122,7 @@ static void payload(void) if (el != AARCH64_EL2) { val_print_primary_pe(WARN, "\n Current EL needs to be in EL2", 0, index); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -131,9 +131,9 @@ static void payload(void) if (VAL_EXTRACT_BITS(data, 25, 28) != 0) { val_print_primary_pe(DEBUG, "\n VTCR_EL2.HWUnn = %llx", VAL_EXTRACT_BITS(data, 25, 28), index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(index, RESULT_FAIL(05)); } else - val_set_status(index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(index, RESULT_PASS); } } diff --git a/test_pool/pe/pe065.c b/test_pool/pe/pe065.c index 406245de..9176c3fd 100644 --- a/test_pool/pe/pe065.c +++ b/test_pool/pe/pe065.c @@ -35,9 +35,9 @@ static void payload(void) data, index); if (data == 1) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } uint32_t pe065_entry(uint32_t num_pe) diff --git a/test_pool/pe/pe066.c b/test_pool/pe/pe066.c index 4eebf824..df2591b7 100644 --- a/test_pool/pe/pe066.c +++ b/test_pool/pe/pe066.c @@ -55,7 +55,7 @@ payload() val_print_primary_pe(ERROR, "\n Number of PE breakpoints reported: %d, expected >= 6", breakpointcount, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_FAIL(1)); return; } @@ -84,7 +84,7 @@ payload() val_print_primary_pe(ERROR, "\n Context-aware breakpoints reported: %u, expected >= 2", context_aware_breakpoints, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(pe_index, RESULT_FAIL(2)); return; } @@ -109,12 +109,12 @@ payload() /* Breakpoints 4 and 5 must be context-aware */ if (ctx_start <= 4 && ctx_end >= 5) - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(pe_index, RESULT_PASS); else { val_print_primary_pe(ERROR, "\n Breakpoints 4 and 5 are not context-aware as required", 0, pe_index); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(pe_index, RESULT_FAIL(3)); } } diff --git a/test_pool/pe/pe068.c b/test_pool/pe/pe068.c index daefe45d..097f8bcd 100644 --- a/test_pool/pe/pe068.c +++ b/test_pool/pe/pe068.c @@ -35,9 +35,9 @@ payload() /* Mask bits 15:11 for Number of counters */ if (((data & PMCR_NUM_COUNTERS_MASK) >> 11) >= 2) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; diff --git a/test_pool/peripherals/d001.c b/test_pool/peripherals/d001.c index 7a7b501a..5a7ba36e 100644 --- a/test_pool/peripherals/d001.c +++ b/test_pool/peripherals/d001.c @@ -30,9 +30,9 @@ /** @brief This functions checks if USBs in system implements preferred type passed as input. @param usb_type - Preferred USB type - @return test_status_t - Status of the check (PASS/FAIL/SKIP) + @return uint32_t - Status of the check (PASS/FAIL/SKIP) **/ -test_status_t check_for_usb_intrf (uint32_t usb_type) +uint32_t check_for_usb_intrf (uint32_t usb_type) { uint32_t interface = 0; uint32_t ret; @@ -131,17 +131,17 @@ void payload_ehci_check() { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - test_status_t status; + uint32_t status; /* Check if USB implements EHCI. If not, skip if it's XHCI; otherwise, fail. */ status = check_for_usb_intrf(USB_TYPE_EHCI); if (status == TEST_SKIP) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); } else if (status == TEST_FAIL) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } } @@ -150,17 +150,17 @@ void payload_xhci_check() { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - test_status_t status; + uint32_t status; /* Check if USB implements XHCI. If not, skip if it's EHCI; otherwise, fail. */ status = check_for_usb_intrf(USB_TYPE_XHCI); if (status == TEST_SKIP) { - val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(1)); } else if (status == TEST_FAIL) { - val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); + val_set_status(index, RESULT_FAIL(1)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM1, 1)); + val_set_status(index, RESULT_PASS); } } @@ -195,4 +195,4 @@ d008_entry(uint32_t num_pe) status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1); val_report_status(0, ACS_END(TEST_NUM1), NULL); return status; -} \ No newline at end of file +} diff --git a/test_pool/peripherals/d002.c b/test_pool/peripherals/d002.c index 46f94639..257d80ff 100644 --- a/test_pool/peripherals/d002.c +++ b/test_pool/peripherals/d002.c @@ -35,7 +35,7 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); if (count == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -45,7 +45,7 @@ payload() if (interface != SATA_TYPE_AHCI) { val_print(DEBUG, "\n Detected SATA CTRL not AHCI 0x%x ", interface); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } @@ -61,20 +61,20 @@ payload() if (ret == PCIE_NO_MAPPING) { val_print(DEBUG, " Reading device class code using PciIo" " protocol failed\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } interface = (interface >> 8) & 0xFF; if (interface != 0x01) { val_print(DEBUG, " Detected SATA CTRL not AHCI\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } } count--; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/peripherals/d003.c b/test_pool/peripherals/d003.c index f13a272c..da5eb006 100644 --- a/test_pool/peripherals/d003.c +++ b/test_pool/peripherals/d003.c @@ -162,19 +162,19 @@ isr() uart_disable_txintr(); val_print(DEBUG, "\n Received interrupt on %d ", int_id); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(int_id); } static -test_status_t +uint32_t check_arm_generic_uart() { uint32_t count = val_peripheral_get_info(NUM_UART, 0); uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t interface_type; - test_status_t status = TEST_STATUS_UNKNOWN; + uint32_t status = TEST_STATE_UNKNOWN; val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); @@ -221,7 +221,7 @@ check_arm_generic_uart() } static -test_status_t +uint32_t check_uart_16550() { uint64_t count = val_peripheral_get_info(NUM_UART, 0); @@ -366,7 +366,7 @@ static void payload_check_uart_compliance() { - test_status_t gen_uart_status, uart_16550_status; + uint32_t gen_uart_status, uart_16550_status; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Run the checks for Arm generic UART and 16550 compatible UART */ @@ -375,13 +375,13 @@ payload_check_uart_compliance() /* Pass if UART is found and is either one of the type required by test */ if (gen_uart_status == TEST_PASS || uart_16550_status == TEST_PASS) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); /* Skip if UART not found by test */ else if (gen_uart_status == TEST_SKIP || uart_16550_status == TEST_SKIP) - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); /* Fail if neither passed or both skipped */ else - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -396,10 +396,10 @@ payload_check_arm_generic_uart_interrupt() if (count == 0) { val_print(ERROR, "\n No UART defined by Platform "); - val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } - val_set_status(index, RESULT_SKIP(TEST_NUM1, 2)); + val_set_status(index, RESULT_SKIP(2)); while (count != 0) { timeout = TIMEOUT_LARGE; int_id = val_peripheral_get_info(UART_GSIV, count - 1); @@ -417,7 +417,7 @@ payload_check_arm_generic_uart_interrupt() /* Check int_id is SPI or ESPI */ if (!(IsSpi(int_id)) && !(val_gic_is_valid_espi(int_id))) { val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -432,7 +432,7 @@ payload_check_arm_generic_uart_interrupt() /* Install ISR */ if (val_gic_install_isr(int_id, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -450,16 +450,16 @@ payload_check_arm_generic_uart_interrupt() test_fail++; } } else { - val_set_status(index, RESULT_SKIP(TEST_NUM1, 3)); + val_set_status(index, RESULT_SKIP(3)); } } count--; } if (test_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM1, 4)); + val_set_status(index, RESULT_FAIL(4)); else - val_set_status(index, RESULT_PASS(TEST_NUM1, 2)); + val_set_status(index, RESULT_PASS); return; } @@ -505,4 +505,4 @@ d006_entry(uint32_t num_pe) status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1); val_report_status(0, ACS_END(TEST_NUM1), NULL); return status; -} \ No newline at end of file +} diff --git a/test_pool/peripherals/d004.c b/test_pool/peripherals/d004.c index d23366a9..dc3dd75b 100644 --- a/test_pool/peripherals/d004.c +++ b/test_pool/peripherals/d004.c @@ -52,7 +52,7 @@ payload_check_dma_mem_attribute(void) if (!target_dev_index) { val_print(INFO, "\n No DMA controllers detected... "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -83,7 +83,7 @@ payload_check_dma_mem_attribute(void) "\n DMA controller %d: Failed to get" " memory attributes\n", target_dev_index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); flag_fail = 1; continue; } @@ -97,17 +97,17 @@ payload_check_dma_mem_attribute(void) "\n DMA controller %d: DMA memory must be inner/outer writeback inner " "shareable, inner/outer non-cacheable, or device type\n", target_dev_index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); flag_fail = 1; } } /* PASS the test if no fail conditions hit */ if (!flag_fail) - val_set_status(index, RESULT_PASS(TEST_NUM, 0)); + val_set_status(index, RESULT_PASS); return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); } /* This test verifies I/O coherent DMA traffic must have the attribute @@ -131,7 +131,7 @@ payload_check_io_coherent_dma_mem_attribute(void) if (!target_dev_index) { val_print(INFO, "\n No DMA controllers detected... "); - val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -152,7 +152,7 @@ payload_check_io_coherent_dma_mem_attribute(void) val_print(ERROR, "\n DMA controller %d: Failed to get memory attributes\n", target_dev_index); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); + val_set_status(index, RESULT_FAIL(1)); flag_fail = 1; continue; } @@ -164,18 +164,18 @@ payload_check_io_coherent_dma_mem_attribute(void) target_dev_index); val_print(TRACE, " be inner/outer writeback, inner shareable\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 2)); + val_set_status(index, RESULT_FAIL(2)); flag_fail = 1; } } } /* PASS the test if no fail conditions hit */ if (!flag_fail) - val_set_status(index, RESULT_PASS(TEST_NUM1, 0)); + val_set_status(index, RESULT_PASS); return; test_warn_unimplemented: - val_set_status(index, RESULT_WARN(TEST_NUM1, 2)); + val_set_status(index, RESULT_WARNING(2)); } uint32_t diff --git a/test_pool/pfdi/pfdi001.c b/test_pool/pfdi/pfdi001.c index 093ed816..d183817f 100644 --- a/test_pool/pfdi/pfdi001.c +++ b/test_pool/pfdi/pfdi001.c @@ -34,7 +34,7 @@ static void payload_version_check(void *arg) if (pfdi_version.x0 >> 31) { val_print(ERROR, "\n PFDI get version failed err = %ld", pfdi_version.x0); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -42,21 +42,21 @@ static void payload_version_check(void *arg) if (val_pfdi_reserved_bits_check_is_zero( VAL_EXTRACT_BITS(pfdi_version.x0, 31, 63)) != ACS_STATUS_PASS) { val_print(ERROR, "\n Failed on PE = %d", index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } major = PFDI_VERSION_GET_MAJOR(pfdi_version.x0); if (major != PFDI_MAJOR_VERSION) { val_print(ERROR, "\n Major Version not as expected, Current version = %d", major); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } minor = PFDI_VERSION_GET_MINOR(pfdi_version.x0); if (minor != PFDI_MINOR_VERSION) { val_print(ERROR, "\n Minor Version not as expected, Current version = %d", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -67,11 +67,11 @@ static void payload_version_check(void *arg) val_print(ERROR, " x2=0x%llx", pfdi_version.x2); val_print(ERROR, " x3=0x%llx", pfdi_version.x3); val_print(ERROR, " x4=0x%llx", pfdi_version.x4); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/pfdi/pfdi002.c b/test_pool/pfdi/pfdi002.c index 663ff0db..952aaac6 100644 --- a/test_pool/pfdi/pfdi002.c +++ b/test_pool/pfdi/pfdi002.c @@ -39,7 +39,7 @@ pfdi_version_check(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -56,7 +56,7 @@ static void payload_all_pe_version_check(void *arg) g_pfdi_version_details = (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_version_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Version Details Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -78,7 +78,7 @@ static void payload_all_pe_version_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -133,9 +133,9 @@ static void payload_all_pe_version_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi003.c b/test_pool/pfdi/pfdi003.c index 7f3e78ea..98d7efe3 100644 --- a/test_pool/pfdi/pfdi003.c +++ b/test_pool/pfdi/pfdi003.c @@ -44,7 +44,7 @@ pfdi_function_check(void) fn_status++; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -60,7 +60,7 @@ static void payload_functions_check(void *arg) g_pfdi_feature_details = (feature_details *) val_memory_calloc(num_pe, sizeof(feature_details)); if (g_pfdi_feature_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Feature Details Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -84,7 +84,7 @@ static void payload_functions_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -112,9 +112,9 @@ static void payload_functions_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi004.c b/test_pool/pfdi/pfdi004.c index a3439716..6d6afae0 100644 --- a/test_pool/pfdi/pfdi004.c +++ b/test_pool/pfdi/pfdi004.c @@ -42,7 +42,7 @@ check_feature() status_buffer->x0 = status; val_pfdi_invalidate_ret_params(status_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -59,7 +59,7 @@ static void payload_feature_check(void *arg) if (g_pfdi_feature_check_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Feature Check Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -81,7 +81,7 @@ static void payload_feature_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -113,9 +113,9 @@ static void payload_feature_check(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi005.c b/test_pool/pfdi/pfdi005.c index f540569f..f54e8832 100644 --- a/test_pool/pfdi/pfdi005.c +++ b/test_pool/pfdi/pfdi005.c @@ -39,7 +39,7 @@ pfdi_st_version_check(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -58,7 +58,7 @@ static void payload_pe_test_id_check(void *arg) if (g_pfdi_st_version_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Self Test Version Details Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -80,7 +80,7 @@ static void payload_pe_test_id_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(i, RESULT_FAIL(5)); goto free_pfdi_details; } } @@ -143,9 +143,9 @@ static void payload_pe_test_id_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi006.c b/test_pool/pfdi/pfdi006.c index 3e28d048..01558a76 100644 --- a/test_pool/pfdi/pfdi006.c +++ b/test_pool/pfdi/pfdi006.c @@ -37,7 +37,7 @@ pfdi_test_part_count(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -75,7 +75,7 @@ static void payload_pe_test_info_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -112,9 +112,9 @@ static void payload_pe_test_info_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi007.c b/test_pool/pfdi/pfdi007.c index 7533c4aa..f2b1d20b 100644 --- a/test_pool/pfdi/pfdi007.c +++ b/test_pool/pfdi/pfdi007.c @@ -49,7 +49,7 @@ pfdi_test_run(void) if (test_parts < PFDI_ACS_SUCCESS) { pfdi_range->x0 = test_parts; val_pfdi_invalidate_ret_params(pfdi_range); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); return; } @@ -59,7 +59,7 @@ pfdi_test_run(void) &pfdi_range->x1, &pfdi_range->x2, &pfdi_range->x3, &pfdi_range->x4); val_pfdi_invalidate_ret_params(pfdi_range); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } static void payload_run(void *arg) @@ -75,7 +75,7 @@ static void payload_run(void *arg) (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_range_status == NULL) { val_print(ERROR, "\n Allocation for g_pfdi_range_status Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -83,7 +83,7 @@ static void payload_run(void *arg) (PFDI_RET_PARAMS *) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_all_parts_status == NULL) { val_print(ERROR, "\n Allocation for g_pfdi_all_parts_status Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_pfdi_details_range; } @@ -103,7 +103,7 @@ static void payload_run(void *arg) while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); goto free_pfdi_details_both; } } @@ -213,9 +213,9 @@ static void payload_run(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(i, RESULT_FAIL(5)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details_both: diff --git a/test_pool/pfdi/pfdi008.c b/test_pool/pfdi/pfdi008.c index e81504a8..fd77303f 100644 --- a/test_pool/pfdi/pfdi008.c +++ b/test_pool/pfdi/pfdi008.c @@ -39,7 +39,7 @@ pfdi_test_results(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -56,7 +56,7 @@ static void payload_test_results(void *arg) if (g_pfdi_results_status_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Results Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -78,7 +78,7 @@ static void payload_test_results(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -142,9 +142,9 @@ static void payload_test_results(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi009.c b/test_pool/pfdi/pfdi009.c index 4c29ad0c..2a09f0ef 100644 --- a/test_pool/pfdi/pfdi009.c +++ b/test_pool/pfdi/pfdi009.c @@ -39,7 +39,7 @@ pfdi_fw_check(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -56,7 +56,7 @@ static void payload_fw_check(void *arg) if (g_pfdi_fw_check_details == NULL) { val_print(ERROR, "\n Allocation for PFDI FW Check Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -78,7 +78,7 @@ static void payload_fw_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); goto free_pfdi_details; } } @@ -114,9 +114,9 @@ static void payload_fw_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi010.c b/test_pool/pfdi/pfdi010.c index 2bd64d5c..774d8ffd 100644 --- a/test_pool/pfdi/pfdi010.c +++ b/test_pool/pfdi/pfdi010.c @@ -39,7 +39,7 @@ check_invalid_fn() val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -56,7 +56,7 @@ static void payload_invalid_fn_check(void *arg) if (g_pfdi_invalid_fn_check_details == NULL) { val_print(ERROR, "\n Allocation for PFDI Reserved Function Support Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -78,7 +78,7 @@ static void payload_invalid_fn_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -110,9 +110,9 @@ static void payload_invalid_fn_check(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi011.c b/test_pool/pfdi/pfdi011.c index 38a6d553..0c4ebd8c 100644 --- a/test_pool/pfdi/pfdi011.c +++ b/test_pool/pfdi/pfdi011.c @@ -90,9 +90,9 @@ static void payload_regs_preserve_check(void *arg) } if (reg_verify_fail) - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/pfdi/pfdi012.c b/test_pool/pfdi/pfdi012.c index b5c02a4c..860f1043 100644 --- a/test_pool/pfdi/pfdi012.c +++ b/test_pool/pfdi/pfdi012.c @@ -134,7 +134,7 @@ static void pfdi_error_injection(void) val_pfdi_invalidate_ret_params(&err[i]); } - val_set_status(index, RESULT_PASS(test_num, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -278,7 +278,7 @@ static void pfdi_error_recovery(void) val_data_cache_ops_by_va((addr_t)&rec_buffer->norm_mode_status[i], CLEAN_AND_INVALIDATE); } - val_set_status(index, RESULT_PASS(test_num, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -295,7 +295,7 @@ static void payload_pfdi_error_injection(void *arg) if (g_pfdi_force_error_check == NULL) { val_print(ERROR, "\n Allocation for PFDI Force Error Check Failed"); - val_set_status(index, RESULT_FAIL(test_num, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -319,7 +319,7 @@ static void payload_pfdi_error_injection(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(test_num, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -361,9 +361,9 @@ static void payload_pfdi_error_injection(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(test_num, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(test_num, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: @@ -385,7 +385,7 @@ static void payload_pfdi_error_recovery_check(void *arg) if (g_pfdi_err_recovery_check == NULL) { val_print(ERROR, "\n Allocation for PFDI Error Recovery Check Failed"); - val_set_status(index, RESULT_FAIL(test_num, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -412,7 +412,7 @@ static void payload_pfdi_error_recovery_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(test_num, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_error_recovery; } } @@ -476,11 +476,11 @@ static void payload_pfdi_error_recovery_check(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(test_num, 3)); + val_set_status(i, RESULT_FAIL(3)); else if (run_skip) - val_set_status(i, RESULT_SKIP(test_num, 1)); + val_set_status(i, RESULT_SKIP(1)); else - val_set_status(i, RESULT_PASS(test_num, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_error_recovery: diff --git a/test_pool/pfdi/pfdi013.c b/test_pool/pfdi/pfdi013.c index 76b49878..2570dc99 100644 --- a/test_pool/pfdi/pfdi013.c +++ b/test_pool/pfdi/pfdi013.c @@ -44,7 +44,7 @@ check_pe_test_run_start_exceeds_end(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate that PFDI_PE_TEST_RUN returns INVALID_PARAMETERS for start > end */ @@ -60,7 +60,7 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -75,7 +75,7 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -109,9 +109,9 @@ payload_check_pe_test_run_start_exceeds_end(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi014.c b/test_pool/pfdi/pfdi014.c index c4d7d1be..59576b6c 100644 --- a/test_pool/pfdi/pfdi014.c +++ b/test_pool/pfdi/pfdi014.c @@ -39,7 +39,7 @@ check_pe_test_run_start_beyond_max(void) /* Get number of test parts supported on current PE */ test_parts = val_pfdi_pe_test_part_count(NULL, NULL, NULL, NULL); if (test_parts < PFDI_ACS_SUCCESS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -53,7 +53,7 @@ check_pe_test_run_start_beyond_max(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate test case where start index is beyond max supported index */ @@ -69,7 +69,7 @@ payload_check_pe_test_run_start_beyond_max(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -84,7 +84,7 @@ payload_check_pe_test_run_start_beyond_max(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -102,7 +102,7 @@ payload_check_pe_test_run_start_beyond_max(void *arg) if (IS_TEST_FAIL(val_get_status(i))) { val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); - val_set_status(i, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(i, RESULT_SKIP(1)); continue; } @@ -125,9 +125,9 @@ payload_check_pe_test_run_start_beyond_max(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(i, RESULT_FAIL(4)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi016.c b/test_pool/pfdi/pfdi016.c index 6c71af9f..f1079557 100644 --- a/test_pool/pfdi/pfdi016.c +++ b/test_pool/pfdi/pfdi016.c @@ -39,7 +39,7 @@ check_invalid_feature() val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -56,7 +56,7 @@ static void payload_invalid_feature_check(void *arg) if (g_pfdi_invalid_feature_check == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Feature Support Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -78,7 +78,7 @@ static void payload_invalid_feature_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -110,9 +110,9 @@ static void payload_invalid_feature_check(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi017.c b/test_pool/pfdi/pfdi017.c index 4f954b3a..cf848914 100644 --- a/test_pool/pfdi/pfdi017.c +++ b/test_pool/pfdi/pfdi017.c @@ -40,7 +40,7 @@ check_unsupp_fn() val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -57,7 +57,7 @@ static void payload_unsupp_fn_check(void *arg) if (g_pfdi_unsupp_function_check == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Feature Support Check Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -79,7 +79,7 @@ static void payload_unsupp_fn_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -111,9 +111,9 @@ static void payload_unsupp_fn_check(void *arg) } if (run_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi018.c b/test_pool/pfdi/pfdi018.c index 3dec196f..9c30fb59 100644 --- a/test_pool/pfdi/pfdi018.c +++ b/test_pool/pfdi/pfdi018.c @@ -39,7 +39,7 @@ check_pe_test_run_end_beyond_max(void) /* Get number of test parts supported on current PE */ test_parts = val_pfdi_pe_test_part_count(NULL, NULL, NULL, NULL); if (test_parts < PFDI_ACS_SUCCESS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -53,7 +53,7 @@ check_pe_test_run_end_beyond_max(void) val_pfdi_invalidate_ret_params(pfdi_buffer); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate that PFDI_PE_TEST_RUN returns INVALID_PARAMETERS for end > max index */ @@ -69,7 +69,7 @@ payload_check_pe_test_run_end_beyond_max(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -84,7 +84,7 @@ payload_check_pe_test_run_end_beyond_max(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -102,7 +102,7 @@ payload_check_pe_test_run_end_beyond_max(void *arg) if (IS_TEST_FAIL(val_get_status(i))) { val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); - val_set_status(i, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(i, RESULT_SKIP(1)); continue; } @@ -125,9 +125,9 @@ payload_check_pe_test_run_end_beyond_max(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(i, RESULT_FAIL(4)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi019.c b/test_pool/pfdi/pfdi019.c index a0c6dc83..0222ad03 100644 --- a/test_pool/pfdi/pfdi019.c +++ b/test_pool/pfdi/pfdi019.c @@ -51,7 +51,7 @@ check_pe_test_run_either_minus_one(void) &pfdi_buffer_case1->x3, &pfdi_buffer_case1->x4); val_pfdi_invalidate_ret_params(pfdi_buffer_case1); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate PFDI returns INVALID_PARAMETERS for start = -1 or end = -1 only */ @@ -68,7 +68,7 @@ payload_check_pe_test_run_either_minus_one(void *arg) val_memory_calloc(2 * num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -83,7 +83,7 @@ payload_check_pe_test_run_either_minus_one(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -124,9 +124,9 @@ payload_check_pe_test_run_either_minus_one(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(i, RESULT_FAIL(4)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi020.c b/test_pool/pfdi/pfdi020.c index 7c0a29f8..38d81cd5 100644 --- a/test_pool/pfdi/pfdi020.c +++ b/test_pool/pfdi/pfdi020.c @@ -43,7 +43,7 @@ check_pe_test_run_less_than_minus_one(void) /* Query number of supported test parts */ test_parts = val_pfdi_pe_test_part_count(NULL, NULL, NULL, NULL); if (test_parts < PFDI_ACS_SUCCESS) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -62,7 +62,7 @@ check_pe_test_run_less_than_minus_one(void) &pfdi_buffer_case1->x3, &pfdi_buffer_case1->x4); val_pfdi_invalidate_ret_params(pfdi_buffer_case1); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate that PFDI_PE_TEST_RUN returns INVALID_PARAMETERS for < -1 inputs */ @@ -79,7 +79,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) val_memory_calloc(2 * num_pe, sizeof(PFDI_RET_PARAMS)); if (g_pfdi_status == NULL) { val_print(ERROR, "\n Allocation for PFDI Run Function Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -94,7 +94,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -108,7 +108,7 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) if (IS_TEST_FAIL(val_get_status(i))) { val_print(ERROR, "\n Failed to get Test Part count on PE %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); continue; } @@ -142,9 +142,9 @@ payload_check_pe_test_run_less_than_minus_one(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(i, RESULT_FAIL(4)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi021.c b/test_pool/pfdi/pfdi021.c index 6048c2fa..d1c5e8dc 100644 --- a/test_pool/pfdi/pfdi021.c +++ b/test_pool/pfdi/pfdi021.c @@ -67,7 +67,7 @@ pfdi_invalid_version_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ static void payload_invalid_pe_version_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_version == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Version Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -109,7 +109,7 @@ static void payload_invalid_pe_version_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -147,9 +147,9 @@ static void payload_invalid_pe_version_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi022.c b/test_pool/pfdi/pfdi022.c index 904ec569..d3ecf9d8 100644 --- a/test_pool/pfdi/pfdi022.c +++ b/test_pool/pfdi/pfdi022.c @@ -61,7 +61,7 @@ pfdi_invalid_feature_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -79,7 +79,7 @@ static void payload_invalid_pe_feature_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_feature == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Feature Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -103,7 +103,7 @@ static void payload_invalid_pe_feature_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -140,9 +140,9 @@ static void payload_invalid_pe_feature_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi023.c b/test_pool/pfdi/pfdi023.c index 7665f4f7..0ad1ec11 100644 --- a/test_pool/pfdi/pfdi023.c +++ b/test_pool/pfdi/pfdi023.c @@ -67,7 +67,7 @@ pfdi_invalid_pe_test_id_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ static void payload_invalid_pe_test_id_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_pe_test_id == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid PE Test ID Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -109,7 +109,7 @@ static void payload_invalid_pe_test_id_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -147,9 +147,9 @@ static void payload_invalid_pe_test_id_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi024.c b/test_pool/pfdi/pfdi024.c index f3878c54..dc0b9e69 100644 --- a/test_pool/pfdi/pfdi024.c +++ b/test_pool/pfdi/pfdi024.c @@ -67,7 +67,7 @@ pfdi_invalid_test_parts_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ static void payload_invalid_pe_test_part_count_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_test_part_count == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Test Part Count Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -109,7 +109,7 @@ static void payload_invalid_pe_test_part_count_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -147,9 +147,9 @@ static void payload_invalid_pe_test_part_count_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi025.c b/test_pool/pfdi/pfdi025.c index 123be870..1581e9ed 100644 --- a/test_pool/pfdi/pfdi025.c +++ b/test_pool/pfdi/pfdi025.c @@ -67,7 +67,7 @@ pfdi_invalid_test_result_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ static void payload_invalid_pe_test_result_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_test_result == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Test Result Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -109,7 +109,7 @@ static void payload_invalid_pe_test_result_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -147,9 +147,9 @@ static void payload_invalid_pe_test_result_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi026.c b/test_pool/pfdi/pfdi026.c index 170bc81a..31b2e2c4 100644 --- a/test_pool/pfdi/pfdi026.c +++ b/test_pool/pfdi/pfdi026.c @@ -67,7 +67,7 @@ pfdi_invalid_fw_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ static void payload_invalid_pe_fw_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_fw_check == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Firmware Check Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -109,7 +109,7 @@ static void payload_invalid_pe_fw_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -147,9 +147,9 @@ static void payload_invalid_pe_fw_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi027.c b/test_pool/pfdi/pfdi027.c index 43e19501..545ea679 100644 --- a/test_pool/pfdi/pfdi027.c +++ b/test_pool/pfdi/pfdi027.c @@ -138,7 +138,7 @@ check_error_overwrite(void) result->first_call_x0 = (int64_t)val_pfdi_fw_check(NULL, NULL, NULL, NULL); val_data_cache_ops_by_va((addr_t)result, CLEAN_AND_INVALIDATE); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } /* Validate error injection overwrite behavior across all PEs */ @@ -154,7 +154,7 @@ payload_check_error_overwrite(void *arg) val_memory_calloc(num_pe * PFDI_FN_MAX_IDX, sizeof(pfdi_error_injection_results)); if (g_results == NULL) { val_print(ERROR, "\n Allocation for results Failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -171,7 +171,7 @@ payload_check_error_overwrite(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_results; } } @@ -234,11 +234,11 @@ payload_check_error_overwrite(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else if (test_skip) - val_set_status(i, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(i, RESULT_SKIP(1)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_results: diff --git a/test_pool/pfdi/pfdi028.c b/test_pool/pfdi/pfdi028.c index f112e14d..adc79653 100644 --- a/test_pool/pfdi/pfdi028.c +++ b/test_pool/pfdi/pfdi028.c @@ -129,7 +129,7 @@ call_pfdi_functions_on_other_pe(void) call_all_pfdi_functions(cross_pe); - val_set_status(index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(index, RESULT_PASS); return; } @@ -150,7 +150,7 @@ payload_check_pe_locality(void *arg) if (num_pe < 2) { val_print(WARN, "\n Test requires minimum 2 PEs, skipping"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -160,7 +160,7 @@ payload_check_pe_locality(void *arg) val_memory_calloc(1, sizeof(pfdi_pe_locality_check)); if (g_pfdi_pe_locality_check == NULL) { val_print(ERROR, "\n Memory allocation failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -188,7 +188,7 @@ payload_check_pe_locality(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** waiting for other PE index = %d", other_pe_index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); goto free_locality_buffer; } @@ -244,11 +244,11 @@ payload_check_pe_locality(void *arg) /* Report aggregate pass/fail for the calling PE */ if (test_fail) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); } else if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } free_locality_buffer: diff --git a/test_pool/pfdi/pfdi029.c b/test_pool/pfdi/pfdi029.c index bbddb520..10d4e9f8 100644 --- a/test_pool/pfdi/pfdi029.c +++ b/test_pool/pfdi/pfdi029.c @@ -57,7 +57,7 @@ pfdi_invalid_run_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -75,7 +75,7 @@ static void payload_invalid_run_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_run == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Test Run Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -99,7 +99,7 @@ static void payload_invalid_run_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -136,9 +136,9 @@ static void payload_invalid_run_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi030.c b/test_pool/pfdi/pfdi030.c index 350b9951..670ba4d2 100644 --- a/test_pool/pfdi/pfdi030.c +++ b/test_pool/pfdi/pfdi030.c @@ -57,7 +57,7 @@ pfdi_invalid_force_error_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -75,7 +75,7 @@ static void payload_invalid_force_error_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_RETURNS)); if (g_pfdi_invalid_force_error == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Force Error Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -99,7 +99,7 @@ static void payload_invalid_force_error_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -136,9 +136,9 @@ static void payload_invalid_force_error_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pfdi/pfdi031.c b/test_pool/pfdi/pfdi031.c index 05c457ed..cc9acec4 100644 --- a/test_pool/pfdi/pfdi031.c +++ b/test_pool/pfdi/pfdi031.c @@ -53,7 +53,7 @@ pfdi_force_error_invalid_fn_check(void) val_pfdi_invalidate_ret_params(&pfdi_buffer->inval[i]); } - val_set_status(index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(index, RESULT_PASS); return; } @@ -71,7 +71,7 @@ static void payload_force_error_invalid_fn_check(void *arg) val_memory_calloc(num_pe, sizeof(PFDI_INVAL_FUNC_RETURNS)); if (g_pfdi_force_error_invalid_fn == NULL) { val_print(ERROR, "\n Allocation for PFDI Invalid Force Error Failed \n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -95,7 +95,7 @@ static void payload_force_error_invalid_fn_check(void *arg) if (timeout == 0) { val_print(ERROR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(i, RESULT_FAIL(2)); goto free_pfdi_details; } } @@ -135,9 +135,9 @@ static void payload_force_error_invalid_fn_check(void *arg) } if (test_fail) - val_set_status(i, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(i, RESULT_FAIL(3)); else - val_set_status(i, RESULT_PASS(TEST_NUM, 1)); + val_set_status(i, RESULT_PASS); } free_pfdi_details: diff --git a/test_pool/pmu/pmu001.c b/test_pool/pmu/pmu001.c index 5fb1a841..1b6e7b33 100644 --- a/test_pool/pmu/pmu001.c +++ b/test_pool/pmu/pmu001.c @@ -51,7 +51,7 @@ isr() /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ val_pe_reg_write(PMOVSCLR_EL0, 0x1); val_print(TRACE, "\n Received PMUIRQ "); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(int_id); return; @@ -71,7 +71,7 @@ payload() if (int_id != 23) { timeout = 0; val_print(ERROR, "\n Incorrect PPI value %d ", int_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -84,7 +84,7 @@ payload() } if (timeout == 0) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); val_pe_reg_write(PMCR_EL0, pmcr_value); } diff --git a/test_pool/pmu/pmu002.c b/test_pool/pmu/pmu002.c index c9116cb7..daefd78a 100644 --- a/test_pool/pmu/pmu002.c +++ b/test_pool/pmu/pmu002.c @@ -33,9 +33,9 @@ payload() data = val_pe_reg_read(PMCR_EL0); if (((data & 0x0F800) >> 11) > 5) //bits 15:11 for Number of counters. - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; diff --git a/test_pool/pmu/pmu003.c b/test_pool/pmu/pmu003.c index 60a935e9..c321579d 100644 --- a/test_pool/pmu/pmu003.c +++ b/test_pool/pmu/pmu003.c @@ -37,9 +37,9 @@ static void payload(void) * MTPMU = 0x1: Implement the ARMv8.6-MTPMU extension. */ if ((VAL_EXTRACT_BITS(data, 48, 51) == 0xF) || (VAL_EXTRACT_BITS(data, 48, 51) == 0x1)) - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } diff --git a/test_pool/pmu/pmu004.c b/test_pool/pmu/pmu004.c index ccc88694..b394bc02 100644 --- a/test_pool/pmu/pmu004.c +++ b/test_pool/pmu/pmu004.c @@ -149,7 +149,7 @@ static void generate_pcie_traffic(uint32_t num_ecam, uint32_t max_dev) /* This routine tests the scenario for the specified node type and primary instance, as listed in the APMT ACPT table. */ -test_status_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE node_type, +uint32_t sys_pmu_test_scenario(TEST_SCENARIO_e scenario, PMU_NODE_INFO_TYPE node_type, uint64_t node_primary_instance) { uint32_t node_index; @@ -309,7 +309,7 @@ static void payload_check_sys_pmu_scenario(void *arg) uint64_t num_mem_range; uint64_t mc_prox_domain; uint8_t run_flag = 0; - test_status_t status; + uint32_t status; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); test_data_t *test_data = (test_data_t *)arg; @@ -327,7 +327,7 @@ static void payload_check_sys_pmu_scenario(void *arg) num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { val_print(ERROR, "\n No Proximity domains in the system"); - val_set_status(index, RESULT_FAIL(test_data->test_num, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -367,16 +367,16 @@ static void payload_check_sys_pmu_scenario(void *arg) if (!run_flag) { val_print(ERROR, "\n No PMU associated with PCIe interface"); - val_set_status(index, RESULT_FAIL(test_data->test_num, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(test_data->test_num, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } - val_set_status(index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(index, RESULT_PASS); } uint32_t pmu004_entry(uint32_t num_pe) diff --git a/test_pool/pmu/pmu005.c b/test_pool/pmu/pmu005.c index ed70fb20..aa0375f7 100644 --- a/test_pool/pmu/pmu005.c +++ b/test_pool/pmu/pmu005.c @@ -66,7 +66,7 @@ typedef struct { } test_data_t; /* This functions checks if counters collectively supports event list passed as parameter */ -test_status_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_events, +uint32_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_events, uint64_t node_primary_instance, PMU_NODE_INFO_TYPE node_type) { uint32_t counter, event_idx; @@ -123,7 +123,7 @@ test_status_t check_event_support(PMU_EVENT_TYPE_e *event_list, uint32_t num_eve /* This payload checks for presence PMU monitor(s) with required event list passed as parameter */ static void payload_check_pmu_monitors(void *arg) { - test_status_t status; + uint32_t status; uint64_t num_mem_range, mem_range_index, mc_prox_domain; uint64_t node_count, node_index, pcie_rc_id; uint32_t fail_cnt = 0; @@ -143,7 +143,7 @@ static void payload_check_pmu_monitors(void *arg) num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { val_print(ERROR, "\n No Proximity domains in the system"); - val_set_status(index, RESULT_FAIL(test_data->test_num, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -182,22 +182,22 @@ static void payload_check_pmu_monitors(void *arg) } } else { val_print(ERROR, "\n Invalid interface type passed to check_monitors()"); - val_set_status(index, RESULT_FAIL(test_data->test_num, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } if (!run_flag) { val_print(ERROR, "\n No PMU associated with PCIe interface"); - val_set_status(index, RESULT_FAIL(test_data->test_num, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(test_data->test_num, 05)); + val_set_status(index, RESULT_FAIL(05)); return; } - val_set_status(index, RESULT_PASS(test_data->test_num, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/pmu/pmu006.c b/test_pool/pmu/pmu006.c index c09b7e43..d00a5314 100644 --- a/test_pool/pmu/pmu006.c +++ b/test_pool/pmu/pmu006.c @@ -41,17 +41,17 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_pe_reg_read(PMBIDR_EL1), 5, 5); if (data == 1) { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } else { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } } /* Implementation of PMU_SPE is optional, skipping the test */ else - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } diff --git a/test_pool/pmu/pmu008.c b/test_pool/pmu/pmu008.c index 29202713..786c6404 100644 --- a/test_pool/pmu/pmu008.c +++ b/test_pool/pmu/pmu008.c @@ -44,7 +44,7 @@ static void payload1(void) { val_memcpy(src_buf, dest_buf, BUFFER_SIZE / 2); - val_set_status(remote_pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(remote_pe_index, RESULT_PASS); } /* This payload generates remote PE traffic for 4 MB*/ @@ -52,7 +52,7 @@ static void payload2(void) { val_memcpy(src_buf, dest_buf, BUFFER_SIZE); - val_set_status(remote_pe_index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(remote_pe_index, RESULT_PASS); } static uint32_t generate_traffic(uint64_t prox_domain, uint32_t size, void (*remote_traffic)(void)) @@ -117,12 +117,12 @@ static void payload(void) val_print(DEBUG, "\n PMU NODES = %d", node_count); if (node_count == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); val_print(INFO, "\n No PMU nodes found in APMT table"); val_print(INFO, "\n The test must be considered fail" " if system has CoreSight PMU"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -131,10 +131,10 @@ static void payload(void) cs_com |= val_pmu_get_info(PMU_NODE_CS_COM, node_index); } if (cs_com != 0x1) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); val_print(INFO, "\n No CoreSight PMU nodes found"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -142,7 +142,7 @@ static void payload(void) num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { val_print(ERROR, "\n No Proximity domains in the system"); - val_set_status(index, RESULT_WARN(TEST_NUM, 2)); + val_set_status(index, RESULT_WARNING(2)); return; } @@ -151,14 +151,14 @@ static void payload(void) pe_prox_domain = val_srat_get_info(SRAT_GICC_PROX_DOMAIN, pe_uid); if (pe_prox_domain == SRAT_INVALID_INFO) { val_print(ERROR, "\n Could not get proximity domain info for given PE"); - val_set_status(index, RESULT_WARN(TEST_NUM, 3)); + val_set_status(index, RESULT_WARNING(3)); return; } /* Get memory controller local to the primary PE */ mc_node_index = val_pmu_get_node_index(pe_prox_domain, PMU_NODE_MEM_CNTR); if (mc_node_index == PMU_INVALID_INDEX) { val_print(ERROR, "\n PMU node not found"); - val_set_status(index, RESULT_WARN(TEST_NUM, 4)); + val_set_status(index, RESULT_WARNING(4)); return; } @@ -166,7 +166,7 @@ static void payload(void) data = val_pmu_get_monitor_count(mc_node_index); if (data < 3) { val_print(ERROR, "\n PMU node must support atleast 3 counter"); - val_set_status(index, RESULT_WARN(TEST_NUM, 5)); + val_set_status(index, RESULT_WARNING(5)); return; } @@ -177,7 +177,7 @@ static void payload(void) val_print(ERROR, "\n Required PMU Event 0x%x not supported", config_events[i]); val_print(ERROR, " at node %d", mc_node_index); - val_set_status(index, RESULT_WARN(TEST_NUM, 6)); + val_set_status(index, RESULT_WARNING(6)); return; } } @@ -190,7 +190,7 @@ static void payload(void) remote_pe_prox_domain = val_srat_get_info(SRAT_GICC_REMOTE_PROX_DOMAIN, pe_prox_domain); if (remote_pe_prox_domain == SRAT_INVALID_INFO) { val_print(ERROR, "\n Could not get remote PE proximity domain"); - val_set_status(index, RESULT_WARN(TEST_NUM, 7)); + val_set_status(index, RESULT_WARNING(7)); return; } remote_pe_uid = val_srat_get_info(SRAT_GICC_PROC_UID, remote_pe_prox_domain); @@ -203,7 +203,7 @@ static void payload(void) status = generate_traffic(pe_prox_domain, BUFFER_SIZE / 2, payload1); if (status) { val_print(ERROR, "\n Memory allocation failed"); - val_set_status(index, RESULT_WARN(TEST_NUM, 8)); + val_set_status(index, RESULT_WARNING(8)); return; } @@ -222,7 +222,7 @@ static void payload(void) if (status) { val_print(ERROR, "\n Memory allocation failed"); - val_set_status(index, RESULT_WARN(TEST_NUM, 9)); + val_set_status(index, RESULT_WARNING(9)); return; } @@ -233,7 +233,7 @@ static void payload(void) /*Consider delta for results*/ for (i = 0 ; i < NUM_PMU_MON ; i++) { if (value2[i] <= value1[i]) { - val_set_status(index, RESULT_WARN(TEST_NUM, 10)); + val_set_status(index, RESULT_WARNING(10)); return; } } @@ -241,7 +241,7 @@ static void payload(void) /* Disable PMU monitors */ val_pmu_disable_all_monitors(mc_node_index); - val_set_status(index, RESULT_PASS(TEST_NUM, 03)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/pmu/pmu009.c b/test_pool/pmu/pmu009.c index c0cceccc..13b90ae7 100644 --- a/test_pool/pmu/pmu009.c +++ b/test_pool/pmu/pmu009.c @@ -48,12 +48,12 @@ static void payload(void) val_print(DEBUG, "\n PMU NODES = %d", pmu_node_count); if (pmu_node_count == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); val_print(INFO, "\n No PMU nodes found in APMT table"); val_print(INFO, "\n The test must be considered fail" " if system has CoreSight PMU"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -62,10 +62,10 @@ static void payload(void) cs_com |= val_pmu_get_info(PMU_NODE_CS_COM, node_index); } if (cs_com != 0x1) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); val_print(INFO, "\n No CoreSight PMU nodes found"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -74,14 +74,14 @@ static void payload(void) ret_status = val_pmu_get_multi_traffic_support_interface(&interface_acpiid, &num_traffic_support); if (ret_status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); return; } /* PMU info table index for the interface */ pmu_node_index = val_pmu_get_index_acpiid(interface_acpiid); if (pmu_node_index == PMU_INVALID_INDEX) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 05)); + val_set_status(index, RESULT_SKIP(05)); return; } @@ -89,7 +89,7 @@ static void payload(void) num_mon = val_pmu_get_monitor_count(pmu_node_index); if (num_mon == 0) { val_print(ERROR, "\n PMU node must support atleast 1 counter"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } @@ -104,7 +104,7 @@ static void payload(void) val_print(ERROR, "\n Required PMU Event 0x%x not supported", config_events[i]); val_print(ERROR, " at node %d", pmu_node_index); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); return; } val_pmu_enable_monitor(pmu_node_index, mon_index); @@ -113,11 +113,11 @@ static void payload(void) ret_status = val_generate_traffic(interface_acpiid, pmu_node_index, mon_index, config_events[i]); if (ret_status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(index, RESULT_WARN(TEST_NUM, 2)); + val_set_status(index, RESULT_WARNING(2)); return; } else if (ret_status) { val_print(ERROR, "\n workload generate function failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); return; } mon_count_value = val_pmu_read_count(pmu_node_index, mon_index); @@ -126,11 +126,11 @@ static void payload(void) ret_status = val_pmu_check_monitor_count_value(interface_acpiid, mon_count_value, config_events[i]); if (ret_status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(index, RESULT_WARN(TEST_NUM, 3)); + val_set_status(index, RESULT_WARNING(3)); return; } else if (ret_status) { val_print(ERROR, "\n count value not as expected"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 8)); + val_set_status(index, RESULT_FAIL(8)); return; } @@ -141,7 +141,7 @@ static void payload(void) /* Disable PMU monitors */ val_pmu_disable_all_monitors(pmu_node_index); - val_set_status(index, RESULT_PASS(TEST_NUM, 9)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/power_wakeup/u001.c b/test_pool/power_wakeup/u001.c index 8647e4ab..a0751766 100644 --- a/test_pool/power_wakeup/u001.c +++ b/test_pool/power_wakeup/u001.c @@ -37,7 +37,7 @@ isr1() val_timer_set_phy_el1(0); val_print(TRACE, " Received EL1 PHY interrupt\n"); g_el1phy_int_received = 1; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -54,7 +54,7 @@ payload1() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); if (val_gic_install_isr(intid, isr1)) { val_print(WARN, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } g_el1phy_int_received = 0; @@ -83,7 +83,7 @@ payload1() intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); val_print(DEBUG, "\n PE wakeup by some other events/int"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); } val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; diff --git a/test_pool/power_wakeup/u002.c b/test_pool/power_wakeup/u002.c index 3841563a..90858482 100644 --- a/test_pool/power_wakeup/u002.c +++ b/test_pool/power_wakeup/u002.c @@ -45,8 +45,9 @@ isr_failsafe() is hit and test interrupt is not rcvd */ if (g_el1vir_int_received == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -80,7 +81,7 @@ isr2() val_timer_set_vir_el1(0); val_print(TRACE, " Received EL1 VIRT interrupt\n"); g_el1vir_int_received = 1; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); @@ -99,7 +100,7 @@ payload2() intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); if (val_gic_install_isr(intid, isr2)) { val_print(WARN, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -133,9 +134,9 @@ payload2() val_timer_set_vir_el1(0); intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_end_of_interrupt(intid); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); val_print(DEBUG, "\n PE wakeup by some other events/int or didn't enter WFI"); + val_set_status(index, RESULT_SKIP(1)); } val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; diff --git a/test_pool/power_wakeup/u003.c b/test_pool/power_wakeup/u003.c index 611a7bd9..ac5445c3 100644 --- a/test_pool/power_wakeup/u003.c +++ b/test_pool/power_wakeup/u003.c @@ -44,8 +44,9 @@ isr_failsafe() is hit and test interrupt is not rcvd */ if (g_el2phy_int_rcvd == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -61,7 +62,7 @@ isr3() val_timer_set_phy_el2(0); val_print(TRACE, " Received EL2 Physical interrupt\n"); g_el2phy_int_rcvd = 1; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); @@ -99,7 +100,7 @@ payload3() intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); if (val_gic_install_isr(intid, isr3)) { val_print(WARN, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } g_failsafe_int_rcvd = 0; @@ -132,9 +133,9 @@ payload3() val_timer_set_phy_el2(0); intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_end_of_interrupt(intid); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); val_print(DEBUG, "\n PE wakeup by some other events/int or didn't enter WFI"); + val_set_status(index, RESULT_SKIP(1)); } val_print(TRACE, "\n delay loop remainig value %d", delay_loop); return; diff --git a/test_pool/power_wakeup/u004.c b/test_pool/power_wakeup/u004.c index a1f49a48..515b8185 100644 --- a/test_pool/power_wakeup/u004.c +++ b/test_pool/power_wakeup/u004.c @@ -45,8 +45,9 @@ isr_failsafe() is hit and test interrupt is not rcvd */ if (g_wd_int_received == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -99,11 +100,11 @@ payload4() wd_num = val_wd_get_info(0, WD_INFO_COUNT); // Assume a test passes until something causes a failure. - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); if (!wd_num) { val_print(DEBUG, "\n No watchdog implemented "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -130,7 +131,7 @@ payload4() if (status) { wakeup_clear_failsafe(); val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } val_power_enter_semantic(BSA_POWER_SEM_B); @@ -157,14 +158,14 @@ payload4() if (!(g_wd_int_received || g_failsafe_int_received)) { intid = val_wd_get_info(wd_num, WD_INFO_GSIV); val_gic_clear_interrupt(intid); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); val_print(DEBUG, "\n PE wakeup by some other events/int or didn't enter WFI"); + val_set_status(index, RESULT_SKIP(1)); } val_print(DEBUG, "\n delay loop remainig value %d", delay_loop); } else { val_print(WARN, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); } /* Disable watchdog so it doesn't trigger after this test. */ @@ -173,7 +174,7 @@ payload4() if (!ns_wdg) { val_print(DEBUG, " No non-secure watchdog implemented\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } diff --git a/test_pool/power_wakeup/u005.c b/test_pool/power_wakeup/u005.c index b20c4fa2..1e8bc26d 100644 --- a/test_pool/power_wakeup/u005.c +++ b/test_pool/power_wakeup/u005.c @@ -45,9 +45,10 @@ isr_failsafe() is hit and test interrupt is not rcvd */ if (g_timer_int_rcvd == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -63,7 +64,7 @@ isr5() val_timer_disable_system_timer((addr_t)cnt_base_n); val_print(TRACE, " Received Sys timer interrupt\n"); g_timer_int_rcvd = 1; - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); val_gic_end_of_interrupt(intid); val_timer_set_phy_el1(0); @@ -104,7 +105,7 @@ payload5() timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); if (!timer_num) { val_print(DEBUG, "\n No system timers implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -117,14 +118,14 @@ payload5() status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); if (status == ACS_STATUS_SKIP) { val_print(DEBUG, " Timer cntbase can't accessed\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { val_print(DEBUG, " Timer cntbase is invalid\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -158,7 +159,7 @@ payload5() if (!(g_timer_int_rcvd || g_failsafe_int_rcvd)) { intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); val_gic_clear_interrupt(intid); - val_set_status(index, RESULT_SKIP(TEST_NUM, 4)); + val_set_status(index, RESULT_SKIP(4)); val_print(DEBUG, "\n PE wakeup by some other events/int or didn't enter WFI", 0); } @@ -167,14 +168,14 @@ payload5() } else{ val_print(WARN, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } if (!ns_timer) { val_print(WARN, " No non-secure systimer implemented\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); + val_set_status(index, RESULT_SKIP(5)); return; } } diff --git a/test_pool/power_wakeup/u006.c b/test_pool/power_wakeup/u006.c index eaadea27..65cde1f2 100644 --- a/test_pool/power_wakeup/u006.c +++ b/test_pool/power_wakeup/u006.c @@ -48,7 +48,7 @@ isr() val_print(ERROR, "\n Setting watchdog timeout failed"); } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -107,7 +107,7 @@ payload_target_pe() val_gic_cpuif_init(); val_suspend_pe(0, 0); // Set the status to indicate that target PE has resumed execution from sleep mode - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } static @@ -142,7 +142,7 @@ payload() wakeup_event = wakeup_event_for_semantic_f(); if (wakeup_event == 0) { val_print(DEBUG, "\n No Watchdogs and system timers present"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -150,7 +150,7 @@ payload() val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); if (val_gic_install_isr(intid, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_gic_route_interrupt_to_pe(intid, index); return; } @@ -172,7 +172,7 @@ payload() status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } @@ -195,7 +195,7 @@ payload() status = val_wd_set_ws0(wd_num, 0); if (status) { val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } @@ -214,7 +214,7 @@ payload() val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); if (val_gic_install_isr(intid, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); val_gic_route_interrupt_to_pe(intid, index); return; } @@ -226,7 +226,7 @@ payload() status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } } @@ -249,7 +249,7 @@ payload() status = val_wd_set_ws0(wd_num, 0); if (status) { val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } } @@ -264,9 +264,9 @@ payload() val_execute_on_pe(target_pe, payload_dummy, 0); if (IS_TEST_FAIL(val_get_status(target_pe)) || IS_RESULT_PENDING(val_get_status(target_pe))) - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); // Step12: Route interrupt back to main PE*/ val_gic_route_interrupt_to_pe(intid, index); diff --git a/test_pool/ras/ras001.c b/test_pool/ras/ras001.c index 2ec6c4d8..59fbb103 100644 --- a/test_pool/ras/ras001.c +++ b/test_pool/ras/ras001.c @@ -46,7 +46,7 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -106,11 +106,11 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras002.c b/test_pool/ras/ras002.c index d24bb76b..2e70d69d 100644 --- a/test_pool/ras/ras002.c +++ b/test_pool/ras/ras002.c @@ -46,7 +46,7 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -120,11 +120,11 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras003.c b/test_pool/ras/ras003.c index 2a1ed724..a6ca38c9 100644 --- a/test_pool/ras/ras003.c +++ b/test_pool/ras/ras003.c @@ -45,12 +45,12 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } if (num_node < 2) { val_print(DEBUG, "\n RAS Nodes should be more than 1. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -106,14 +106,14 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } else if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras004.c b/test_pool/ras/ras004.c index dd065ba5..ed16461b 100644 --- a/test_pool/ras/ras004.c +++ b/test_pool/ras/ras004.c @@ -45,13 +45,13 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } if (num_node < 2) { val_print(DEBUG, "\n RAS Nodes should be more than 1. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -107,15 +107,15 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } else if (test_skip) { val_print(ERROR, "\n No ERI found in RAS nodes "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras005.c b/test_pool/ras/ras005.c index cd5fb58e..db46107a 100644 --- a/test_pool/ras/ras005.c +++ b/test_pool/ras/ras005.c @@ -65,7 +65,7 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -159,13 +159,13 @@ payload() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/ras/ras006.c b/test_pool/ras/ras006.c index 1f64d8f4..f67cbb09 100644 --- a/test_pool/ras/ras006.c +++ b/test_pool/ras/ras006.c @@ -63,7 +63,7 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -71,7 +71,7 @@ payload() status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -287,13 +287,13 @@ payload() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/ras/ras007.c b/test_pool/ras/ras007.c index 7f7c1045..9c86b014 100644 --- a/test_pool/ras/ras007.c +++ b/test_pool/ras/ras007.c @@ -46,7 +46,7 @@ payload() val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if system \ components supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -99,14 +99,14 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } else if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras008.c b/test_pool/ras/ras008.c index f53a4258..2434a638 100644 --- a/test_pool/ras/ras008.c +++ b/test_pool/ras/ras008.c @@ -52,7 +52,7 @@ esr(uint64_t interrupt_type, void *context) val_pe_update_elr(context, branch_to_test); val_print(ERROR, "\n Error : Received Sync Exception type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } static @@ -71,14 +71,14 @@ payload(void) if (count == 0) { val_print(WARN, "\n No UART defined by Platform "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } while (count != 0) { l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1); if (l_uart_base == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -88,7 +88,7 @@ payload(void) *((volatile uint32_t *)(l_uart_base + UART_RES)) = (uint32_t)(0xDEAD); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); count--; } diff --git a/test_pool/ras/ras009.c b/test_pool/ras/ras009.c index 348cf021..187a8394 100644 --- a/test_pool/ras/ras009.c +++ b/test_pool/ras/ras009.c @@ -73,7 +73,7 @@ payload() if (anerr == FEAT_ANERR_VAL2 || anerr == FEAT_ANERR_VAL3) { val_print(TRACE, "\n FEAT_ANERR implemented."); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } @@ -85,7 +85,7 @@ payload() status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { val_print(ERROR, "\n RAS nodes not found."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -93,7 +93,7 @@ payload() status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { val_print(ERROR, "\n RAS MC nodes not found."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -143,7 +143,7 @@ payload() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } branch_to_test = &&exception_return; @@ -203,13 +203,13 @@ payload() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/ras/ras010.c b/test_pool/ras/ras010.c index 3b02b802..f7a1d3be 100644 --- a/test_pool/ras/ras010.c +++ b/test_pool/ras/ras010.c @@ -41,7 +41,7 @@ payload() num_of_mem_blocks = val_ras2_get_mem_info(RAS2_NUM_MEM_BLOCK, 0); if (num_of_mem_blocks == 0) { val_print(DEBUG, "\n No nodes in RAS2 table or RAS2 table not present"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -57,11 +57,11 @@ payload() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/ras/ras011.c b/test_pool/ras/ras011.c index 80d18c62..8c8acb24 100644 --- a/test_pool/ras/ras011.c +++ b/test_pool/ras/ras011.c @@ -89,7 +89,7 @@ payload_poison_supported() status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -98,7 +98,7 @@ payload_poison_supported() status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -107,7 +107,7 @@ payload_poison_supported() status = val_ras_get_info(RAS_INFO_NODE_INDEX_FOR_AFF, mpidr, &pe_node_index); if (status) { val_print(DEBUG, "\n RAS Node not found for PE"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -115,7 +115,7 @@ payload_poison_supported() poison_check = val_ras_check_plat_poison_support(); if (!poison_check) { val_print(ERROR, "\n Poison storage & forward not supported. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -164,7 +164,7 @@ payload_poison_supported() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } branch_to_test = &&exception_return; @@ -251,13 +251,13 @@ payload_poison_supported() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(index, RESULT_FAIL(04)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } @@ -290,7 +290,7 @@ payload_poison_unsupported() status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -299,7 +299,7 @@ payload_poison_unsupported() status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); if (status || (num_mc_node == 0)) { val_print(ERROR, "\n RAS MC nodes not found. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM1, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -308,7 +308,7 @@ payload_poison_unsupported() status = val_ras_get_info(RAS_INFO_NODE_INDEX_FOR_AFF, mpidr, &pe_node_index); if (status) { val_print(DEBUG, "\n RAS Node not found for PE"); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -316,7 +316,7 @@ payload_poison_unsupported() poison_check = val_ras_check_plat_poison_support(); if (poison_check) { val_print(ERROR, "\n Poison storage & forward supported. Skipping..."); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } @@ -365,7 +365,7 @@ payload_poison_unsupported() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } branch_to_test = &&exception_return; @@ -422,17 +422,17 @@ payload_poison_unsupported() } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM1, 04)); + val_set_status(index, RESULT_FAIL(04)); return; } else if (warn_cnt) { - val_set_status(index, RESULT_WARN(TEST_NUM1, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } else if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM1, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras012.c b/test_pool/ras/ras012.c index ac3eab58..e713f36d 100644 --- a/test_pool/ras/ras012.c +++ b/test_pool/ras/ras012.c @@ -56,7 +56,7 @@ payload() status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); if (status || (num_node == 0)) { val_print(DEBUG, "\n RAS Nodes not found. Skipping..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -84,7 +84,7 @@ payload() if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } branch_to_test = &&exception_return; @@ -92,7 +92,7 @@ payload() /* Setup an error in an implementation defined way */ status = val_ras_setup_error(err_in_params, &err_out_params); if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -118,13 +118,13 @@ payload() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/ras/ras013.c b/test_pool/ras/ras013.c index a6aa7cd4..9ce0eef5 100644 --- a/test_pool/ras/ras013.c +++ b/test_pool/ras/ras013.c @@ -47,7 +47,7 @@ static void payload(void) val_print(DEBUG, "\n No RAS Nodes found in AEST table."); val_print(DEBUG, "\n The test must be considered fail if PE \ supports RAS nodes"); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } /* Get Number of RAS nodes */ @@ -95,16 +95,16 @@ static void payload(void) } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } else if (test_skip) { val_print(ERROR, "\n No Resource are Shared between two or more PE. " "Skipping... ", 0); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ras013_entry(uint32_t num_pe) diff --git a/test_pool/ras/ras014.c b/test_pool/ras/ras014.c index f4235ae1..e6ab63a3 100644 --- a/test_pool/ras/ras014.c +++ b/test_pool/ras/ras014.c @@ -87,14 +87,14 @@ static void payload(void) } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } else if (test_skip) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t ras014_entry(uint32_t num_pe) diff --git a/test_pool/ras/ras016.c b/test_pool/ras/ras016.c index b244a9a6..3c5b0507 100644 --- a/test_pool/ras/ras016.c +++ b/test_pool/ras/ras016.c @@ -47,7 +47,7 @@ payload() { val_print(ERROR, "\n RASv2 not implemented (ID_AA64PFR0_EL1.RAS = 0x%x).", ras_field); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -56,7 +56,7 @@ payload() if (status || (num_nodes == 0)) { val_print(ERROR, "\n RAS Nodes not found. "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -97,9 +97,9 @@ payload() } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras017.c b/test_pool/ras/ras017.c index 04b21267..eb5ef581 100644 --- a/test_pool/ras/ras017.c +++ b/test_pool/ras/ras017.c @@ -47,7 +47,7 @@ payload(void) val_print(ERROR, "\n RASv2 not implemented (ID_AA64PFR0_EL1.RAS = 0x%x).", ras_field); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -55,7 +55,7 @@ payload(void) status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_nodes); if (status || (num_nodes == 0)) { val_print(ERROR, "\n RAS Nodes not found. "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -129,9 +129,9 @@ payload(void) } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/ras/ras018.c b/test_pool/ras/ras018.c index 4453ccef..522b81e1 100644 --- a/test_pool/ras/ras018.c +++ b/test_pool/ras/ras018.c @@ -72,7 +72,7 @@ payload() if (aderr == FEAT_ADERR_VAL2 || aderr == FEAT_ADERR_VAL3) { val_print(TRACE, "\n FEAT_ADERR implemented."); - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); return; } @@ -86,7 +86,7 @@ payload() val_print(ERROR, "\n RAS nodes not found. " "Firmware interface is missing. Please conduct a paper-based analysis."); - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); return; } @@ -111,7 +111,7 @@ payload() if (!dev_addr) { val_print(ERROR, "\n Failed to obtain Device memory address.\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -123,7 +123,7 @@ payload() status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); if (status) { val_print(ERROR, "\n Failed in installing the exception handler"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } branch_to_test = &&exception_return; @@ -184,18 +184,18 @@ payload() if (usable_node_cnt == 0) { val_print(TRACE, "\n No usable MMIO RAS nodes -- skipping test.\n"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } if (fail_cnt) - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); else if (warn_cnt) - val_set_status(index, RESULT_WARN(TEST_NUM, 01)); + val_set_status(index, RESULT_WARNING(01)); else if (test_skip) - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); else - val_set_status(index, RESULT_PASS(TEST_NUM, 02)); + val_set_status(index, RESULT_PASS); return; } diff --git a/test_pool/smmu/i001.c b/test_pool/smmu/i001.c index 1270a9f0..44a5d47e 100644 --- a/test_pool/smmu/i001.c +++ b/test_pool/smmu/i001.c @@ -36,7 +36,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -50,11 +50,11 @@ payload() } if ((smmuv2_flag) && (smmuv3_flag)) { val_print(ERROR, "\n ALL SMMUs are not of the same Architecture version\n"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i002.c b/test_pool/smmu/i002.c index 8e793154..29646602 100644 --- a/test_pool/smmu/i002.c +++ b/test_pool/smmu/i002.c @@ -40,7 +40,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -68,7 +68,7 @@ payload() /*PE FEAT_LPA2 is implemeted, SMMU must support 4KB granule size and 52-bit * addressing. i.e data_oas == 0x6*/ if ((is_smmu_4k != 1) && (data_oas != 0x6)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_print(ERROR, "\n PE supports 4kB granule and FEAT_LPA2 is " "implemented, but SMMU %x does not support 52 bit " "addressing", num_smmu); @@ -83,7 +83,7 @@ payload() /*PE FEAT_LPA2 is implemeted, SMMU must support 16KB granule size and 52-bit * addressing. i.e data_oas == 0x6*/ if ((is_smmu_16k != 1) && (data_oas != 0x6)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); val_print(ERROR, "\n PE supports 16kB granule and FEAT_LPA2 is " "implemented, but SMMU %x does not support 52 bit " " addressing", num_smmu); @@ -95,7 +95,7 @@ payload() if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 28, 31) == 0x0) || (VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x2)) { if (is_smmu_4k != 1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); val_print(ERROR, "\n PE supports 4kB granules, " "but SMMU %x does not", num_smmu); return; @@ -106,7 +106,7 @@ payload() if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 20, 23) == 0x1) || (VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x2)) { if (is_smmu_16k != 1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); val_print(ERROR, "\n PE supports 16kB granules, " "but SMMU %x does not", num_smmu); return; @@ -117,7 +117,7 @@ payload() if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 24, 27) == 0x0) || (VAL_EXTRACT_BITS(data_pe_mmfr0, 36, 39) == 0x2)) { if (is_smmu_64k != 1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); val_print(ERROR, "\n PE supports 64kB granules, " "but SMMU %x does not", num_smmu); return; @@ -125,7 +125,7 @@ payload() } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i003.c b/test_pool/smmu/i003.c index acfa9900..52fdc6e9 100644 --- a/test_pool/smmu/i003.c +++ b/test_pool/smmu/i003.c @@ -39,7 +39,7 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(DEBUG, "\n No SMMU Controllers are discovered"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -66,14 +66,14 @@ payload() } if (smmu_52bit && (data_pa_range == 0x6)) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } if (((smmu_52bit == 0) || (data_pa_range != 0x6)) && memmap_addr_52bit) { val_print(ERROR, "\n PE or SMMU doesn't support 52-bit, \ but uefi mem map has 52-bit addr"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -82,7 +82,7 @@ payload() system physical addr space is 52-bit addr,but uefi mem map doesn't map any 52 bit addr. In this case if PE or SMMU is not supporting 52-bit addressing, test will skip */ - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); } uint32_t diff --git a/test_pool/smmu/i004.c b/test_pool/smmu/i004.c index 8e592e35..10085c22 100644 --- a/test_pool/smmu/i004.c +++ b/test_pool/smmu/i004.c @@ -51,7 +51,7 @@ payload(void *arg) num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(test_data->test_num, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -68,7 +68,7 @@ payload(void *arg) if (!s1ts) { val_print(ERROR, "\n SMMUv2 not providing Stage1 functionality "); - val_set_status(index, RESULT_FAIL(test_data->test_num, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } @@ -82,25 +82,25 @@ payload(void *arg) if (!s1p) { val_print(ERROR, "\n SMMUv3.%d not providing Stage1 functionality ", minor); - val_set_status(index, RESULT_FAIL(test_data->test_num, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } else { /* If both PE & SMMU Implement S_EL2, Skip this test */ val_print(DEBUG, "\n S-EL2 implemented...Skipping"); - val_set_status(index, RESULT_SKIP(test_data->test_num, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } } if (smmu_rev < 2) { val_print(ERROR, "\n SMMU revision must be at least v2 "); - val_set_status(index, RESULT_FAIL(test_data->test_num, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } - val_set_status(index, RESULT_PASS(test_data->test_num, 1)); + val_set_status(index, RESULT_PASS); } uint32_t @@ -146,4 +146,4 @@ i031_entry(uint32_t num_pe) return status; -} \ No newline at end of file +} diff --git a/test_pool/smmu/i005.c b/test_pool/smmu/i005.c index 283410ba..8ead2b39 100644 --- a/test_pool/smmu/i005.c +++ b/test_pool/smmu/i005.c @@ -30,7 +30,7 @@ /* This function iterates over all SMMU present in system and checks if it supports stage 2 translation support */ -test_status_t check_smmu_stg2_support (void) +uint32_t check_smmu_stg2_support (void) { uint32_t num_smmu; uint32_t i; @@ -86,14 +86,14 @@ payload_check_smmu_stg2_support() if its behind SMMU with stage 2 support, hence checking super set that all SMMUs support stage 2 translation, report as warning if failure */ - test_status_t status; + uint32_t status; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); status = check_smmu_stg2_support(); if (status == TEST_FAIL) { - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } } @@ -101,7 +101,7 @@ static void payload_check_sel2_and_smmu_stg2_support() { - test_status_t status; + uint32_t status; uint32_t pe_s_el2; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); @@ -111,7 +111,7 @@ payload_check_sel2_and_smmu_stg2_support() /* Skip the test if Secure EL2 is implemented */ if (pe_s_el2 == 0x1) { val_print(DEBUG, "\n Secure EL2 is supported, skipping the test."); - val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } diff --git a/test_pool/smmu/i006.c b/test_pool/smmu/i006.c index d57557db..eaa95973 100644 --- a/test_pool/smmu/i006.c +++ b/test_pool/smmu/i006.c @@ -34,26 +34,26 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(DEBUG, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { val_print(DEBUG, "\n Not valid for SMMU v3 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } if (!val_iovirt_check_unique_ctx_intid(num_smmu)) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); val_print(ERROR, "\n Unique interrupt ID per context bank check " "failed for SMMU %x"); + val_set_status(index, RESULT_FAIL(1)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 0)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i007.c b/test_pool/smmu/i007.c index 9822087a..f61af079 100644 --- a/test_pool/smmu/i007.c +++ b/test_pool/smmu/i007.c @@ -37,7 +37,7 @@ payload() data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); if (data == 0) { val_print(WARN, "\n PCIe Subsystem not discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -45,14 +45,14 @@ payload() if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -60,12 +60,12 @@ payload() // Check I/O coherent access if (VAL_EXTRACT_BITS(data, 4, 4) == 0) { val_print(ERROR, "\n\t IO-Coherent access not supported "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/smmu/i008.c b/test_pool/smmu/i008.c index 167090b7..7cc926d8 100644 --- a/test_pool/smmu/i008.c +++ b/test_pool/smmu/i008.c @@ -44,7 +44,7 @@ payload_check_smmu_stg1_support(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -53,7 +53,7 @@ payload_check_smmu_stg1_support(void) if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { val_print(ERROR, "\n SMMUv3, or higher must be supported."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } else { val_print(TRACE, "\n Detected SMMUv3, or higher implementation "); @@ -61,13 +61,13 @@ payload_check_smmu_stg1_support(void) /* Check Stage 1 translation support */ if ((data & BIT1) == 0) { val_print(ERROR, "\n Stage 1 translation not supported "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } static @@ -81,7 +81,7 @@ payload_check_smmu_stg2_support(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered."); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -90,7 +90,7 @@ payload_check_smmu_stg2_support(void) if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { val_print(ERROR, "\n SMMUv3, or higher must be supported."); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } else { val_print(TRACE, "\n Detected SMMUv3, or higher implementation "); @@ -98,13 +98,13 @@ payload_check_smmu_stg2_support(void) /* Check Stage 2 translation support */ if ((data & BIT0) == 0) { val_print(ERROR, "\n Stage 2 translation not supported "); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(index, RESULT_PASS); } uint32_t @@ -137,4 +137,4 @@ i025_entry(uint32_t num_pe) status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1); val_report_status(0, ACS_END(TEST_NUM1), TEST_RULE1); return status; -} \ No newline at end of file +} diff --git a/test_pool/smmu/i009.c b/test_pool/smmu/i009.c index f25acecd..98889c64 100644 --- a/test_pool/smmu/i009.c +++ b/test_pool/smmu/i009.c @@ -44,7 +44,7 @@ check_smmuv3_2_or_higher(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -66,9 +66,9 @@ check_smmuv3_2_or_higher(void) } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } } @@ -87,7 +87,7 @@ payload_check_l1_l2_table_resizing(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM1, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -113,9 +113,9 @@ payload_check_l1_l2_table_resizing(void) } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM1, 01)); + val_set_status(index, RESULT_FAIL(01)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM1, 01)); + val_set_status(index, RESULT_PASS); } } @@ -132,7 +132,7 @@ payload_check_smmuv3_3_or_higher(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM2, 01)); + val_set_status(index, RESULT_SKIP(01)); return; } @@ -155,9 +155,9 @@ payload_check_smmuv3_3_or_higher(void) } if (fail_cnt) { - val_set_status(index, RESULT_FAIL(TEST_NUM2, 01)); + val_set_status(index, RESULT_FAIL(01)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM2, 01)); + val_set_status(index, RESULT_PASS); } } diff --git a/test_pool/smmu/i010.c b/test_pool/smmu/i010.c index 3c971490..79f4bb5d 100644 --- a/test_pool/smmu/i010.c +++ b/test_pool/smmu/i010.c @@ -42,14 +42,14 @@ payload() if (!s_el2) { val_print(ERROR, "\n Secure EL2 not implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -59,14 +59,14 @@ payload() if (smmu_rev < 3) { val_print(ERROR, "\n SMMUv2 or lower detected: revision must be v3.2 or higher "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } else { minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); if (minor < 2) { val_print(ERROR, "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } s1p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 1, 1); @@ -74,14 +74,14 @@ payload() val_print(ERROR, "\n SMMUv3.%d detected: but " "Stage 1 translation not supported ", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i011.c b/test_pool/smmu/i011.c index 1a75df75..b484d763 100644 --- a/test_pool/smmu/i011.c +++ b/test_pool/smmu/i011.c @@ -42,14 +42,14 @@ payload() if (!s_el2) { val_print(ERROR, "\n Secure EL2 not implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -59,14 +59,14 @@ payload() if (smmu_rev < 3) { val_print(ERROR, "\n SMMUv2 or lower detected: revision must be v3.2 or higher "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } else { minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); if (minor < 2) { val_print(ERROR, "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } s2p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 0, 0); @@ -74,14 +74,14 @@ payload() val_print(ERROR, "\n SMMUv3.%d detected: but Stage 2 " "translation not supported ", minor); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i012.c b/test_pool/smmu/i012.c index 4bab05bb..0f772a58 100644 --- a/test_pool/smmu/i012.c +++ b/test_pool/smmu/i012.c @@ -47,13 +47,13 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(DEBUG, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } if (!(pe_mpam || frac)) { val_print(DEBUG, "\n No MPAM controlled resources present "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -62,7 +62,7 @@ payload() if (smmu_rev < 3) { /* MPAM support not required for SMMUv2 and below */ val_print(DEBUG, "\n SMMU revision v2 or lower detected "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } else { @@ -78,7 +78,7 @@ payload() if (!(mpam && max_id)) { val_print(ERROR, "\n SMMU without MPAM support detected "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } @@ -86,13 +86,13 @@ payload() /* MPAM support not required for SMMUv3.0/3.1 */ val_print(WARN, "\n SMMU revision v3.0/3.1 detected "); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i013.c b/test_pool/smmu/i013.c index c29317dd..369f937e 100644 --- a/test_pool/smmu/i013.c +++ b/test_pool/smmu/i013.c @@ -38,14 +38,14 @@ payload(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -53,12 +53,12 @@ payload(void) /* Check If SMMU_IDR0.HTTU == 0b10 */ if (data != 2) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i014.c b/test_pool/smmu/i014.c index b03d0568..8e13d585 100644 --- a/test_pool/smmu/i014.c +++ b/test_pool/smmu/i014.c @@ -38,14 +38,14 @@ payload() if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -53,12 +53,12 @@ payload() /* Check If SMMU_IDR0.MSI[13:13] == 0b1*/ if (data != 0b1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i015.c b/test_pool/smmu/i015.c index bdb7e77d..d0f90bad 100644 --- a/test_pool/smmu/i015.c +++ b/test_pool/smmu/i015.c @@ -41,28 +41,28 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 18, 18); if (!data && pe_vmid) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_print(ERROR, "\n 16 bit VMID not " "supported for SMMU %x", num_smmu); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i016.c b/test_pool/smmu/i016.c index 20a63f79..3574e31c 100644 --- a/test_pool/smmu/i016.c +++ b/test_pool/smmu/i016.c @@ -38,21 +38,21 @@ payload() data_va_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 16, 19); if (data_va_range == 0) { val_print(DEBUG, "\n Large VA Not Supported by PE "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Large VA Not Supported in SMMUv2"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -62,13 +62,13 @@ payload() if (data_va_range == 1) { if (data_vax != 1) { val_print(ERROR, "\n Large VA Not Supported in SMMU %x", num_smmu); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i017.c b/test_pool/smmu/i017.c index 2cc008dd..33b5151a 100644 --- a/test_pool/smmu/i017.c +++ b/test_pool/smmu/i017.c @@ -39,7 +39,7 @@ payload() if (data_pe_tlb != 0x2) { val_print(DEBUG, "\n TLB Range Invalid Not " "Supported For PE "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -47,7 +47,7 @@ payload() if (num_smmu == 0) { val_print(DEBUG, "\n No SMMU Controllers are discovered" " "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -55,7 +55,7 @@ payload() if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { val_print(DEBUG, "\n Not valid for SMMUv2 or older" "version "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -66,13 +66,13 @@ payload() if (data_ril != 0x1) { val_print(ERROR, "\n Range Invalidation unsupported " "for SMMU %x", num_smmu); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i018.c b/test_pool/smmu/i018.c index 60884567..e0332eea 100644 --- a/test_pool/smmu/i018.c +++ b/test_pool/smmu/i018.c @@ -42,14 +42,14 @@ payload() if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -59,14 +59,14 @@ payload() asid = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 12, 12); if (s1p && !asid && pe_asid) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_print(ERROR, "\n 16 bit ASID unsupported " "for SMMU %x", num_smmu); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i019.c b/test_pool/smmu/i019.c index f901ae01..5e0e8827 100644 --- a/test_pool/smmu/i019.c +++ b/test_pool/smmu/i019.c @@ -41,7 +41,7 @@ payload() if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -55,7 +55,7 @@ payload() while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -63,20 +63,20 @@ payload() if ((data_pe_endian == 1) && ((data == 1) || (data == 2))) { /* If PE supports big endian */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); val_print(ERROR, "\n PE supports big endian, " "but SMMU %x does not", num_smmu); return; } else if ((data_pe_endian == 0) && ((data == 1) || (data == 3))) { /* If PE supports little endian */ - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); val_print(ERROR, "\n PE supports little endian, " "but SMMU %x does not", num_smmu); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i020.c b/test_pool/smmu/i020.c index 01c86cbf..96e86ec6 100644 --- a/test_pool/smmu/i020.c +++ b/test_pool/smmu/i020.c @@ -41,14 +41,14 @@ payload(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -56,12 +56,12 @@ payload(void) /* Check If SMMU_IDR0.COHACC == 1*/ if (data != 1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i021.c b/test_pool/smmu/i021.c index 7fe6e0d3..526aaf76 100644 --- a/test_pool/smmu/i021.c +++ b/test_pool/smmu/i021.c @@ -123,11 +123,11 @@ static void payload_pmcg_present(void) uint32_t result = check_smmu_pmcg(0); if (result == ACS_STATUS_SKIP) - val_set_status(index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(index, RESULT_SKIP(01)); else val_set_status(index, result == ACS_STATUS_FAIL ? - RESULT_FAIL(TEST_NUM, 01) : - RESULT_PASS(TEST_NUM, 01)); + RESULT_FAIL(01) : + RESULT_PASS); } /** @@ -139,11 +139,11 @@ static void payload_counter_check(void) uint32_t result = check_smmu_pmcg(1); if (result == ACS_STATUS_SKIP) - val_set_status(index, RESULT_SKIP(TEST_NUM1, 01)); + val_set_status(index, RESULT_SKIP(01)); else val_set_status(index, result == ACS_STATUS_FAIL ? - RESULT_FAIL(TEST_NUM1, 01) : - RESULT_PASS(TEST_NUM1, 01)); + RESULT_FAIL(01) : + RESULT_PASS); } /** diff --git a/test_pool/smmu/i022.c b/test_pool/smmu/i022.c index 502b936c..c7e8bddc 100644 --- a/test_pool/smmu/i022.c +++ b/test_pool/smmu/i022.c @@ -84,12 +84,12 @@ payload() } if (test_fails) - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); else if (!num_dma_req) { val_print(DEBUG, "\n No DMA requestors present"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } } diff --git a/test_pool/smmu/i023.c b/test_pool/smmu/i023.c index 9e1f5c8a..c585c9c7 100644 --- a/test_pool/smmu/i023.c +++ b/test_pool/smmu/i023.c @@ -47,13 +47,13 @@ payload(void) status = val_get_device_path("ARMHC97C", etr_path); if (status != 0) { val_print(ERROR, "\n Unable to get ETR device info from ACPI namespace"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } if ((char)etr_path[0][0] == '\0') { val_print(ERROR, "\n No ETR devices are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } else { /*Counting num of ETR Devices*/ @@ -98,21 +98,21 @@ payload(void) if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) { val_print(DEBUG, "\n val_smmu_is_etr_behind_catu API not implemented"); - val_set_status(index, RESULT_WARN(TEST_NUM, 1)); + val_set_status(index, RESULT_WARNING(1)); return; } else if (status) { val_print(DEBUG, "\n No CATU found in ETR path at index %d", i); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } } if (!smmu_found) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/smmu/i024.c b/test_pool/smmu/i024.c index bc93136a..135020b7 100644 --- a/test_pool/smmu/i024.c +++ b/test_pool/smmu/i024.c @@ -36,14 +36,14 @@ static void payload(void) if (num_smmu == 0) { val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 02)); + val_set_status(index, RESULT_SKIP(02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(03)); return; } @@ -52,12 +52,12 @@ static void payload(void) data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 10, 10); if (data != 1) { val_print(ERROR, "\n ATS is not supported for Smmu Index : %d ", num_smmu); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t i024_entry(uint32_t num_pe) diff --git a/test_pool/smmu/i025.c b/test_pool/smmu/i025.c index 3deda853..c86dd713 100644 --- a/test_pool/smmu/i025.c +++ b/test_pool/smmu/i025.c @@ -54,7 +54,7 @@ payload() if (num_smmu == 0) { val_print(DEBUG, "\n No SMMU Controllers are discovered" " "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -62,7 +62,7 @@ payload() if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) { val_print(DEBUG, "\n Not valid for SMMUv2 or older" "version "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -73,13 +73,13 @@ payload() if (data_btm != 0x1) { val_print(ERROR, "\n Broadcast TLB Maintenance unsupported " "for SMMU %x", num_smmu); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } } } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } uint32_t diff --git a/test_pool/timer/t001.c b/test_pool/timer/t001.c index 47d108e2..c9a927a2 100644 --- a/test_pool/timer/t001.c +++ b/test_pool/timer/t001.c @@ -41,10 +41,10 @@ payload_check_system_counter_presence() if (counter_freq == 0) { val_print(DEBUG, "\n Generic system counter not implemented," " CNTFRQ_EL0 = 0"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } } @@ -78,7 +78,7 @@ payload_check_system_timer_freq() /* Check if Generic system counter frequency is greater than 10MHz */ if (counter_freq > 10*1000*1000) { - val_set_status(index, RESULT_PASS(TEST_NUM1, 1)); + val_set_status(index, RESULT_PASS); return; } @@ -88,7 +88,7 @@ payload_check_system_timer_freq() else val_print(ERROR, "\n Counter frequency is %ld KHz", print_freq); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); + val_set_status(index, RESULT_FAIL(1)); } uint32_t diff --git a/test_pool/timer/t002.c b/test_pool/timer/t002.c index 2267e050..26595be3 100644 --- a/test_pool/timer/t002.c +++ b/test_pool/timer/t002.c @@ -41,14 +41,14 @@ payload() if ((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON) && (val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON) && (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON)) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } else { val_print(ERROR, "\n PE Timers are not always-on\n" " And no system wake up timer"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } } else { - val_set_status(index, RESULT_PASS(TEST_NUM, 2)); + val_set_status(index, RESULT_PASS); } } diff --git a/test_pool/timer/t003.c b/test_pool/timer/t003.c index e2948913..5fabf6fa 100644 --- a/test_pool/timer/t003.c +++ b/test_pool/timer/t003.c @@ -37,7 +37,7 @@ payload() if (!timer_num) { val_print(DEBUG, "\n No System timers are defined "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -53,7 +53,7 @@ payload() if (cnt_ctl_base == 0) { val_print(DEBUG, "\n CNTCTL BASE is zero "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } //Read CNTACR to determine whether access permission from NS state is permitted @@ -61,7 +61,7 @@ payload() if (status == ACS_STATUS_SKIP) { val_print(DEBUG, "\n Security doesn't allow access to timer registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -71,13 +71,13 @@ payload() if (data != val_mmio_read(cnt_ctl_base + CNTTIDR)) { val_print(DEBUG, "\n Read-write check failed for" " CNTCTLBase.CNTTIDR, expected value %x ", data); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } if (cnt_base_n == 0) { val_print(DEBUG, "\n CNT_BASE_N is zero "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 4)); + val_set_status(index, RESULT_SKIP(4)); return; } @@ -89,8 +89,8 @@ payload() val_mmio_write64(cnt_base_n + CNTPCT_LOWER, (data1 - ARBIT_VALUE)); if (val_mmio_read64(cnt_base_n + CNTPCT_LOWER) < data1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); val_print(DEBUG, "\n CNTBaseN: CNTPCT reg must be read-only "); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -102,8 +102,8 @@ payload() val_mmio_write64(cnt_base_n + CNTVCT_LOWER, (data1 - ARBIT_VALUE)); if (val_mmio_read64(cnt_base_n + CNTVCT_LOWER) < data1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); val_print(DEBUG, "\n CNTBaseN: CNTVCT reg must be read-only "); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -116,8 +116,8 @@ payload() val_mmio_write(cnt_base_n + CNTBaseN_CNTFRQ, (data - ARBIT_VALUE)); if (val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ) != data) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); val_print(DEBUG, "\n CNTBaseN: CNTFRQ reg must be read-only "); + val_set_status(index, RESULT_FAIL(4)); return; } @@ -129,7 +129,7 @@ payload() "CNTBaseN.CNTP_CTL, expected value %x ", data); val_print(DEBUG, "\n Read value %x ", val_mmio_read(cnt_base_n + CNTP_CTL)); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); val_mmio_write(cnt_base_n + CNTP_CTL, 0x0); // Disable the timer before return return; } @@ -145,7 +145,7 @@ payload() val_print(DEBUG, "\n Read-write check failed for " "CNTBaseN.CNTP_CVAL[31:0], read value %x ", val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER)); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); + val_set_status(index, RESULT_FAIL(6)); return; } @@ -153,16 +153,16 @@ payload() val_print(DEBUG, "\n Read-write check failed for" " CNTBaseN.CNTP_CVAL[63:32], read value %x ", val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER)); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } if (!ns_timer) { val_print(DEBUG, "\n No non-secure systimer implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); + val_set_status(index, RESULT_SKIP(5)); return; } diff --git a/test_pool/timer/t004.c b/test_pool/timer/t004.c index 06b6cc77..623d1340 100644 --- a/test_pool/timer/t004.c +++ b/test_pool/timer/t004.c @@ -36,7 +36,7 @@ isr() val_print(TRACE, "\n Received sys timer interrupt "); val_timer_disable_system_timer((addr_t)cnt_base_n); - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); val_gic_end_of_interrupt(intid); } @@ -54,7 +54,7 @@ payload() if (!timer_num) { val_print(DEBUG, "\n No System timers are defined "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -73,14 +73,14 @@ payload() if (status == ACS_STATUS_SKIP) { val_print(WARN, "\n Security doesn't allow access to timer registers "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { val_print(WARN, "\n CNT_BASE_N is zero "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -89,14 +89,14 @@ payload() /* Check intid is SPI or ESPI */ if (!(IsSpi(intid)) && !(val_gic_is_valid_espi(intid))) { val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } /* Install ISR */ if (val_gic_install_isr(intid, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } @@ -108,14 +108,14 @@ payload() if (timeout == 0) { val_print(ERROR, "\n Sys timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } } if (!ns_timer) { val_print(WARN, "\n No non-secure systimer implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 5)); + val_set_status(index, RESULT_SKIP(5)); return; } diff --git a/test_pool/timer/t005.c b/test_pool/timer/t005.c index 5d51dde9..5b82c371 100644 --- a/test_pool/timer/t005.c +++ b/test_pool/timer/t005.c @@ -86,7 +86,7 @@ payload() if (!ns_timer) { val_print(DEBUG, "\n No non-secure systimer implemented"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -94,7 +94,7 @@ payload() cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); if (cnt_base_n == 0) { val_print(WARN, "\n CNT_BASE_N is zero "); - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(2)); return; } @@ -118,7 +118,7 @@ payload() val_timer_disable_system_timer((addr_t)cnt_base_n); val_gic_clear_interrupt(intid); val_timer_set_phy_el1(0); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); return; } @@ -127,7 +127,7 @@ payload() val_timer_disable_system_timer((addr_t)cnt_base_n); val_gic_clear_interrupt(intid); val_timer_set_phy_el1(0); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } @@ -143,9 +143,9 @@ payload() /* Check whether count is moved or not*/ if ((timer_cnt < ((pe_timer_ticks - sys_timer_ticks) + (sys_timer_ticks/100))) && (timer_cnt != 0)) - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); else - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); } uint32_t diff --git a/test_pool/timer/t006.c b/test_pool/timer/t006.c index f9fdfbda..b54e1a05 100644 --- a/test_pool/timer/t006.c +++ b/test_pool/timer/t006.c @@ -48,11 +48,11 @@ payload() val_print(ERROR, "\n Counter frequency is %ld KHz", print_freq); if (counter_freq >= 50*1000*1000) { - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); return; } - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); } uint32_t diff --git a/test_pool/timer/t008.c b/test_pool/timer/t008.c index 052a82dc..22a436dc 100644 --- a/test_pool/timer/t008.c +++ b/test_pool/timer/t008.c @@ -136,11 +136,11 @@ void payload(void) } if (test_fail == 1) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/tpm/tpm001.c b/test_pool/tpm/tpm001.c index cae023b4..67a12f9b 100644 --- a/test_pool/tpm/tpm001.c +++ b/test_pool/tpm/tpm001.c @@ -37,7 +37,7 @@ payload() tpm_is_present = val_tpm2_get_info(TPM2_INFO_IS_PRESENT); if (tpm_is_present == 0) { val_print(ERROR, "\n TPM not present"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -45,12 +45,12 @@ payload() tpm_family_version = val_tpm2_get_version(); if (tpm_family_version != 2) { val_print(ERROR, "\n TPM version is not 2.0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(pe_index, RESULT_FAIL(02)); return; } /* TPM is present and version is 2.0 */ - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/tpm/tpm002.c b/test_pool/tpm/tpm002.c index cccc7ea4..c009d59b 100644 --- a/test_pool/tpm/tpm002.c +++ b/test_pool/tpm/tpm002.c @@ -43,7 +43,7 @@ payload() tpm_present = val_tpm2_get_info(TPM2_INFO_IS_PRESENT); if (tpm_present == 0) { val_print(ERROR, "\n TPM not present"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_FAIL(01)); return; } @@ -58,7 +58,7 @@ payload() tpm_start_method == TPM_IF_START_METHOD_CRB_FFA) { val_print(TRACE, "\n Skipping test: TPM locality not accessible at current privilege level"); - val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(01)); return; } @@ -93,7 +93,7 @@ payload() cap_locality = VAL_EXTRACT_BITS(interface_id_val, 8, 8); /* CapLocality is bit[8] */ if (cap_locality == 0) { val_print(ERROR, "\n TPM FIFO interface supports only locality 0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(pe_index, RESULT_FAIL(03)); return; } } @@ -117,7 +117,7 @@ payload() cap_locality = VAL_EXTRACT_BITS(interface_id_val, 8, 8); /* CapLocality is bit[8] */ if (cap_locality == 0) { val_print(ERROR, "\n TPM CRB interface supports only locality 0"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04)); + val_set_status(pe_index, RESULT_FAIL(04)); return; } } @@ -125,12 +125,12 @@ payload() /* Step 7: Catch any unknown/unhandled interface types */ else { val_print(ERROR, "\n Invalid TPM interface type per TPM2 spec"); - val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 05)); + val_set_status(pe_index, RESULT_FAIL(05)); return; } /* Interface supports localities 0 - 4 */ - val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(pe_index, RESULT_PASS); return; } diff --git a/test_pool/watchdog/w001.c b/test_pool/watchdog/w001.c index 7dee9cd3..47de07c7 100644 --- a/test_pool/watchdog/w001.c +++ b/test_pool/watchdog/w001.c @@ -43,9 +43,9 @@ payload() if (wd_num == 0) { if (g_build_sbsa || g_build_pcbsa) - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } @@ -65,21 +65,21 @@ payload() data = val_mmio_read(ctrl_base); /*Control register bits 31:3 are reserved 0*/ if (data >> WD_CSR_RSRV_SHIFT) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } data = val_mmio_read(refresh_base); /*refresh frame offset 0 must return 0 on reads.*/ if (data) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } /* WOR.Upper word [31:16] is reserved & must be zero */ data = val_mmio_read(ctrl_base + WD_OR_UPPER_WORD_OFFSET); if (data >> WD_OR_RSRV_SHIFT) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } } while (wd_num); @@ -87,15 +87,16 @@ payload() if (!ns_wdg) { if (g_build_sbsa || g_build_pcbsa) { val_print(ERROR, "\n No non-secure Watchdogs reported"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); + } else { val_print(WARN, "\n No non-secure Watchdogs reported"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(3)); } return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); } diff --git a/test_pool/watchdog/w002.c b/test_pool/watchdog/w002.c index 2123551e..cc0476ba 100644 --- a/test_pool/watchdog/w002.c +++ b/test_pool/watchdog/w002.c @@ -66,8 +66,9 @@ isr_failsafe() is hit and test interrupt is not rcvd */ if (g_wd_int_received == 0) { - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); } + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -105,14 +106,14 @@ payload() if (wd_num == 0) { val_print(DEBUG, "\n No Watchdogs reported %d ", wd_num); if (g_build_sbsa || g_build_pcbsa) - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + val_set_status(index, RESULT_FAIL(1)); else - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(1)); return; } /* Assume pass until proven otherwise. */ - val_set_status(index, RESULT_PASS(TEST_NUM, 1)); + val_set_status(index, RESULT_PASS); do { wd_num--; /*array index starts from 0, so subtract 1 from count*/ @@ -128,14 +129,14 @@ payload() /* Check intid is SPI or ESPI */ if (!(IsSpi(int_id)) && !(val_gic_is_valid_espi(int_id))) { val_print(ERROR, "\n Interrupt-%d is neither SPI nor ESPI", int_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 2)); + val_set_status(index, RESULT_FAIL(2)); return; } /* Install ISR */ if (val_gic_install_isr(int_id, isr)) { val_print(ERROR, "\n GIC Install Handler Failed..."); - val_set_status(index, RESULT_FAIL(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(3)); return; } @@ -149,7 +150,7 @@ payload() status = val_wd_set_ws0(wd_num, timer_expire_ticks); if (status) { val_print(ERROR, "\n Setting watchdog timeout failed"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(4)); return; } wakeup_set_failsafe(); @@ -166,13 +167,13 @@ payload() if (g_failsafe_int_received && (g_wd_int_received == 0)) { val_print(ERROR, "\n Failsafe interrupt received, no WS0 interrupt"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 7)); + val_set_status(index, RESULT_FAIL(7)); return; } if ((timeout == 0) && (g_wd_int_received == 0)) { val_print(ERROR, "\n WS0 Interrupt not rcvd within timeout %d", int_id); - val_set_status(index, RESULT_FAIL(TEST_NUM, 5)); + val_set_status(index, RESULT_FAIL(5)); return; } @@ -181,10 +182,10 @@ payload() if (!ns_wdg) { if (g_build_sbsa || g_build_pcbsa) { val_print(ERROR, "\n No non-secure Watchdogs reported"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 6)); } else { val_print(WARN, "\n No non-secure Watchdogs reported"); - val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); + val_set_status(index, RESULT_FAIL(6)); + val_set_status(index, RESULT_SKIP(3)); } return; } diff --git a/test_pool/watchdog/w003.c b/test_pool/watchdog/w003.c index 29980018..7712e184 100644 --- a/test_pool/watchdog/w003.c +++ b/test_pool/watchdog/w003.c @@ -38,7 +38,7 @@ payload(void) if (wd_num == 0) { val_print(WARN, "\n No Watchdogs reported %d ", wd_num); - val_set_status(index, RESULT_FAIL(TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(01)); return; } @@ -58,7 +58,7 @@ payload(void) if (data != 1) { val_print(ERROR, "\n Watchdog Architecture version is %x", data); - val_set_status(index, RESULT_FAIL(TEST_NUM, 02)); + val_set_status(index, RESULT_FAIL(02)); return; } @@ -66,11 +66,11 @@ payload(void) if(!ns_wdg) { val_print(WARN, "\n No non-secure Watchdogs reported"); - val_set_status(index, RESULT_FAIL(TEST_NUM, 03)); + val_set_status(index, RESULT_FAIL(03)); return; } - val_set_status(index, RESULT_PASS(TEST_NUM, 01)); + val_set_status(index, RESULT_PASS); } diff --git a/val/ValLib.inf b/val/ValLib.inf index 18e66488..ee2d2054 100644 --- a/val/ValLib.inf +++ b/val/ValLib.inf @@ -32,6 +32,7 @@ src/AArch64/Drtm.S src/AArch64/SystemReg.S src/acs_status.c + src/val_status.c src/acs_pe.c src/acs_pe_infra.c src/acs_gic.c diff --git a/val/ValLibRB.inf b/val/ValLibRB.inf index 4866a764..b6455d4e 100644 --- a/val/ValLibRB.inf +++ b/val/ValLibRB.inf @@ -34,6 +34,7 @@ src/AArch64/Drtm.S src/AArch64/SystemReg.S src/acs_status.c + src/val_status.c src/acs_pe.c src/acs_pe_infra.c src/acs_gic.c diff --git a/val/include/acs_common.h b/val/include/acs_common.h index a083da29..f93b4039 100644 --- a/val/include/acs_common.h +++ b/val/include/acs_common.h @@ -19,6 +19,7 @@ /** This file is common to all test cases and Val layer of the Suite */ #include "val_logger.h" +#include "val_status.h" #ifndef __ACS_COMMON_H__ #define __ACS_COMMON_H__ @@ -76,24 +77,7 @@ typedef enum { #define STATE_MASK 0xF /*These are the states a test can be in */ -#define TEST_START_VAL 0x1 -#define TEST_END_VAL 0x2 #define TEST_PENDING_VAL 0x3 -/****************************************************************************** - * The numeric values below are ordered by severity. - * DO NOT reassign or change them, as code relies on the fact that - * higher values represent worse outcomes (used in consolidated status). - ******************************************************************************/ -#define TEST_PASS_VAL 0x4 -#define TEST_PARTIAL_COV 0x5 -#define TEST_WARN_VAL 0x6 -#define TEST_SKIP_VAL 0x7 -#define TEST_FAIL_VAL 0x8 - -/* Test support defines */ -#define TEST_NOT_IMPLEMENTED 0xA -#define TEST_PAL_NOT_SUPPORTED 0xB -#define TEST_SUPPORTED 0x0 #define CPU_NUM_BIT 32 #define CPU_NUM_MASK 0xFFFFFFFF @@ -109,53 +93,29 @@ typedef enum { /* TEST start and Stop defines */ -#define ACS_START(test_num) (((TEST_START_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT)) -#define ACS_END(test_num) (((TEST_END_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT)) +#define ACS_START(test_num) (((TEST_START) << STATE_BIT) | ((test_num) << TEST_NUM_BIT)) +#define ACS_END(test_num) (((TEST_END) << STATE_BIT) | ((test_num) << TEST_NUM_BIT)) /* TEST Result defines */ #define ENCODE_STATUS(test_status) ((test_status) << STATE_BIT) -#define RESULT_PASS(test_num, status) (((TEST_PASS_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) +#define RESULT_PENDING(test_num) (((TEST_PENDING_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT)) -#define RESULT_FAIL(test_num, status) (((TEST_FAIL_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) - -#define RESULT_SKIP(test_num, status) (((TEST_SKIP_VAL) << STATE_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) - -#define RESULT_PENDING(test_num) (((TEST_PENDING_VAL) << STATE_BIT) | \ - ((test_num) << TEST_NUM_BIT)) - -#define RESULT_WARN(test_num, status) (((TEST_WARN_VAL) << STATE_BIT) | \ - ((test_num) << TEST_NUM_BIT) | (status)) #define TEST_STATUS(test_num, status, checkpoint) (((status) << STATE_BIT) | \ ((test_num) << TEST_NUM_BIT) | (checkpoint)) -#define IS_TEST_START(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_START_VAL) -#define IS_TEST_END(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_END_VAL) +#define IS_TEST_START(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_START) +#define IS_TEST_END(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_END) #define IS_RESULT_PENDING(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_PENDING_VAL) -#define IS_TEST_PASS(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_PASS_VAL) -#define IS_TEST_FAIL(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_FAIL_VAL) -#define IS_TEST_SKIP(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_SKIP_VAL) #define IS_TEST_FAIL_SKIP(value) ((IS_TEST_FAIL(value)) || (IS_TEST_SKIP(value))) -#define IS_TEST_WARN(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_WARN_VAL) typedef struct { uint32_t test_num; /* ACS test number */ char *desc; /* ACS test description */ char *rule; /* Rule covered by the test */ } test_config_t; -/* Test status enum defs */ -typedef enum { - TEST_PASS = TEST_PASS_VAL, - TEST_PART_COV = TEST_PARTIAL_COV, - TEST_WARN = TEST_WARN_VAL, - TEST_SKIP = TEST_SKIP_VAL, - TEST_FAIL = TEST_FAIL_VAL, - TEST_NO_IMP = TEST_NOT_IMPLEMENTED, - TEST_PAL_NS = TEST_PAL_NOT_SUPPORTED, - TEST_STATUS_UNKNOWN = 0xFFFFFFFF -} test_status_t; uint8_t val_mmio_read8(addr_t addr); diff --git a/val/include/acs_pmu.h b/val/include/acs_pmu.h index bb17de70..51eb4b35 100644 --- a/val/include/acs_pmu.h +++ b/val/include/acs_pmu.h @@ -63,7 +63,7 @@ uint32_t val_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index uint32_t val_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value, uint32_t eventid); void val_pmu_set_node_coresight_complaint(uint32_t flag, uint32_t node_index); -test_status_t is_coresight_pmu_present(void); +uint32_t is_coresight_pmu_present(void); uint32_t pmu001_entry(uint32_t num_pe); uint32_t pmu002_entry(uint32_t num_pe); diff --git a/val/include/acs_val.h b/val/include/acs_val.h index 36a18d33..35e8d589 100644 --- a/val/include/acs_val.h +++ b/val/include/acs_val.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020,2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020,2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,11 +51,5 @@ val_is_el2_enabled(void); void val_report_status(uint32_t id, uint32_t status, char8_t *ruleid); -void -val_set_status(uint32_t index, uint32_t status); - -uint32_t -val_get_status(uint32_t id); - #endif diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 6bfb21ed..ba4a4107 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -96,8 +96,6 @@ typedef INT16 int16_t; typedef INT32 int32_t; typedef INT64 int64_t; - typedef CHAR8 char8_t; - typedef CHAR16 char16_t; typedef UINT8 uint8_t; typedef UINT16 uint16_t; typedef UINT32 uint32_t; @@ -108,6 +106,8 @@ typedef INTN intptr_t; typedef INT64 intmax_t; typedef UINT64 uintmax_t; + typedef CHAR8 char8_t; + typedef CHAR16 char16_t; #if defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L /* bool is a keyword */ diff --git a/val/include/val_interface.h b/val/include/val_interface.h index c643e911..42755f48 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -22,17 +22,19 @@ #include "acs_drtm.h" #include "acs_pfdi.h" #include "acs_cxl.h" +#include "val_status.h" extern uint32_t g_print_level; -#define ACS_STATUS_FAIL 0x90000000 #define ACS_STATUS_ERR 0xEDCB1234 //some impropable value? -#define ACS_STATUS_SKIP 0x10000000 -#define ACS_STATUS_PASS 0x0 #define ACS_STATUS_NIST_PASS 0x1 #define ACS_INVALID_INDEX 0xFFFFFFFF -#define ACS_STATUS_UNKNOWN 0xFFFFFFFF + +#define ACS_STATUS_FAIL STATUS_ERROR +#define ACS_STATUS_PASS STATUS_SUCCESS +#define ACS_STATUS_SKIP STATUS_SKIP +#define ACS_STATUS_UNKNOWN STATUS_UNKNOWN #define val_print(level, ...) \ do { \ @@ -66,7 +68,7 @@ extern uint32_t g_print_level; typedef struct { uint32_t total_rules_run; /* Total rules/tests that reported a status */ uint32_t passed; /* Count of TEST_PASS */ - uint32_t partial_coverage; /* Count of TEST_PART_COV */ + uint32_t partial_coverage; /* Count of TEST_PARTIAL_COV */ uint32_t warnings; /* Count of TEST_WARN */ uint32_t skipped; /* Count of TEST_SKIP */ uint32_t failed; /* Count of TEST_FAIL */ @@ -101,6 +103,7 @@ typedef char char8_t; /* GENERIC VAL APIs */ void val_allocate_shared_mem(void); +uintptr_t val_get_status_region_base(void); void val_free_shared_mem(void); //void val_print(uint32_t level, char8_t *string, uint64_t data); void val_print_raw(uint64_t uart_addr, uint32_t level, char8_t *string, uint64_t data); diff --git a/val/src/acs_gic_support.c b/val/src/acs_gic_support.c index 027da426..378610f4 100644 --- a/val/src/acs_gic_support.c +++ b/val/src/acs_gic_support.c @@ -53,7 +53,7 @@ val_gic_reg_read(uint32_t reg_id) return read_ich_misr_el2(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, 0xFF), NULL); + RESULT_FAIL(0xFF), NULL); } return 0x0; @@ -90,7 +90,7 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data) break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, 0xFF), NULL); + RESULT_FAIL(0xFF), NULL); } } diff --git a/val/src/acs_mpam.c b/val/src/acs_mpam.c index 18dad63f..0cbc159e 100644 --- a/val/src/acs_mpam.c +++ b/val/src/acs_mpam.c @@ -123,7 +123,7 @@ val_mpam_reg_read(MPAM_SYS_REGS reg_id) return read_mpam1_el1(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, STATUS_SYS_REG_ACCESS_FAIL), NULL); + RESULT_FAIL(STATUS_SYS_REG_ACCESS_FAIL), NULL); } return 0; @@ -149,7 +149,7 @@ val_mpam_reg_write(MPAM_SYS_REGS reg_id, uint64_t write_data) break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, STATUS_SYS_REG_ACCESS_FAIL), NULL); + RESULT_FAIL(STATUS_SYS_REG_ACCESS_FAIL), NULL); } return; diff --git a/val/src/acs_pe.c b/val/src/acs_pe.c index d92988b2..d2431ba9 100644 --- a/val/src/acs_pe.c +++ b/val/src/acs_pe.c @@ -230,7 +230,7 @@ val_pe_reg_read(uint32_t reg_id) return read_vtcr_el2(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, 0xFF), NULL); + RESULT_FAIL(0xFF), NULL); break; } @@ -291,7 +291,7 @@ val_pe_reg_write(uint32_t reg_id, uint64_t write_data) break; default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), - RESULT_FAIL(0, 0xFF), NULL); + RESULT_FAIL(0xFF), NULL); } } @@ -344,7 +344,7 @@ val_pe_get_pmu_gsiv(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); + val_report_status(index, RESULT_FAIL(0xFF), NULL); return 0xFFFFFF; } @@ -367,7 +367,7 @@ val_pe_get_gicc_trbe_interrupt(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); + val_report_status(index, RESULT_FAIL(0xFF), NULL); return 0xFFFFFF; } @@ -391,7 +391,7 @@ val_pe_get_gmain_gsiv(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); + val_report_status(index, RESULT_FAIL(0xFF), NULL); return 0xFFFFFF; } diff --git a/val/src/acs_pe_infra.c b/val/src/acs_pe_infra.c index 7b456f84..082602c2 100644 --- a/val/src/acs_pe_infra.c +++ b/val/src/acs_pe_infra.c @@ -176,7 +176,7 @@ val_pe_get_mpid_index(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); + val_report_status(index, RESULT_FAIL(0xFF), NULL); return 0xFFFFFF; } @@ -262,7 +262,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) int timeout = TIMEOUT_LARGE; if (index > g_pe_info_table->header.num_of_pe) { val_print(ERROR, "Input Index exceeds Num of PE %x\n", index); - val_report_status(index, RESULT_FAIL(0, 0xFF), NULL); + val_report_status(index, RESULT_FAIL(0xFF), NULL); return; } @@ -283,7 +283,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) val_print(WARN, "\n WARNING: Skipping test for PE index %d " "since it is already on\n", index); - val_set_status(index, RESULT_SKIP(0, 0x120 - (int)g_smc_args.Arg0)); + val_set_status(index, RESULT_SKIP(0x120 - (int)g_smc_args.Arg0)); return; } else { @@ -295,7 +295,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) val_print(ERROR, "\n PSCI_CPU_ON: failure[%d]", g_smc_args.Arg0); } - val_set_status(index, RESULT_FAIL(0, 0x120 - (int)g_smc_args.Arg0)); + val_set_status(index, RESULT_FAIL(0x120 - (int)g_smc_args.Arg0)); } /** @@ -389,7 +389,7 @@ val_pe_default_esr(uint64_t interrupt_type, void *context) if (pal_target_is_dt()) { val_print(WARN, "\n FAR reported = 0x%llx", bsa_gic_get_far()); val_print(WARN, "\n ESR reported = 0x%llx", bsa_gic_get_esr()); - val_set_status(index, RESULT_FAIL(0, 1)); + val_set_status(index, RESULT_FAIL(1)); val_pe_update_elr(context, g_exception_ret_addr); return; } @@ -403,7 +403,7 @@ val_pe_default_esr(uint64_t interrupt_type, void *context) } #endif - val_set_status(index, RESULT_FAIL(0, 1)); + val_set_status(index, RESULT_FAIL(1)); val_pe_update_elr(context, g_exception_ret_addr); } diff --git a/val/src/acs_pmu.c b/val/src/acs_pmu.c index 0232f766..109609ed 100644 --- a/val/src/acs_pmu.c +++ b/val/src/acs_pmu.c @@ -669,7 +669,7 @@ val_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, @return TEST_PASS - success status non-zero - error status **/ -test_status_t is_coresight_pmu_present(void) +uint32_t is_coresight_pmu_present(void) { uint32_t node_count; uint32_t cs_com = 0; @@ -685,7 +685,7 @@ test_status_t is_coresight_pmu_present(void) " if system has CoreSight PMU"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); - return TEST_SKIP; + return TEST_WARNING; } /* The test uses PMU CoreSight arch register map, skip if pmu node is not cs */ @@ -696,7 +696,7 @@ test_status_t is_coresight_pmu_present(void) val_print(INFO, "\n No CoreSight PMU nodes found"); val_print(INFO, "\n For non CoreSight PMU, manually verify A.4 PMU rules " "in the SBSA specification"); - return TEST_WARN; + return TEST_WARNING; } return TEST_PASS; diff --git a/val/src/acs_status.c b/val/src/acs_status.c index 1af59237..496e76f2 100644 --- a/val/src/acs_status.c +++ b/val/src/acs_status.c @@ -56,8 +56,8 @@ val_report_status(uint32_t index, uint32_t status, char8_t *ruleid) val_print(DEBUG, "\n "); val_print(INFO, " : Result: PASS\n", status); } - else if (IS_TEST_WARN(status)) { - val_print(INFO, " : Result: WARN\n"); + else if (IS_TEST_WARNING(status)) { + val_print(INFO, " : Result: WARN\n", 0); } else if (IS_TEST_FAIL(status)) { @@ -90,45 +90,3 @@ val_report_status(uint32_t index, uint32_t status, char8_t *ruleid) } -/** - @brief Record the state and status of the test execution - 1. Caller - Test Suite - 2. Prerequisite - val_allocate_shared_mem - @param index - index of the PE who is reporting this status. - @param status - 32-bit value concatenated from state, level, error value - - @return none -**/ -void -val_set_status(uint32_t index, uint32_t status) -{ - volatile VAL_SHARED_MEM_t *mem; - - mem = (VAL_SHARED_MEM_t *) pal_mem_get_shared_addr(); - mem = mem + index; - mem->status = status; - - val_data_cache_ops_by_va((addr_t)&mem->status, CLEAN_AND_INVALIDATE); -} - -/** - @brief Return the state and status for the input PE index - 1. Caller - Test Suite - 2. Prerequisite - val_allocate_shared_mem - @param index - index of the PE who is reporting this status. - @return 32-bit value concatenated from state, level, error value -**/ -uint32_t -val_get_status(uint32_t index) -{ - volatile VAL_SHARED_MEM_t *mem; - - mem = (VAL_SHARED_MEM_t *) pal_mem_get_shared_addr(); - mem = mem + index; - - val_data_cache_ops_by_va((addr_t)&mem->status, INVALIDATE); - - return (uint32_t)(mem->status); - -} - diff --git a/val/src/acs_test_infra.c b/val/src/acs_test_infra.c index a732bd30..9c028bbe 100644 --- a/val/src/acs_test_infra.c +++ b/val/src/acs_test_infra.c @@ -21,6 +21,7 @@ #include "acs_exception.h" #include "pal_interface.h" #include "val_interface.h" +#include "val_status.h" uint32_t g_override_skip; @@ -410,7 +411,7 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe) /* Skip the test if it one of the -skip option parameters */ for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == test_num) { - val_set_status(index, RESULT_SKIP(test_num, 0)); + val_set_status(index, RESULT_SKIP(0)); return ACS_STATUS_SKIP; } } @@ -432,7 +433,7 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe) } if ((!g_override_skip) && (g_num_tests || g_num_modules)) { - val_set_status(index, RESULT_SKIP(test_num, 0)); + val_set_status(index, RESULT_SKIP(0)); return ACS_STATUS_SKIP; } @@ -474,9 +475,24 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe) void val_allocate_shared_mem() { + uint32_t num_pe = val_pe_get_num(); - pal_mem_allocate_shared(val_pe_get_num(), sizeof(VAL_SHARED_MEM_t)); + uint32_t total_size = + (num_pe * sizeof(VAL_SHARED_MEM_t)) + + (num_pe * sizeof(val_test_status_t)); + pal_mem_allocate_shared(1, total_size); + +} + +uintptr_t val_get_status_region_base(void) +{ + uintptr_t base = (uintptr_t)pal_mem_get_shared_addr(); + uint32_t npe = val_pe_get_num(); + + /* Status region starts after ACS data region */ + base += (uintptr_t)(npe * sizeof(VAL_SHARED_MEM_t)); + return base; } /** @@ -584,6 +600,8 @@ val_wait_for_test_completion(uint32_t test_num, uint32_t num_pe, uint32_t timeou uint32_t i = 0, j = 0; + val_print(TRACE, "Test_num= %d\n", test_num); + //For single PE tests, there is no need to wait for the results if (num_pe == 1) return; @@ -602,7 +620,7 @@ val_wait_for_test_completion(uint32_t test_num, uint32_t num_pe, uint32_t timeou return; } //We are here if we timed-out, set the last index PE as failed - val_set_status(j-1, RESULT_FAIL(test_num, 0xF)); + val_set_status(j-1, RESULT_FAIL(0xF)); } /** @@ -728,37 +746,39 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid) (void)ruleid; (void)test_num; - uint32_t i; + uint32_t i, checkpoint; uint32_t overall_status; - uint32_t status = TEST_FAIL; - uint32_t checkpoint; + uint32_t status = RESULT_FAIL(0); uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid()); if (num_pe == 1) { status = val_get_status(my_index); - checkpoint = status & STATUS_MASK; - status = (status >> STATE_BIT) & STATE_MASK; overall_status = status; } else { /* Start with least severe status */ - overall_status = TEST_PASS; + overall_status = RESULT_PASS; for (i = 0; i < num_pe; i++) { status = val_get_status(i); /* Checkpoint info from last PE would be reflected */ - checkpoint = status & STATUS_MASK; - status = (status >> STATE_BIT) & STATE_MASK; + //checkpoint = status & STATUS_MASK; + //status = (status >> STATE_BIT) & STATE_MASK; /* Overwrite status if higher severity status found*/ if (status > overall_status) { overall_status = status; } } } - if (overall_status == TEST_FAIL) { - val_print(ERROR, "\n Failed at checkpoint - %2d", checkpoint); - } else if (overall_status == TEST_SKIP) { - val_print(ERROR, "\n Skipped at checkpoint - %2d", checkpoint); + + checkpoint = (uint32_t)GET_CODE(overall_status); + if (GET_STATE(overall_status) == TEST_FAIL) { + val_print(ERROR, "\nFailed at checkpoint - %2d", checkpoint); + } else if (GET_STATE(overall_status) == TEST_SKIP) { + val_print(ERROR, "\nSkipped at checkpoint - %2d", checkpoint); + } else if (GET_STATE(overall_status) == TEST_WARNING) { + val_print(WARN, "\ncheckpoint - %2d", checkpoint); } + return overall_status; } #endif @@ -924,7 +944,7 @@ val_check_for_prerequisite(uint32_t num_pe, uint32_t prereq_status, val_print(ERROR, "\n Pre-requisite rule "); val_print(ERROR, prereq_config->rule); val_print(ERROR, " did not pass. Skipping the test"); - val_set_status(index, RESULT_SKIP(curr_config->test_num, 0)); + val_set_status(index, RESULT_SKIP(0)); return ACS_STATUS_SKIP; } diff --git a/val/src/rule_based_execution_helpers.c b/val/src/rule_based_execution_helpers.c index 7b805185..3832266f 100644 --- a/val/src/rule_based_execution_helpers.c +++ b/val/src/rule_based_execution_helpers.c @@ -253,7 +253,7 @@ print_rule_test_status(uint32_t rule_enum, uint32_t indent, uint32_t status) val_print(INFO, "\n"); /* Print other PAL(s) that validate this rule */ - if (status == TEST_PAL_NS) { + if (status == TEST_PAL_NOT_SUPPORTED) { print_pal_validation_info(rule_enum, indent); } /* Print indent spaces */ @@ -262,46 +262,43 @@ print_rule_test_status(uint32_t rule_enum, uint32_t indent, uint32_t status) indent--; } - val_print(INFO, " Result: "); - val_print(INFO, " "); + uint8_t state = (uint8_t)GET_STATE(status); + + val_print(INFO, " Result: ", 0); + val_print(INFO, " ", 0); /* Update global counters for top-level rules only */ if (top_level_rule) { g_rule_test_stats.total_rules_run++; } - switch (status) { + switch (state) { case TEST_PASS: - val_print(INFO, "PASSED"); if (top_level_rule) g_rule_test_stats.passed++; break; - case TEST_PART_COV: - val_print(INFO, "PASSED(*PARTIAL)"); + case TEST_PARTIAL_COVERED: if (top_level_rule) g_rule_test_stats.partial_coverage++; break; - case TEST_WARN: - val_print(INFO, "WARNING"); + case TEST_WARNING: if (top_level_rule) g_rule_test_stats.warnings++; break; case TEST_SKIP: - val_print(INFO, "SKIPPED"); if (top_level_rule) g_rule_test_stats.skipped++; break; case TEST_FAIL: - val_print(INFO, "FAILED"); if (top_level_rule) g_rule_test_stats.failed++; break; - case TEST_NO_IMP: - val_print(INFO, "NOT TESTED (TEST NOT IMPLEMENTED)"); + case TEST_NOT_IMPLEMENTED: if (top_level_rule) g_rule_test_stats.not_implemented++; break; - case TEST_PAL_NS: - val_print(INFO, "NOT TESTED (PAL NOT SUPPORTED)"); + case TEST_PAL_NOT_SUPPORTED: if (top_level_rule) g_rule_test_stats.pal_not_supported++; break; default: - val_print(INFO, "STATUS:0x%x", status); + val_print(INFO, "STATUS:0x%08x", status); } + + test_report_status(status); return; } @@ -316,7 +313,7 @@ void rule_status_map_reset(void) { uint32_t i; for (i = 0; i < RULE_ID_SENTINEL; i++) { - rule_status_map[i] = TEST_STATUS_UNKNOWN; + rule_status_map[i] = TEST_STATE_UNKNOWN; } } diff --git a/val/src/rule_based_orchestrator.c b/val/src/rule_based_orchestrator.c index 65186453..bdabc8e5 100644 --- a/val/src/rule_based_orchestrator.c +++ b/val/src/rule_based_orchestrator.c @@ -55,10 +55,10 @@ static uint32_t check_rule_support(RULE_ID_e rule_id) /* Report if rule is not supported by ACS across all available PALs*/ if (plat_bitmask == 0) { /* Not covered by ACS in any supported PAL */ - return TEST_NOT_IMPLEMENTED; + return RESULT_NOT_IMPLEMENTED; } else { /* Test not supported with current PAL */ - return TEST_PAL_NOT_SUPPORTED; + return RESULT_PAL_NOT_SUPPORTED; } } @@ -484,14 +484,14 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) test_entry_func_table[rule_test_map[rule_list[i]].test_entry_id](num_pe); /* If precheck fails, report alias rule status as SKIP as it wont be applicable */ - if (precheck_status == TEST_FAIL) { - rule_test_status = TEST_SKIP; + if (precheck_status == TEST_FAIL || (GET_STATE(precheck_status) == TEST_FAIL)) { + rule_test_status = RESULT_SKIP(0); goto report_status; } } /* reset rule test status to unknown */ - rule_test_status = TEST_STATUS_UNKNOWN; + rule_test_status = TEST_STATE_UNKNOWN; /* init a flag to track partial coverage */ test_ns_flag = 0; /* track whether any base rule completed with PASS */ @@ -545,20 +545,20 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) } else { - val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r "); - base_rule_status = TEST_FAIL; + val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r ", 0); + base_rule_status = RESULT_FAIL(1); } /* record base rule status */ rule_status_map[base_rule_id] = base_rule_status; - if (base_rule_status == TEST_PASS) + if (GET_STATE(base_rule_status) == TEST_PASS) test_pass_flag = 1; - if (base_rule_status == TEST_WARN) + if (GET_STATE(base_rule_status) == TEST_WARNING) test_warn_flag = 1; /* report status of base rule run */ print_rule_test_status(base_rule_list[j], 1, base_rule_status); /* update overall alias rule status */ if ((base_rule_status > rule_test_status) - || (rule_test_status == TEST_STATUS_UNKNOWN)) { + || (rule_test_status == TEST_STATE_UNKNOWN)) { rule_test_status = base_rule_status; } } @@ -567,15 +567,16 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) WARN or SKIP, report partial coverage. 2) If any base rule was not supported and the aggregated alias status is PASS, report partial coverage. */ - if ((test_pass_flag && - ((rule_test_status == TEST_SKIP) || - (rule_test_status == TEST_WARN))) || - (test_ns_flag && (rule_test_status == TEST_PASS))) { - rule_test_status = TEST_PART_COV; - } - /* If the alias only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ - if (test_warn_flag && (rule_test_status == TEST_SKIP)) { - rule_test_status = TEST_WARN; + if ((test_pass_flag && + ((GET_STATE(rule_test_status) == TEST_SKIP) || + (GET_STATE(rule_test_status) == TEST_WARNING))) || + (test_ns_flag && + (GET_STATE(rule_test_status) == TEST_PASS))) { + rule_test_status = RESULT_PARTIAL_COVERED; + } + /* If the alias only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ + if (test_warn_flag && (GET_STATE(rule_test_status) == TEST_SKIP)) { + rule_test_status = TEST_WARNING; } /* Print end header for alias rule */ @@ -593,7 +594,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) else { val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r ", 0); - rule_test_status = TEST_FAIL; + rule_test_status = RESULT_FAIL(1); } } report_status: diff --git a/val/src/test_wrappers.c b/val/src/test_wrappers.c index 01d5c0c8..e6c830d7 100644 --- a/val/src/test_wrappers.c +++ b/val/src/test_wrappers.c @@ -37,32 +37,33 @@ extern RULE_ID_e g_base_rule; static uint32_t run_test_entries(TEST_ENTRY_ID_e *tst_entry_list, uint32_t num_pe) { uint32_t i; - uint32_t entry_status = TEST_STATUS_UNKNOWN; - uint32_t rule_status = TEST_STATUS_UNKNOWN; + uint32_t entry_status = TEST_STATE_UNKNOWN; + uint32_t rule_status = TEST_STATE_UNKNOWN; bool test_pass_flag = 0; bool test_ns_flag = 0; bool test_warn_flag = 0; + for (i = 0; tst_entry_list[i] != TEST_ENTRY_SENTINEL ; i++) { if (test_entry_func_table[tst_entry_list[i]] != NULL) { entry_status = test_entry_func_table[tst_entry_list[i]](num_pe); } else { /* If entry is NULL, then the entry is not supported in current PAL */ - entry_status = TEST_PART_COV; + entry_status = RESULT_PARTIAL_COVERED; test_ns_flag = 1; } /* Track atleast one pass */ - if (entry_status == TEST_PASS) { + if (GET_STATE(entry_status) == TEST_PASS) { test_pass_flag = 1; } /* Track atleast one warn */ - if (entry_status == TEST_WARN) { + if (GET_STATE(entry_status) == TEST_WARNING) { test_warn_flag = 1; } /* Update overall status for the rule */ - if ((entry_status > rule_status) || (rule_status == TEST_STATUS_UNKNOWN)) { + if ((entry_status > rule_status) || (rule_status == TEST_STATE_UNKNOWN)) { rule_status = entry_status; } } @@ -70,14 +71,16 @@ static uint32_t run_test_entries(TEST_ENTRY_ID_e *tst_entry_list, uint32_t num_p /* Mixed PASS+SKIP/WARN or PASS+unsupported entry should be reported as partial coverage rather than worst-case max. */ if ((test_pass_flag && - ((rule_status == TEST_SKIP) || (rule_status == TEST_WARN))) || - (test_ns_flag && (rule_status == TEST_PASS))) { - rule_status = TEST_PART_COV; + ((GET_STATE(rule_status) == TEST_SKIP) || + (GET_STATE(rule_status) == TEST_WARNING))) || + (test_ns_flag && + (GET_STATE(rule_status) == TEST_PASS))) { + rule_status = RESULT_PARTIAL_COVERED; } /* If the combined result only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ if (test_warn_flag && (rule_status == TEST_SKIP)) { - rule_status = TEST_WARN; + rule_status = TEST_WARNING; } return rule_status; @@ -99,17 +102,17 @@ static uint32_t run_pcie_static_and_exerciser(TEST_ENTRY_ID_e *static_list, /* Report partial coverage for mixed PASS+SKIP/WARN aggregated results. */ if (((static_status == TEST_PASS) && - ((exr_status == TEST_SKIP) || (exr_status == TEST_WARN))) || + ((exr_status == TEST_SKIP) || (exr_status == TEST_WARNING))) || ((exr_status == TEST_PASS) && - ((static_status == TEST_SKIP) || (static_status == TEST_WARN)))) - return TEST_PART_COV; + ((static_status == TEST_SKIP) || (static_status == TEST_WARNING)))) + return TEST_PARTIAL_COVERED; /* For all other combinations, fall back to severity-based aggregation. */ rule_status = max_status(static_status, exr_status); /* If the combined result only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ - if (((static_status == TEST_WARN) || (exr_status == TEST_WARN)) && + if (((static_status == TEST_WARNING) || (exr_status == TEST_WARNING)) && (rule_status == TEST_SKIP)) { - rule_status = TEST_WARN; + rule_status = TEST_WARNING; } return rule_status; From 0c5096c71a4b041982d2cedcf20e59cf0becd3de Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Thu, 2 Apr 2026 09:06:29 +0000 Subject: [PATCH 08/13] License related updates - Provide support to BSD-3 license for sysarch-acs - These changes have been made as a part of Unified VAL Signed-off-by: Avi Nawal Change-Id: Iac2d1bd8a885182a70dc23c9c9e5c1fdd90d464d --- LICENSE | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/LICENSE b/LICENSE index 261eeb9e..efcb0cb7 100644 --- a/LICENSE +++ b/LICENSE @@ -199,3 +199,46 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. + +# Other Licenses + - BSD-3-Clause + - Some source files originate from the [cca-rmm-acs](https://github.com/ARM-software/cca-rmm-acs). These files are licensed under the BSD-3-Clause which are a permissive licenses compatible with Apache License, Version 2.0. Any contributions to this code must also be made under the terms of BSD-3-Clause. + - These files are: + - val/include/val_arch.h + - val/include/val_logger.h + - val/include/val_sysreg.h + - val/include/val_sysreg_gic.h + - val/include/val_sysreg_mpam.h + - val/include/val_sysreg_pe.h + - val/include/val_sysreg_pmu_reg.h + - val/include/val_sysreg_ras.h + - val/include/val_sysreg_timer.h + - val/src/val_logger.c + - val/xlat_tables_v2/CMakeLists.txt + - val/xlat_tables_v2/include/arch.h + - val/xlat_tables_v2/include/arch_features.h + - val/xlat_tables_v2/include/arch_helpers.h + - val/xlat_tables_v2/include/asm_macros.S + - val/xlat_tables_v2/include/asm_macros_common.S + - val/xlat_tables_v2/include/assert.h + - val/xlat_tables_v2/include/assert_macros.S + - val/xlat_tables_v2/include/cdefs.h + - val/xlat_tables_v2/include/config.h + - val/xlat_tables_v2/include/debug.h + - val/xlat_tables_v2/include/def.h + - val/xlat_tables_v2/include/smc.h + - val/xlat_tables_v2/include/xlat_mmu_helpers.h + - val/xlat_tables_v2/include/xlat_tables.h + - val/xlat_tables_v2/include/xlat_tables_aarch64.h + - val/xlat_tables_v2/include/xlat_tables_arch.h + - val/xlat_tables_v2/include/xlat_tables_compat.h + - val/xlat_tables_v2/include/xlat_tables_defs.h + - val/xlat_tables_v2/include/xlat_tables_private.h + - val/xlat_tables_v2/include/xlat_tables_v2.h + - val/xlat_tables_v2/include/xlat_tables_v2_helpers.h + - val/xlat_tables_v2/src/cache_helpers.S + - val/xlat_tables_v2/src/enable_mmu.S + - val/xlat_tables_v2/src/smc.S + - val/xlat_tables_v2/src/xlat_tables_arch.c + - val/xlat_tables_v2/src/xlat_tables_core.c + - val/xlat_tables_v2/src/xlat_tables_utils.c From ecd35cde6c4dc0de52ac6e0a47172c2e88d08c97 Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Fri, 3 Apr 2026 09:39:23 +0000 Subject: [PATCH 09/13] Fix: Update unified val changes as per RB Execution -update RB exection infra files for new status report design -align exerciser and SMMU tests -align val_prints as per the log parser -update SbsaValNistLib.inf as per unified val changes Signed-off-by: Shruti Ghadge Change-Id: I8b75be4c7018b96343e485e81bc7484c5ea0cab7 --- test_pool/exerciser/e016.c | 2 +- test_pool/exerciser/e017.c | 2 +- test_pool/exerciser/e033.c | 2 +- test_pool/exerciser/e039.c | 2 +- test_pool/smmu/i005.c | 6 +++++- val/SbsaValNistLib.inf | 7 ++----- val/driver/smmu_v3/smmu_v3.c | 2 +- val/src/rule_based_execution_helpers.c | 2 +- val/src/rule_based_orchestrator.c | 4 ++-- val/src/test_wrappers.c | 24 ++++++++++++------------ 10 files changed, 27 insertions(+), 26 deletions(-) diff --git a/test_pool/exerciser/e016.c b/test_pool/exerciser/e016.c index e5997f9a..61c7dc36 100644 --- a/test_pool/exerciser/e016.c +++ b/test_pool/exerciser/e016.c @@ -160,7 +160,7 @@ e016_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP; + return RESULT_SKIP(0); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e017.c b/test_pool/exerciser/e017.c index 92e5da80..b367e4ec 100644 --- a/test_pool/exerciser/e017.c +++ b/test_pool/exerciser/e017.c @@ -263,7 +263,7 @@ e034_entry(uint32_t num_pe) status = val_initialize_test(data.test_num, test_entries[1].desc, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP; + return RESULT_SKIP(0); val_run_test_configurable_payload(&data, payload); } diff --git a/test_pool/exerciser/e033.c b/test_pool/exerciser/e033.c index fecc496e..92b9d30d 100644 --- a/test_pool/exerciser/e033.c +++ b/test_pool/exerciser/e033.c @@ -179,7 +179,7 @@ e033_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP; + return RESULT_SKIP(0); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/exerciser/e039.c b/test_pool/exerciser/e039.c index 40974687..6c87accf 100644 --- a/test_pool/exerciser/e039.c +++ b/test_pool/exerciser/e039.c @@ -167,7 +167,7 @@ e039_entry(uint32_t num_pe) status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) { if (val_exerciser_test_init() != ACS_STATUS_PASS) - return TEST_SKIP; + return RESULT_SKIP(0); val_run_test_payload(TEST_NUM, num_pe, payload, 0); } diff --git a/test_pool/smmu/i005.c b/test_pool/smmu/i005.c index 8ead2b39..37e08749 100644 --- a/test_pool/smmu/i005.c +++ b/test_pool/smmu/i005.c @@ -117,7 +117,11 @@ payload_check_sel2_and_smmu_stg2_support() /* If Secure EL2 not implemented then all SMMUs in system must support stage 2 translation */ status = check_smmu_stg2_support(); - val_set_status(index, TEST_STATUS(TEST_NUM1, status, 2)); + if (status == TEST_FAIL) { + val_set_status(index, RESULT_FAIL(2)); + } else { + val_set_status(index, RESULT_PASS); + } return; } diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf index 73490603..5cae9bb1 100644 --- a/val/SbsaValNistLib.inf +++ b/val/SbsaValNistLib.inf @@ -29,15 +29,11 @@ [Sources.common] src/AArch64/PeRegSysSupport.S src/AArch64/PeTestSupport.S - src/AArch64/ArchTimerSupport.S - src/AArch64/GicSupport.S - src/AArch64/MpamSupport.S - src/AArch64/RasSupport.S - src/AArch64/PmuRegSupport.S src/AArch64/Drtm.S src/AArch64/SystemReg.S src/AArch64/generic_sysreg_support.S src/acs_status.c + src/val_status.c src/acs_pe.c src/acs_pe_infra.c src/acs_gic.c @@ -82,6 +78,7 @@ src/sbsa_execute_test.c src/mpam_execute_test.c src/drtm_execute_test.c + src/val_logger.c [Packages] MdePkg/MdePkg.dec diff --git a/val/driver/smmu_v3/smmu_v3.c b/val/driver/smmu_v3/smmu_v3.c index a4a02575..76f9c3ab 100644 --- a/val/driver/smmu_v3/smmu_v3.c +++ b/val/driver/smmu_v3/smmu_v3.c @@ -1385,7 +1385,7 @@ val_smmu_get_info(SMMU_INFO_e type, uint32_t smmu_index) if (smmu_index >= g_num_smmus) { val_print(ERROR, - "\n val_smmu_get_info: invalid smmu index(%d) ", + "\n val_smmu_get_info - invalid smmu index(%d) ", smmu_index); return 0; } diff --git a/val/src/rule_based_execution_helpers.c b/val/src/rule_based_execution_helpers.c index 3832266f..c2732506 100644 --- a/val/src/rule_based_execution_helpers.c +++ b/val/src/rule_based_execution_helpers.c @@ -253,7 +253,7 @@ print_rule_test_status(uint32_t rule_enum, uint32_t indent, uint32_t status) val_print(INFO, "\n"); /* Print other PAL(s) that validate this rule */ - if (status == TEST_PAL_NOT_SUPPORTED) { + if (status == RESULT_PAL_NOT_SUPPORTED) { print_pal_validation_info(rule_enum, indent); } /* Print indent spaces */ diff --git a/val/src/rule_based_orchestrator.c b/val/src/rule_based_orchestrator.c index bdabc8e5..e8ffa729 100644 --- a/val/src/rule_based_orchestrator.c +++ b/val/src/rule_based_orchestrator.c @@ -484,7 +484,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) test_entry_func_table[rule_test_map[rule_list[i]].test_entry_id](num_pe); /* If precheck fails, report alias rule status as SKIP as it wont be applicable */ - if (precheck_status == TEST_FAIL || (GET_STATE(precheck_status) == TEST_FAIL)) { + if ((GET_STATE(precheck_status) == TEST_FAIL)) { rule_test_status = RESULT_SKIP(0); goto report_status; } @@ -576,7 +576,7 @@ run_tests(RULE_ID_e *rule_list, uint32_t list_size) } /* If the alias only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ if (test_warn_flag && (GET_STATE(rule_test_status) == TEST_SKIP)) { - rule_test_status = TEST_WARNING; + rule_test_status = RESULT_WARNING(0); } /* Print end header for alias rule */ diff --git a/val/src/test_wrappers.c b/val/src/test_wrappers.c index e6c830d7..d3590379 100644 --- a/val/src/test_wrappers.c +++ b/val/src/test_wrappers.c @@ -79,8 +79,8 @@ static uint32_t run_test_entries(TEST_ENTRY_ID_e *tst_entry_list, uint32_t num_p } /* If the combined result only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ - if (test_warn_flag && (rule_status == TEST_SKIP)) { - rule_status = TEST_WARNING; + if (test_warn_flag && (GET_STATE(rule_status) == TEST_SKIP)) { + rule_status = RESULT_WARNING(0); } return rule_status; @@ -101,18 +101,18 @@ static uint32_t run_pcie_static_and_exerciser(TEST_ENTRY_ID_e *static_list, uint32_t rule_status; /* Report partial coverage for mixed PASS+SKIP/WARN aggregated results. */ - if (((static_status == TEST_PASS) && - ((exr_status == TEST_SKIP) || (exr_status == TEST_WARNING))) || - ((exr_status == TEST_PASS) && - ((static_status == TEST_SKIP) || (static_status == TEST_WARNING)))) - return TEST_PARTIAL_COVERED; + if (((GET_STATE(static_status) == TEST_PASS) && + ((GET_STATE(exr_status) == TEST_SKIP) || (GET_STATE(exr_status) == TEST_WARNING))) || + ((GET_STATE(exr_status) == TEST_PASS) && + ((GET_STATE(static_status) == TEST_SKIP) || (GET_STATE(static_status) == TEST_WARNING)))) + return RESULT_PARTIAL_COVERED; /* For all other combinations, fall back to severity-based aggregation. */ rule_status = max_status(static_status, exr_status); /* If the combined result only saw WARN/SKIP outcomes, prefer WARN over SKIP. */ - if (((static_status == TEST_WARNING) || (exr_status == TEST_WARNING)) && - (rule_status == TEST_SKIP)) { - rule_status = TEST_WARNING; + if (((GET_STATE(static_status) == TEST_WARNING) || (GET_STATE(exr_status) == TEST_WARNING)) && + (GET_STATE(rule_status) == TEST_SKIP)) { + rule_status = RESULT_WARNING(0); } return rule_status; @@ -450,7 +450,7 @@ v_l1wk_02_05_entry(uint32_t num_pe) if (g_el1skiptrap_mask & EL1SKIPTRAP_CNTPCT) { val_print(INFO, "\n Skipping rule as EL1 physical timer access not supported", 0); - return TEST_SKIP; + return RESULT_SKIP(0); } TEST_ENTRY_ID_e tst_entry_list[] = {U001_ENTRY, U002_ENTRY, TEST_ENTRY_SENTINEL}; @@ -471,7 +471,7 @@ v_l1pp_00_entry(uint32_t num_pe) { #ifdef TARGET_LINUX // Test not applicable for Linux target - return TEST_SKIP; + return RESULT_SKIP(0); #endif TEST_ENTRY_ID_e skip_list[] = {G007_ENTRY, TEST_ENTRY_SENTINEL}; From 8a73073a6b244c146a77760166e141c3359fdb59 Mon Sep 17 00:00:00 2001 From: Shruti Ghadge Date: Fri, 3 Apr 2026 11:45:09 +0000 Subject: [PATCH 10/13] Fix: Update Unified val design for Linux builds -avoid inclusion of std C headers in kernel builds -Uupdate VAL headers to support cross-platform compilation Change-Id: I5d8079119cde7c6e8f8d3981f9ec73c799e2c1e4 --- val/SbsaValNistLib.inf | 3 +-- val/include/val_interface.h | 1 - val/include/val_logger.h | 8 +++++--- val/include/val_status.h | 2 +- val/include/val_sysreg.h | 4 +++- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf index 5cae9bb1..ff3593a1 100644 --- a/val/SbsaValNistLib.inf +++ b/val/SbsaValNistLib.inf @@ -31,7 +31,6 @@ src/AArch64/PeTestSupport.S src/AArch64/Drtm.S src/AArch64/SystemReg.S - src/AArch64/generic_sysreg_support.S src/acs_status.c src/val_status.c src/acs_pe.c @@ -93,4 +92,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.6-a+sve+profile - GCC:*_*_*_CC_FLAGS = $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI + GCC:*_*_*_CC_FLAGS = -O0 -march=armv8.6-a+sve+profile+lse $(ACS_CORE_INCLUDE_FLAGS) $(ACS_GIC_INCLUDE_FLAGS) $(ACS_PCIE_INCLUDE_FLAGS) -DTARGET_UEFI diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 42755f48..f0de6bc0 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -26,7 +26,6 @@ extern uint32_t g_print_level; - #define ACS_STATUS_ERR 0xEDCB1234 //some impropable value? #define ACS_STATUS_NIST_PASS 0x1 #define ACS_INVALID_INDEX 0xFFFFFFFF diff --git a/val/include/val_logger.h b/val/include/val_logger.h index 223c90f4..37c7b0b4 100644 --- a/val/include/val_logger.h +++ b/val/include/val_logger.h @@ -8,13 +8,15 @@ #ifndef VAL_LOG_H #define VAL_LOG_H -#ifndef TARGET_UEFI +#ifdef TARGET_UEFI +#include +#elif !defined(TARGET_LINUX) #include +#include +#include #endif #include "pal_interface.h" -#include -#include /* Verbosity enums, Lower the value, higher the verbosity */ typedef enum { diff --git a/val/include/val_status.h b/val/include/val_status.h index bf19de90..2d3ee891 100644 --- a/val/include/val_status.h +++ b/val/include/val_status.h @@ -17,7 +17,7 @@ #ifndef VAL_STATUS_H #define VAL_STATUS_H -#ifndef TARGET_UEFI +#if !defined(TARGET_UEFI) && !defined(TARGET_LINUX) #include #endif diff --git a/val/include/val_sysreg.h b/val/include/val_sysreg.h index fe12d746..a5733e4e 100644 --- a/val/include/val_sysreg.h +++ b/val/include/val_sysreg.h @@ -8,8 +8,10 @@ #ifndef VAL_SYSREG_H #define VAL_SYSREG_H +#ifdef TARGET_UEFI +#include +#elif !defined(TARGET_LINUX) #include -#ifndef TARGET_UEFI #include #include #endif From 8ebedfbb4fcb14867f7d4153268a5cc9ea2c8e06 Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Fri, 3 Apr 2026 08:30:44 +0000 Subject: [PATCH 11/13] fix(license): wrap lines to 100 character limit Signed-off-by: Avi Nawal Change-Id: I5fb837358584a1da4442bbafb2b352ca0dcafbb8 --- LICENSE | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/LICENSE b/LICENSE index efcb0cb7..01b9b639 100644 --- a/LICENSE +++ b/LICENSE @@ -202,7 +202,11 @@ # Other Licenses - BSD-3-Clause - - Some source files originate from the [cca-rmm-acs](https://github.com/ARM-software/cca-rmm-acs). These files are licensed under the BSD-3-Clause which are a permissive licenses compatible with Apache License, Version 2.0. Any contributions to this code must also be made under the terms of BSD-3-Clause. + - Some source files originate from the + [cca-rmm-acs](https://github.com/ARM-software/cca-rmm-acs). These files + are licensed under the BSD-3-Clause which are a permissive licenses + compatible with Apache License, Version 2.0. Any contributions to this + code must also be made under the terms of BSD-3-Clause. - These files are: - val/include/val_arch.h - val/include/val_logger.h From dd9f45a89a29ef7477fbf062d90a0ed5300669eb Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Fri, 3 Apr 2026 21:15:31 +0000 Subject: [PATCH 12/13] Fix: Linux compilation errors Change-Id: I26f3b1c0801e3c5e96f11f4e399a169688ed2c5d --- test_pool/Makefile | 1 + val/Makefile | 5 ++++ val/include/pal_common_intf.h | 11 ++++++--- val/include/val_arch.h | 46 +++++++++-------------------------- val/include/val_sysreg.h | 19 ++++++++++++--- 5 files changed, 41 insertions(+), 41 deletions(-) diff --git a/test_pool/Makefile b/test_pool/Makefile index 3b41e078..dad48ce8 100644 --- a/test_pool/Makefile +++ b/test_pool/Makefile @@ -17,6 +17,7 @@ export CROSS_COMPILE ?= aarch64-linux-gnu- export ARCH ?= arm64 +export KBUILD_MODPOST_WARN ?= 1 #since we have copied the files locally ACS_DIR ?= . diff --git a/val/Makefile b/val/Makefile index 85503b3b..f116f4db 100644 --- a/val/Makefile +++ b/val/Makefile @@ -19,6 +19,7 @@ export CROSS_COMPILE ?= aarch64-linux-gnu- export ARCH ?= arm64 +export KBUILD_MODPOST_WARN ?= 1 #since we have copied the files locally ACS_DIR ?= . @@ -34,6 +35,7 @@ ccflags-y = \ -I$(PWD)/$(ACS_DIR)/include \ -I$(PWD)/$(ACS_DIR) \ -DTARGET_LINUX \ + -DSTATIC_ASSERT_CHECKS \ -Wall \ -Werror \ -DCOMPILE_RB_EXE @@ -54,6 +56,7 @@ bsa_acs_val-objs += $(VAL_SRC)/acs_status.o $(VAL_SRC)/acs_memory.o \ $(VAL_SRC)/acs_peripherals.o $(VAL_SRC)/acs_dma.o $(VAL_SRC)/acs_smmu.o \ $(VAL_SRC)/acs_test_infra.o $(VAL_SRC)/acs_pcie.o $(VAL_SRC)/acs_pe_infra.o \ $(VAL_SRC)/acs_iovirt.o $(VAL_SRC)/bsa_execute_test.o\ + $(VAL_SRC)/val_status.o $(VAL_SRC)/val_logger.o \ $(VAL_SRC)/../driver/smmu_v3/smmu_v3.o $(VAL_SRC)/../driver/pcie/pcie.o \ $(VAL_SRC)/rule_based_execution_helpers.o \ $(VAL_SRC)/rule_based_orchestrator.o \ @@ -68,6 +71,7 @@ sbsa_acs_val-objs += $(VAL_SRC)/acs_status.o $(VAL_SRC)/acs_memory.o \ $(VAL_SRC)/acs_peripherals.o $(VAL_SRC)/acs_smmu.o $(VAL_SRC)/acs_dma.o \ $(VAL_SRC)/acs_test_infra.o $(VAL_SRC)/acs_pcie.o $(VAL_SRC)/acs_pe_infra.o \ $(VAL_SRC)/acs_iovirt.o $(VAL_SRC)/../driver/smmu_v3/smmu_v3.o \ + $(VAL_SRC)/val_status.o $(VAL_SRC)/val_logger.o \ $(VAL_SRC)/sbsa_execute_test.o $(VAL_SRC)/../driver/pcie/pcie.o \ $(VAL_SRC)/rule_based_execution_helpers.o \ $(VAL_SRC)/rule_based_orchestrator.o \ @@ -81,6 +85,7 @@ pcbsa_acs_val-objs += $(VAL_SRC)/acs_status.o $(VAL_SRC)/acs_memory.o \ $(VAL_SRC)/acs_peripherals.o $(VAL_SRC)/acs_smmu.o $(VAL_SRC)/acs_dma.o\ $(VAL_SRC)/acs_test_infra.o $(VAL_SRC)/acs_pcie.o $(VAL_SRC)/acs_pe_infra.o \ $(VAL_SRC)/acs_iovirt.o $(VAL_SRC)/../driver/smmu_v3/smmu_v3.o \ + $(VAL_SRC)/val_status.o $(VAL_SRC)/val_logger.o \ $(VAL_SRC)/pc_bsa_execute_test.o $(VAL_SRC)/../driver/pcie/pcie.o endif diff --git a/val/include/pal_common_intf.h b/val/include/pal_common_intf.h index e60d375d..86e31599 100644 --- a/val/include/pal_common_intf.h +++ b/val/include/pal_common_intf.h @@ -18,17 +18,22 @@ #ifndef _PAL_COMMON_INTF_H_ #define _PAL_COMMON_INTF_H_ +#ifdef TARGET_LINUX +#include +#include +#include +#else #include #include #include +#endif #define LOG_BUFFER_SIZE 8192 +#ifndef static_assert #define static_assert _Static_assert +#endif void pal_uart_putc(char c); #endif /* _PAL_COMMON_INTF_H_ */ - - - diff --git a/val/include/val_arch.h b/val/include/val_arch.h index 1bb58a29..1a1d9303 100644 --- a/val/include/val_arch.h +++ b/val/include/val_arch.h @@ -8,45 +8,21 @@ #ifndef VAL_ARCH_H #define VAL_ARCH_H -/* - * For those constants to be shared between C and other sources, apply a 'U', - * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid - * undefined or unintended behaviour. - * - * The GNU assembler and linker do not support these suffixes (it causes the - * build process to fail) therefore the suffix is omitted when used in linker - * scripts and assembler files. -*/ -#if defined(__LINKER__) || defined(__ASSEMBLY__) -# define U(_x) (_x) -# define UL(_x) (_x) -# define ULL(_x) (_x) -# define L(_x) (_x) -# define LL(_x) (_x) -#else -# define U(_x) (_x##U) -# define UL(_x) (_x##UL) -# define ULL(_x) (_x##ULL) -# define L(_x) (_x##L) -# define LL(_x) (_x##LL) -#endif - - /* CPSR/SPSR definitions */ -#define DAIF_FIQ_BIT (U(1) << 0) -#define DAIF_IRQ_BIT (U(1) << 1) -#define DAIF_ABT_BIT (U(1) << 2) -#define DAIF_DBG_BIT (U(1) << 3) -#define DAIF_CONFIG (U(0x7)) +#define DAIF_FIQ_BIT (1U << 0) +#define DAIF_IRQ_BIT (1U << 1) +#define DAIF_ABT_BIT (1U << 2) +#define DAIF_DBG_BIT (1U << 3) +#define DAIF_CONFIG (0x7U) -#define PMSELR_EL0_SEL_MASK U(0x1f) +#define PMSELR_EL0_SEL_MASK (0x1fU) -#define EL_IMPL_NONE ULL(0) -#define MODE_EL_SHIFT U(0x2) -#define MODE_EL_MASK U(0x3) +#define EL_IMPL_NONE (0ULL) +#define MODE_EL_SHIFT (0x2U) +#define MODE_EL_MASK (0x3U) #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) -#define ID_AA64PFR0_EL1_SHIFT U(4) -#define ID_AA64PFR0_ELX_MASK ULL(0xf) +#define ID_AA64PFR0_EL1_SHIFT (4U) +#define ID_AA64PFR0_ELX_MASK (0xfULL) #endif /* VAL_ARCH_H */ diff --git a/val/include/val_sysreg.h b/val/include/val_sysreg.h index a5733e4e..464d9760 100644 --- a/val/include/val_sysreg.h +++ b/val/include/val_sysreg.h @@ -23,6 +23,19 @@ typedef unsigned long u_register_t; #define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory") +#ifdef isb +#undef isb +#endif +#ifdef wfi +#undef wfi +#endif +#ifdef wfe +#undef wfe +#endif +#ifdef sev +#undef sev +#endif + #ifndef __dead2 #define __dead2 __attribute__((noreturn)) #endif @@ -106,7 +119,7 @@ static inline void write_ ## _name(u_register_t v) \ * TLB maintenance accessor prototypes ******************************************************************************/ -#if ERRATA_A57_813419 +#ifdef ERRATA_A57_813419 /* * Define function for TLBI instruction with type specifier that implements * the workaround for errata 813419 of Cortex-A57. @@ -136,7 +149,7 @@ SYSOP_TYPE_FUNC(tlbi, alle1) SYSOP_TYPE_FUNC(tlbi, alle1is) SYSOP_TYPE_FUNC(tlbi, alle2) SYSOP_TYPE_FUNC(tlbi, alle2is) -#if ERRATA_A57_813419 +#ifdef ERRATA_A57_813419 TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) #else @@ -149,7 +162,7 @@ SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) -#if ERRATA_A57_813419 +#ifdef ERRATA_A57_813419 TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) #else From a1b794bccfec4d055708d2730f831bcbdffa49d7 Mon Sep 17 00:00:00 2001 From: Avi Nawal Date: Tue, 7 Apr 2026 08:10:12 +0000 Subject: [PATCH 13/13] Use consistent #if defined() style for preprocessor checks Signed-off-by: Avi Nawal Change-Id: Ie6a5437588bc53b262357e342321c083f85b9b90 --- val/include/val_logger.h | 9 +-------- val/include/val_status.h | 4 ++-- val/include/val_sysreg.h | 9 +-------- val/src/val_logger.c | 3 +-- 4 files changed, 5 insertions(+), 20 deletions(-) diff --git a/val/include/val_logger.h b/val/include/val_logger.h index 37c7b0b4..9da13ef0 100644 --- a/val/include/val_logger.h +++ b/val/include/val_logger.h @@ -8,15 +8,8 @@ #ifndef VAL_LOG_H #define VAL_LOG_H -#ifdef TARGET_UEFI -#include -#elif !defined(TARGET_LINUX) -#include -#include -#include -#endif - #include "pal_interface.h" +#include "pal_common_intf.h" /* Verbosity enums, Lower the value, higher the verbosity */ typedef enum { diff --git a/val/include/val_status.h b/val/include/val_status.h index 2d3ee891..503f276d 100644 --- a/val/include/val_status.h +++ b/val/include/val_status.h @@ -17,8 +17,8 @@ #ifndef VAL_STATUS_H #define VAL_STATUS_H -#if !defined(TARGET_UEFI) && !defined(TARGET_LINUX) -#include +#if !defined(TARGET_LINUX) +#include #endif #include "pal_interface.h" diff --git a/val/include/val_sysreg.h b/val/include/val_sysreg.h index 464d9760..0130440c 100644 --- a/val/include/val_sysreg.h +++ b/val/include/val_sysreg.h @@ -8,16 +8,9 @@ #ifndef VAL_SYSREG_H #define VAL_SYSREG_H -#ifdef TARGET_UEFI -#include -#elif !defined(TARGET_LINUX) -#include -#include -#include -#endif - #include "val_arch.h" #include "pal_interface.h" +#include "pal_common_intf.h" typedef unsigned long u_register_t; diff --git a/val/src/val_logger.c b/val/src/val_logger.c index 91846203..bfb5288a 100644 --- a/val/src/val_logger.c +++ b/val/src/val_logger.c @@ -5,8 +5,7 @@ * */ -#include "include/val_logger.h" -#include "include/pal_common_intf.h" +#include "val_logger.h" static void val_putc(char c) {