From b884c0036256f401651f97ded06e19c251a1d88a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 Apr 2026 16:12:13 +0200 Subject: [PATCH 01/62] vc/amd/opensil/phoenix_poc/mpio/chip.c: Set parameters for GFX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set parameters for GFX IP block intialization. Some of them are duplicated with NBIO, so we want to keep them in sync. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index ee678539400..e640dd6467e 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +97,7 @@ WEAK_DEV_PTR(usb4_pcie_bridge_1); static void nbio_params_config(SIL_CONTEXT *SilContext) { NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilContext, SilId_NbioClass, 0); + GFXCLASS_INPUT_BLK *gfx_data = SilFindStructure(SilContext, SilId_GfxClass, 0); NBIO_CONFIG_DATA *input = &nbio_data->NbioConfigData; input->EsmEnableAllRootPorts = false; input->EsmTargetSpeed = 16; @@ -105,6 +107,8 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) input->Usb4Rt0PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_0)); input->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1)); input->Usb4Rt1PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_1)); + gfx_data->Usb4Rt0En = input->Usb4Rt0En; + gfx_data->Usb4Rt1En = input->Usb4Rt1En; } #ifndef MPIO_ENGINE_DATA_INITIALIZER From 404d68cac618fcbcf2029f1d65b22a28a9bda487 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 14 Apr 2026 16:23:42 +0200 Subject: [PATCH 02/62] payloads/external/edk2: Add support for AMD GOP integration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass AMD GOP EFI driver and VBIOS file to EDK2 build system to be integrated in the DXE FV. The PciPlatformDriver will fetch the VBIOS from FV for given PCI device ID and vendor ID passed in the VGA_BIOS_ID Konfig option as PCDs. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- payloads/external/Makefile.mk | 7 +++++-- payloads/external/edk2/Kconfig | 10 +++++++++- payloads/external/edk2/Makefile | 11 +++++++++++ 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index d770ddc3ca4..3b8770833de 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -305,8 +305,11 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) CONFIG_EDK2_FW_VERSION=L"$(CONFIG_LOCALVERSION)" \ CONFIG_EDK2_FW_VENDOR=L"$(CONFIG_BIOS_VENDOR)" \ CONFIG_EDK2_FW_RELEASE_DATE=L"$(call get_build_value,COREBOOT_DMI_DATE)" \ - CONFIG_EDK2_FW_REVISION=$(shell printf 0x"%04x%04x" $(DASHARO_MAJOR_VERSION) $(DASHARO_MINOR_VERSION)) - + CONFIG_EDK2_FW_REVISION=$(shell printf 0x"%04x%04x" $(DASHARO_MAJOR_VERSION) $(DASHARO_MINOR_VERSION)) \ + CONFIG_EDK2_AMD_GOP_DRIVER=$(CONFIG_EDK2_AMD_GOP_DRIVER) \ + CONFIG_EDK2_VGA_BIOS_VENDOR_ID=0x$(word 1,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \ + CONFIG_EDK2_VGA_BIOS_DEVICE_ID=0x$(word 2,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \ + CONFIG_VGA_BIOS_FILE=$(CONFIG_VGA_BIOS_FILE) $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/edk2 UniversalPayload \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 870e2ad66e1..e3c4c654371 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -291,9 +291,17 @@ config EDK2_GOP_DRIVER help Select this option to have edk2 use an external GOP driver for display init. +config EDK2_AMD_GOP_DRIVER + bool "Add an AMD GOP driver to the Tianocore build" + depends on VGA_BIOS && NO_GFX_INIT && !EDK2_REPO_OFFICIAL && !EDK2_DISABLE_OPTION_ROMS + default y if VGA_BIOS && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX + help + Select this option to have edk2 use an external GOP driver for AMD display init. + config EDK2_GOP_FILE string "GOP driver file" - depends on EDK2_GOP_DRIVER + depends on EDK2_GOP_DRIVER || EDK2_AMD_GOP_DRIVER + default "AmdGopDriver.efi" if EDK2_AMD_GOP_DRIVER default "IntelGopDriver.efi" help The name of the GOP driver file passed to edk2. diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 64fe3eb9e5d..2c1af8f801a 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -462,6 +462,12 @@ endif ifneq ($(CONFIG_EDK2_FUM_AUTO_IPXE_BOOT),y) BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdFumAutoIpxeBoot=FALSE endif +# USE_AMD_PLATFORM_GOP = FALSE +ifeq ($(CONFIG_EDK2_AMD_GOP_DRIVER),y) +BUILD_STR += -D USE_AMD_PLATFORM_GOP=TRUE +BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomVendorId=$(CONFIG_EDK2_VGA_BIOS_VENDOR_ID) +BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomDeviceId=$(CONFIG_EDK2_VGA_BIOS_DEVICE_ID) +endif BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString=$(CONFIG_EDK2_FW_VERSION) BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor=$(CONFIG_EDK2_FW_VENDOR) @@ -560,6 +566,11 @@ gop_driver: $(EDK2_PATH) cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/IntelGopDriver.efi; \ cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/vbt.bin; \ fi; \ + if [ -n "$(CONFIG_EDK2_AMD_GOP_DRIVER)" ]; then \ + echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/AmdGopDriver.efi; \ + cp $(top)/$(CONFIG_VGA_BIOS_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/Vbios.bin; \ + fi; \ lan_rom: $(EDK2_PATH) case "$(CONFIG_EDK2_LAN_ROM_DRIVER)" in \ From 530048742b6b0d107efaf4e0fab41fe6fd98f525 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 Apr 2026 16:13:39 +0200 Subject: [PATCH 03/62] vc/amd/opensil/phoenix_poc/opensil: Bump for GFX init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/opensil | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 0f806f9815c..85cfb0f91f4 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 0f806f9815c5ed14d69acbc40202078af67964e8 +Subproject commit 85cfb0f91f4e1262cc4a5aa37664fe30d5027c15 From e7be23bfe666b6b37aee13a55ab8170cbe31b5fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 4 May 2026 12:48:25 +0200 Subject: [PATCH 04/62] vc/amd/opensil/phoenix_poc/mpio: Add support for specifying DDI ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DDI ports, as MPIO ports, are board specific. Add chip configuration to allow boards to specify DDI links via devicetree and pass the DDI link list to openSIL. TEST=HDMI display works on MSI PRO B850-P WIFI with PiKVM. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- .../amd/opensil/phoenix_poc/mpio/chip.c | 109 ++++++++++++------ .../amd/opensil/phoenix_poc/mpio/chip.h | 42 +++++++ 2 files changed, 115 insertions(+), 36 deletions(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index e640dd6467e..5dd5eae7f0b 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -13,6 +13,8 @@ #include "chip.h" +MPIO_DDI_DESCRIPTOR ddi_descriptor_list[MAX_DDI_PORTS]; + static void mpio_params_config(SIL_CONTEXT *SilContext) { MPIOCLASS_COMMON_INPUT_BLK *mpio_data = SilFindStructure(SilContext, SilId_MpioClass, 0); @@ -87,6 +89,8 @@ static void mpio_params_config(SIL_CONTEXT *SilContext) /* TODO handle this differently on multisocket */ mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST; mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList; + ddi_descriptor_list[0].Flags = DESCRIPTOR_TERMINATE_LIST; + mpio_data->PcieTopologyData.PlatformData[0].DdiLinkList = ddi_descriptor_list; } WEAK_DEV_PTR(usb4_router_0); @@ -112,32 +116,42 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) } #ifndef MPIO_ENGINE_DATA_INITIALIZER -#define MPIO_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane, mHotplug, mGpioGroupId) \ - { .EngineType = mType, \ - .HotPluggable = mHotplug, \ - .StartLane = mStartLane, \ - .EndLane = mEndLane, \ - .GpioGroupId = mGpioGroupId, \ - } +#define MPIO_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane, mHotplug, mGpioGroupId) \ + { \ + .EngineType = mType, \ + .HotPluggable = mHotplug, \ + .StartLane = mStartLane, \ + .EndLane = mEndLane, \ + .GpioGroupId = mGpioGroupId, \ + } #endif #ifndef MPIO_PORT_DATA_INITIALIZER_PCIE -#define MPIO_PORT_DATA_INITIALIZER_PCIE(mPortPresent, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, \ - mMaxLinkCap, mAspm, mAspmL1_1, mAspmL1_2, mClkPmSupport) \ - { \ - .PortPresent = mPortPresent, \ - .DeviceNumber = mDevAddress, \ - .FunctionNumber = mDevFunction, \ - .LinkSpeedCapability = mMaxLinkSpeed, \ - .LinkAspm = mAspm, \ - .LinkAspmL1_1 = mAspmL1_1, \ - .LinkAspmL1_2 = mAspmL1_2, \ - .LinkHotplug = mHotplug, \ - .MiscControls = { \ - .LinkSafeMode = mMaxLinkCap, \ - .ClkPmSupport = mClkPmSupport, \ - .TurnOffUnusedLanes = 1, \ - }, \ - } +#define MPIO_PORT_DATA_INITIALIZER_PCIE(mPortPresent, mDevAddress, mDevFunction, mHotplug, \ + mMaxLinkSpeed, mMaxLinkCap, mAspm, mAspmL1_1, \ + mAspmL1_2, mClkPmSupport) \ + { \ + .PortPresent = mPortPresent, \ + .DeviceNumber = mDevAddress, \ + .FunctionNumber = mDevFunction, \ + .LinkSpeedCapability = mMaxLinkSpeed, \ + .LinkAspm = mAspm, \ + .LinkAspmL1_1 = mAspmL1_1, \ + .LinkAspmL1_2 = mAspmL1_2, \ + .LinkHotplug = mHotplug, \ + .MiscControls = { \ + .LinkSafeMode = mMaxLinkCap, \ + .ClkPmSupport = mClkPmSupport, \ + .TurnOffUnusedLanes = 1, \ + }, \ + } +#endif +#ifndef MPIO_DDI_DATA_INITIALIZER +#define MPIO_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHdpIndex) \ + { \ + .ConnectorType = mConnectorType, \ + .AuxIndex = mAuxIndex, \ + .HdpIndex = mHdpIndex, \ + } #endif void opensil_mpio_per_device_config(struct device *dev) @@ -157,12 +171,15 @@ void opensil_mpio_per_device_config(struct device *dev) } } - static uint32_t slot_num; const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info; - printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", - domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + static int ddi_port = 0; + if (is_pci(dev)) + printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", + domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + else if (config->type == IFTYPE_DDI) + printk(BIOS_DEBUG, "Setting DDI port %u\n", ddi_port); if (config->type == IFTYPE_UNUSED) { if (is_dev_enabled(dev)) { @@ -174,9 +191,11 @@ void opensil_mpio_per_device_config(struct device *dev) return; } - static int mpio_port = 0; - MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; if (config->type == IFTYPE_PCIE) { + static uint32_t slot_num; + static int mpio_port = 0; + + MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, config->start_lane, config->end_lane, @@ -198,14 +217,32 @@ void opensil_mpio_per_device_config(struct device *dev) port.Port = port_data; port.Port.MiscControls.SbLink = config->sb_link; + + port.Port.AlwaysExpose = 1; + port.Port.SlotNum = ++slot_num; + mpio_data->PcieTopologyData.PortList[mpio_port] = port; + /* Update TERMINATE list */ + if (mpio_port > 0) + mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0; + mpio_port++; + } else if (config->type == IFTYPE_DDI) { + MPIO_DDI_DESCRIPTOR ddi = { .Flags = DESCRIPTOR_TERMINATE_LIST }; + const MPIO_DDI_DATA ddi_data = MPIO_DDI_DATA_INITIALIZER(config->ddi_connector, + config->aux, + config->hdp); + + if (ddi_port >= MAX_DDI_PORTS) { + printk(BIOS_WARNING, "Exceeded maximum number of DDI ports.\n"); + return; + } + + ddi.Ddi = ddi_data; + ddi_descriptor_list[ddi_port] = ddi; + /* Update TERMINATE list */ + if (ddi_port > 0) + ddi_descriptor_list[ddi_port - 1].Flags = 0; + ddi_port++; } - port.Port.AlwaysExpose = 1; - port.Port.SlotNum = ++slot_num; - mpio_data->PcieTopologyData.PortList[mpio_port] = port; - /* Update TERMINATE list */ - if (mpio_port > 0) - mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0; - mpio_port++; } void opensil_mpio_global_config(void) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h index 227d6e8a97b..6e0514c30cc 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h @@ -5,6 +5,8 @@ #include +#define MAX_DDI_PORTS 5 + /* * PHOENIX MPIO mapping * PCIE0 -> [0-19] bridges 1.1-1.5 @@ -15,6 +17,7 @@ enum mpio_type { IFTYPE_UNUSED, IFTYPE_PCIE, IFTYPE_SATA, + IFTYPE_DDI, }; /* Sync with PCIE_HOTPLUG_TYPE */ @@ -46,6 +49,41 @@ enum pcie_aspm { L0sL1, }; +enum ddi_type { + ConnDP, + ConnEDP, + ConnSingleLinkDVI, + ConnDualLinkDVI, + ConnHDMI, + ConnDpToVga, + ConnDpToLvds, + ConnNutmegDpToVga, + ConnSingleLinkDviI, + ConnDpWithTypeC, + ConnDpWithTypeCWithoutRetimer, + ConnDpWithoutTypeC, + ConnEDPToLvds, + ConnEDPToLvdsSwInit, + ConnAutoDetect, +}; + +enum ddi_aux { + DdiAux1, + DdiAux2, + DdiAux3, + DdiAux4, + DdiAux5, + DdiAux6, +}; + +enum ddi_hdp { + DdiHdp1, + DdiHdp2, + DdiHdp3, + DdiHdp4, + DdiHdp5, + DdiHdp6, +}; struct drivers_amd_opensil_mpio_config { enum mpio_type type; uint8_t start_lane; @@ -58,6 +96,10 @@ struct drivers_amd_opensil_mpio_config { uint8_t aspm_l1_2 : 1; uint8_t clock_pm : 1; uint8_t sb_link : 1; + /* DDI specific */ + enum ddi_type ddi_connector; + enum ddi_aux aux; + enum ddi_hdp hdp; }; #endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */ From 51e3a3b819e94c783a4aed529f6eb166051cf212 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 4 May 2026 12:50:34 +0200 Subject: [PATCH 05/62] mb/msi/ms7e56: Initialize integrated display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update APCB blobs to include the display parameters used by HDMI port. Describe the HDMI port as DDI link in devicetree, so that it will be passed to openSIL to prepare integrated graphics for GOP driver. TEST=HDMI display works on MSI PRO B850-P WIFI with PiKVM with AMD GOP in EDK2. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/data.apcb | Bin 12288 -> 12288 bytes src/mainboard/msi/ms7e56/data_rec.apcb | Bin 32768 -> 32768 bytes src/mainboard/msi/ms7e56/data_rec68.apcb | Bin 12288 -> 12288 bytes src/mainboard/msi/ms7e56/devicetree.cb | 10 +++++++++- 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/msi/ms7e56/data.apcb b/src/mainboard/msi/ms7e56/data.apcb index 3147362a84ee42a6dee230d8deae01b6323bd582..8712aced36922575a96738571b368d9fc6377c2b 100644 GIT binary patch delta 253 zcmZojXh;xr3~+X8U@%~qz|6q#{Chrw^hCjYXLmm*cUEx$21W)31_dSt23Bz<0RbQl z1Of~U|Nk>EF*5WpFoL8}00)Br6OSQC=*dJ!>xlt6xRID@h`+ZVg8{^n4f3$5u|D~V)9WY^~o&E0h4o> QRW@&A_Se~bfVq Date: Mon, 4 May 2026 13:39:13 +0200 Subject: [PATCH 06/62] configs/config.msi_ms7e56: Update configs to init GFX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Inappropriate [custom config] Signed-off-by: Michał Żygowski --- configs/config.msi_ms7e56 | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/configs/config.msi_ms7e56 b/configs/config.msi_ms7e56 index cfa7d3b5192..9820a36378c 100644 --- a/configs/config.msi_ms7e56 +++ b/configs/config.msi_ms7e56 @@ -1,3 +1,4 @@ +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS=y @@ -10,21 +11,24 @@ CONFIG_VGA_BIOS_FILE="Phoenix_generic_vbios.bin" CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_BOARD_MSI_PRO_B850_P=y +CONFIG_TPM_MEASURED_BOOT=y CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE=y -# CONFIG_ON_DEVICE_ROM_LOAD is not set -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y -CONFIG_YABEL_DIRECTHW=y +CONFIG_NO_GFX_INIT=y CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_TPM2=y +# CONFIG_TPM_HASH_SHA1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_TAG_OR_REV="origin/cbmem_pci_rb_info" -CONFIG_EDK2_DEBUG=y +CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_LOAD_OPTION_ROMS=y # CONFIG_EDK2_PS2_SUPPORT is not set -CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask=0x07" +CONFIG_EDK2_SERIAL_SUPPORT=y CONFIG_EDK2_ENABLE_IPXE=y CONFIG_IPXE_ADD_SCRIPT=y CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" @@ -42,11 +46,11 @@ CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y CONFIG_EDK2_DASHARO_POWER_CONFIG=y CONFIG_EDK2_DASHARO_PCI_CONFIG=y -CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y CONFIG_EDK2_BOOT_MENU_KEY=0x0015 CONFIG_EDK2_SETUP_MENU_KEY=0x0008 CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y # CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS is not set @@ -54,5 +58,4 @@ CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y CONFIG_DISPLAY_MTRRS=y CONFIG_OPENSIL_DEBUG_PREFIX=y CONFIG_OPENSIL_DEBUG_APOB=y -# CONFIG_OPENSIL_DEBUG_FCH is not set # CONFIG_OPENSIL_DEBUG_XUSL_CMN is not set From 003ca7818363fffa057ea8a7b94f3857df50b194 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 09:33:03 +0200 Subject: [PATCH 07/62] util/amdfwtool: Integrate Promontory firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Promontory firmware variants to the PSP directories. Also add a pointer to the Promontory firmware inside EFS. It will be used by coreboot to easily locate the firmware, load it to RAM and pass it to silicon initialization module. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- util/amdfwtool/amdfwread.c | 1 + util/amdfwtool/amdfwtool.c | 20 ++++++++++++++++++++ util/amdfwtool/amdfwtool.h | 3 ++- util/amdfwtool/data_parse.c | 8 ++++++++ util/amdfwtool/sbom.c | 1 + 5 files changed, 32 insertions(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index 74cd24ed81e..6de5dde2893 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -707,6 +707,7 @@ static int dump_efw(const embedded_firmware *fw_header) printf("\nMisc info"); printf("\n Promontory FW: %08x", fw_header->promontory_fw_ptr); printf("\n LP Promontory FW: %08x", fw_header->lp_promontory_fw_ptr); + printf("\n Promontory19 FW: %08x", fw_header->promontory19_fw_ptr); printf("\n Vendor ID: %04x", fw_header->vendor_id); printf("\n Board ID: %04x", fw_header->board_id); printf("\n ESPI0 Config: %02x", fw_header->espi0_config); diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 0234dac95d7..17b1c4a7626 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -291,6 +291,8 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_USB4, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PROM19, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB}, + { .type = AMD_FW_PROM19, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB}, { .type = AMD_FW_INVALID }, }; @@ -838,6 +840,14 @@ static void integrate_firmwares(context *ctx, case AMD_FW_XHCI: romsig->xhci_entry = RUN_CURRENT(*ctx); break; + case AMD_FW_PROM21: + if (fw_table[i].inst == 0) + romsig->promontory_fw_ptr = RUN_BASE(*ctx); + break; + case AMD_FW_PROM19: + if (fw_table[i].inst == 0) + romsig->promontory19_fw_ptr = RUN_BASE(*ctx); + break; default: /* Error */ break; @@ -1241,6 +1251,15 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].addr = RUN_CURRENT(*ctx); pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); + + /* Save as offsets in flash */ + if (fw_table[i].type == AMD_FW_PROM21 && fw_table[i].inst == 0) + ctx->amd_romsig_ptr->promontory_fw_ptr = + (uint32_t)RUN_OFFSET_MODE(*ctx, ctx->current, AMD_ADDR_REL_BIOS); + if (fw_table[i].type == AMD_FW_PROM19 && fw_table[i].inst == 0) + ctx->amd_romsig_ptr->promontory19_fw_ptr = + (uint32_t)RUN_OFFSET_MODE(*ctx, ctx->current, AMD_ADDR_REL_BIOS); + adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); } @@ -1882,6 +1901,7 @@ int main(int argc, char **argv) ctx.amd_romsig_ptr->psp_bak_directory = 0; ctx.amd_romsig_ptr->promontory_fw_ptr = 0; ctx.amd_romsig_ptr->lp_promontory_fw_ptr = 0; + ctx.amd_romsig_ptr->promontory19_fw_ptr = 0; ctx.amd_romsig_ptr->vendor_id = 0; ctx.amd_romsig_ptr->board_id = 0; ctx.amd_romsig_ptr->ubu_table = 0; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 94852e53e9c..86010c1dfbd 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -133,6 +133,7 @@ typedef enum _amd_fw_type { AMD_FW_USBDP = 0xa4, AMD_FW_USBSS = 0xa5, AMD_FW_USB4 = 0xa6, + AMD_FW_PROM19 = 0xa7, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, @@ -193,7 +194,7 @@ typedef struct _embedded_firmware { uint32_t psp_bak_directory; uint32_t promontory_fw_ptr; uint32_t lp_promontory_fw_ptr; - uint32_t reserved_38h; + uint32_t promontory19_fw_ptr; uint32_t reserved_3Ch; uint8_t spi_readmode_f15_mod_60_6f; uint8_t fast_speed_new_f15_mod_60_6f; diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index ae72145d7d8..2405a014d62 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -413,6 +413,14 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_FW_PROM21; subprog = 0; instance = 1; + } else if (strcmp(fw_name, "PROM19_FW_FILE") == 0) { + fw_type = AMD_FW_PROM19; + subprog = 0; + instance = 0; + } else if (strcmp(fw_name, "PROM19_FW_INS1_FILE") == 0) { + fw_type = AMD_FW_PROM19; + subprog = 0; + instance = 1; } else if (strcmp(fw_name, "LSDMA_FILE") == 0) { fw_type = AMD_FW_LSDMA; subprog = 0; diff --git a/util/amdfwtool/sbom.c b/util/amdfwtool/sbom.c index 4234afa0fc7..09e6a248df0 100644 --- a/util/amdfwtool/sbom.c +++ b/util/amdfwtool/sbom.c @@ -303,6 +303,7 @@ static const char *psp_fw_type_name(amd_fw_entry *entry) case AMD_FW_GMI3_PHY: return "AMD GMI3 PHY Firmware"; case AMD_FW_MPDMA_PM: return "AMD MPDMA PM Firmware"; case AMD_FW_PROM21: return "AMD Promontory 21 Firmware"; + case AMD_FW_PROM19: return "AMD Promontory 19 Firmware"; case AMD_FW_LSDMA: return "AMD LSDMA Firmware"; case AMD_FW_C20_MP: return "AMD C20 MP Firmware"; case AMD_FW_MINIMSMU: return "AMD Mini-SMU Firmware"; From dbe16c1fcfa50edd218ca2c32bc50f8e7e88891f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 09:36:52 +0200 Subject: [PATCH 08/62] soc/amd: Allocate 256KiB in early reserved DRAM for Promontory FW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allocate early memory for Promontory FW in the memory layout. The Promontory initialization should run with the FW in RAM. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 8 ++++++++ src/soc/amd/phoenix/Kconfig | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 024afbe7e5f..bb37c9ae1eb 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -36,6 +36,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | (VERSTAGE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR * | | + * | Promontory FW (if reqd) | + * | (256K) | + * +--------------------------------+ PROMONTORY_FW_ADDR + * | | * | FSP-M | * | (FSP_M_SIZE) | * +--------------------------------+ FSP_M_ADDR @@ -102,6 +106,10 @@ SECTIONS REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #endif +#if CONFIG_PROMONTORY_FW_ADDR > 0 + REGION(promontory, CONFIG_PROMONTORY_FW_ADDR, 256K, 4K) +#endif + #if CONFIG(VBOOT_SEPARATE_VERSTAGE) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 6f82513e3be..fc5ba462590 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -228,6 +228,15 @@ config VERSTAGE_ADDR Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. +config PROMONTORY_FW_ADDR + hex + default 0x21A0000 if SOC_AMD_PHOENIX_AM5 + default 0x0 + help + Sets the address in DRAM where Promontory FW should be loaded on AM5. + Promontory needs ~160KB of space. We allocate 256KB between romstage + and verstage, so that it will be placed in early reserved DRAM. + config VERSTAGE_SIZE hex depends on VBOOT_SEPARATE_VERSTAGE From 155baa73dac887d11385d7a108ce2694caf74c1f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 09:40:28 +0200 Subject: [PATCH 09/62] soc/amd/common/block/psp_efs: Add API to load Promontory FW from EFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add API for searching promontory FW in EFS and loading it to RAM at desired address. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- .../common/block/include/amdblocks/psp_efs.h | 3 +- src/soc/amd/common/block/psp/Makefile.mk | 1 + src/soc/amd/common/block/psp/psp_efs.c | 63 +++++++++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 9f1c1e8cbd5..fe05d9c4d5f 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -47,7 +47,7 @@ struct embedded_firmware { uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; uint32_t lp_promontory_fw_ptr; - uint32_t reserved_38h; + uint32_t promontory19_fw_ptr; uint32_t reserved_3Ch; uint8_t spi_readmode_f15_mod_60_6f; uint8_t fast_speed_new_f15_mod_60_6f; @@ -65,5 +65,6 @@ struct embedded_firmware { } __packed __aligned(16); bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed); +size_t efs_read_promontory_fw(void *buf); #endif /* AMD_COMMON_PSP_EFS_H */ diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index 9e12743190a..c8dbb0965ab 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -10,6 +10,7 @@ smm-y += psp_smm.c bootblock-y += psp_efs.c verstage-y += psp_efs.c +ramstage-y += psp_efs.c all-y += ftpm.c diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index fa69aea5548..a22c17dcadf 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -3,9 +3,13 @@ #include #include #include +#include #include +#include #include +#define PSP_FW_FILE_HEADER_SIZE 256 + bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) { bool ret = false; @@ -28,3 +32,62 @@ bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) rdev_munmap(boot_device_ro(), efs); return ret; } + +size_t efs_read_promontory_fw(void *buf) +{ + struct embedded_firmware *efs; + const struct region_device *boot_dev = boot_device_ro(); + uint8_t file_header[PSP_FW_FILE_HEADER_SIZE + 8]; + size_t read_bytes, fw_size; + uint32_t offset; + + if (!boot_dev || !buf) + return 0; + + efs = rdev_mmap(boot_dev, EFS_OFFSET, sizeof(*efs)); + if (!efs) + return 0; + + if (efs->signature != EMBEDDED_FW_SIGNATURE) { + rdev_munmap(boot_dev, efs); + return 0; + } + + offset = efs->promontory_fw_ptr; + rdev_munmap(boot_dev, efs); + + read_bytes = rdev_readat(boot_dev, file_header, offset, sizeof(file_header)); + if (read_bytes != sizeof(file_header)) + return 0; + + /* Get Promontory FW size */ + if (strncmp((char *)&file_header[0x10], "$PS1", 4)) { + /* Check Promontory FW signature */ + if (!strncmp((char *)file_header, "_PT_", 4)) + fw_size = *(uint32_t *)&file_header[4]; + else + return 0; + } else { + /* Check Promontory FW signature */ + if (!strncmp((char *)&file_header[PSP_FW_FILE_HEADER_SIZE], "_PT_", 4)) + fw_size = *(uint32_t *)&file_header[PSP_FW_FILE_HEADER_SIZE + 4]; + else + return 0; + + offset += PSP_FW_FILE_HEADER_SIZE; + } + + if (fw_size > 256 * KiB) { + printk(BIOS_DEBUG, "Found Promontory FW too big (size: %lx)\n", fw_size); + return 0; + } + + printk(BIOS_DEBUG, "Found Promontory FW @ 0x%08x (size: %lx)\n", + offset, fw_size); + + read_bytes = rdev_readat(boot_dev, buf, offset, fw_size); + if (read_bytes != fw_size) + return 0; + + return fw_size; +} From d954783b773f1be31d2aa668672761893f20a807 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 09:42:26 +0200 Subject: [PATCH 10/62] vc/amd/opensil/phoenix_poc: Add Promontory initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize Promontory chipset with newly added support for Promontory in openSIL. Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/Kconfig.debug | 6 ++++ .../amd/opensil/phoenix_poc/filter.h | 4 ++- .../amd/opensil/phoenix_poc/opensil | 2 +- .../amd/opensil/phoenix_poc/ramstage.c | 30 ++++++++++++++++++- 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/opensil/Kconfig.debug b/src/vendorcode/amd/opensil/Kconfig.debug index 3066844e56f..c57574c20b3 100644 --- a/src/vendorcode/amd/opensil/Kconfig.debug +++ b/src/vendorcode/amd/opensil/Kconfig.debug @@ -96,6 +96,12 @@ config OPENSIL_DEBUG_GFX help Enable printing graphics related messages. +config OPENSIL_DEBUG_PROM + bool "Enable Promontory messages" + default y + help + Enable printing Promontory related messages. + config OPENSIL_DEBUG_XUSL_CMN bool "Enable xUSL CommonLib messages" default y diff --git a/src/vendorcode/amd/opensil/phoenix_poc/filter.h b/src/vendorcode/amd/opensil/phoenix_poc/filter.h index 9852a7c2642..533884e8add 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/filter.h +++ b/src/vendorcode/amd/opensil/phoenix_poc/filter.h @@ -13,6 +13,7 @@ #define DEBUG_FILTER_CXL 0x00000200UL #define DEBUG_FILTER_RCMGR 0x00000800UL #define DEBUG_FILTER_GFX 0x00001000UL +#define DEBUG_FILTER_PROM 0x00002000UL #define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0) @@ -28,4 +29,5 @@ SIL_DEBUG(RAS) | \ SIL_DEBUG(CXL) | \ SIL_DEBUG(RCMGR) | \ - SIL_DEBUG(GFX)) + SIL_DEBUG(GFX) | \ + SIL_DEBUG(PROM)) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 85cfb0f91f4..4b607108764 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 85cfb0f91f4e1262cc4a5aa37664fe30d5027c15 +Subproject commit 4b607108764028252a0af32d39dd0968a98453b8 diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 7fdf5441dbb..0bc2192c903 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -5,7 +5,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -286,7 +288,7 @@ WEAK_DEV_PTR(lpc_bridge); static void configure_fch_acpi(SIL_CONTEXT *SilContext) { - FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpiP, 0); + FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpi, 0); FCHCLASS_INPUT_BLK *fch_data = SilFindStructure(SilContext, SilId_FchClass, 0); struct device *smb = DEV_PTR(smbus); @@ -340,6 +342,30 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) FCH_DEV_ENABLE(hid, 31); } +static void configure_promontory(SIL_CONTEXT *SilContext) +{ + PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); + size_t prom_fw_size; + + if (!prom_data) + return; + + prom_data->PromInputBlk.PT21ClkPMEnable = CONFIG(PCIEXP_CLK_PM); + prom_data->PromInputBlk.PT21L1Enable = CONFIG(PCIEXP_ASPM); + prom_data->PromInputBlk.PT21L1ssEnable = CONFIG(PCIEXP_L1_SUB_STATE); + prom_data->PromInputBlk.PT21DisableUnusedPciePort = 1; + + prom_fw_size = efs_read_promontory_fw((void *)CONFIG_PROMONTORY_FW_ADDR); + if (prom_fw_size) { + prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + prom_data->PromInputBlk.PT21FWLoading = 0; + prom_data->PromInputBlk.PT21RuninRam = 1; + } else { + prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + prom_data->PromInputBlk.PT21FWLoading = 1; + } +} + void setup_opensil(void) { SIL_CONTEXT SilContext; @@ -362,6 +388,8 @@ void setup_opensil(void) configure_usb(&SilContext); configure_ccx(&SilContext); configure_fch_acpi(&SilContext); + if (CONFIG(SOC_AMD_PHOENIX_AM5)) + configure_promontory(&SilContext); } static void opensil_entry(SIL_TIMEPOINT timepoint) From f7df7a474acdc06bb4550db2815877047c78d5cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 15:00:50 +0200 Subject: [PATCH 11/62] util/amdtool: Add Promontory configuration dumping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I83aa2363678c0c5a70cde4c34b65f87c87bb68ae Signed-off-by: Michał Żygowski --- util/amdtool/Makefile | 2 +- util/amdtool/amdtool.c | 17 +- util/amdtool/amdtool.h | 14 ++ util/amdtool/promontory.c | 395 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 424 insertions(+), 4 deletions(-) create mode 100644 util/amdtool/promontory.c diff --git a/util/amdtool/Makefile b/util/amdtool/Makefile index 7bf65ddefc5..59a28992193 100644 --- a/util/amdtool/Makefile +++ b/util/amdtool/Makefile @@ -14,7 +14,7 @@ CPPFLAGS += -I$(top)/util/amdtool CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include CPPFLAGS += -I$(top)/src/arch/x86/include -OBJS = amdtool.o gpio.o acpimmio.o spi.o lpc.o psb.o smn.o cpu.o irq.o espi.o ahci.o +OBJS = amdtool.o gpio.o acpimmio.o spi.o lpc.o psb.o smn.o cpu.o irq.o espi.o ahci.o promontory.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/amdtool/amdtool.c b/util/amdtool/amdtool.c index a3b44796600..e0646cb4873 100644 --- a/util/amdtool/amdtool.c +++ b/util/amdtool/amdtool.c @@ -119,7 +119,7 @@ static void print_version(void) static void print_usage(const char *name) { - printf("usage: %s [-vh?gicspGlMAa]\n", name); + printf("usage: %s [-vh?gicspGlMAaPa]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -133,6 +133,7 @@ static void print_usage(const char *name) " -A | --acpimmio: dump southbridge ACPI MMIO registers\n" " -R | --ahci: dump southbridge AHCI registers\n" " -p | --psb: dump Platform Secure Boot state\n" + " -P | --promontory: dump Promontory 21 chipset registers\n" " -a | --all: dump all known (safe) registers\n" "\n"); exit(1); @@ -185,7 +186,7 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_coremsrs = 0, dump_acpimmio = 0, dump_cpu = 0; int dump_spi = 0, dump_lpc = 0, show_gpio_diffs = 0, dump_psb = 0, dump_irq = 0; - int dump_ahci = 0; + int dump_ahci = 0, dump_promontory = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, @@ -200,11 +201,12 @@ int main(int argc, char *argv[]) {"ahci", 0, 0, 'R'}, {"psb", 0, 0, 'p'}, {"spi", 0, 0, 's'}, + {"promontory", 0, 0, 'P'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGilcMARpsa", + while ((opt = getopt_long(argc, argv, "vh?gGilcMARpsPa", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -241,6 +243,9 @@ int main(int argc, char *argv[]) case 's': dump_spi = 1; break; + case 'P': + dump_promontory = 1; + break; case 'a': dump_gpios = 1; show_gpio_diffs = 1; @@ -252,6 +257,7 @@ int main(int argc, char *argv[]) dump_spi = 1; dump_psb = 1; dump_ahci = 1; + dump_promontory = 1; break; case 'h': case '?': @@ -413,6 +419,11 @@ int main(int argc, char *argv[]) printf("\n\n"); } + if (dump_promontory) { + print_promontory(pacc); + printf("\n\n"); + } + /* Clean up */ acpimmio_cleanup(); pci_free_dev(nb); diff --git a/util/amdtool/amdtool.h b/util/amdtool/amdtool.h index 490e904ca5d..8c76df20415 100644 --- a/util/amdtool/amdtool.h +++ b/util/amdtool/amdtool.h @@ -99,6 +99,19 @@ static inline void outl(uint32_t value, uint16_t port) #define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_6 0x14f6 #define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_7 0x14f7 +/* Promontory 21 external PCIe chipset */ +#define PCI_DEVICE_ID_AMD_PT21_USP 0x43F4 +#define PCI_DEVICE_ID_AMD_PT21_DSP 0x43F5 +#define PCI_DEVICE_ID_AMD_PT21_SATA 0x43F6 +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L1 0x43F7 +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L2 0x43F8 +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L3 0x43F9 +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L4 0x43FA +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L5 0x43FB +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L6 0x43FC +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L7 0x43FD +#define PCI_DEVICE_ID_AMD_PT21_XHCI_L8 0x43FE + #define CPUID_TURIN_C1 0x00b00f21 #define CPUID_PHOENIX_A1 0x00a70f41 #define CPUID_PHOENIX_A2 0x00a70f52 @@ -140,5 +153,6 @@ int print_acpimmio(struct pci_dev *sb); void print_psb(struct pci_dev *nb); int print_irq_routing(struct pci_dev *sb, struct pci_dev *nb); int print_ahci_devs(struct pci_access *pacc, struct pci_dev *nb); +int print_promontory(struct pci_access *pacc); #endif diff --git a/util/amdtool/promontory.c b/util/amdtool/promontory.c new file mode 100644 index 00000000000..c927f15644d --- /dev/null +++ b/util/amdtool/promontory.c @@ -0,0 +1,395 @@ +/* amdtool: dump AMD Promontory 21 chipset registers */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Register addresses and access methods derived from: + * src/vendorcode/amd/opensil/phoenix_poc/opensil/xUSL/PROM/ + */ + +#include +#include +#include +#include "amdtool.h" + +/* Promontory 21 PCI Device IDs (AMD vendor 0x1022) */ +#define PT21_USP_DID 0x43F4 +#define PT21_SATA_DID 0x43F6 +#define PT21_XHCI_DID_MIN 0x43F7 +#define PT21_XHCI_DID_MAX 0x43FE + +/* + * Indirect register access via xHCI MMIO offsets. + * Write 3-byte address (MSB first), then read data byte. + * Status bit 7 = busy; poll until clear after each address byte write. + */ +#define PT21_IND_ADDR2 0x3002 +#define PT21_IND_ADDR1 0x3001 +#define PT21_IND_ADDR0 0x3000 +#define PT21_IND_DATA 0x3008 +#define PT21_IND_STATUS 0x3009 +#define PT21_IND_BUSY 0x80 + +/* Promontory 21 internal (indirect) register addresses */ +#define PT21_PME_REG 0x18515 +#define PT21_DBC_REG 0x18A61 +#define PT21_EFUSE_REG 0x2E37B +#define PT21_SATA_CTRL_REG 0x10151 +#define PT21_SATA_PORT_EN1 0x2471C +#define PT21_SATA_PORT_EN2 0x2E006 +#define PT21_SATA_CLKREQ 0x24720 + +#define PT21_NUM_USB3_PORTS 6 +#define PT21_NUM_USB2_PORT_GROUPS 3 /* 2 ports per group */ +#define PT21_NUM_HW_LPM 3 +#define PT21_NUM_SATA_PORTS 4 + +#define PT21_XHCI_MMIO_SIZE 0x4000 +#define PT21_GPIO_MMIO_SIZE 0x20 + +static const uint32_t hw_lpm_en[PT21_NUM_HW_LPM] = { + 0x1A58C, 0x1C58C, 0x1E58C +}; + +static const uint32_t usb3_gen1_swing[PT21_NUM_USB3_PORTS] = { + 0x19490, 0x1A490, 0x1B490, 0x1C490, 0x1D490, 0x1E490 +}; + +static const uint32_t usb3_gen1_ep[PT21_NUM_USB3_PORTS] = { + 0x19250, 0x1A250, 0x1B250, 0x1C250, 0x1D250, 0x1E250 +}; + +static const uint32_t usb3_gen2_swing[PT21_NUM_USB3_PORTS] = { + 0x194A0, 0x1A4A0, 0x1B4A0, 0x1C4A0, 0x1D4A0, 0x1E4A0 +}; + +static const uint32_t usb3_gen2_cp0_ep[PT21_NUM_USB3_PORTS] = { + 0x19252, 0x1A252, 0x1B252, 0x1C252, 0x1D252, 0x1E252 +}; + +static const uint32_t usb3_gen2_cp13_ep[PT21_NUM_USB3_PORTS] = { + 0x1925C, 0x1A25C, 0x1B25C, 0x1C25C, 0x1D25C, 0x1E25C +}; + +static const uint32_t usb3_gen2_cp14_ep[PT21_NUM_USB3_PORTS] = { + 0x1925E, 0x1A25E, 0x1B25E, 0x1C25E, 0x1D25E, 0x1E25E +}; + +static const uint32_t usb3_gen2_cp15_ep[PT21_NUM_USB3_PORTS] = { + 0x19260, 0x1A260, 0x1B260, 0x1C260, 0x1D260, 0x1E260 +}; + +static const uint32_t usb3_gen2_cp16_ep[PT21_NUM_USB3_PORTS] = { + 0x19262, 0x1A262, 0x1B262, 0x1C262, 0x1D262, 0x1E262 +}; + +/* + * USB2 TX regs: 4 entries per port-group (slew, drive, drive-dup, term). + * The duplicate at index 2/6/10 mirrors the driving-current register. + */ +static const uint32_t usb2_tx_reg[12] = { + 0x1A598, 0x1A599, 0x1A598, 0x1A59A, + 0x1C598, 0x1C599, 0x1C598, 0x1C59A, + 0x1E598, 0x1E599, 0x1E598, 0x1E59A +}; + +static const uint32_t sata_gen12_swing[PT21_NUM_SATA_PORTS] = { + 0x2D188, 0x2D388, 0x2D588, 0x2D788 +}; + +static const uint32_t sata_gen3_swing[PT21_NUM_SATA_PORTS] = { + 0x2D189, 0x2D389, 0x2D589, 0x2D789 +}; + +static const uint32_t sata_gen1_emph[PT21_NUM_SATA_PORTS] = { + 0x2D18B, 0x2D38B, 0x2D58B, 0x2D78B +}; + +static const uint32_t sata_gen2_emph[PT21_NUM_SATA_PORTS] = { + 0x2D18C, 0x2D38C, 0x2D58C, 0x2D78C +}; + +static const uint32_t sata_gen3_emph[PT21_NUM_SATA_PORTS] = { + 0x2D18D, 0x2D38D, 0x2D58D, 0x2D78D +}; + +static const uint32_t sata_speed_reg[PT21_NUM_SATA_PORTS] = { + 0x2D12B, 0x2D32B, 0x2D52B, 0x2D72B +}; + +static void pt21_wait_ready(uint8_t *mmio) +{ + unsigned int retries = 10000; + + while ((read8(mmio + PT21_IND_STATUS) & PT21_IND_BUSY) && retries--) + ; +} + +/* + * Read one byte from a Promontory 21 internal register via the indirect + * access mechanism at xHCI MMIO offsets 0x3000-0x3009. + * Matches Prom21XhciReadByte() in PromAccess.c. + */ +static uint8_t pt21_read_byte(uint8_t *mmio, uint32_t addr) +{ + /* Dummy status read (matches firmware behaviour) */ + (void)read8(mmio + PT21_IND_STATUS); + + write8(mmio + PT21_IND_ADDR2, (addr >> 16) & 0xFF); + pt21_wait_ready(mmio); + + write8(mmio + PT21_IND_ADDR1, (addr >> 8) & 0xFF); + pt21_wait_ready(mmio); + + write8(mmio + PT21_IND_ADDR0, addr & 0xFF); + pt21_wait_ready(mmio); + + return read8(mmio + PT21_IND_DATA); +} + +static void dump_pci_cfg(struct pci_dev *dev, const char *label) +{ + int i; + uint32_t val; + + printf("\n--- PCI Config: %s (%04x:%04x @ %02x:%02x.%u) ---\n", + label, dev->vendor_id, dev->device_id, + dev->bus, dev->dev, dev->func); + + for (i = 0; i < 0x100; i += 4) { + val = pci_read_long(dev, i); + if (val != 0xFFFFFFFF) + printf(" 0x%03x: 0x%08x\n", i, val); + } +} + +static void dump_usb_settings(uint8_t *mmio) +{ + int i; + uint8_t val; + + printf("\n--- USB Settings ---\n"); + + val = pt21_read_byte(mmio, PT21_PME_REG); + printf(" PME Control (0x%05x): 0x%02x PME %s\n", + PT21_PME_REG, val, (val & 0x80) ? "disabled" : "enabled"); + + val = pt21_read_byte(mmio, PT21_DBC_REG); + printf(" DbC Control (0x%05x): 0x%02x\n", PT21_DBC_REG, val); + + printf(" HW LPM:\n"); + for (i = 0; i < PT21_NUM_HW_LPM; i++) { + val = pt21_read_byte(mmio, hw_lpm_en[i]); + printf(" Group %d (0x%05x): 0x%02x bits[4:1]=0x%x\n", + i, hw_lpm_en[i], val, (val >> 1) & 0xF); + } +} + +static void dump_usb3_phy(uint8_t *mmio) +{ + int i; + + printf("\n--- USB3 PHY Tuning ---\n"); + for (i = 0; i < PT21_NUM_USB3_PORTS; i++) { + printf(" Port %d:\n", i); + printf(" Gen1 Swing (0x%05x): 0x%02x\n", + usb3_gen1_swing[i], pt21_read_byte(mmio, usb3_gen1_swing[i])); + printf(" Gen1 Emph/Preshoot (0x%05x): 0x%02x\n", + usb3_gen1_ep[i], pt21_read_byte(mmio, usb3_gen1_ep[i])); + printf(" Gen2 Swing (0x%05x): 0x%02x\n", + usb3_gen2_swing[i], pt21_read_byte(mmio, usb3_gen2_swing[i])); + printf(" Gen2 CP0 Emph/Pre (0x%05x): 0x%02x\n", + usb3_gen2_cp0_ep[i], pt21_read_byte(mmio, usb3_gen2_cp0_ep[i])); + printf(" Gen2 CP13 Emph/Pre (0x%05x): 0x%02x\n", + usb3_gen2_cp13_ep[i], pt21_read_byte(mmio, usb3_gen2_cp13_ep[i])); + printf(" Gen2 CP14 Emph/Pre (0x%05x): 0x%02x\n", + usb3_gen2_cp14_ep[i], pt21_read_byte(mmio, usb3_gen2_cp14_ep[i])); + printf(" Gen2 CP15 Emph/Pre (0x%05x): 0x%02x\n", + usb3_gen2_cp15_ep[i], pt21_read_byte(mmio, usb3_gen2_cp15_ep[i])); + printf(" Gen2 CP16 Emph/Pre (0x%05x): 0x%02x\n", + usb3_gen2_cp16_ep[i], pt21_read_byte(mmio, usb3_gen2_cp16_ep[i])); + } +} + +static void dump_usb2_phy(uint8_t *mmio) +{ + int i; + + printf("\n--- USB2 PHY Tuning ---\n"); + for (i = 0; i < PT21_NUM_USB2_PORT_GROUPS; i++) { + printf(" Port group %d (ports %d-%d):\n", i, i * 2, i * 2 + 1); + printf(" SlewRate (0x%05x): 0x%02x\n", + usb2_tx_reg[i * 4 + 0], + pt21_read_byte(mmio, usb2_tx_reg[i * 4 + 0])); + printf(" DrivingCurrent (0x%05x): 0x%02x\n", + usb2_tx_reg[i * 4 + 1], + pt21_read_byte(mmio, usb2_tx_reg[i * 4 + 1])); + printf(" Termination (0x%05x): 0x%02x\n", + usb2_tx_reg[i * 4 + 3], + pt21_read_byte(mmio, usb2_tx_reg[i * 4 + 3])); + } +} + +static void dump_sata_settings(uint8_t *mmio) +{ + int i; + uint8_t val; + + printf("\n--- SATA Settings ---\n"); + + val = pt21_read_byte(mmio, PT21_SATA_CTRL_REG); + printf(" SATA Controller (0x%05x): 0x%02x SATA %s\n", + PT21_SATA_CTRL_REG, val, (val & 0x02) ? "disabled" : "enabled"); + + val = pt21_read_byte(mmio, PT21_SATA_PORT_EN1); + printf(" Port Enable 1 (0x%05x): 0x%02x\n", PT21_SATA_PORT_EN1, val); + + val = pt21_read_byte(mmio, PT21_SATA_PORT_EN2); + printf(" Port Enable 2 (0x%05x): 0x%02x\n", PT21_SATA_PORT_EN2, val); + + val = pt21_read_byte(mmio, PT21_SATA_CLKREQ); + printf(" CLKREQ (0x%05x): 0x%02x\n", PT21_SATA_CLKREQ, val); + + printf("\n--- SATA PHY Tuning ---\n"); + for (i = 0; i < PT21_NUM_SATA_PORTS; i++) { + printf(" Port %d:\n", i); + printf(" Gen1/2 Swing (0x%05x): 0x%02x\n", + sata_gen12_swing[i], pt21_read_byte(mmio, sata_gen12_swing[i])); + printf(" Gen3 Swing (0x%05x): 0x%02x\n", + sata_gen3_swing[i], pt21_read_byte(mmio, sata_gen3_swing[i])); + printf(" Gen1 Emph (0x%05x): 0x%02x\n", + sata_gen1_emph[i], pt21_read_byte(mmio, sata_gen1_emph[i])); + printf(" Gen2 Emph (0x%05x): 0x%02x\n", + sata_gen2_emph[i], pt21_read_byte(mmio, sata_gen2_emph[i])); + printf(" Gen3 Emph (0x%05x): 0x%02x\n", + sata_gen3_emph[i], pt21_read_byte(mmio, sata_gen3_emph[i])); + printf(" Speed Reg (0x%05x): 0x%02x\n", + sata_speed_reg[i], pt21_read_byte(mmio, sata_speed_reg[i])); + } +} + +static void dump_gpio(uint64_t gpio_phys) +{ + const uint8_t *gpio_mmio; + + if (!gpio_phys) { + printf("\n--- GPIO: BAR not assigned ---\n"); + return; + } + + gpio_mmio = map_physical(gpio_phys, PT21_GPIO_MMIO_SIZE); + if (!gpio_mmio) { + printf("\n--- GPIO: failed to map 0x%08llx ---\n", + (unsigned long long)gpio_phys); + return; + } + + printf("\n--- GPIO (MMIO base 0x%08llx) ---\n", + (unsigned long long)gpio_phys); + printf(" Direction (0x00): 0x%08x\n", read32(gpio_mmio + 0x0)); + printf(" Output (0x08): 0x%08x\n", read32(gpio_mmio + 0x8)); + + unmap_physical((void *)gpio_mmio, PT21_GPIO_MMIO_SIZE); +} + +static struct pci_dev *find_pt21_xhci(struct pci_access *pacc) +{ + struct pci_dev *dev; + + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_IDENT); + if (dev->vendor_id == PCI_VENDOR_ID_AMD && + dev->device_id >= PT21_XHCI_DID_MIN && + dev->device_id <= PT21_XHCI_DID_MAX) + return dev; + } + return NULL; +} + +static struct pci_dev *find_pt21_dev(struct pci_access *pacc, uint16_t device) +{ + struct pci_dev *dev; + struct pci_filter filter; + + pci_filter_init(NULL, &filter); + filter.vendor = PCI_VENDOR_ID_AMD; + filter.device = device; + + for (dev = pacc->devices; dev; dev = dev->next) + if (pci_filter_match(&filter, dev)) + return dev; + return NULL; +} + +int print_promontory(struct pci_access *pacc) +{ + struct pci_dev *usp, *xhci, *sata; + uint8_t *xhci_mmio; + uint64_t xhci_phys, gpio_phys; + uint8_t efuse; + + printf("\n============= Promontory 21 ==============\n"); + + usp = find_pt21_dev(pacc, PT21_USP_DID); + if (!usp) { + printf("No Promontory 21 USP found (1022:%04x).\n", PT21_USP_DID); + return -1; + } + + printf("Found Promontory 21 USP (%04x:%04x) at %02x:%02x.%u\n", + usp->vendor_id, usp->device_id, + usp->bus, usp->dev, usp->func); + + xhci = find_pt21_xhci(pacc); + if (!xhci) { + printf("No Promontory 21 xHCI endpoint found.\n"); + return -1; + } + + printf("Found Promontory 21 xHCI (%04x:%04x) at %02x:%02x.%u\n", + xhci->vendor_id, xhci->device_id, + xhci->bus, xhci->dev, xhci->func); + + sata = find_pt21_dev(pacc, PT21_SATA_DID); + if (sata) + printf("Found Promontory 21 SATA (%04x:%04x) at %02x:%02x.%u\n", + sata->vendor_id, sata->device_id, + sata->bus, sata->dev, sata->func); + + dump_pci_cfg(usp, "Promontory21 USP"); + if (sata) + dump_pci_cfg(sata, "Promontory21 SATA"); + dump_pci_cfg(xhci, "Promontory21 xHCI"); + + pci_fill_info(xhci, PCI_FILL_BASES); + xhci_phys = xhci->base_addr[0] & ~(uint64_t)0xF; + + if (!xhci_phys || xhci_phys == (uint64_t)~0ULL) { + printf("xHCI BAR0 not assigned, cannot read indirect registers.\n"); + return -1; + } + + printf("\nxHCI MMIO base: 0x%08llx\n", (unsigned long long)xhci_phys); + + xhci_mmio = map_physical(xhci_phys, PT21_XHCI_MMIO_SIZE); + if (!xhci_mmio) { + printf("Failed to map xHCI MMIO.\n"); + return -1; + } + + efuse = pt21_read_byte(xhci_mmio, PT21_EFUSE_REG); + printf("\nSilicon Revision (eFUSE 0x%05x): 0x%02x (%s)\n", + PT21_EFUSE_REG, efuse, (efuse & 0x08) ? "A2" : "A0/A1"); + + dump_usb_settings(xhci_mmio); + dump_usb3_phy(xhci_mmio); + dump_usb2_phy(xhci_mmio); + dump_sata_settings(xhci_mmio); + + unmap_physical((void *)xhci_mmio, PT21_XHCI_MMIO_SIZE); + + /* GPIO MMIO BAR at USP PCI config offset 0x40, 16-byte aligned */ + gpio_phys = (uint64_t)(pci_read_long(usp, 0x40) & 0xFFFFFFF0U); + dump_gpio(gpio_phys); + + return 0; +} From c55adb74ca22be9a95837955931e4537a3b1c125 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 15:04:36 +0200 Subject: [PATCH 12/62] util/cbmem: Fix missing size parameter in TCG log dumps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I0ab522f0ee613781b3bbec1d79804f7364ec6891 Signed-off-by: Michał Żygowski --- util/cbmem/cbmem.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ddcd263665d..f04c4a08f13 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -646,7 +646,7 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log, size_t } /* Dump the TPM log table in format defined by specifications */ -static void dump_tpm_std_log(void *buf) +static void dump_tpm_std_log(void *buf, size_t size) { const struct tcpa_spec_entry *tspec_entry; const struct tcg_efi_spec_id_event *tcg_spec_entry; @@ -704,10 +704,13 @@ static void dump_tpm_cb_log(void) static void dump_tpm_log(void) { uint8_t *buf; + size_t size; - if (cbmem_drv_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, NULL, NULL) || - cbmem_drv_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, NULL, NULL)) { - dump_tpm_std_log(buf); + if (cbmem_drv_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size, NULL)) { + dump_tpm_std_log(buf, size); + free(buf); + } else if (cbmem_drv_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size, NULL)) { + dump_tpm_std_log(buf, size); free(buf); } else dump_tpm_cb_log(); From 7ea840ed4a6642a108dce728c40135e987b68288 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 8 May 2026 15:25:42 +0200 Subject: [PATCH 13/62] util/amdtool: Add Promontory PCIe configuration dumping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: Ifa9edbcf59c23d240af4f057552c0868e10b1a77 Signed-off-by: Michał Żygowski --- util/amdtool/promontory.c | 369 ++++++++++++++++++++++++++++++++------ 1 file changed, 310 insertions(+), 59 deletions(-) diff --git a/util/amdtool/promontory.c b/util/amdtool/promontory.c index c927f15644d..714c7f57776 100644 --- a/util/amdtool/promontory.c +++ b/util/amdtool/promontory.c @@ -19,29 +19,82 @@ /* * Indirect register access via xHCI MMIO offsets. - * Write 3-byte address (MSB first), then read data byte. + * Write 3-byte address (MSB first), then read/write data byte. * Status bit 7 = busy; poll until clear after each address byte write. */ #define PT21_IND_ADDR2 0x3002 #define PT21_IND_ADDR1 0x3001 #define PT21_IND_ADDR0 0x3000 -#define PT21_IND_DATA 0x3008 +#define PT21_IND_DATA_R 0x3008 +#define PT21_IND_DATA_W 0x3004 #define PT21_IND_STATUS 0x3009 #define PT21_IND_BUSY 0x80 /* Promontory 21 internal (indirect) register addresses */ + +/* USB settings */ #define PT21_PME_REG 0x18515 #define PT21_DBC_REG 0x18A61 -#define PT21_EFUSE_REG 0x2E37B -#define PT21_SATA_CTRL_REG 0x10151 -#define PT21_SATA_PORT_EN1 0x2471C -#define PT21_SATA_PORT_EN2 0x2E006 +/* USB port control bitmaps (1 bit per port, 0=enabled, 1=disabled) */ +#define PT21_USB_PORT_USB3 0x1C51C /* USB3 ports 0-5 */ +#define PT21_USB_PORT_USB2_L 0x1C51D /* USB2 ports 0-7 */ +#define PT21_USB_PORT_USB2_H 0x1C51E /* USB2 ports 8-11 */ + +/* PCIe / general configuration */ +/* + * Access gate for the 0x247xx register bank: write 0x86 to unlock, + * 0x00 to lock. Applies to DSP enable, SSID, CLKREQ, and SATA port regs. + */ +#define PT21_BANK_GATE 0x24788 +#define PT21_BANK_UNLOCK 0x86 +#define PT21_BANK_LOCK 0x00 +#define PT21_DSP_ENABLE 0x24734 /* 16-bit bitmap, bit N = DSP port N enabled */ +#define PT21_CLKREQ_MODE 0x24720 /* 16-bit, 2 bits per CLKREQ: mode */ +#define PT21_CLKREQ_PINSEL 0x24724 /* 32-bit, 4 bits per CLKREQ: pin select */ +/* + * Lane reversal per DSP port: PORM21_LANE_REVERSAL_REG(a) = 0x28003 + a*0x400 + * Valid for DSP ports 0..10 (PROM21_MAX_LANE_REVERSAL_DSP_NUMBER = 11) + */ +#define PT21_LANE_REV_BASE 0x28003 +#define PT21_LANE_REV_STEP 0x400 +/* PCIe Gen1 TX swing per lane: 0x2C001 + lane*0x100, lanes 0..11 */ +#define PT21_GEN1_SWING_BASE 0x2C001 +#define PT21_GEN1_SWING_STEP 0x100 +/* Thermal throttle control */ +#define PT21_THERMAL_CTRL 0x1C51F /* bit1=throttle en, bit2=gen1 applied, bit7=SI applied */ +#define PT21_THERMAL_THRESH 0x1E521 + +/* SATA */ +#define PT21_SATA_CTRL_REG 0x10151 /* bit1=SATA enabled */ +#define PT21_SATA_PORT_EN1 0x2471C /* gated: byte bitmap, bit N = port N enabled */ +#define PT21_SATA_PORT_EN2 0x2E006 /* ungated: byte bitmap */ #define PT21_SATA_CLKREQ 0x24720 +#define PT21_SATA_CAP 0x2E000 /* 32-bit AHCI CAP register */ +#define PT21_SATA_DEVSLP 0x2E00A /* byte bitmap: bit N = port N DevSleep enabled */ +#define PT21_SATA_HOTPLUG0 0x2E0C8 /* +PortNum for ports 0-3, bit3=hotplug enabled */ +#define PT21_AHCI_MSI_CAP 0x23C34 /* 0x50=MSI enabled, 0x70=disabled */ + +/* eFUSE / silicon revision */ +#define PT21_EFUSE_REG 0x2E37B /* bit3=1 - A2, else A0/A1 */ + +/* xHCI MSI and MSI-X capability header pointer register */ +#define PT21_XHCI_MSI_CAP 0x23834 /* 0x50=MSI enabled, 0x68=disabled */ +#define PT21_XHCI_MSIX_CAP 0x23851 /* 0x68=MSI-X enabled, 0x78=disabled */ +/* + * EqPreset register: bits[1:0] hold PT21EqPreset. + * Bit6 is also used by newer firmware as a load-done flag. + */ +#define PT21_EQ_PRESET_REG 0x1E51C /* bits[1:0] = PT21EqPreset */ +/* SATA device ID (16-bit) - behind the bank access gate */ +#define PT21_SATA_DID_REG 0x24706 /* SATA function device ID */ +#define PT21_SATA_DID_RAID 0x43BD /* RAID mode device ID */ #define PT21_NUM_USB3_PORTS 6 #define PT21_NUM_USB2_PORT_GROUPS 3 /* 2 ports per group */ #define PT21_NUM_HW_LPM 3 #define PT21_NUM_SATA_PORTS 4 +#define PT21_NUM_PCIE_LANES 12 +#define PT21_NUM_PCIE_CLKREQ 6 #define PT21_XHCI_MMIO_SIZE 0x4000 #define PT21_GPIO_MMIO_SIZE 0x20 @@ -116,6 +169,17 @@ static const uint32_t sata_speed_reg[PT21_NUM_SATA_PORTS] = { 0x2D12B, 0x2D32B, 0x2D52B, 0x2D72B }; +/* + * USB3 port speed-select registers (r_force_superspeed in Prom21.h): + * bit2 = force_function_enable + * bits[2:0]: 0x3 = hw default (no force) + * 0x4 = force Gen1x1, 0x5 = force Gen1x2 + * 0x6 = force Gen2x1, 0x7 = force Gen2x2 + */ +static const uint32_t usb3_force_ss[PT21_NUM_USB3_PORTS] = { + 0x19211, 0x1A211, 0x1B211, 0x1C211, 0x1D211, 0x1E211 +}; + static void pt21_wait_ready(uint8_t *mmio) { unsigned int retries = 10000; @@ -124,6 +188,16 @@ static void pt21_wait_ready(uint8_t *mmio) ; } +static void pt21_set_addr(uint8_t *mmio, uint32_t addr) +{ + write8(mmio + PT21_IND_ADDR2, (addr >> 16) & 0xFF); + pt21_wait_ready(mmio); + write8(mmio + PT21_IND_ADDR1, (addr >> 8) & 0xFF); + pt21_wait_ready(mmio); + write8(mmio + PT21_IND_ADDR0, addr & 0xFF); + pt21_wait_ready(mmio); +} + /* * Read one byte from a Promontory 21 internal register via the indirect * access mechanism at xHCI MMIO offsets 0x3000-0x3009. @@ -131,34 +205,60 @@ static void pt21_wait_ready(uint8_t *mmio) */ static uint8_t pt21_read_byte(uint8_t *mmio, uint32_t addr) { - /* Dummy status read (matches firmware behaviour) */ - (void)read8(mmio + PT21_IND_STATUS); - - write8(mmio + PT21_IND_ADDR2, (addr >> 16) & 0xFF); - pt21_wait_ready(mmio); - - write8(mmio + PT21_IND_ADDR1, (addr >> 8) & 0xFF); - pt21_wait_ready(mmio); + (void)read8(mmio + PT21_IND_STATUS); /* dummy status read */ + pt21_set_addr(mmio, addr); + return read8(mmio + PT21_IND_DATA_R); +} - write8(mmio + PT21_IND_ADDR0, addr & 0xFF); - pt21_wait_ready(mmio); +/* Read a 16-bit little-endian value via two consecutive byte reads. */ +static uint16_t pt21_read_word(uint8_t *mmio, uint32_t addr) +{ + uint16_t val; - return read8(mmio + PT21_IND_DATA); + (void)read8(mmio + PT21_IND_STATUS); + pt21_set_addr(mmio, addr); + val = read8(mmio + PT21_IND_DATA_R); + pt21_set_addr(mmio, addr + 1); + val |= (uint16_t)read8(mmio + PT21_IND_DATA_R) << 8; + return val; } -static void dump_pci_cfg(struct pci_dev *dev, const char *label) +/* Read a 32-bit little-endian value via four consecutive byte reads. */ +static uint32_t pt21_read_dword(uint8_t *mmio, uint32_t addr) { + uint32_t val = 0; int i; - uint32_t val; - printf("\n--- PCI Config: %s (%04x:%04x @ %02x:%02x.%u) ---\n", - label, dev->vendor_id, dev->device_id, - dev->bus, dev->dev, dev->func); + (void)read8(mmio + PT21_IND_STATUS); + for (i = 0; i < 4; i++) { + pt21_set_addr(mmio, addr + i); + val |= (uint32_t)read8(mmio + PT21_IND_DATA_R) << (8 * i); + } + return val; +} - for (i = 0; i < 0x100; i += 4) { - val = pci_read_long(dev, i); - if (val != 0xFFFFFFFF) - printf(" 0x%03x: 0x%08x\n", i, val); +/* + * Write one byte to a Promontory 21 internal register. + * Used only for the access-gate toggle (0x24788), not for configuration writes. + * Matches Prom21XhciWriteByte() in PromAccess.c. + */ +static void pt21_write_byte(uint8_t *mmio, uint32_t addr, uint8_t data) +{ + (void)read8(mmio + PT21_IND_STATUS); + pt21_set_addr(mmio, addr); + write8(mmio + PT21_IND_DATA_W, data); + pt21_wait_ready(mmio); +} + +static const char *decode_xhci_port_gen(uint8_t val) +{ + switch (val & 0x7) { + case 0x3: return "hw default"; + case 0x4: return "force Gen1x1"; + case 0x5: return "force Gen1x2"; + case 0x6: return "force Gen2x1"; + case 0x7: return "force Gen2x2"; + default: return "unknown"; } } @@ -170,11 +270,11 @@ static void dump_usb_settings(uint8_t *mmio) printf("\n--- USB Settings ---\n"); val = pt21_read_byte(mmio, PT21_PME_REG); - printf(" PME Control (0x%05x): 0x%02x PME %s\n", + printf(" PME Control (0x%05x): 0x%02x PME %s\n", PT21_PME_REG, val, (val & 0x80) ? "disabled" : "enabled"); val = pt21_read_byte(mmio, PT21_DBC_REG); - printf(" DbC Control (0x%05x): 0x%02x\n", PT21_DBC_REG, val); + printf(" DbC Control (0x%05x): 0x%02x\n", PT21_DBC_REG, val); printf(" HW LPM:\n"); for (i = 0; i < PT21_NUM_HW_LPM; i++) { @@ -182,6 +282,58 @@ static void dump_usb_settings(uint8_t *mmio) printf(" Group %d (0x%05x): 0x%02x bits[4:1]=0x%x\n", i, hw_lpm_en[i], val, (val >> 1) & 0xF); } + + /* + * Register 0x1C51C layout (USBGen2by1_port_mapping[] in Prom21.h): + * bit0 = USB3 GenSelect (PT21Usb3GenSelect) + * bits[6:1] = USB3 port 0-5 disable flags (1=disabled, 0=enabled) + */ + val = pt21_read_byte(mmio, PT21_USB_PORT_USB3); + printf(" USB3 ports 0-5 (0x%05x): 0x%02x" + " (bit0=GenSelect, bits[6:1]=disabled mask)\n", + PT21_USB_PORT_USB3, val); + printf(" GenSelect (bit0): 0x%x\n", val & 0x01); + for (i = 0; i < PT21_NUM_USB3_PORTS; i++) + printf(" USB3 Port %d (bit%d): %s\n", i, i + 1, + (val & (1 << (i + 1))) ? "disabled" : "enabled"); + + val = pt21_read_byte(mmio, PT21_USB_PORT_USB2_L); + printf(" USB2 ports 0-7 (0x%05x): 0x%02x\n", PT21_USB_PORT_USB2_L, val); + for (i = 0; i < 8; i++) + printf(" USB2 Port %d: %s\n", i, + (val & (1 << i)) ? "disabled" : "enabled"); + + val = pt21_read_byte(mmio, PT21_USB_PORT_USB2_H); + printf(" USB2 ports 8-11 (0x%05x): 0x%02x\n", PT21_USB_PORT_USB2_H, val); + for (i = 0; i < 4; i++) + printf(" USB2 Port %d: %s\n", 8 + i, + (val & (1 << i)) ? "disabled" : "enabled"); + + /* + * USB3 port speed: r_force_superspeed[] registers. + * bit2=force_function_enable; bits[2:0]: 3=hw default, + * 4=Gen1x1, 5=Gen1x2, 6=Gen2x1, 7=Gen2x2. + */ + printf(" USB3 Port Speed:\n"); + for (i = 0; i < PT21_NUM_USB3_PORTS; i++) { + val = pt21_read_byte(mmio, usb3_force_ss[i]); + printf(" Port %d (0x%05x): 0x%02x %s\n", + i, usb3_force_ss[i], val, + decode_xhci_port_gen(val)); + } + + /* EqPreset: bits[1:0] of 0x1E51C */ + val = pt21_read_byte(mmio, PT21_EQ_PRESET_REG); + printf(" EqPreset (0x%05x): 0x%02x bits[1:0]=0x%x\n", + PT21_EQ_PRESET_REG, val, val & 0x3); + + /* xHCI MSI and MSI-X capability header pointer */ + val = pt21_read_byte(mmio, PT21_XHCI_MSI_CAP); + printf(" xHCI MSI (0x%05x): 0x%02x MSI %s\n", + PT21_XHCI_MSI_CAP, val, (val == 0x50) ? "enabled" : "disabled"); + val = pt21_read_byte(mmio, PT21_XHCI_MSIX_CAP); + printf(" xHCI MSI-X (0x%05x): 0x%02x MSI-X %s\n", + PT21_XHCI_MSIX_CAP, val, (val == 0x68) ? "enabled" : "disabled"); } static void dump_usb3_phy(uint8_t *mmio) @@ -193,20 +345,26 @@ static void dump_usb3_phy(uint8_t *mmio) printf(" Port %d:\n", i); printf(" Gen1 Swing (0x%05x): 0x%02x\n", usb3_gen1_swing[i], pt21_read_byte(mmio, usb3_gen1_swing[i])); - printf(" Gen1 Emph/Preshoot (0x%05x): 0x%02x\n", - usb3_gen1_ep[i], pt21_read_byte(mmio, usb3_gen1_ep[i])); + /* + * Emphasis/preshoot registers are 16-bit words: + * bits[7:4] = EmpLevel, bit3 = PreshootEn, bits[2:0] = Preshoot + * bit8 = EmpLevelEn (PT21USB3PortGen*EmpLevelEn) + * Read as word so EmpLevelEn is captured in the upper byte. + */ + printf(" Gen1 Emph/Preshoot (0x%05x): 0x%04x\n", + usb3_gen1_ep[i], pt21_read_word(mmio, usb3_gen1_ep[i])); printf(" Gen2 Swing (0x%05x): 0x%02x\n", usb3_gen2_swing[i], pt21_read_byte(mmio, usb3_gen2_swing[i])); - printf(" Gen2 CP0 Emph/Pre (0x%05x): 0x%02x\n", - usb3_gen2_cp0_ep[i], pt21_read_byte(mmio, usb3_gen2_cp0_ep[i])); - printf(" Gen2 CP13 Emph/Pre (0x%05x): 0x%02x\n", - usb3_gen2_cp13_ep[i], pt21_read_byte(mmio, usb3_gen2_cp13_ep[i])); - printf(" Gen2 CP14 Emph/Pre (0x%05x): 0x%02x\n", - usb3_gen2_cp14_ep[i], pt21_read_byte(mmio, usb3_gen2_cp14_ep[i])); - printf(" Gen2 CP15 Emph/Pre (0x%05x): 0x%02x\n", - usb3_gen2_cp15_ep[i], pt21_read_byte(mmio, usb3_gen2_cp15_ep[i])); - printf(" Gen2 CP16 Emph/Pre (0x%05x): 0x%02x\n", - usb3_gen2_cp16_ep[i], pt21_read_byte(mmio, usb3_gen2_cp16_ep[i])); + printf(" Gen2 CP0 Emph/Pre (0x%05x): 0x%04x\n", + usb3_gen2_cp0_ep[i], pt21_read_word(mmio, usb3_gen2_cp0_ep[i])); + printf(" Gen2 CP13 Emph/Pre (0x%05x): 0x%04x\n", + usb3_gen2_cp13_ep[i], pt21_read_word(mmio, usb3_gen2_cp13_ep[i])); + printf(" Gen2 CP14 Emph/Pre (0x%05x): 0x%04x\n", + usb3_gen2_cp14_ep[i], pt21_read_word(mmio, usb3_gen2_cp14_ep[i])); + printf(" Gen2 CP15 Emph/Pre (0x%05x): 0x%04x\n", + usb3_gen2_cp15_ep[i], pt21_read_word(mmio, usb3_gen2_cp15_ep[i])); + printf(" Gen2 CP16 Emph/Pre (0x%05x): 0x%04x\n", + usb3_gen2_cp16_ep[i], pt21_read_word(mmio, usb3_gen2_cp16_ep[i])); } } @@ -229,25 +387,125 @@ static void dump_usb2_phy(uint8_t *mmio) } } +static void dump_pcie_config(uint8_t *mmio) +{ + int i; + uint16_t dsp_en, clkreq_mode; + uint32_t clkreq_pinsel; + uint8_t val; + + printf("\n--- PCIe DSP Configuration ---\n"); + + /* + * The 0x247xx register bank requires the access gate to be unlocked + * (write 0x86 to 0x24788) before reading, and locked again after + * (write 0x00). This matches the firmware sequence in Prom21.c / + * Prom21Sata.c for Prom21DSPortSetting / Prom21GppClockOutput. + */ + pt21_write_byte(mmio, PT21_BANK_GATE, PT21_BANK_UNLOCK); + dsp_en = pt21_read_word(mmio, PT21_DSP_ENABLE); + clkreq_mode = pt21_read_word(mmio, PT21_CLKREQ_MODE); + clkreq_pinsel = pt21_read_dword(mmio, PT21_CLKREQ_PINSEL); + pt21_write_byte(mmio, PT21_BANK_GATE, PT21_BANK_LOCK); + + printf(" DSP Port Enable (0x%05x): 0x%04x\n", PT21_DSP_ENABLE, dsp_en); + for (i = 0; i <= 12; i++) + printf(" DSP port %2d: %s\n", i, + (dsp_en & (1 << i)) ? "enabled" : "disabled"); + + printf("\n CLKREQ Mode (0x%05x): 0x%04x\n", PT21_CLKREQ_MODE, clkreq_mode); + for (i = 0; i < PT21_NUM_PCIE_CLKREQ; i++) + printf(" CLKREQ%d mode: %u\n", i, (clkreq_mode >> (i * 2)) & 0x3); + + printf("\n CLKREQ PinSel (0x%05x): 0x%08x\n", PT21_CLKREQ_PINSEL, clkreq_pinsel); + for (i = 0; i < PT21_NUM_PCIE_CLKREQ; i++) + printf(" CLKREQ%d pin: %u\n", i, (clkreq_pinsel >> (i * 4)) & 0xF); + + /* Lane reversal: one byte per DSP port, no access gate needed */ + printf("\n Lane Reversal (DSP ports 0-%d):\n", PT21_NUM_PCIE_LANES - 1); + for (i = 0; i < PT21_NUM_PCIE_LANES; i++) { + uint32_t reg = PT21_LANE_REV_BASE + i * PT21_LANE_REV_STEP; + + val = pt21_read_byte(mmio, reg); + printf(" DSP port %2d (0x%05x): 0x%02x %s\n", + i, reg, val, (val & 0x01) ? "reversed" : "normal"); + } + + /* PCIe Gen1 TX swing per lane, no access gate */ + printf("\n PCIe Gen1 TX Swing (lanes 0-%d):\n", PT21_NUM_PCIE_LANES - 1); + for (i = 0; i < PT21_NUM_PCIE_LANES; i++) { + uint32_t reg = PT21_GEN1_SWING_BASE + i * PT21_GEN1_SWING_STEP; + + val = pt21_read_byte(mmio, reg); + printf(" Lane %2d (0x%05x): 0x%02x\n", i, reg, val); + } + + /* Thermal throttle */ + val = pt21_read_byte(mmio, PT21_THERMAL_CTRL); + printf("\n Thermal Control (0x%05x): 0x%02x\n", PT21_THERMAL_CTRL, val); + printf(" Throttle enable: %s\n", (val & 0x02) ? "yes" : "no"); + printf(" Gen1 swing applied: %s\n", (val & 0x04) ? "yes" : "no"); + printf(" SI config applied: %s\n", (val & 0x80) ? "yes" : "no"); + val = pt21_read_byte(mmio, PT21_THERMAL_THRESH); + printf(" Thermal Threshold (0x%05x): 0x%02x\n", PT21_THERMAL_THRESH, val); +} + static void dump_sata_settings(uint8_t *mmio) { int i; uint8_t val; + uint16_t sata_did; + uint32_t cap; printf("\n--- SATA Settings ---\n"); val = pt21_read_byte(mmio, PT21_SATA_CTRL_REG); printf(" SATA Controller (0x%05x): 0x%02x SATA %s\n", - PT21_SATA_CTRL_REG, val, (val & 0x02) ? "disabled" : "enabled"); - - val = pt21_read_byte(mmio, PT21_SATA_PORT_EN1); - printf(" Port Enable 1 (0x%05x): 0x%02x\n", PT21_SATA_PORT_EN1, val); + PT21_SATA_CTRL_REG, val, (val & 0x02) ? "enabled" : "disabled"); + + /* Port enable and device ID are behind the access gate */ + pt21_write_byte(mmio, PT21_BANK_GATE, PT21_BANK_UNLOCK); + val = pt21_read_byte(mmio, PT21_SATA_PORT_EN1); + sata_did = pt21_read_word(mmio, PT21_SATA_DID_REG); + pt21_write_byte(mmio, PT21_BANK_GATE, PT21_BANK_LOCK); + printf(" SATA Mode (0x%05x): 0x%04x %s\n", + PT21_SATA_DID_REG, sata_did, + (sata_did == PT21_SATA_DID_RAID) ? "RAID" : "AHCI"); + printf(" Port Enable 1 (0x%05x): 0x%02x", PT21_SATA_PORT_EN1, val); + for (i = 0; i < PT21_NUM_SATA_PORTS; i++) + printf(" P%d=%s", i, (val & (1 << i)) ? "on" : "off"); + printf("\n"); val = pt21_read_byte(mmio, PT21_SATA_PORT_EN2); - printf(" Port Enable 2 (0x%05x): 0x%02x\n", PT21_SATA_PORT_EN2, val); - - val = pt21_read_byte(mmio, PT21_SATA_CLKREQ); - printf(" CLKREQ (0x%05x): 0x%02x\n", PT21_SATA_CLKREQ, val); + printf(" Port Enable 2 (0x%05x): 0x%02x", PT21_SATA_PORT_EN2, val); + for (i = 0; i < PT21_NUM_SATA_PORTS; i++) + printf(" P%d=%s", i, (val & (1 << i)) ? "on" : "off"); + printf("\n"); + + cap = pt21_read_dword(mmio, PT21_SATA_CAP); + printf(" AHCI CAP (0x%05x): 0x%08x\n", PT21_SATA_CAP, cap); + printf(" AggrLinkPmCap (bit26): %s\n", (cap & (1 << 26)) ? "yes" : "no"); + printf(" SscCap (bit14): %s\n", (cap & (1 << 14)) ? "yes" : "no"); + printf(" PscCap (bit13): %s\n", (cap & (1 << 13)) ? "yes" : "no"); + printf(" CccsCap (bit 7): %s\n", (cap & (1 << 7)) ? "yes" : "no"); + + val = pt21_read_byte(mmio, PT21_SATA_DEVSLP); + printf(" DevSleep (0x%05x): 0x%02x", PT21_SATA_DEVSLP, val); + for (i = 0; i < PT21_NUM_SATA_PORTS; i++) + printf(" P%d=%s", i, (val & (1 << i)) ? "on" : "off"); + printf("\n"); + + val = pt21_read_byte(mmio, PT21_AHCI_MSI_CAP); + printf(" AHCI MSI Cap (0x%05x): 0x%02x MSI %s\n", + PT21_AHCI_MSI_CAP, val, (val == 0x50) ? "enabled" : "disabled"); + + printf(" Hotplug per port:\n"); + for (i = 0; i < PT21_NUM_SATA_PORTS; i++) { + val = pt21_read_byte(mmio, PT21_SATA_HOTPLUG0 + i); + printf(" Port %d (0x%05x): 0x%02x hotplug %s\n", + i, PT21_SATA_HOTPLUG0 + i, val, + (val & 0x08) ? "enabled" : "disabled"); + } printf("\n--- SATA PHY Tuning ---\n"); for (i = 0; i < PT21_NUM_SATA_PORTS; i++) { @@ -322,7 +580,7 @@ static struct pci_dev *find_pt21_dev(struct pci_access *pacc, uint16_t device) int print_promontory(struct pci_access *pacc) { - struct pci_dev *usp, *xhci, *sata; + struct pci_dev *usp, *xhci; uint8_t *xhci_mmio; uint64_t xhci_phys, gpio_phys; uint8_t efuse; @@ -349,16 +607,8 @@ int print_promontory(struct pci_access *pacc) xhci->vendor_id, xhci->device_id, xhci->bus, xhci->dev, xhci->func); - sata = find_pt21_dev(pacc, PT21_SATA_DID); - if (sata) - printf("Found Promontory 21 SATA (%04x:%04x) at %02x:%02x.%u\n", - sata->vendor_id, sata->device_id, - sata->bus, sata->dev, sata->func); - - dump_pci_cfg(usp, "Promontory21 USP"); - if (sata) - dump_pci_cfg(sata, "Promontory21 SATA"); - dump_pci_cfg(xhci, "Promontory21 xHCI"); + if (find_pt21_dev(pacc, PT21_SATA_DID)) + printf("Found Promontory 21 SATA\n"); pci_fill_info(xhci, PCI_FILL_BASES); xhci_phys = xhci->base_addr[0] & ~(uint64_t)0xF; @@ -380,6 +630,7 @@ int print_promontory(struct pci_access *pacc) printf("\nSilicon Revision (eFUSE 0x%05x): 0x%02x (%s)\n", PT21_EFUSE_REG, efuse, (efuse & 0x08) ? "A2" : "A0/A1"); + dump_pcie_config(xhci_mmio); dump_usb_settings(xhci_mmio); dump_usb3_phy(xhci_mmio); dump_usb2_phy(xhci_mmio); From ed1244e638fa71513693b880426e2bb229d51e5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 18 May 2026 13:28:16 +0200 Subject: [PATCH 14/62] vc/amd/opensil/phoenix_poc,drivers/amd: Add PROM21 driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Promontory 21 chip driver that will serve as openSIL configuration setter based on devicetree config values. Change-Id: Ice1ae8cd882c13d5fa1186dded53326430db9621 Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/drivers/amd/promontory21/Kconfig | 6 + src/drivers/amd/promontory21/Makefile.mk | 3 + src/drivers/amd/promontory21/chip.c | 28 ++ src/drivers/amd/promontory21/chip.h | 156 +++++++++++ .../amd/promontory21/prom21_template.cb | 92 ++++++ .../amd/opensil/phoenix_poc/Makefile.mk | 1 + .../amd/opensil/phoenix_poc/mpio/chip.c | 4 + .../amd/opensil/phoenix_poc/opensil | 2 +- .../opensil/phoenix_poc/prom21/Makefile.mk | 5 + .../phoenix_poc/prom21/chip_to_opensil.c | 261 ++++++++++++++++++ .../amd/opensil/phoenix_poc/prom21/prom21.h | 6 + .../amd/opensil/phoenix_poc/ramstage.c | 27 -- 12 files changed, 563 insertions(+), 28 deletions(-) create mode 100644 src/drivers/amd/promontory21/Kconfig create mode 100644 src/drivers/amd/promontory21/Makefile.mk create mode 100644 src/drivers/amd/promontory21/chip.c create mode 100644 src/drivers/amd/promontory21/chip.h create mode 100644 src/drivers/amd/promontory21/prom21_template.cb create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/prom21/Makefile.mk create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/prom21/prom21.h diff --git a/src/drivers/amd/promontory21/Kconfig b/src/drivers/amd/promontory21/Kconfig new file mode 100644 index 00000000000..6dfc58f0cdb --- /dev/null +++ b/src/drivers/amd/promontory21/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_AMD_PROMONTORY21 + bool + help + Enable AMD Promontory21 chip driver. diff --git a/src/drivers/amd/promontory21/Makefile.mk b/src/drivers/amd/promontory21/Makefile.mk new file mode 100644 index 00000000000..ca1f7fb08df --- /dev/null +++ b/src/drivers/amd/promontory21/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_AMD_PROMONTORY21) += chip.c diff --git a/src/drivers/amd/promontory21/chip.c b/src/drivers/amd/promontory21/chip.c new file mode 100644 index 00000000000..f1859bfea78 --- /dev/null +++ b/src/drivers/amd/promontory21/chip.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static const char *prom21_sata_acpi_name(const struct device *dev) +{ + return "STCR"; +} + +struct device_operations prom21_sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .acpi_name = prom21_sata_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +struct chip_operations drivers_amd_promontory21_ops = { + .name = "AMD Promontory21", +}; diff --git a/src/drivers/amd/promontory21/chip.h b/src/drivers/amd/promontory21/chip.h new file mode 100644 index 00000000000..7ed45bfe77c --- /dev/null +++ b/src/drivers/amd/promontory21/chip.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PROMONTORY21_CHIP_H +#define PROMONTORY21_CHIP_H + +#include +#include +#include + +#define PROM21_MAX_PCIE_LANES 12 +#define PROM21_MAX_PCIE_CLKREQ 6 +#define PROM21_MAX_SATA_PORTS 4 +#define PROM21_XHCI_MAX_USB3_PORTS 6 +#define PROM21_XHCI_MAX_USB2_PORTS 12 + +#define PROM21_XHCI_DEVFN PCI_DEVFN(0xc, 0) +#define PROM21_SATA_DEVFN PCI_DEVFN(0xd, 0) + +struct prom21_sata_phy { + bool override; + uint8_t gen1_swing; + uint8_t gen2_swing; + uint8_t gen3_swing; + uint8_t gen1_emp_level; + uint8_t gen2_emp_level; + uint8_t gen3_emp_level; +}; + +struct prom21_usb3_phy { + bool override; + uint8_t gen1_swing; + uint8_t gen1_emp_level_en; + uint8_t gen1_emp_level; + uint8_t gen1_preshoot_en; + uint8_t gen1_preshoot; + uint8_t gen2_swing; + uint8_t gen2_cp0_emp_level_en; + uint8_t gen2_cp0_emp_level; + uint8_t gen2_cp0_preshoot_en; + uint8_t gen2_cp0_preshoot; + uint8_t gen2_cp13_emp_level_en; + uint8_t gen2_cp13_emp_level; + uint8_t gen2_cp13_preshoot_en; + uint8_t gen2_cp13_preshoot; + uint8_t gen2_cp14_emp_level_en; + uint8_t gen2_cp14_emp_level; + uint8_t gen2_cp14_preshoot_en; + uint8_t gen2_cp14_preshoot; + uint8_t gen2_cp15_emp_level_en; + uint8_t gen2_cp15_emp_level; + uint8_t gen2_cp15_preshoot_en; + uint8_t gen2_cp15_preshoot; + uint8_t gen2_cp16_emp_level_en; + uint8_t gen2_cp16_emp_level; + uint8_t gen2_cp16_preshoot_en; + uint8_t gen2_cp16_preshoot; +}; + +struct prom21_usb2_phy { + bool override; + uint8_t slew_rate; + uint8_t driving_current; + uint8_t termination; +}; + +enum prom21_xhci_port_gen { + XhciPortGenDefault = 0, + XhciPortGen1 = 1, + XhciPortGen2 = 2 +}; + +enum prom21_xhci_gen { + XhciGenDefault = 0, + XhciGen2x2 = 1, + XhciGen2x1 = 2 +}; + +enum prom21_boolean { + HwDefault = 0, + Disable = 1, + Enable = 2 +}; + +enum prom21_sata_mode { + SataAhci = 0, + SataRAID = 1 +}; + +enum prom21_clkreq_pin_select { + ClkreqPort0, + ClkreqPort1, + ClkreqPort2, + ClkreqPort3, + ClkreqPort4, + ClkreqPort5, + ClkreqPort6, + ClkreqPort7, + ClkreqPort8, + ClkreqPort9, + ClkreqPort10, + ClkreqPort11, + ClkreqUnused = 0xe +}; + +enum prom21_clkreq_mode { + ClkreqMode, + ClkAlwaysOn, + ClkAlwaysOff, + GpioMode +}; + +struct prom21_sata_config { + enum prom21_sata_mode sata_mode; + enum prom21_boolean aggresive_link_pm_cap; + enum prom21_boolean psc_cap; + enum prom21_boolean ssc_cap; + enum prom21_boolean hot_plug; + enum prom21_boolean cccs_cap; + enum prom21_boolean msi_cap; + uint8_t port_enable[PROM21_MAX_SATA_PORTS]; + enum prom21_boolean aggressive_dev_slp[PROM21_MAX_SATA_PORTS]; +}; + +struct prom21_usb_config { + enum prom21_xhci_gen usb3_gen; + enum prom21_xhci_port_gen port_gen[PROM21_XHCI_MAX_USB3_PORTS]; + enum prom21_boolean hw_lpm; + enum prom21_boolean dbc; +}; + +struct prom21_pcie_config { + enum prom21_boolean report_small_ltr; + bool gen1_swing_enable; + uint8_t pcie_gen1_swing[PROM21_MAX_PCIE_LANES]; + uint8_t eq_preset; + bool gpio_perst_enable; + enum prom21_boolean msi; + enum prom21_boolean msix; + enum prom21_clkreq_pin_select clkreq_pin_select[PROM21_MAX_PCIE_CLKREQ]; + enum prom21_clkreq_mode clkreq_mode[PROM21_MAX_PCIE_CLKREQ]; + enum prom21_boolean lane_reversal_en[PROM21_MAX_PCIE_LANES / 2]; + uint8_t port_target_speed[PROM21_MAX_PCIE_LANES]; +}; + +struct drivers_amd_promontory21_config { + enum prom21_boolean si_prog_enable; + struct prom21_usb3_phy usb3_phy[PROM21_XHCI_MAX_USB3_PORTS]; + struct prom21_usb2_phy usb2_phy[PROM21_XHCI_MAX_USB2_PORTS]; + struct prom21_sata_phy sata_phy[PROM21_MAX_SATA_PORTS]; + + struct prom21_usb_config usb; + struct prom21_sata_config sata; + struct prom21_pcie_config pcie; +}; + +#endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */ diff --git a/src/drivers/amd/promontory21/prom21_template.cb b/src/drivers/amd/promontory21/prom21_template.cb new file mode 100644 index 00000000000..dd9aaa0c64a --- /dev/null +++ b/src/drivers/amd/promontory21/prom21_template.cb @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# This file is a template. Mainboards should replicate this structure +# under the root port where the Promontory 21 chipset is located at. +# Placing the below topology under the root port is required for the driver +# to correctly parse the topology and apply settings based on the devicetree. + +chip drivers/amd/promontory21 + device pci 00.0 alias prom21_usp on # Upstream Port + device pci 00.0 alias prom21_dsp_pcie_1 off end + device pci 01.0 alias prom21_dsp_pcie_2 off end + device pci 02.0 alias prom21_dsp_pcie_3 off end + device pci 03.0 alias prom21_dsp_pcie_4 off end + device pci 04.0 alias prom21_dsp_pcie_5 off end + device pci 05.0 alias prom21_dsp_pcie_6 off end + device pci 06.0 alias prom21_dsp_pcie_7 off end + device pci 07.0 alias prom21_dsp_pcie_8 off end + device pci 08.0 alias prom21_dsp_pcie_9 off end + device pci 09.0 alias prom21_dsp_pcie_10 off end + device pci 0a.0 alias prom21_dsp_pcie_11 off end + device pci 0b.0 alias prom21_dsp_pcie_12 off end + device pci 0c.0 alias prom21_dsp_xhci off + device pci 00.0 alias prom21_xhci off + ops xhci_pci_ops + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias prom_21_xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias prom21_usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias prom21_usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias prom21_usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias prom21_usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias prom21_usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias prom21_usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias prom21_usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias prom21_usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias prom21_usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias prom21_usb2_port10 off end + end + chip drivers/usb/acpi + device usb 2.a alias prom21_usb2_port11 off end + end + chip drivers/usb/acpi + device usb 2.b alias prom21_usb2_port12 off end + end + chip drivers/usb/acpi + device usb 3.0 alias prom21_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias prom21_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias prom21_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias prom21_usb3_port4 off end + end + chip drivers/usb/acpi + device usb 3.4 alias prom21_usb3_port5 off end + end + chip drivers/usb/acpi + device usb 3.5 alias prom21_usb3_port6 off end + end + end + end + end + end + device pci 0d.0 alias prom21_dsp_sata off + device pci 00.0 alias prom21_sata off + ops prom21_sata_ops + end + end + end +end diff --git a/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk index 5d36d56f934..fc97ac90238 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk +++ b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += mpio +subdirs-$(CONFIG_DRIVERS_AMD_PROMONTORY21) += prom21 CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index 5dd5eae7f0b..e45f5b034d3 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -12,6 +12,7 @@ #include #include "chip.h" +#include "../prom21/prom21.h" MPIO_DDI_DESCRIPTOR ddi_descriptor_list[MAX_DDI_PORTS]; @@ -218,6 +219,9 @@ void opensil_mpio_per_device_config(struct device *dev) port.Port = port_data; port.Port.MiscControls.SbLink = config->sb_link; + if (CONFIG(DRIVERS_AMD_PROMONTORY21) && config->sb_link) + opensil_promontory21_config(&SilContext, dev); + port.Port.AlwaysExpose = 1; port.Port.SlotNum = ++slot_num; mpio_data->PcieTopologyData.PortList[mpio_port] = port; diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 4b607108764..0f946edc16e 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 4b607108764028252a0af32d39dd0968a98453b8 +Subproject commit 0f946edc16e15381af6b9487cd71c1d7206e37c6 diff --git a/src/vendorcode/amd/opensil/phoenix_poc/prom21/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/prom21/Makefile.mk new file mode 100644 index 00000000000..b0a411729ba --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/prom21/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_AMD_PROMONTORY21) += chip_to_opensil.c + +$(obj)/ramstage/vendorcode/amd/opensil/phoenix_poc/promontory21/chip_to_opensil.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c new file mode 100644 index 00000000000..9d8b960aa3f --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "prom21.h" + +static void prom21_boolean_to_opensil(enum prom21_boolean b, uint8_t *out) +{ + if (b == HwDefault) + return; + + *out = (b == Enable) ? 1 : 0; +} + +static uint8_t xhci_gen_to_opensil(enum prom21_xhci_gen gen) +{ + return (gen == XhciGenDefault) ? 0xf : gen - 1; +} + +static uint8_t port_gen_to_opensil(enum prom21_xhci_port_gen gen) +{ + return (gen == XhciPortGenDefault) ? 0xf : gen - 1; +} + +static void apply_usb3_phy(const struct prom21_usb3_phy *src, + PROM21_USB3_PHY_TUNING *dst) +{ + if (!src->override) + return; + + dst->PT21USB3PortGen1Swing = src->gen1_swing; + dst->PT21USB3PortGen1EmpLevelEn = src->gen1_emp_level_en; + dst->PT21USB3PortGen1EmpLevel = src->gen1_emp_level; + dst->PT21USB3PortGen1PreshootEn = src->gen1_preshoot_en; + dst->PT21USB3PortGen1Preshoot = src->gen1_preshoot; + dst->PT21USB3PortGen2Swing = src->gen2_swing; + dst->PT21USB3PortGen2Cp0EmpLevelEn = src->gen2_cp0_emp_level_en; + dst->PT21USB3PortGen2Cp0EmpLevel = src->gen2_cp0_emp_level; + dst->PT21USB3PortGen2Cp0PreshootEn = src->gen2_cp0_preshoot_en; + dst->PT21USB3PortGen2Cp0Preshoot = src->gen2_cp0_preshoot; + dst->PT21USB3PortGen2Cp13EmpLevelEn = src->gen2_cp13_emp_level_en; + dst->PT21USB3PortGen2Cp13EmpLevel = src->gen2_cp13_emp_level; + dst->PT21USB3PortGen2Cp13PreshootEn = src->gen2_cp13_preshoot_en; + dst->PT21USB3PortGen2Cp13Preshoot = src->gen2_cp13_preshoot; + dst->PT21USB3PortGen2Cp14EmpLevelEn = src->gen2_cp14_emp_level_en; + dst->PT21USB3PortGen2Cp14EmpLevel = src->gen2_cp14_emp_level; + dst->PT21USB3PortGen2Cp14PreshootEn = src->gen2_cp14_preshoot_en; + dst->PT21USB3PortGen2Cp14Preshoot = src->gen2_cp14_preshoot; + dst->PT21USB3PortGen2Cp15EmpLevelEn = src->gen2_cp15_emp_level_en; + dst->PT21USB3PortGen2Cp15EmpLevel = src->gen2_cp15_emp_level; + dst->PT21USB3PortGen2Cp15PreshootEn = src->gen2_cp15_preshoot_en; + dst->PT21USB3PortGen2Cp15Preshoot = src->gen2_cp15_preshoot; + dst->PT21USB3PortGen2Cp16EmpLevelEn = src->gen2_cp16_emp_level_en; + dst->PT21USB3PortGen2Cp16EmpLevel = src->gen2_cp16_emp_level; + dst->PT21USB3PortGen2Cp16PreshootEn = src->gen2_cp16_preshoot_en; + dst->PT21USB3PortGen2Cp16Preshoot = src->gen2_cp16_preshoot; +} + +static void apply_usb2_phy(const struct prom21_usb2_phy *src, + PROM21_USB2_PHY_TUNING *dst) +{ + if (!src->override) + return; + + dst->PT21USB2SlewRate = src->slew_rate; + dst->PT21USB2DrivingCurrent = src->driving_current; + dst->PT21USB2Termination = src->termination; +} + +static void apply_sata_phy(const struct prom21_sata_phy *src, + PROM21_SATA_PHY_TUNING *dst) +{ + if (!src->override) + return; + + dst->PT21SataPortGen1Swing = src->gen1_swing; + dst->PT21SataPortGen2Swing = src->gen2_swing; + dst->PT21SataPortGen3Swing = src->gen3_swing; + dst->PT21SataPortGen1EmpLevel = src->gen1_emp_level; + dst->PT21SataPortGen2EmpLevel = src->gen2_emp_level; + dst->PT21SataPortGen3EmpLevel = src->gen3_emp_level; +} + +static void config_usb_port_enables(struct device *xhci_dev, + PROM21_DATA_BLK *primary) +{ + struct bus *xhci_bus = xhci_dev->downstream; + if (!xhci_bus) + return; + + /* The root hub is the first (and only) child on the xHCI PCI link. */ + struct device *root_hub = xhci_bus->children; + if (!root_hub || !root_hub->downstream) + return; + + for (struct device *port = root_hub->downstream->children; + port; port = port->sibling) { + unsigned int port_type, port_id; + + if (port->path.type != DEVICE_PATH_USB) + continue; + + port_type = port->path.usb.port_type; + port_id = port->path.usb.port_id; + + if (port_type == 3 && port_id < PROM21_XHCI_NUM_USB3_PORTS) + primary->PT21Usb3Port[port_id] = port->enabled; + else if (port_type == 2 && port_id < PROM21_XHCI_NUM_USB2_PORTS) + primary->PT21Usb2Port[port_id] = port->enabled; + } +} + +void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_port) +{ + PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); + PROMCLASS_INPUT_BLK *input_blk; + PROM21_DATA_BLK *primary; + const struct drivers_amd_promontory21_config *cfg; + const struct prom21_pcie_config *pcie; + const struct prom21_usb_config *usb; + const struct prom21_sata_config *sata; + struct device *usp, *dsp; + size_t prom_fw_size; + int i; + + if (!prom_data) { + printk(BIOS_ERR, "Could not find OpenSIL PROM data\n"); + return; + } + + input_blk = &prom_data->PromInputBlk; + + prom_fw_size = efs_read_promontory_fw((void *)CONFIG_PROMONTORY_FW_ADDR); + if (prom_fw_size) { + input_blk->PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + input_blk->PT21FWLoading = 0; + input_blk->PT21RuninRam = 1; + } else { + input_blk->PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + input_blk->PT21FWLoading = 1; + } + + input_blk->PT21DisableUnusedPciePort = false; + input_blk->PT21ClkPMEnable = CONFIG(PCIEXP_CLK_PM); + input_blk->PT21L1Enable = CONFIG(PCIEXP_ASPM); + input_blk->PT21L1ssEnable = CONFIG(PCIEXP_L1_SUB_STATE); + + /* The USP (Upstream Switch Port) is the first PCI child of root_port. */ + if (!root_port->downstream) + return; + + usp = root_port->downstream->children; + if (!usp || !usp->chip_info) + return; + + cfg = usp->chip_info; + primary = &input_blk->Primary; + + /* + * Walk USP's downstream PCIe bus to derive port and function enables. + * DSP devices: pci 00.0-0b.0 - PCIe ports 0-11 + * pci 0c.0 - xHCI (USB port enables come from here) + * pci 0d.0 - SATA + */ + for (dsp = usp->downstream ? usp->downstream->children : NULL; + dsp; dsp = dsp->sibling) { + unsigned int slot; + + if (dsp->path.type != DEVICE_PATH_PCI) + continue; + + slot = PCI_SLOT(dsp->path.pci.devfn); + + if (slot < PROM21_NUM_PCIE_LANES) { + /* DSP PCIe port: slot 0-11 maps to port index 0-11 */ + primary->PT21PciePortEnable[slot] = dsp->enabled; + } else if (dsp->path.pci.devfn == PROM21_XHCI_DEVFN) { + struct device *xhci = dsp->downstream + ? dsp->downstream->children : NULL; + if (xhci) + config_usb_port_enables(xhci, primary); + } else if (dsp->path.pci.devfn == PROM21_SATA_DEVFN) { + primary->PT21SataEnable = dsp->enabled ? 1 : 0; + } + } + + /* PCIe configuration from chip config */ + pcie = &cfg->pcie; + + prom21_boolean_to_opensil(pcie->report_small_ltr, &primary->PT21LtrSmallEnable); + primary->PT21PcieGen1SwingEnable = pcie->gen1_swing_enable; + if (pcie->gen1_swing_enable) { + for (i = 0; i < PROM21_NUM_PCIE_LANES; i++) + primary->PT21PcieGen1Swing[i] = pcie->pcie_gen1_swing[i]; + } + + primary->PT21EqPreset = pcie->eq_preset; + primary->PT21GpioPerstEnable = pcie->gpio_perst_enable; + prom21_boolean_to_opensil(pcie->msi, &primary->PT21Msi); + prom21_boolean_to_opensil(pcie->msix, &primary->PT21Msix); + + for (i = 0; i < PROM21_NUM_PCIE_CLKREQ; i++) { + primary->PT21PcieClkreqPinSelect[i] = pcie->clkreq_pin_select[i]; + primary->PT21PcieClkreqMode[i] = pcie->clkreq_mode[i]; + } + + for (i = 0; i < PROM21_NUM_PCIE_LANES / 2; i++) + prom21_boolean_to_opensil(pcie->lane_reversal_en[i], + &primary->PT21PciePortLaneRev[i]); + + /* Only write port_target_speed when explicitly set (non-zero). */ + for (i = 0; i < PROM21_NUM_PCIE_LANES; i++) + if (pcie->port_target_speed[i]) + primary->PT21PciePortTargetSpeed[i] = pcie->port_target_speed[i]; + + /* Global SI program enable */ + prom21_boolean_to_opensil(cfg->si_prog_enable, &primary->PT21SIProgEnable); + + if (cfg->si_prog_enable == Enable) { + for (i = 0; i < PROM21_XHCI_NUM_USB3_PORTS; i++) + apply_usb3_phy(&cfg->usb3_phy[i], &primary->PT21USB3Phy[i]); + for (i = 0; i < PROM21_XHCI_NUM_USB2_PORTS / 2; i++) + apply_usb2_phy(&cfg->usb2_phy[i], &primary->PT21USB2Phy[i]); + for (i = 0; i < PROM21_NUM_SATA_PORTS; i++) + apply_sata_phy(&cfg->sata_phy[i], &primary->PT21SataPhy[i]); + } + + /* USB functional settings from chip config */ + usb = &cfg->usb; + + primary->PT21Usb3GenSelect = xhci_gen_to_opensil(usb->usb3_gen); + for (i = 0; i < PROM21_XHCI_NUM_USB3_PORTS; i++) + primary->PT21XhciPortGen[i] = port_gen_to_opensil(usb->port_gen[i]); + + prom21_boolean_to_opensil(usb->hw_lpm, &primary->PT21HW_LPM); + prom21_boolean_to_opensil(usb->dbc, &primary->PT21DbC); + + /* SATA functional settings from chip config */ + sata = &cfg->sata; + primary->PT21SataMode = sata->sata_mode; + + prom21_boolean_to_opensil(sata->aggresive_link_pm_cap, &primary->PT21SataAggrLinkPmCap); + prom21_boolean_to_opensil(sata->psc_cap, &primary->PT21SataPscCap); + prom21_boolean_to_opensil(sata->ssc_cap, &primary->PT21SataSscCap); + prom21_boolean_to_opensil(sata->hot_plug, &primary->PT21SataHotPlug); + prom21_boolean_to_opensil(sata->cccs_cap, &primary->PT21SataPTSataCCCSCap); + prom21_boolean_to_opensil(sata->msi_cap, &primary->PT21AhciMsiCap); + + for (i = 0; i < PROM21_NUM_SATA_PORTS; i++) { + primary->PT21SataPortEnable[i] = sata->port_enable[i]; + prom21_boolean_to_opensil(sata->aggressive_dev_slp[i], + &primary->PT21SataAggressiveDevSlp[i]); + } +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/prom21/prom21.h b/src/vendorcode/amd/opensil/phoenix_poc/prom21/prom21.h new file mode 100644 index 00000000000..0106ba33072 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/prom21/prom21.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_port); diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 0bc2192c903..c8375324be1 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -342,30 +341,6 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) FCH_DEV_ENABLE(hid, 31); } -static void configure_promontory(SIL_CONTEXT *SilContext) -{ - PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); - size_t prom_fw_size; - - if (!prom_data) - return; - - prom_data->PromInputBlk.PT21ClkPMEnable = CONFIG(PCIEXP_CLK_PM); - prom_data->PromInputBlk.PT21L1Enable = CONFIG(PCIEXP_ASPM); - prom_data->PromInputBlk.PT21L1ssEnable = CONFIG(PCIEXP_L1_SUB_STATE); - prom_data->PromInputBlk.PT21DisableUnusedPciePort = 1; - - prom_fw_size = efs_read_promontory_fw((void *)CONFIG_PROMONTORY_FW_ADDR); - if (prom_fw_size) { - prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; - prom_data->PromInputBlk.PT21FWLoading = 0; - prom_data->PromInputBlk.PT21RuninRam = 1; - } else { - prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; - prom_data->PromInputBlk.PT21FWLoading = 1; - } -} - void setup_opensil(void) { SIL_CONTEXT SilContext; @@ -388,8 +363,6 @@ void setup_opensil(void) configure_usb(&SilContext); configure_ccx(&SilContext); configure_fch_acpi(&SilContext); - if (CONFIG(SOC_AMD_PHOENIX_AM5)) - configure_promontory(&SilContext); } static void opensil_entry(SIL_TIMEPOINT timepoint) From fe9912c1fd8e571a2c5d572bb8faadcec304d4eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 11:50:49 +0200 Subject: [PATCH 15/62] drivers/amd/promontory21: Add device_operations for PROM21 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assing ops for each device of Promontory chipset, so that proper ACPI code is generated on boot. Upstream-Status: Pending Change-Id: I018eb0ea45a386ae718b3a38716cfbe2043da55a Signed-off-by: Michał Żygowski --- src/drivers/amd/promontory21/chip.c | 47 ++++++++++++++++++- .../amd/promontory21/prom21_template.cb | 27 ++++++----- 2 files changed, 61 insertions(+), 13 deletions(-) diff --git a/src/drivers/amd/promontory21/chip.c b/src/drivers/amd/promontory21/chip.c index f1859bfea78..e73b294ac45 100644 --- a/src/drivers/amd/promontory21/chip.c +++ b/src/drivers/amd/promontory21/chip.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include "chip.h" @@ -14,6 +14,25 @@ static const char *prom21_sata_acpi_name(const struct device *dev) return "STCR"; } +static const char *prom21_usp_acpi_name(const struct device *dev) +{ + return "UP00"; +} + +static const char *prom21_dsp_acpi_name(const struct device *dev) +{ + char *name; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + name = malloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "DP%02X", dev->path.pci.devfn); + name[4] = '\0'; + + return name; +} + struct device_operations prom21_sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -23,6 +42,32 @@ struct device_operations prom21_sata_ops = { .acpi_fill_ssdt = acpi_device_write_pci_dev, }; +static struct pci_operations prom21_pcie_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations amd_prom21_usp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = prom21_usp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, + .ops_pci = &prom21_pcie_ops, +}; + +struct device_operations amd_prom21_dsp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = prom21_dsp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, + .ops_pci = &prom21_pcie_ops, +}; + struct chip_operations drivers_amd_promontory21_ops = { .name = "AMD Promontory21", }; diff --git a/src/drivers/amd/promontory21/prom21_template.cb b/src/drivers/amd/promontory21/prom21_template.cb index dd9aaa0c64a..387d2b3e55c 100644 --- a/src/drivers/amd/promontory21/prom21_template.cb +++ b/src/drivers/amd/promontory21/prom21_template.cb @@ -7,19 +7,21 @@ chip drivers/amd/promontory21 device pci 00.0 alias prom21_usp on # Upstream Port - device pci 00.0 alias prom21_dsp_pcie_1 off end - device pci 01.0 alias prom21_dsp_pcie_2 off end - device pci 02.0 alias prom21_dsp_pcie_3 off end - device pci 03.0 alias prom21_dsp_pcie_4 off end - device pci 04.0 alias prom21_dsp_pcie_5 off end - device pci 05.0 alias prom21_dsp_pcie_6 off end - device pci 06.0 alias prom21_dsp_pcie_7 off end - device pci 07.0 alias prom21_dsp_pcie_8 off end - device pci 08.0 alias prom21_dsp_pcie_9 off end - device pci 09.0 alias prom21_dsp_pcie_10 off end - device pci 0a.0 alias prom21_dsp_pcie_11 off end - device pci 0b.0 alias prom21_dsp_pcie_12 off end + ops amd_prom21_usp_ops + device pci 00.0 alias prom21_dsp_pcie_1 off ops amd_prom21_dsp_ops end + device pci 01.0 alias prom21_dsp_pcie_2 off ops amd_prom21_dsp_ops end + device pci 02.0 alias prom21_dsp_pcie_3 off ops amd_prom21_dsp_ops end + device pci 03.0 alias prom21_dsp_pcie_4 off ops amd_prom21_dsp_ops end + device pci 04.0 alias prom21_dsp_pcie_5 off ops amd_prom21_dsp_ops end + device pci 05.0 alias prom21_dsp_pcie_6 off ops amd_prom21_dsp_ops end + device pci 06.0 alias prom21_dsp_pcie_7 off ops amd_prom21_dsp_ops end + device pci 07.0 alias prom21_dsp_pcie_8 off ops amd_prom21_dsp_ops end + device pci 08.0 alias prom21_dsp_pcie_9 off ops amd_prom21_dsp_ops end + device pci 09.0 alias prom21_dsp_pcie_10 off ops amd_prom21_dsp_ops end + device pci 0a.0 alias prom21_dsp_pcie_11 off ops amd_prom21_dsp_ops end + device pci 0b.0 alias prom21_dsp_pcie_12 off ops amd_prom21_dsp_ops end device pci 0c.0 alias prom21_dsp_xhci off + ops amd_prom21_dsp_ops device pci 00.0 alias prom21_xhci off ops xhci_pci_ops chip drivers/usb/acpi @@ -84,6 +86,7 @@ chip drivers/amd/promontory21 end end device pci 0d.0 alias prom21_dsp_sata off + ops amd_prom21_dsp_ops device pci 00.0 alias prom21_sata off ops prom21_sata_ops end From f5691ecde53aeec42a373f683969a3ac498d61bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 18 May 2026 13:37:18 +0200 Subject: [PATCH 16/62] mainboard/msi/ms7e56: Add initial Promontory configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on output from amdtool. Change-Id: I31f5601f5e9721764c74bea8a78f614af53f7eb6 Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 1 + src/mainboard/msi/ms7e56/devicetree.cb | 347 ++++++++++++++++++++++++- 2 files changed, 347 insertions(+), 1 deletion(-) diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index 159894093c1..11739bb211b 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE select SUPERIO_NUVOTON_NCT6687D select DRIVERS_UART_8250IO + select DRIVERS_AMD_PROMONTORY21 select HAVE_ACPI_TABLES select MEMORY_MAPPED_TPM select HAVE_X86_64_SUPPORT diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index f211c5ced4b..86e9795f2e8 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -222,7 +222,352 @@ chip soc/amd/phoenix register "start_lane" = "20" register "end_lane" = "23" register "sb_link" = "1" - device ref gpp_bridge_2_1 on end + device ref gpp_bridge_2_1 on + chip drivers/amd/promontory21 + device pci 00.0 alias prom21_usp on # Upstream Port + register "pcie.report_small_ltr" = "Enable" + register "pcie.gen1_swing_enable" = "true" + + register "pcie.pcie_gen1_swing" = "{ + 0x3f, 0x3f, 0x3f, 0x3f, + 0x13, 0x13, 0x13, 0x13, + 0x3f, 0x3f, 0x3f, 0x3f + }" + + register "pcie.clkreq_pin_select" = "{ + ClkreqPort2, + ClkreqPort0, + ClkreqPort8, + ClkreqPort10, + ClkreqPort11, + ClkreqPort3 + }" + + register "pcie.port_target_speed[0]" = "4" + register "pcie.port_target_speed[2]" = "3" + register "pcie.port_target_speed[3]" = "3" + register "pcie.port_target_speed[8]" = "4" + register "pcie.port_target_speed[10]" = "3" + register "pcie.port_target_speed[11]" = "3" + + register "pcie.msi" = "Enable" + register "pcie.msix" = "Enable" + + device pci 00.0 alias prom21_dsp_pcie_1 on # PCI_E3 + ops amd_prom21_dsp_ops + end + device pci 01.0 alias prom21_dsp_pcie_2 off + ops amd_prom21_dsp_ops + end + device pci 02.0 alias prom21_dsp_pcie_3 on # PCI_E2 + ops amd_prom21_dsp_ops + end + device pci 03.0 alias prom21_dsp_pcie_4 on # PCI_E4 + ops amd_prom21_dsp_ops + end + device pci 04.0 alias prom21_dsp_pcie_5 off # used as SATA + ops amd_prom21_dsp_ops + end + device pci 05.0 alias prom21_dsp_pcie_6 off # used as SATA + ops amd_prom21_dsp_ops + end + device pci 06.0 alias prom21_dsp_pcie_7 off # used as SATA + ops amd_prom21_dsp_ops + end + device pci 07.0 alias prom21_dsp_pcie_8 off # used as SATA + ops amd_prom21_dsp_ops + end + device pci 08.0 alias prom21_dsp_pcie_9 on # M2_3 + ops amd_prom21_dsp_ops + end + device pci 09.0 alias prom21_dsp_pcie_10 off + ops amd_prom21_dsp_ops + end + device pci 0a.0 alias prom21_dsp_pcie_11 on # Ethernet Realtek + ops amd_prom21_dsp_ops + end + device pci 0b.0 alias prom21_dsp_pcie_12 on # WiFi Qualcomm + ops amd_prom21_dsp_ops + end + device pci 0c.0 alias prom21_dsp_xhci on + device pci 00.0 alias prom21_xhci on + ops xhci_pci_ops + + register "usb.hw_lpm" = "Enable" + register "usb.dbc" = "Enable" + register "usb.usb3_gen" = "XhciGen2x2" + register "usb.port_gen" = "{ + XhciPortGen1, + XhciPortGen1, + XhciPortGen1, + XhciPortGen1, + XhciPortGen1 + }" + + register "usb3_phy[0]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + register "usb3_phy[1]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + register "usb3_phy[2]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + register "usb3_phy[3]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + register "usb3_phy[4]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + register "usb3_phy[5]" = "{ + .override = true, + .gen1_swing = 0xf, + .gen1_emp_level_en = 0x1, + .gen1_emp_level = 0x3, + .gen1_preshoot_en = 0x0, + .gen1_preshoot = 0x0, + .gen2_swing = 0xc, + .gen2_cp0_emp_level_en = 0x1, + .gen2_cp0_emp_level = 0x3, + .gen2_cp0_preshoot_en = 0x1, + .gen2_cp0_preshoot = 0x1, + .gen2_cp13_emp_level_en = 0x0, + .gen2_cp13_emp_level = 0x3, + .gen2_cp13_preshoot_en = 0x1, + .gen2_cp13_preshoot = 0x1, + .gen2_cp14_emp_level_en = 0x1, + .gen2_cp14_emp_level = 0x3, + .gen2_cp14_preshoot_en = 0x0, + .gen2_cp14_preshoot = 0x1, + .gen2_cp15_emp_level_en = 0x1, + .gen2_cp15_emp_level = 0x3, + .gen2_cp15_preshoot_en = 0x1, + .gen2_cp15_preshoot = 0x1, + .gen2_cp16_emp_level_en = 0x0, + .gen2_cp16_emp_level = 0x3, + .gen2_cp16_preshoot_en = 0x0, + .gen2_cp16_preshoot = 0x1 + }" + + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias prom_21_xhci_root_hub on + chip drivers/usb/acpi + device usb 2.0 alias prom21_usb2_port1 on end + end + chip drivers/usb/acpi + device usb 2.1 alias prom21_usb2_port2 on end + end + chip drivers/usb/acpi + device usb 2.2 alias prom21_usb2_port3 on end + end + chip drivers/usb/acpi + device usb 2.3 alias prom21_usb2_port4 on end + end + chip drivers/usb/acpi + device usb 2.4 alias prom21_usb2_port5 on end + end + chip drivers/usb/acpi + device usb 2.5 alias prom21_usb2_port6 on end + end + chip drivers/usb/acpi + device usb 2.6 alias prom21_usb2_port7 on end + end + chip drivers/usb/acpi + device usb 2.7 alias prom21_usb2_port8 on end + end + chip drivers/usb/acpi + device usb 2.8 alias prom21_usb2_port9 on end + end + chip drivers/usb/acpi + device usb 2.9 alias prom21_usb2_port10 on end + end + chip drivers/usb/acpi + device usb 2.a alias prom21_usb2_port11 on end + end + chip drivers/usb/acpi + device usb 2.b alias prom21_usb2_port12 on end + end + chip drivers/usb/acpi + device usb 3.0 alias prom21_usb3_port1 on end + end + chip drivers/usb/acpi + device usb 3.1 alias prom21_usb3_port2 on end + end + chip drivers/usb/acpi + device usb 3.2 alias prom21_usb3_port3 on end + end + chip drivers/usb/acpi + device usb 3.3 alias prom21_usb3_port4 on end + end + chip drivers/usb/acpi + device usb 3.4 alias prom21_usb3_port5 on end + end + chip drivers/usb/acpi + device usb 3.5 alias prom21_usb3_port6 on end + end + end + end + end + end + device pci 0d.0 alias prom21_dsp_sata on + device pci 00.0 alias prom21_sata on + ops prom21_sata_ops + + register "sata.port_enable" = "{ 1, 1, 1, 1 }" + register "sata.aggressive_dev_slp" = "{ + Disable, + Disable, + Disable, + Disable + }" + + register "sata.aggresive_link_pm_cap" = "Enable" + register "sata.psc_cap" = "Enable" + register "sata.ssc_cap" = "Enable" + register "sata.hot_plug" = "Disable" + register "sata.cccs_cap" = "Disable" + register "sata.msi_cap" = "Enable" + end + end + end + end + end end # M2_2: x4 M.2 slot, DXIO lanes 24-27 chip drivers/amd/opensil/mpio From dd1871fef8783c0e50e6a96d6e49bd14c5e7d1b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 11:51:46 +0200 Subject: [PATCH 17/62] mainboard/msi/ms7e56/devicetree.cb: Assign ops and SSID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assign device operations to Promontory devices and set subsystem IDs. Upstream-Status: Pending Change-Id: I032201989c977a01ad76845312a4ee74f361e208 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 1 + src/mainboard/msi/ms7e56/devicetree.cb | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index 11739bb211b..75e0b91c4ac 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select SOC_AMD_PHOENIX_AM5_OPENSIL + select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN select SOC_AMD_COMMON_BLOCK_PSP_RPMC diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 86e9795f2e8..1b7b8abe00b 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -200,6 +200,8 @@ chip soc/amd/phoenix register "usb3_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf }" device domain 0 on + subsystemid 0x1462 0x7e56 inherit + device ref iommu on end # PCIE_E1: x8 PCIe slot, DXIO lanes 0-7 @@ -225,6 +227,8 @@ chip soc/amd/phoenix device ref gpp_bridge_2_1 on chip drivers/amd/promontory21 device pci 00.0 alias prom21_usp on # Upstream Port + ops amd_prom21_usp_ops + register "pcie.report_small_ltr" = "Enable" register "pcie.gen1_swing_enable" = "true" @@ -289,7 +293,9 @@ chip soc/amd/phoenix device pci 0b.0 alias prom21_dsp_pcie_12 on # WiFi Qualcomm ops amd_prom21_dsp_ops end - device pci 0c.0 alias prom21_dsp_xhci on + device pci 0c.0 alias prom21_dsp_xhci on + ops amd_prom21_dsp_ops + device pci 00.0 alias prom21_xhci on ops xhci_pci_ops @@ -546,6 +552,8 @@ chip soc/amd/phoenix end end device pci 0d.0 alias prom21_dsp_sata on + ops amd_prom21_dsp_ops + device pci 00.0 alias prom21_sata on ops prom21_sata_ops From aaf4c401d311b930d9c44aa6de7cceb7ed4d64b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 09:26:55 +0200 Subject: [PATCH 18/62] mainboard/msi/ms7e56: Add HDA verbs for external codec and iGPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add codec verbs with pin configs as seen by Linux in sysfs. Upstream-Status: Pending Change-Id: I438292f2af90364d6ebecb9c056cfd8976e9f582 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 1 + src/mainboard/msi/ms7e56/devicetree.cb | 8 +- src/mainboard/msi/ms7e56/hda_verb.c | 140 +++++++++++++++++++++++++ 3 files changed, 147 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/msi/ms7e56/hda_verb.c diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index 75e0b91c4ac..cb5e4f94049 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -5,6 +5,7 @@ if BOARD_MSI_PRO_B850_P config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select AZALIA_HDA_CODEC_SUPPORT select SOC_AMD_PHOENIX_AM5_OPENSIL select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_USE_ESPI diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 1b7b8abe00b..d7931d024db 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -595,7 +595,9 @@ chip soc/amd/phoenix device generic 0 on end end end # Internal GPU (GFX) - device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref gfx_hda on + ops default_azalia_audio_ops + end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor device ref xhci_0 on chip drivers/usb/acpi @@ -641,7 +643,9 @@ chip soc/amd/phoenix end end end - device ref acp on end # Audio Processor (ACP) + device ref acp on + ops default_azalia_audio_ops + end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref usb4_xhci_0 on diff --git a/src/mainboard/msi/ms7e56/hda_verb.c b/src/mainboard/msi/ms7e56/hda_verb.c new file mode 100644 index 00000000000..105cb92709a --- /dev/null +++ b/src/mainboard/msi/ms7e56/hda_verb.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define AC_VERB_SET_PROC_COEF 0x400 +#define AC_VERB_SET_COEF_INDEX 0x500 + +#define ALC_WRITE_COEF(codec, idx, val) \ + AZALIA_VERB_12B(codec, 0x20, AC_VERB_SET_COEF_INDEX, (idx) & 0xffff), \ + AZALIA_VERB_12B(codec, 0x20, AC_VERB_SET_PROC_COEF, (val) & 0xffff) \ + +static const u32 realtek_alc897_verbs[] = { + AZALIA_RESET(0x1), + AZALIA_SUBVENDOR(0, 0x14629e56), + AZALIA_PIN_CFG(0, 0x11, 0x4033c040), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01011010), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a11040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4027c26b), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + /* TODO: confirm below */ + // ALC_WRITE_COEF(0, 0x3b, 0x80), + // ALC_WRITE_COEF(0, 0x39, 0x4031), + + // ALC_WRITE_COEF(0, 0x13, 0x53), + // ALC_WRITE_COEF(0, 0x30, 0x92D1), + + // ALC_WRITE_COEF(0, 0x21, 0x00), + // ALC_WRITE_COEF(0, 0x23, 0x00), + + // ALC_WRITE_COEF(0, 0x25, 0x00), + // ALC_WRITE_COEF(0, 0x27, 0x00), + + // ALC_WRITE_COEF(0, 0x29, 0x00), + // ALC_WRITE_COEF(0, 0x2A, 0x1640), + + // ALC_WRITE_COEF(0, 0x2B, 0x1640), + // ALC_WRITE_COEF(0, 0x21, 0xC00), + + // ALC_WRITE_COEF(0, 0x23, 0xC00), + // ALC_WRITE_COEF(0, 0x25, 0xC00), + + // ALC_WRITE_COEF(0,0x027, 0xC00), + // ALC_WRITE_COEF(0,0x029, 0xC00), + + // ALC_WRITE_COEF(0, 0x2A, 0x1641), + // ALC_WRITE_COEF(0, 0x2B, 0x1641), + + // ALC_WRITE_COEF(0, 0x30, 0x9251), + // ALC_WRITE_COEF(0, 0x2A, 0x1649), + + // ALC_WRITE_COEF(0, 0x2B, 0x1649), + // ALC_WRITE_COEF(0, 0xC, 0x3F06), + + // ALC_WRITE_COEF(0, 0x7, 0xF808), + // ALC_WRITE_COEF(0, 0x7, 0xF808), +}; + +static const u32 amd_display_audio_verbs[] = { + AZALIA_RESET(0x1), + AZALIA_SUBVENDOR(0, 0x00aa0100), + AZALIA_PIN_CFG(0, 0x03, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, 0 + )), + AZALIA_PIN_CFG(0, 0x05, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, 0 + )), + AZALIA_PIN_CFG(0, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, 0 + )), + AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, 0 + )), + AZALIA_PIN_CFG(0, 0x0b, AZALIA_PIN_DESC( + AZALIA_NC, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, 0 + )) +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC897", + .vendor_id = 0x10ec0897, + .subsystem_id = 0x14629e56, + .address = 0, + .verbs = realtek_alc897_verbs, + .verb_count = ARRAY_SIZE(realtek_alc897_verbs), + }, + { + .name = "AMD Display Audio (HDMI/DP)", + .vendor_id = 0x1002aa01, + .subsystem_id = 0x00aa0100, + .address = 0, + .verbs = amd_display_audio_verbs, + .verb_count = ARRAY_SIZE(amd_display_audio_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; From 07bc8ea5f0a9d221769ba1ecb54b4b486c031dc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 09:38:35 +0200 Subject: [PATCH 19/62] mainboard/msi/ms7e56/devicetree.cb: Add B850 chipset USB descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on https://blog.3mdeb.com/2026/2026-02-09-msi_pro_b850p_part1/ Upstream-Status: Pending Change-Id: Iacb2af8ab8daceceed406a411a795c9ab6553eee Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index d7931d024db..b1329c54e3c 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -494,54 +494,86 @@ chip soc/amd/phoenix register "type" = "UPC_TYPE_HUB" device usb 0.0 alias prom_21_xhci_root_hub on chip drivers/usb/acpi + register "desc" = ""JUSB3"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.0 alias prom21_usb2_port1 on end end chip drivers/usb/acpi + register "desc" = ""JUSB3"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.1 alias prom21_usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""JUSB4"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.2 alias prom21_usb2_port3 on end end chip drivers/usb/acpi + register "desc" = ""JUSB4"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.3 alias prom21_usb2_port4 on end end chip drivers/usb/acpi + register "desc" = ""JUSBC5"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.4 alias prom21_usb2_port5 on end end chip drivers/usb/acpi device usb 2.5 alias prom21_usb2_port6 on end end chip drivers/usb/acpi + register "desc" = ""JUSB1"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.6 alias prom21_usb2_port7 on end end chip drivers/usb/acpi + register "desc" = ""JUSB1"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.7 alias prom21_usb2_port8 on end end chip drivers/usb/acpi + register "desc" = ""JUSB2"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.8 alias prom21_usb2_port9 on end end chip drivers/usb/acpi + register "desc" = ""JUSB2"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.9 alias prom21_usb2_port10 on end end chip drivers/usb/acpi + register "desc" = ""WIFI/BT"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.a alias prom21_usb2_port11 on end end chip drivers/usb/acpi + register "desc" = ""MSI MYSTIC LIGHT"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.b alias prom21_usb2_port12 on end end chip drivers/usb/acpi + register "desc" = ""JUSB3"" + register "type" = "UPC_TYPE_INTERNAL" device usb 3.0 alias prom21_usb3_port1 on end end chip drivers/usb/acpi + register "desc" = ""JUSB3"" + register "type" = "UPC_TYPE_INTERNAL" device usb 3.1 alias prom21_usb3_port2 on end end chip drivers/usb/acpi + register "desc" = ""JUSB4"" + register "type" = "UPC_TYPE_INTERNAL" device usb 3.2 alias prom21_usb3_port3 on end end chip drivers/usb/acpi + register "desc" = ""JUSB4"" + register "type" = "UPC_TYPE_INTERNAL" device usb 3.3 alias prom21_usb3_port4 on end end chip drivers/usb/acpi + register "desc" = ""JUSBC5"" + register "type" = "UPC_TYPE_INTERNAL" device usb 3.4 alias prom21_usb3_port5 on end end chip drivers/usb/acpi From ae198923cdaa995840134223a9c2767978a224a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 09:48:28 +0200 Subject: [PATCH 20/62] mainboard/msi/ms7e56/devicetree.cb: Add PCIe slot descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on https://blog.3mdeb.com/2026/2026-02-09-msi_pro_b850p_part1/ and MSI POR B850-P WIFI manual. Upstream-Status: Pending Change-Id: I864ea0745bd89f05c32726ce8ffe4edaab608d18 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index b1329c54e3c..997b0434b29 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -209,14 +209,18 @@ chip soc/amd/phoenix register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "7" - device ref gpp_bridge_1_1 on end + device ref gpp_bridge_1_1 on + smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong" "PCIE_E1" "SlotDataBusWidth8X" + end end # M2_1: x4 M.2 slot, DXIO lanes 16-19 chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "19" - device ref gpp_bridge_1_2 on end + device ref gpp_bridge_1_2 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" + end end # Promontory B850 chipset: x4 link, DXIO lanes 20-23 chip drivers/amd/opensil/mpio @@ -259,18 +263,22 @@ chip soc/amd/phoenix device pci 00.0 alias prom21_dsp_pcie_1 on # PCI_E3 ops amd_prom21_dsp_ops + smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong" "PCI_E3" "SlotDataBusWidth4X" end device pci 01.0 alias prom21_dsp_pcie_2 off ops amd_prom21_dsp_ops end device pci 02.0 alias prom21_dsp_pcie_3 on # PCI_E2 ops amd_prom21_dsp_ops + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E2" "SlotDataBusWidth1X" end device pci 03.0 alias prom21_dsp_pcie_4 on # PCI_E4 ops amd_prom21_dsp_ops + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCI_E4" "SlotDataBusWidth1X" end device pci 04.0 alias prom21_dsp_pcie_5 off # used as SATA ops amd_prom21_dsp_ops + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_3" "SlotDataBusWidth4X" end device pci 05.0 alias prom21_dsp_pcie_6 off # used as SATA ops amd_prom21_dsp_ops @@ -283,6 +291,7 @@ chip soc/amd/phoenix end device pci 08.0 alias prom21_dsp_pcie_9 on # M2_3 ops amd_prom21_dsp_ops + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_3" "SlotDataBusWidth4X" end device pci 09.0 alias prom21_dsp_pcie_10 off ops amd_prom21_dsp_ops @@ -614,7 +623,9 @@ chip soc/amd/phoenix register "type" = "IFTYPE_PCIE" register "start_lane" = "24" register "end_lane" = "27" - device ref gpp_bridge_2_2 on end + device ref gpp_bridge_2_2 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_2" "SlotDataBusWidth4X" + end end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A From 7bb685d5fde6d7ffc878f6b3b1503ed33b5e3b06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 09:54:05 +0200 Subject: [PATCH 21/62] mainboard/msi/ms7e56/devicetree.cb: Add SMBIOS type 41 entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe SMBIOS type 41 onboard devices using the devicetree entries. Upstream-Status: Pending Change-Id: I0119f2975ae722641c2d6208043602c384602964 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 1 + src/mainboard/msi/ms7e56/devicetree.cb | 14 +++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index cb5e4f94049..a6a4fecbc8f 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PSP_SMI select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE select SUPERIO_NUVOTON_NCT6687D + select SMBIOS_TYPE41_PROVIDED_BY_DEVTREE select DRIVERS_UART_8250IO select DRIVERS_AMD_PROMONTORY21 select HAVE_ACPI_TABLES diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 997b0434b29..8ff22dc0c9a 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -298,9 +298,15 @@ chip soc/amd/phoenix end device pci 0a.0 alias prom21_dsp_pcie_11 on # Ethernet Realtek ops amd_prom21_dsp_ops + device pci 00.0 on + smbios_dev_info 1 "Onboard LAN" + end end device pci 0b.0 alias prom21_dsp_pcie_12 on # WiFi Qualcomm ops amd_prom21_dsp_ops + device pci 00.0 on + smbios_dev_info 1 "Onboard WIFI" + end end device pci 0c.0 alias prom21_dsp_xhci on ops amd_prom21_dsp_ops @@ -630,6 +636,7 @@ chip soc/amd/phoenix device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on + smbios_dev_info 1 "Onboard IGD" chip drivers/amd/opensil/mpio register "type" = "IFTYPE_DDI" register "ddi_connector" = "ConnHDMI" @@ -640,6 +647,7 @@ chip soc/amd/phoenix end # Internal GPU (GFX) device ref gfx_hda on ops default_azalia_audio_ops + smbios_dev_info 1 "IGD Audio" end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor device ref xhci_0 on @@ -686,9 +694,9 @@ chip soc/amd/phoenix end end end - device ref acp on - ops default_azalia_audio_ops - end # Audio Processor (ACP) + device ref hda on + smbios_dev_info 2 "Onboard Audio" + end end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref usb4_xhci_0 on From 5155db5455d2765a217dc1284d162646ecf1e01a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 10:23:52 +0200 Subject: [PATCH 22/62] soc/amd/phoenix/root_complex.c: Write ACPI _PRT for host bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing _PRT method for the host bridge to convery IRQ routing information to the OS about the devices on bus 0. Upstream-Status: Pending Change-Id: Ic447baea95dad9e337a1c4eec1ccf3132caaebbd Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/root_complex.c | 98 ++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 724121c1aaa..7fc8a374660 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -2,8 +2,12 @@ /* TODO: Update for Phoenix */ +#include #include +#include +#include #include +#include #include #include #include @@ -85,10 +89,104 @@ static void acipgen_dptci(void) sizeof(no_battery_input)); } +struct pci_dev_int_routes { + unsigned int devfn; + unsigned int num_irqs; + unsigned int irq_base; +}; + +static const struct pci_dev_int_routes iohc_devs[] = { + { .devfn = PCI_DEVFN(0x14, 0), .num_irqs = 4, .irq_base = 16 }, + { .devfn = PCI_DEVFN(0x08, 0), .num_irqs = 1, .irq_base = 28 }, +}; + +static void acpigen_write_PRT_GSI(const struct device *rb) +{ + char *pkg_count; + const struct device *dev; + + pkg_count = acpigen_write_package(0); /* Package - APIC Routing */ + + for (unsigned int d = 0; d < ARRAY_SIZE(iohc_devs); d++) { + dev = pcidev_path_behind(rb->upstream, iohc_devs[d].devfn); + if (!dev || !dev->enabled) + continue; + + for (unsigned int i = 0; i < iohc_devs[d].num_irqs; ++i) { + (*pkg_count)++; + acpigen_write_PRT_GSI_entry( + PCI_SLOT(iohc_devs[d].devfn), + i, /* pin */ + iohc_devs[d].irq_base + i); + } + } + + acpigen_pop_len(); /* Package - APIC Routing */ +} + +static void acpigen_write_PRT_PIC(const struct device *rb) +{ + char link_template[] = "\\_SB.INTX"; + char *pkg_count; + const struct device *dev; + + pkg_count = acpigen_write_package(0); /* Package - PIC Routing */ + for (unsigned int d = 0; d < ARRAY_SIZE(iohc_devs); d++) { + dev = pcidev_path_behind(rb->upstream, iohc_devs[d].devfn); + if (!dev || !dev->enabled) + continue; + + for (unsigned int i = 0; i < iohc_devs[d].num_irqs; i++) { + link_template[8] = 'A' + ((iohc_devs[d].irq_base + i) % 8); + (*pkg_count)++; + acpigen_write_PRT_source_entry( + PCI_SLOT(iohc_devs[d].devfn), + i, /* pin */ + link_template /* Source */, + 0 /* Source Index */); + } + } + + acpigen_pop_len(); /* Package - PIC Routing */ +} + +static void acpigen_write_host_bridge_PRT(const struct device *dev) +{ + acpigen_write_method("_PRT", 0); + + /* If (PICM) */ + acpigen_write_if(); + acpigen_emit_namestring("PICM"); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_GSI(dev); + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_PIC(dev); + + acpigen_pop_len(); /* End Else */ + + acpigen_pop_len(); /* Method */ +} + static void root_complex_fill_ssdt(const struct device *device) { + const char *acpi_scope = acpi_device_path(dev_get_domain(device)); + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); + + acpigen_write_scope(acpi_scope); + + printk(BIOS_DEBUG, "%s: writing _PRT\n", acpi_scope); + acpigen_write_host_bridge_PRT(device); + + acpigen_pop_len(); /* Scope */ } static const char *gnb_acpi_name(const struct device *dev) From 98f5d99857033baea569d5ae959d9635504cc878 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 11:49:37 +0200 Subject: [PATCH 23/62] vendorcode/amd/opensil/phoenix_poc: Assign PCI SSID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Get PCI SSID from the devicetree and pass to openSIL. Upstream-Status: Pending Change-Id: I6236215e0cef77d35fc0314b311be1186b81a97f Signed-off-by: Michał Żygowski --- .../amd/opensil/phoenix_poc/mpio/chip.c | 56 +++++++++++++++++-- .../phoenix_poc/prom21/chip_to_opensil.c | 26 ++++++++- .../amd/opensil/phoenix_poc/ramstage.c | 20 ++++++- 3 files changed, 91 insertions(+), 11 deletions(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index e45f5b034d3..5d6360ce3bb 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -5,8 +5,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -19,6 +21,47 @@ MPIO_DDI_DESCRIPTOR ddi_descriptor_list[MAX_DDI_PORTS]; static void mpio_params_config(SIL_CONTEXT *SilContext) { MPIOCLASS_COMMON_INPUT_BLK *mpio_data = SilFindStructure(SilContext, SilId_MpioClass, 0); + MPIOCLASS_PHX_INPUT_BLK *phx_data = SilFindStructure(SilContext, SilId_MpioClass, 1); + struct device *gnb = DEV_PTR(gnb); + struct device *iommu = DEV_PTR(iommu); + struct device *psp = DEV_PTR(crypto); + struct device *nbif = pcidev_on_root(8, 0); + struct device *acp = DEV_PTR(acp); + struct device *hda = DEV_PTR(hda); + struct device *mp2 = DEV_PTR(mp2); + struct device *gfx = DEV_PTR(gfx); + struct device *gfx_hda = DEV_PTR(gfx_hda); + struct device *nbifrc = DEV_PTR(gpp_bridge_a); + + phx_data->AcpController = is_dev_enabled(acp); + phx_data->CfgHdAudioEnable = is_dev_enabled(hda); + phx_data->CfgSensorHubEnable = is_dev_enabled(mp2); + + if (acp) + phx_data->CfgAcpSsid = acp->subsystem_vendor | + ((uint32_t)acp->subsystem_device << 16); + if (gfx) + phx_data->AmdCfgGnbIGPUSSID = gfx->subsystem_vendor | + ((uint32_t)gfx->subsystem_device << 16); + if (gfx_hda) + phx_data->AmdCfgGnbIGPUAudioSSID = gfx_hda->subsystem_vendor | + ((uint32_t)gfx_hda->subsystem_device << 16); + if (nbifrc) + phx_data->CfgNbifRCSsid = nbifrc->subsystem_vendor | + ((uint32_t)nbifrc->subsystem_device << 16); + if (gnb) + mpio_data->CfgNbioSsid = gnb->subsystem_vendor | + ((uint32_t)gnb->subsystem_device << 16); + if (iommu) + mpio_data->CfgIommuSsid = iommu->subsystem_vendor | + ((uint32_t)iommu->subsystem_device << 16); + if (psp) + mpio_data->CfgPspccpSsid = psp->subsystem_vendor | + ((uint32_t)psp->subsystem_device << 16); + if (nbif) + mpio_data->CfgNbifF0Ssid = nbif->subsystem_vendor | + ((uint32_t)nbif->subsystem_device << 16); + mpio_data->CfgDxioClockGating = 1; mpio_data->PcieDxioTimingControlEnable = 0; mpio_data->PCIELinkReceiverDetectionPolling = 0; @@ -54,14 +97,8 @@ static void mpio_params_config(SIL_CONTEXT *SilContext) mpio_data->CfgPcieAriSupport = 1; mpio_data->CfgNbioCTOtoSC = 0; mpio_data->CfgNbioCTOIgnoreError = 1; - mpio_data->CfgNbioSsid = 0; - mpio_data->CfgIommuSsid = 0; - mpio_data->CfgPspccpSsid = 0; mpio_data->CfgNtbccpSsid = 0; - mpio_data->CfgNbifF0Ssid = 0; mpio_data->CfgNtbSsid = 0; - mpio_data->AmdPcieSubsystemDeviceID = 0x1453; - mpio_data->AmdPcieSubsystemVendorID = 0x1022; mpio_data->GppAtomicOps = 1; mpio_data->GfxAtomicOps = 1; mpio_data->AmdNbioReportEdbErrors = 0; @@ -104,6 +141,8 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilContext, SilId_NbioClass, 0); GFXCLASS_INPUT_BLK *gfx_data = SilFindStructure(SilContext, SilId_GfxClass, 0); NBIO_CONFIG_DATA *input = &nbio_data->NbioConfigData; + input->IoApicMMIOAddressReservedEnable = false; + input->CfgGnbIoapicAddress = GNB_IO_APIC_ADDR; input->EsmEnableAllRootPorts = false; input->EsmTargetSpeed = 16; input->CfgRxMarginPersistenceMode = 1; @@ -219,6 +258,11 @@ void opensil_mpio_per_device_config(struct device *dev) port.Port = port_data; port.Port.MiscControls.SbLink = config->sb_link; + if (dev->subsystem_vendor && dev->subsystem_device) { + mpio_data->AmdPcieSubsystemVendorID = dev->subsystem_vendor; + mpio_data->AmdPcieSubsystemDeviceID = dev->subsystem_device; + } + if (CONFIG(DRIVERS_AMD_PROMONTORY21) && config->sb_link) opensil_promontory21_config(&SilContext, dev); diff --git a/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c index 9d8b960aa3f..4bc29328abf 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c @@ -117,6 +117,11 @@ static void config_usb_port_enables(struct device *xhci_dev, } } +static uint32_t get_pci_ssid(struct device *dev) +{ + return (uint32_t)(dev->subsystem_vendor | ((uint32_t)dev->subsystem_device << 16)); +} + void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_port) { PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); @@ -163,6 +168,11 @@ void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_po cfg = usp->chip_info; primary = &input_blk->Primary; + if (get_pci_ssid(usp)) { + primary->PT21SsidOverride = 1; + primary->PT21PcieUspSsid = get_pci_ssid(usp); + } + /* * Walk USP's downstream PCIe bus to derive port and function enables. * DSP devices: pci 00.0-0b.0 - PCIe ports 0-11 @@ -181,13 +191,23 @@ void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_po if (slot < PROM21_NUM_PCIE_LANES) { /* DSP PCIe port: slot 0-11 maps to port index 0-11 */ primary->PT21PciePortEnable[slot] = dsp->enabled; + if (dsp->enabled) + primary->PT21PcieDspSsid = get_pci_ssid(dsp); } else if (dsp->path.pci.devfn == PROM21_XHCI_DEVFN) { - struct device *xhci = dsp->downstream - ? dsp->downstream->children : NULL; - if (xhci) + struct device *xhci = dsp->downstream ? dsp->downstream->children : + NULL; + primary->PT21PcieDspXhciSsid = get_pci_ssid(dsp); + if (xhci) { config_usb_port_enables(xhci, primary); + primary->PT21XhciSsid = get_pci_ssid(xhci); + } } else if (dsp->path.pci.devfn == PROM21_SATA_DEVFN) { primary->PT21SataEnable = dsp->enabled ? 1 : 0; + struct device *ahci = dsp->downstream ? dsp->downstream->children : + NULL; + primary->PT21PcieDspAhciSsid = get_pci_ssid(dsp); + if (ahci) + primary->PT21AhciSsid = get_pci_ssid(ahci); } } diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index c8375324be1..4bbd50a5108 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -147,6 +147,9 @@ static void configure_usb(SIL_CONTEXT *SilContext) if (!fch_usb_data) return; + fch_usb_data->XhciSsid = usb_ctrlr[0]->subsystem_vendor | + ((uint32_t)usb_ctrlr[0]->subsystem_device << 16); + fch_usb_data->Xhci0Enable = is_dev_enabled(usb_ctrlr[0]); fch_usb_data->Xhci1Enable = is_dev_enabled(usb_ctrlr[1]); fch_usb_data->Usb4Host[0].Usb3HCDisable = !is_dev_enabled(usb_ctrlr[2]); @@ -290,6 +293,8 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpi, 0); FCHCLASS_INPUT_BLK *fch_data = SilFindStructure(SilContext, SilId_FchClass, 0); struct device *smb = DEV_PTR(smbus); + struct device *xhci = DEV_PTR(xhci_0); + struct device *hda = DEV_PTR(hda); if (!fch_hwacpi_data) { printk(BIOS_ERR, "OpenSIL: FCH HW ACPI data not found\n"); @@ -307,8 +312,19 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) return; } - fch_data->Smbus.SmbusSsid = smb->subsystem_vendor | - ((uint32_t)smb->subsystem_device << 16); + if (smb) { + fch_data->Smbus.SmbusSsid = smb->subsystem_vendor | + ((uint32_t)smb->subsystem_device << 16); + fch_data->FchBldCfg.CfgSmbusSsid = fch_data->Smbus.SmbusSsid; + } + + if (hda) + fch_data->FchBldCfg.CfgAzaliaSsid = hda->subsystem_vendor | + ((uint32_t)hda->subsystem_device << 16); + + if (xhci) + fch_data->FchBldCfg.CfgXhciSsid = xhci->subsystem_vendor | + ((uint32_t)xhci->subsystem_device << 16); fch_data->FchBldCfg.CfgSioPmeBaseAddress = 0; fch_data->FchBldCfg.CfgAcpiPm1EvtBlkAddr = ACPI_PM_EVT_BLK; From 32aa3099fc181021edbc54594980f28248018822 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 11:53:27 +0200 Subject: [PATCH 24/62] vc/amd/opensil/phoenix_poc/opensil: Bump for fixed GNB IOAPIC address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I174cf78d745e714e2a1abb0820239c7cdae44ac4 Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/opensil | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 0f946edc16e..aa8d9b6b50b 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 0f946edc16e15381af6b9487cd71c1d7206e37c6 +Subproject commit aa8d9b6b50b80c2fae95802ae6094b37a6bf5ad9 From bf7eb9cb01ce32e78bd0247d3e22044841ff31de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 13:01:06 +0200 Subject: [PATCH 25/62] vc/amd/opensil/phoenix_poc: Set predefined IOAPIC IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replicate what vendor firmware does on Phoenix AM5. Upstream-Status: Pending Change-Id: I1bdad04e2f0df15cf5256066b4f5104d3452eff9 Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c | 4 ++++ src/vendorcode/amd/opensil/phoenix_poc/ramstage.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index 5d6360ce3bb..811a6bc9893 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -143,6 +143,10 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) NBIO_CONFIG_DATA *input = &nbio_data->NbioConfigData; input->IoApicMMIOAddressReservedEnable = false; input->CfgGnbIoapicAddress = GNB_IO_APIC_ADDR; + if (CONFIG(IOAPIC_PREDEFINED_ID)) { + input->IoApicIdPreDefineEn = 1; + input->IoApicIdBase = 33; + } input->EsmEnableAllRootPorts = false; input->EsmTargetSpeed = 16; input->CfgRxMarginPersistenceMode = 1; diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 4bbd50a5108..b16b75b67e6 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -334,6 +334,11 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) fch_data->FchBldCfg.CfgAcpiGpe0BlkAddr = ACPI_GPE0_BLK; fch_data->FchBldCfg.CfgSmiCmdPortAddr = APM_CNT; + if (CONFIG(IOAPIC_PREDEFINED_ID)) { + fch_data->CfgIoApicIdPreDefEnable = 1; + fch_data->FchIoApicId = 32; + } + fch_data->WdtEnable = false; /* eSPI always enabled (bit 27) */ From 81591d37f938c134233a547fa89ff1771c54f7bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 13:01:59 +0200 Subject: [PATCH 26/62] soc/amd/phoenix/acpi.c: Fix printing PSP message status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the new line so that "OK" is printed in the same line as the PSP message we send. Upstream-Status: Pending Change-Id: Ia675640438cfa093121658e4dad6afbcf4d1d11d Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 90738bf1608..85eac9bd906 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -118,7 +118,7 @@ static void send_ivrs_to_psp(struct acpi_rsdp *rsdp) buffer.info.ivrs_table_buffer = (uint64_t)hdr; buffer.info.ivrs_table_size = hdr->length; - printk(BIOS_DEBUG, "PSP: Sending IVRS ACPI table\n"); + printk(BIOS_DEBUG, "PSP: Sending IVRS ACPI table "); cmd_status = send_psp_command(MBOX_BIOS_CMD_SEND_IVRS_ACPI_TABLE, &buffer); From d380efe2a8a705d876e1a91f19241f5646f3fcf8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 13:02:40 +0200 Subject: [PATCH 27/62] mainboard/msi/ms7e56: Enabel IOAPIC 8bit IDs and IPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IPU is not disabled on this platform. Enable it so the resources will be allocated appropriately. Enable 8bit IOAPIC IDs, to avoid issues with upper nibble not being programmed correctly. Upstream-Status: Pending Change-Id: Ic6051ae95a84b8474ee8cf2d713fc35f5f57d0eb Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 2 ++ src/mainboard/msi/ms7e56/devicetree.cb | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index a6a4fecbc8f..c0b52238400 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS select MEMORY_MAPPED_TPM select HAVE_X86_64_SUPPORT select USE_X86_64_SUPPORT + select IOAPIC_8BIT_ID + select IOAPIC_PREDEFINED_ID config FMDFILE default "src/mainboard/msi/ms7e56/board.fmd" diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 8ff22dc0c9a..df68dd1df89 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -698,6 +698,9 @@ chip soc/amd/phoenix smbios_dev_info 2 "Onboard Audio" end end + device ref gpp_bridge_b on # Internal GPP Bridge 1 to Bus B + device ref ipu on end + end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref usb4_xhci_0 on chip drivers/usb/acpi From 5dc3fbbcfe365bdbb3f6b9441a505b2efef9d3a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 13:33:23 +0200 Subject: [PATCH 28/62] include/device/device.h: Add helper to get 32bit SSID from device struct MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add helper to obtain 32bit SSID from device structure for better code readability when 32bit SSID is needed. Upstream-Status: Pending Change-Id: I11761b0e12891a089e64ec6c7846d4352888e6df Signed-off-by: Michał Żygowski --- src/include/device/device.h | 8 ++++ .../amd/opensil/phoenix_poc/mpio/chip.c | 42 ++++++++----------- .../phoenix_poc/prom21/chip_to_opensil.c | 19 ++++----- .../amd/opensil/phoenix_poc/ramstage.c | 21 ++++------ 4 files changed, 41 insertions(+), 49 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index ad9d9c5318f..5063e52d718 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -508,6 +508,14 @@ static inline bool is_root_device(const struct device *dev) (dev->upstream->dev == dev); } +static inline uint32_t pcidev_get_ssid(const struct device *dev) +{ + if (!dev) + return 0; + + return (dev->subsystem_vendor | ((uint32_t)dev->subsystem_device << 16)); +} + void enable_static_device(struct device *dev); void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index 811a6bc9893..59ba565b32c 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -37,30 +37,22 @@ static void mpio_params_config(SIL_CONTEXT *SilContext) phx_data->CfgHdAudioEnable = is_dev_enabled(hda); phx_data->CfgSensorHubEnable = is_dev_enabled(mp2); - if (acp) - phx_data->CfgAcpSsid = acp->subsystem_vendor | - ((uint32_t)acp->subsystem_device << 16); - if (gfx) - phx_data->AmdCfgGnbIGPUSSID = gfx->subsystem_vendor | - ((uint32_t)gfx->subsystem_device << 16); - if (gfx_hda) - phx_data->AmdCfgGnbIGPUAudioSSID = gfx_hda->subsystem_vendor | - ((uint32_t)gfx_hda->subsystem_device << 16); - if (nbifrc) - phx_data->CfgNbifRCSsid = nbifrc->subsystem_vendor | - ((uint32_t)nbifrc->subsystem_device << 16); - if (gnb) - mpio_data->CfgNbioSsid = gnb->subsystem_vendor | - ((uint32_t)gnb->subsystem_device << 16); - if (iommu) - mpio_data->CfgIommuSsid = iommu->subsystem_vendor | - ((uint32_t)iommu->subsystem_device << 16); - if (psp) - mpio_data->CfgPspccpSsid = psp->subsystem_vendor | - ((uint32_t)psp->subsystem_device << 16); - if (nbif) - mpio_data->CfgNbifF0Ssid = nbif->subsystem_vendor | - ((uint32_t)nbif->subsystem_device << 16); + if (pcidev_get_ssid(acp)) + phx_data->CfgAcpSsid = pcidev_get_ssid(acp); + if (pcidev_get_ssid(gfx)) + phx_data->AmdCfgGnbIGPUSSID = pcidev_get_ssid(gfx); + if (pcidev_get_ssid(gfx_hda)) + phx_data->AmdCfgGnbIGPUAudioSSID = pcidev_get_ssid(gfx_hda); + if (pcidev_get_ssid(nbifrc)) + phx_data->CfgNbifRCSsid = pcidev_get_ssid(nbifrc); + if (pcidev_get_ssid(gnb)) + mpio_data->CfgNbioSsid = pcidev_get_ssid(gnb); + if (pcidev_get_ssid(iommu)) + mpio_data->CfgIommuSsid = pcidev_get_ssid(iommu); + if (pcidev_get_ssid(psp)) + mpio_data->CfgPspccpSsid = pcidev_get_ssid(psp); + if (pcidev_get_ssid(nbif)) + mpio_data->CfgNbifF0Ssid = pcidev_get_ssid(nbif); mpio_data->CfgDxioClockGating = 1; mpio_data->PcieDxioTimingControlEnable = 0; @@ -262,7 +254,7 @@ void opensil_mpio_per_device_config(struct device *dev) port.Port = port_data; port.Port.MiscControls.SbLink = config->sb_link; - if (dev->subsystem_vendor && dev->subsystem_device) { + if (pcidev_get_ssid(dev)) { mpio_data->AmdPcieSubsystemVendorID = dev->subsystem_vendor; mpio_data->AmdPcieSubsystemDeviceID = dev->subsystem_device; } diff --git a/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c index 4bc29328abf..fb65af40f4a 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/prom21/chip_to_opensil.c @@ -117,11 +117,6 @@ static void config_usb_port_enables(struct device *xhci_dev, } } -static uint32_t get_pci_ssid(struct device *dev) -{ - return (uint32_t)(dev->subsystem_vendor | ((uint32_t)dev->subsystem_device << 16)); -} - void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_port) { PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); @@ -168,9 +163,9 @@ void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_po cfg = usp->chip_info; primary = &input_blk->Primary; - if (get_pci_ssid(usp)) { + if (pcidev_get_ssid(usp)) { primary->PT21SsidOverride = 1; - primary->PT21PcieUspSsid = get_pci_ssid(usp); + primary->PT21PcieUspSsid = pcidev_get_ssid(usp); } /* @@ -192,22 +187,22 @@ void opensil_promontory21_config(SIL_CONTEXT *SilContext, struct device *root_po /* DSP PCIe port: slot 0-11 maps to port index 0-11 */ primary->PT21PciePortEnable[slot] = dsp->enabled; if (dsp->enabled) - primary->PT21PcieDspSsid = get_pci_ssid(dsp); + primary->PT21PcieDspSsid = pcidev_get_ssid(dsp); } else if (dsp->path.pci.devfn == PROM21_XHCI_DEVFN) { struct device *xhci = dsp->downstream ? dsp->downstream->children : NULL; - primary->PT21PcieDspXhciSsid = get_pci_ssid(dsp); + primary->PT21PcieDspXhciSsid = pcidev_get_ssid(dsp); if (xhci) { config_usb_port_enables(xhci, primary); - primary->PT21XhciSsid = get_pci_ssid(xhci); + primary->PT21XhciSsid = pcidev_get_ssid(xhci); } } else if (dsp->path.pci.devfn == PROM21_SATA_DEVFN) { primary->PT21SataEnable = dsp->enabled ? 1 : 0; struct device *ahci = dsp->downstream ? dsp->downstream->children : NULL; - primary->PT21PcieDspAhciSsid = get_pci_ssid(dsp); + primary->PT21PcieDspAhciSsid = pcidev_get_ssid(dsp); if (ahci) - primary->PT21AhciSsid = get_pci_ssid(ahci); + primary->PT21AhciSsid = pcidev_get_ssid(ahci); } } diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index b16b75b67e6..d0581e57b94 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -147,8 +147,8 @@ static void configure_usb(SIL_CONTEXT *SilContext) if (!fch_usb_data) return; - fch_usb_data->XhciSsid = usb_ctrlr[0]->subsystem_vendor | - ((uint32_t)usb_ctrlr[0]->subsystem_device << 16); + if (pcidev_get_ssid(usb_ctrlr[0])) + fch_usb_data->XhciSsid = pcidev_get_ssid(usb_ctrlr[0]); fch_usb_data->Xhci0Enable = is_dev_enabled(usb_ctrlr[0]); fch_usb_data->Xhci1Enable = is_dev_enabled(usb_ctrlr[1]); @@ -312,19 +312,16 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) return; } - if (smb) { - fch_data->Smbus.SmbusSsid = smb->subsystem_vendor | - ((uint32_t)smb->subsystem_device << 16); - fch_data->FchBldCfg.CfgSmbusSsid = fch_data->Smbus.SmbusSsid; + if (pcidev_get_ssid(smb)) { + fch_data->Smbus.SmbusSsid = pcidev_get_ssid(smb); + fch_data->FchBldCfg.CfgSmbusSsid = pcidev_get_ssid(smb); } - if (hda) - fch_data->FchBldCfg.CfgAzaliaSsid = hda->subsystem_vendor | - ((uint32_t)hda->subsystem_device << 16); + if (pcidev_get_ssid(hda)) + fch_data->FchBldCfg.CfgAzaliaSsid = pcidev_get_ssid(hda); - if (xhci) - fch_data->FchBldCfg.CfgXhciSsid = xhci->subsystem_vendor | - ((uint32_t)xhci->subsystem_device << 16); + if (pcidev_get_ssid(xhci)) + fch_data->FchBldCfg.CfgXhciSsid = pcidev_get_ssid(xhci); fch_data->FchBldCfg.CfgSioPmeBaseAddress = 0; fch_data->FchBldCfg.CfgAcpiPm1EvtBlkAddr = ACPI_PM_EVT_BLK; From c9fad590c039423f2d4010a7e0cd89d2dde37a23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 13:34:31 +0200 Subject: [PATCH 29/62] mainboard/msi/ms7e56/devicetree.cb: Fix ACPI errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix Linux unable to init sleep button and non existent PROM21 USB3 port 6 with wrong ACPI path. Upstream-Status: Pending Change-Id: Iae99021dbda3243073ed0e31678eac346d00c469 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index df68dd1df89..4b93ff9a779 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -3,6 +3,7 @@ chip soc/amd/phoenix # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES" + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, @@ -592,7 +593,7 @@ chip soc/amd/phoenix device usb 3.4 alias prom21_usb3_port5 on end end chip drivers/usb/acpi - device usb 3.5 alias prom21_usb3_port6 on end + device usb 3.5 alias prom21_usb3_port6 off end end end end From 4cb67d1ccc333adda17a30daef5e83498c48afa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 14:11:28 +0200 Subject: [PATCH 30/62] util/amdtool/gpio.c: Print GPIO number when dumping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Print the GPIO number when dumping its configuration to map it easily with PPR. Upstream-Status: Pending Change-Id: If94ada421f71983401e0b2c946d7200b3bf810dd Signed-off-by: Michał Żygowski --- util/amdtool/gpio.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/util/amdtool/gpio.c b/util/amdtool/gpio.c index 029d106ae6a..0fc46a29428 100644 --- a/util/amdtool/gpio.c +++ b/util/amdtool/gpio.c @@ -265,7 +265,7 @@ const uint32_t tacoma_gpio_group_defaults[] = { [0x0240 / 4] = 0x00240000, 0x00000000, 0x00060000, 0x00000000, [0x0250 / 4] = 0x00060000, 0x00000000, 0x00000000, 0x00000000, [0x0260 / 4] = 0x00000000, 0x00240000, 0x00140000, 0x00240000, - [0x0260 / 4] = 0x00140000, 0x00240000, 0x00000000, 0x00000000, + [0x0270 / 4] = 0x00140000, 0x00240000, 0x00000000, 0x00000000 }; #pragma GCC diagnostic pop @@ -357,16 +357,16 @@ const char * const trigger_type[] = { static void print_iomux_reg(uint16_t addr, uint8_t reg, const char *const *gpio_names) { - printf("IOMUXx%02x: 0x%02x (%s)\n", - addr, reg, gpio_names[addr * 4 + reg]); + printf("IOMUXx%02x (GPIO%03u): 0x%02x (%s)\n", + addr, addr, reg, gpio_names[addr * 4 + reg]); } static void print_iomux_diff(const uint8_t reg, const uint8_t def, const uint8_t diff, const char *const *gpio_names) { - printf("IOMUXx%02x: 0x%02x (%s) DEFAULT\n", - reg, def, gpio_names[reg * 4 + def]); - printf("IOMUXx%02x: 0x%02x DIFF\n", reg, diff); + printf("IOMUXx%02x (GPIO%03u): 0x%02x (%s) DEFAULT\n", + reg, reg, def, gpio_names[reg * 4 + def]); + printf("IOMUXx%02x (GPIO%03u): 0x%02x DIFF\n", reg, reg, diff); } static void print_gpio_reg(uint16_t addr, uint32_t reg, bool verbose) @@ -374,7 +374,7 @@ static void print_gpio_reg(uint16_t addr, uint32_t reg, bool verbose) size_t i; const char *attr; - printf("GPIOx%04x: 0x%08"PRIx32"\n", addr * 4, reg); + printf("GPIOx%04x (GPIO%03u): 0x%08"PRIx32"\n", addr * 4, addr, reg); if (!verbose) return; @@ -398,8 +398,8 @@ static void print_gpio_reg(uint16_t addr, uint32_t reg, bool verbose) static void print_gpio_diff(const uint16_t reg, const uint32_t def, const uint32_t diff) { - printf("GPIOx%04x: 0x%08x DEFAULT\n", reg * 4, def); - printf("GPIOx%04x: 0x%08x DIFF\n", reg * 4, diff); + printf("GPIOx%04x (GPIO%03u): 0x%08x DEFAULT\n", reg * 4, reg, def); + printf("GPIOx%04x (GPIO%03u): 0x%08x DIFF\n", reg * 4, reg, diff); } static bool is_special_gpio_register(uint16_t reg, const struct gpio_group *sb_gpio_group) From 435193b974950e4182937eaf474963e73b98af43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 14:56:28 +0200 Subject: [PATCH 31/62] soc/amd/phoenix/fch.c: Set FORCE_STPCLK_RETRY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mimic default setting of vendor BIOSes. Upstream-Status: Pending Change-Id: Ib3dd82786226c1e60798a275f80942bb0a60db2a Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/fch.c | 1 + src/soc/amd/phoenix/include/soc/southbridge.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index df1dd8850d1..f3b717f664a 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -105,6 +105,7 @@ static void fch_init_acpi_ports(void) response of the I/O write. */ reg = pm_read32(PM_PCI_CTRL); reg |= FORCE_SLPSTATE_RETRY; + reg &= ~FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, reg); /* Disable SlpTyp feature */ diff --git a/src/soc/amd/phoenix/include/soc/southbridge.h b/src/soc/amd/phoenix/include/soc/southbridge.h index 60ac3951f9d..8663907aef1 100644 --- a/src/soc/amd/phoenix/include/soc/southbridge.h +++ b/src/soc/amd/phoenix/include/soc/southbridge.h @@ -9,6 +9,7 @@ #define PM_ISACONTROL 0x04 #define ABCLKGATEEN BIT(16) #define PM_PCI_CTRL 0x08 +#define FORCE_STPCLK_RETRY BIT(24) #define FORCE_SLPSTATE_RETRY BIT(25) #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) From 28b1883ce37727cf25030b3a8d8e875198bd9c5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 14:57:50 +0200 Subject: [PATCH 32/62] soc/amd/common/block/lpc/espi_util.c: Set IRQ mask via devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set eSPI IRQ mask based on the devicetree settings, if provided. Upstream-Status: Pending Change-Id: I2329fbb515deeaa48189126ad50af630a560683d Signed-off-by: Michał Żygowski --- src/soc/amd/common/block/include/amdblocks/espi.h | 2 ++ src/soc/amd/common/block/lpc/espi_util.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 5781dea3af8..8b793dd1cc6 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -124,6 +124,8 @@ struct espi_config { /* Use ESPI_VW_IRQ_* above */ uint32_t vw_irq_polarity; + + uint32_t irq_mask; }; /* diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index f05575ab748..fd540c60877 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -1103,6 +1104,9 @@ enum cb_err espi_setup(void) espi_write32(ESPI_GLOBAL_CONTROL_1, ctrl); + if (cfg->irq_mask) + pm_write32(PM_ESPI_INTR_CTRL, cfg->irq_mask); + printk(BIOS_SPEW, "Finished initializing ESPI.\n"); return CB_SUCCESS; From d91bedf55b49ed98d824ea4839a9ae47407631f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 14:58:52 +0200 Subject: [PATCH 33/62] vc/amd/opensil/phoenix_poc: Update settings based on SoC config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I156da2279bc7839cdb7420401e25cc70fb9802f1 Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/ramstage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index d0581e57b94..444c4cc41b1 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -292,6 +292,7 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) { FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpi, 0); FCHCLASS_INPUT_BLK *fch_data = SilFindStructure(SilContext, SilId_FchClass, 0); + struct soc_amd_phoenix_config *cfg = config_of_soc(); struct device *smb = DEV_PTR(smbus); struct device *xhci = DEV_PTR(xhci_0); struct device *hda = DEV_PTR(hda); @@ -336,7 +337,10 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) fch_data->FchIoApicId = 32; } - fch_data->WdtEnable = false; + if(cfg && !(cfg->common_config.fadt_boot_arch & ACPI_FADT_8042)) + fch_data->Misc.NoneSioKbcSupport = true; + + fch_data->WdtEnable = true; /* eSPI always enabled (bit 27) */ fch_data->FchRunTime.FchDeviceEnableMap = (1 << 27); From bbc192e1c452a9e928cb76bbb3102eeefefe553d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 16:58:04 +0200 Subject: [PATCH 34/62] util/amdtool/gpio.c: Add missing PHX GPIO27 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I54dfc1b80a0946c8fb01d1a220f3463b1ddd71d2 Signed-off-by: Michał Żygowski --- util/amdtool/gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/amdtool/gpio.c b/util/amdtool/gpio.c index 0fc46a29428..6f3f3afbbe4 100644 --- a/util/amdtool/gpio.c +++ b/util/amdtool/gpio.c @@ -130,6 +130,7 @@ const char *const tacoma_iomux_gpio_names[] = { [ 23 * 4] = "AC_PRES", "GPIO23", "GPIO23", "GPIO23", [ 24 * 4] = "USB_OC3_L", "GPIO24", "GPIO24", "GPIO24", [ 26 * 4] = "PCIE_RST0_L", "GPIO26", "GPIO26", "GPIO26", + [ 27 * 4] = "GPIO27", "PCIE_RST1_L", "GPIO27", "GPIO27", [ 29 * 4] = "SPI_TPM_CS_L", "GPIO29", "GPIO29", "GPIO29", [ 30 * 4] = "SPI_CS2_L", "ESPI_CS_L", "GPIO30", "GPIO30", [ 31 * 4] = "SPI_CS3_L", "GPIO31", "GPIO31", "GPIO31", From 28ce36f44f481e96fbff42453f9b5f890f6e11ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 16:58:35 +0200 Subject: [PATCH 35/62] vc/amd/opensil/phoenix_poc/ramstage.c: Enable XTAL pad power saving MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mimic vendor BIOS settings. Upstream-Status: Pending Change-Id: I5b180ed8f067919ec42017f49845b6749490ac06 Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/ramstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 444c4cc41b1..7b1178ef274 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -300,6 +300,8 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) if (!fch_hwacpi_data) { printk(BIOS_ERR, "OpenSIL: FCH HW ACPI data not found\n"); } else { + fch_hwacpi_data->Xtal48MPadPowerSaving = true; + if (CONFIG_MAINBOARD_POWER_FAILURE_STATE == 2) fch_hwacpi_data->PwrFailShadow = UsePrevious; else if (CONFIG_MAINBOARD_POWER_FAILURE_STATE == 1) From 760bdc65140cf20a1b39e0d7aee8f058bf6b0f99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 16:59:22 +0200 Subject: [PATCH 36/62] mainboard/msi/ms7e56: Update GPIO configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update GPIO configuration to match vendor BIOS. Upstream-Status: Pending Change-Id: I72ba373a268febd41288ddfb744fcdea80346bb4 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/early_gpio.c | 49 ++++++++++++--------------- src/mainboard/msi/ms7e56/gpio.c | 21 ++++++++++-- 2 files changed, 41 insertions(+), 29 deletions(-) diff --git a/src/mainboard/msi/ms7e56/early_gpio.c b/src/mainboard/msi/ms7e56/early_gpio.c index af71f7e2852..f3dc89764ad 100644 --- a/src/mainboard/msi/ms7e56/early_gpio.c +++ b/src/mainboard/msi/ms7e56/early_gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include "gpio.h" @@ -7,39 +8,33 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* TPM CS */ - PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_UP), /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + PAD_NF(GPIO_30, ESPI_CS_L, PULL_UP), /* ESPI_SOC_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + PAD_NF(GPIO_77, SPI1_CLK, PULL_DOWN), /* ESPI_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + PAD_NF(GPIO_81, SPI1_DAT0, PULL_DOWN), /* ESPI_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + PAD_NF(GPIO_80, SPI1_DAT1, PULL_DOWN), /* ESPI_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + PAD_NF(GPIO_68, SPI1_DAT2, PULL_UP), /* ESPI_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + PAD_NF(GPIO_69, SPI1_DAT3, PULL_UP), /* ESPI_ALERT_L */ PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* TPM IRQ */ - // PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* ESPI_RESET_L */ + PAD_NF(GPIO_21, ESPI_RESET_L, PULL_UP), /* SPI_ROM_REQ */ - PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_UP), /* SPI_ROM_GNT */ - PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), - /* KBRST_L */ - PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_DOWN), + /* SPI1_CS3_L */ + PAD_NF(GPIO_79, SPI1_CS3_L, PULL_UP), /* Deassert PCIe Reset lines */ /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), - /* PCIE_RST1_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* M2_SSD0_RST_L */ - PAD_GPO(GPIO_78, HIGH), - /* M2_SSD1_RST_L */ - PAD_GPO(GPIO_79, HIGH), /* I2C0 SCL */ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), @@ -49,14 +44,14 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), /* I2C1 SDA */ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* SMBUS0_SCL */ + PAD_NF(GPIO_113, SMBUS0_SCL, PULL_NONE), + /* SMBUS0_SDA */ + PAD_NF(GPIO_114, SMBUS0_SDA, PULL_NONE), + /* SMBUS1_SCL */ + PAD_NF(GPIO_19, SMBUS1_SCL, PULL_NONE), + /* SMBUS1_SDA */ + PAD_NF(GPIO_20, SMBUS1_SDA, PULL_NONE), }; void mainboard_program_early_gpios(void) diff --git a/src/mainboard/msi/ms7e56/gpio.c b/src/mainboard/msi/ms7e56/gpio.c index 5a09ba578fd..481993a4229 100644 --- a/src/mainboard/msi/ms7e56/gpio.c +++ b/src/mainboard/msi/ms7e56/gpio.c @@ -6,8 +6,25 @@ /* GPIO pins used by coreboot should be initialized in bootblock */ static const struct soc_amd_gpio gpio_table[] = { - /* S0A3 */ - PAD_NF(GPIO_10, S0A3_GPIO, PULL_NONE) + PAD_GPI(GPIO_2, PULL_UP), + PAD_INT(GPIO_3, PULL_UP, LEVEL_LOW, STATUS_DELIVERY), + PAD_GPO(GPIO_5, HIGH), + PAD_GPO(GPIO_6, HIGH), + PAD_GPO(GPIO_7, HIGH), + PAD_GPO(GPIO_8, LOW), + PAD_GPI(GPIO_9, PULL_NONE), + PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), + PAD_NF(GPIO_11, BLINK, PULL_UP), + PAD_GPI(GPIO_12, PULL_UP), + PAD_GPI(GPIO_18, PULL_UP), + PAD_GPI(GPIO_23, PULL_UP), + PAD_GPI(GPIO_27, PULL_UP), + PAD_INT(GPIO_32, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + PAD_GPO(GPIO_40, HIGH), + PAD_GPI(GPIO_42, PULL_UP), + PAD_GPI(GPIO_78, PULL_UP), + PAD_NF(GPIO_91, SPKR, PULL_NONE), + PAD_GPI(GPIO_115, PULL_UP), }; void mainboard_program_gpios(void) From bcc79abe4ec1d20e3715b939bf84f72aac60c5ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 19 May 2026 16:59:54 +0200 Subject: [PATCH 37/62] mainboard/msi/ms7e56: Udpate settings to match vendor BIOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Program clocks, eSPI IRQ masking and I2C devices enabling as vendor BIOS does. Upstream-Status: Pending Change-Id: I7727764611e7e6916ea288b7eb2ab198f0bd9648 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 4b93ff9a779..2895b198f23 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -40,10 +40,19 @@ chip soc/amd/phoenix .vw_ch_en = 1, .oob_ch_en = 1, .flash_ch_en = 1, + .irq_mask = 0xffe107, }" register "s0ix_enable" = "false" + register "gpp_clk_config[0]" = "GPP_CLK_ON" + register "gpp_clk_config[1]" = "GPP_CLK_ON" + register "gpp_clk_config[2]" = "GPP_CLK_ON" + register "gpp_clk_config[3]" = "GPP_CLK_ON" + register "gpp_clk_config[4]" = "GPP_CLK_ON" + register "gpp_clk_config[5]" = "GPP_CLK_ON" + register "gpp_clk_config[6]" = "GPP_CLK_ON" + register "pspp_policy" = "DXIO_PSPP_DISABLED" register "usb_phy_custom" = "true" @@ -923,8 +932,6 @@ chip soc/amd/phoenix end end - device ref i2c_0 on end - device ref i2c_1 on end - device ref i2c_2 on end - device ref i2c_3 on end + device ref i2c_0 hidden end + device ref i2c_1 hidden end end From 0b2a3b257ea0b80796705e341a3fd5fa69505cdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 20 May 2026 09:33:29 +0200 Subject: [PATCH 38/62] mainboard/msi/ms7e56: Add ACPI code for SIO and MSI utilities installer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I2b551413691d6a8be4db470a190697b20ee1183e Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/acpi/mainboard.asl | 12 ++++++++++++ src/mainboard/msi/ms7e56/acpi/superio.asl | 8 ++++++++ src/mainboard/msi/ms7e56/dsdt.asl | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 src/mainboard/msi/ms7e56/acpi/mainboard.asl create mode 100644 src/mainboard/msi/ms7e56/acpi/superio.asl diff --git a/src/mainboard/msi/ms7e56/acpi/mainboard.asl b/src/mainboard/msi/ms7e56/acpi/mainboard.asl new file mode 100644 index 00000000000..da058a0e0e5 --- /dev/null +++ b/src/mainboard/msi/ms7e56/acpi/mainboard.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (\_SB.PCI0) { + /* This device triggers automatic drivers and MSI utilities installation on Windows */ + Device (MSIV) { + Name (_HID, "MBAD0002") + Name (_UID, 1) + Method (_STA, 0, NotSerialized){ + Return (1) + } + } +} diff --git a/src/mainboard/msi/ms7e56/acpi/superio.asl b/src/mainboard/msi/ms7e56/acpi/superio.asl new file mode 100644 index 00000000000..6c2ae3d9d71 --- /dev/null +++ b/src/mainboard/msi/ms7e56/acpi/superio.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x4e +#define NCT6687D_SHOW_SP1 +#define NCT6687D_SHOW_EC + +#include diff --git a/src/mainboard/msi/ms7e56/dsdt.asl b/src/mainboard/msi/ms7e56/dsdt.asl index 7b8982a645c..3388ca99f04 100644 --- a/src/mainboard/msi/ms7e56/dsdt.asl +++ b/src/mainboard/msi/ms7e56/dsdt.asl @@ -13,4 +13,12 @@ DefinitionBlock ( #include #include + + + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + + #include "acpi/mainboard.asl" } From 2f148a47045b1e11cf9a933f8171e4bbd768b9f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 20 May 2026 11:39:38 +0200 Subject: [PATCH 39/62] util/msi/romholetool: Add support for MS-7E56 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MS-7E56 board, aka MSI PRO B850-P WIFI has small differences in the romhole structure. Use preprocessor defines in a Kconfig option to override the romhole structure and construct the romhole binary that matches the format of the board. Changes are made in a way that previous boards are not affected. Upstream-Status: Pending Change-Id: I21f0de69957d3610761a8ab32d999fc6fd9d463f Signed-off-by: Michał Żygowski --- util/msi/Makefile.mk | 2 ++ util/msi/romholetool/romholetool.c | 26 +++++++++++++++++++------- 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/util/msi/Makefile.mk b/util/msi/Makefile.mk index 6079cbf24d8..98b382a9d6a 100644 --- a/util/msi/Makefile.mk +++ b/util/msi/Makefile.mk @@ -2,6 +2,8 @@ TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler MSIROMHOLETOOL:= $(objutil)/msi/romholetool +TOOLCPPFLAGS += $(call strip_quotes, $(CONFIG_MSI_ROMHOLE_TOOL_FLAGS)) + $(MSIROMHOLETOOL): $(dir)/romholetool/romholetool.c printf " HOSTCC Creating MSI ROMHOLE tool\n" mkdir -p $(objutil)/msi diff --git a/util/msi/romholetool/romholetool.c b/util/msi/romholetool/romholetool.c index 4fa8a2341ff..8636c717716 100644 --- a/util/msi/romholetool/romholetool.c +++ b/util/msi/romholetool/romholetool.c @@ -25,7 +25,11 @@ #define FTB_SIZE 105 #define FIB_SIZE 512 #define FDP_SIZE 1024 +#ifndef MSI_ROMHOLE_BUV_SIZE #define BUV_SIZE 1024 +#else +#define BUV_SIZE MSI_ROMHOLE_BUV_SIZE +#endif #define NUM_VOLUMES 7 struct uuid_structure { @@ -73,7 +77,11 @@ struct us_entry { struct ucsc_structure { uint8_t magic[4]; // always uCsC - uint16_t length; // structure length +#ifndef MSI_ROMHOLE_32BIT_LENGTHS + uint16_t length; // length of the structure +#else + uint32_t length; // length of the structure +#endif struct us_entry entries[NUM_US_ENTRIES]; } __packed; @@ -140,7 +148,11 @@ struct ris_structure { /* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ struct msi_romhole { uint32_t magic0; // 0x10012501 +#ifndef MSI_ROMHOLE_32BIT_LENGTHS uint16_t length; // length of the structure +#else + uint32_t length; // length of the structure +#endif char magic1[4]; // always SYSD uint32_t address; // romhole address in flash uint32_t size; // romhole total size @@ -152,7 +164,9 @@ struct msi_romhole { struct type2_rw t2rw; struct ftb_structure ftb; struct fib_structure fib; +#ifndef MSI_ROMHOLE_NO_FDP struct fdp_structure fdp; +#endif struct buv_structure buv; struct ris_structure ris; // the rest is padded with 0xff by cbfstool @@ -326,11 +340,7 @@ int main(int argc, char **argv) romhole->address = romhole_addr; romhole->size = romhole_size; memset(romhole->pad0, 0xff, 48); - romhole->length = (uint16_t)sizeof(*romhole); - - // For some reason the actual data size is reduced by 64K - if (romhole_size > 0x10000) - romhole->length -= 0x10000; + romhole->length = sizeof(*romhole); // Structures @@ -365,7 +375,7 @@ int main(int argc, char **argv) // UCSC strncpy(romhole->ucsc.magic, "uCsC", 4); - romhole->ucsc.length = (uint16_t)sizeof(struct ucsc_structure); + romhole->ucsc.length = sizeof(struct ucsc_structure); for (i = 0; i < NUM_US_ENTRIES; i++) { strncpy(romhole->ucsc.entries[i].magic, "$uS", 3); // The first 6 entries are in order @@ -403,12 +413,14 @@ int main(int argc, char **argv) strncpy(romhole->fib.magic1, "$MFX", 4); memset(romhole->fib.data, 0xfa, FIB_SIZE); +#ifndef MSI_ROMHOLE_NO_FDP // FDP strncpy(romhole->fdp.magic0, "$FDP", 4); romhole->fdp.length = (uint16_t)sizeof(struct fdp_structure); strncpy(romhole->fdp.magic1, "$Fd", 3); romhole->fdp.number = 1; memset(romhole->fdp.data, 0xff, FDP_SIZE); +#endif // BUV strncpy(romhole->buv.magic0, "$BuV", 4); From 2f0f93681415d502dae77470dadbcb9240188020 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 20 May 2026 11:44:33 +0200 Subject: [PATCH 40/62] mainboard/msi/ms7e56: Add MSI FlashBIOS support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add necessary regions, options and structures to the resutling image to make FlashBIOS work. Use the freshly added ROMHOLE as a source for the SMBIOS type 2 values. Upstream-Status: Pending Change-Id: If4fe27fc0701c4458d3a10bae68da4adfe8602fa Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Kconfig | 8 ++ src/mainboard/msi/ms7e56/Makefile.mk | 15 +++ src/mainboard/msi/ms7e56/board.fmd | 15 ++- src/mainboard/msi/ms7e56/msi_id.S | 62 ++++++++++++ src/mainboard/msi/ms7e56/romhole.h | 139 +++++++++++++++++++++++++++ src/mainboard/msi/ms7e56/smbios.c | 134 ++++++++++++++++++++++++++ 6 files changed, 369 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/msi/ms7e56/msi_id.S create mode 100644 src/mainboard/msi/ms7e56/romhole.h create mode 100644 src/mainboard/msi/ms7e56/smbios.c diff --git a/src/mainboard/msi/ms7e56/Kconfig b/src/mainboard/msi/ms7e56/Kconfig index c0b52238400..065722d5a30 100644 --- a/src/mainboard/msi/ms7e56/Kconfig +++ b/src/mainboard/msi/ms7e56/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select USE_X86_64_SUPPORT select IOAPIC_8BIT_ID select IOAPIC_PREDEFINED_ID + select BOARD_HAS_MSI_ROMHOLE config FMDFILE default "src/mainboard/msi/ms7e56/board.fmd" @@ -39,6 +40,9 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY default "Default string" +config MAINBOARD_VERSION + default "2.0" + config UART_FOR_CONSOLE default 0 @@ -92,4 +96,8 @@ config MRC_SETTINGS_CACHE_SIZE config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 +config MSI_ROMHOLE_TOOL_FLAGS + string + default "-DMSI_ROMHOLE_NO_FDP -DMSI_ROMHOLE_32BIT_LENGTHS -DMSI_ROMHOLE_BUV_SIZE=2048" + endif # BOARD_MSI_PRO_B850_P diff --git a/src/mainboard/msi/ms7e56/Makefile.mk b/src/mainboard/msi/ms7e56/Makefile.mk index 761c6a1c175..f4352025962 100644 --- a/src/mainboard/msi/ms7e56/Makefile.mk +++ b/src/mainboard/msi/ms7e56/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += bootblock.c bootblock-y += early_gpio.c ramstage-y += gpio.c +ramstage-y += smbios.c ramstage-y += update_devicetree.c ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/data*.apcb),) @@ -13,3 +14,17 @@ APCB_SOURCES_68 = $(src)/mainboard/$(MAINBOARDDIR)/data_rec68.apcb else show_notices:: warn_no_apcb endif + +$(call src-to-obj,bootblock,$(dir)/msi_id.S): $(obj)/fmap_config.h $(obj)/build.h + +bootblock-y += msi_id.S + +$(obj)/msi_id.bin: $(obj)/bootblock/mainboard/$(MAINBOARDDIR)/msi_id.o + $(OBJCOPY_bootblock) -O binary $< $@ + +# The MSI ID must be in the last sectors of the image for the MSI FlashBIOS to +# detect it +$(call add_intermediate, add_msi_id, $(obj)/msi_id.bin) + @printf " WRITE MSI_ID\n" + $(CBFSTOOL) $< write -u -i 255 -r MSI_ID -f $(obj)/msi_id.bin + rm $(obj)/msi_id.bin diff --git a/src/mainboard/msi/ms7e56/board.fmd b/src/mainboard/msi/ms7e56/board.fmd index 4f60ca47e42..261da79416b 100644 --- a/src/mainboard/msi/ms7e56/board.fmd +++ b/src/mainboard/msi/ms7e56/board.fmd @@ -1,10 +1,17 @@ FLASH 32M { BIOS 16M { - COREBOOT(CBFS) FMAP 4K - PSP_NVRAM 128K - PSP_RPMC_NVRAM 256K + COREBOOT(CBFS) SMMSTORE(PRESERVE) 512K - RW_MRC_CACHE 1M } + RW_MRC_CACHE 1M + PSP_NVRAM 128K + PSP_RPMC_NVRAM 256K + UNUSED + BPA(PRESERVE)@0x1B50000 320K + UNUSED2 + # ROMHOLE must be at flash offset 0x1BE0000 + ROMHOLE(PRESERVE)@0x1BE0000 128K + UNUSED3 + MSI_ID 4K } diff --git a/src/mainboard/msi/ms7e56/msi_id.S b/src/mainboard/msi/ms7e56/msi_id.S new file mode 100644 index 00000000000..9e78be477ef --- /dev/null +++ b/src/mainboard/msi/ms7e56/msi_id.S @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +.section .text, "a", @progbits + +/* The following structures must reside in the last 64KiB of flash */ + +.align 16 + +build_date: + .ascii "$MSESGN$" + .ascii "E7E56AMSI.2" + .byte 0x30 + DASHARO_MAJOR_VERSION + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte ' ' + .asciz COREBOOT_DMI_DATE + +.align 8 + +msi_sign_on: + .ascii "$MS1E7E56AMSI2" + .byte 0x30 + DASHARO_MAJOR_VERSION + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte 0x11 + .byte 0xe9 + .ascii "$MSVIDS$" + .byte 0x11 + +.align 8 + +bpa: + .ascii "$BPA" + .byte bpa_end - bpa + .byte 1 + .long 0x1000 + .long 6 + .byte 2 + .long 0x1be0000 + .long 0x20000 + .byte 3 + .long 0x1b90000 + .long 63 + .byte 4 + .byte 2 +bpa_end: + .zero 5 + + .asciz "@FC@" + .byte '2' + .byte 0 + .byte '1' + .byte 0 + .asciz "/P /fab /N /K" + .byte '2' + .byte 0 + .ascii "NULL" + .ascii "@@" + .zero 58 diff --git a/src/mainboard/msi/ms7e56/romhole.h b/src/mainboard/msi/ms7e56/romhole.h new file mode 100644 index 00000000000..bb58b2216ce --- /dev/null +++ b/src/mainboard/msi/ms7e56/romhole.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROMHOLE_H_ +#define _ROMHOLE_H_ + +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define BUV_SIZE 2048 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint32_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint32_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +#endif diff --git a/src/mainboard/msi/ms7e56/smbios.c b/src/mainboard/msi/ms7e56/smbios.c new file mode 100644 index 00000000000..b660373d526 --- /dev/null +++ b/src/mainboard/msi/ms7e56/smbios.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "romhole.h" + +struct smbios_type2_v3_4 { + struct smbios_header header; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag; + u8 feature_flags; + u8 location_in_chassis; + u16 chassis_handle; + u8 board_type; + u8 contained_objects; + u8 eos[2]; +} __packed; + +static struct msi_romhole *romhole_addr = NULL; + +static struct msi_romhole *get_msi_romhole_address(void) +{ + struct region_device rdev; + + if (romhole_addr) + return romhole_addr; + + if (fmap_locate_area_as_rdev("ROMHOLE", &rdev)) + return NULL; + + romhole_addr = (struct msi_romhole *)rdev_mmap_full(&rdev); + + return romhole_addr; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_product_name(void) +{ + return "MS-7E56"; +} + +const char *smbios_mainboard_product_name(void) +{ + return CONFIG_MAINBOARD_PART_NUMBER; +} + +/* Only baseboard serial number is populated */ +const char *smbios_system_serial_number(void) +{ + return "Default string"; +} + +const char *smbios_system_sku(void) +{ + return "Default string"; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + if (!get_msi_romhole_address()) + return; + + memcpy(uuid, romhole_addr->uuid.uuid, 16); +} + +static const char* get_smbios_string(u8 *str_table_start, u8 string_index, + const char *fallback) +{ + u8 i; + char *smbios_str = (char *)str_table_start; + + for (i = 1; i < string_index; i++) { + if (strlen(smbios_str)) + smbios_str += strlen(smbios_str) + 1; + else + return fallback; + } + + return strlen(smbios_str) ? (const char *)smbios_str : fallback; +} + +const char *smbios_mainboard_serial_number(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + return get_smbios_string(type2->eos, type2->serial_number, + CONFIG_MAINBOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_VERSION; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_VERSION; + + return get_smbios_string(type2->eos, type2->version, + CONFIG_MAINBOARD_VERSION); +} From 1426f955a19ae57c33d0077bfc06593bb9162904 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 20 May 2026 13:46:52 +0200 Subject: [PATCH 41/62] soc/amd/phoenix/Kconfig: Enable AMD memory context save/restore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On modern platforms the state of APOB NV copy is stored in CMOS. Upstream-Status: Pending Change-Id: I6b5c5745fb9d0a30dc61542c5ca266eb70611e6e Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index fc5ba462590..e3132fc1147 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -116,6 +116,7 @@ config SOC_AMD_PHOENIX_OPENSIL select SOC_AMD_PHOENIX_BASE select SOC_AMD_OPENSIL select SOC_AMD_OPENSIL_PHOENIX_POC + select SOC_AMD_COMMON_BLOCK_APOB_MEMCTX_CMOS select UDK_2017_BINDING help AMD Phoenix support using OpenSIL (Proof of Comcept) From e849288412904c33b6923734110633600caa4b07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 25 May 2026 18:36:00 +0200 Subject: [PATCH 42/62] util/amdtool/espi.c: Add more eSPI registers to dump MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I3f23c95e5a1d30c26c06c48f77f4a99881511c04 Signed-off-by: Michał Żygowski --- util/amdtool/espi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/util/amdtool/espi.c b/util/amdtool/espi.c index 29495dd01c1..1448fb7da7e 100644 --- a/util/amdtool/espi.c +++ b/util/amdtool/espi.c @@ -21,9 +21,11 @@ #define ESPI1_SMN_BASE 0x02DCA000 static const io_register_t espi_cfg_registers[] = { + {0x20, 4, "ZSTATE_S0I3_VW"}, {0x2C, 4, "MASTER_CAP"}, - {0x30, 4, "GLBL_CTL0"}, - {0x34, 4, "GLBL_CTL1"}, + {0x30, 4, "GLOBAL_CONTROL0"}, + {0x34, 4, "GLOBAL_CONTROL1"}, + {0x38, 4, "MISC_CONTROL0"}, {0x40, 4, "SLAVE0_DECODE_EN"}, {0x44, 2, "IO_BASE[0]"}, {0x46, 2, "IO_BASE[1]"}, @@ -60,6 +62,10 @@ static const io_register_t espi_cfg_registers[] = { {0x95, 1, "IO_SIZE[9]"}, {0x96, 1, "IO_SIZE[10]"}, {0x97, 1, "IO_SIZE[11]"}, + {0x98, 4, "RXVW_IRQ_INACTIVE_POALRITY"}, + {0x9C, 4, "SLAVE0_RXVW"}, + {0xA0, 4, "SLAVE0_RXVW_DATA"}, + {0xA4, 4, "SLAVE0_RXVW_INDEX"}, {0xA8, 4, "SLAVE0_RXVW_MISC_CNTL"}, {0xAC, 4, "SLAVE0_RXVW_POLARITY"}, {0xB0, 2, "IO_BASE[12]"}, From 6a1d4a5cf1982b0c4c92ea2bb2945976a91f93f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 1 Jun 2026 14:06:08 +0200 Subject: [PATCH 43/62] util/amdtool/lpc.c: Read LPC CFG space with SMN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes the LPC configuration space may be locked from host access. Use SMN to retrieve the LPC CFG space values as a backup. Upstream-Status: Pending Change-Id: I26f8bca135aec3589401ccb84dd5f668efa67311 Signed-off-by: Michał Żygowski --- util/amdtool/lpc.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/util/amdtool/lpc.c b/util/amdtool/lpc.c index e2ace6b1fd5..21abb56cbdb 100644 --- a/util/amdtool/lpc.c +++ b/util/amdtool/lpc.c @@ -6,6 +6,9 @@ #include #include #include "amdtool.h" +#include "smn.h" + +#define AMD_LPC_CFG_SMN 0x02dc6000 static const io_register_t lpc_cfg_registers[] = { {0x00, 4, "ID"}, @@ -122,5 +125,34 @@ int print_lpc(struct pci_dev *sb) } } + printf("\n======== LPC (SMN) =======\n\n"); + + for (i = 0; i < cfg_registers_size; i++) { + switch (cfg_registers[i].size) { + case 4: + printf("0x%04x: 0x%08x (%s)\n", + cfg_registers[i].addr, + smn_read32(AMD_LPC_CFG_SMN + cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + cfg_registers[i].addr, + smn_read16(AMD_LPC_CFG_SMN + cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + cfg_registers[i].addr, + smn_read8(AMD_LPC_CFG_SMN + cfg_registers[i].addr), + cfg_registers[i].name); + break; + default: + printf("Error: register size %d not implemented.\n", + cfg_registers[i].size); + break; + } + } + return 0; } From d418615753abbbd965ff3ba066e92e8d2199004c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 1 Jun 2026 15:13:36 +0200 Subject: [PATCH 44/62] util/superiotool/nuvoton.c: Dump IRQ registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before accessign IRQ type and IRQ polarity registers, register 0x1d bit 3 must be set in global LDN. Upstream-Status: Pending Change-Id: I5847651342922b78f1956dc8af3460f5f29023de Signed-off-by: Michał Żygowski --- util/superiotool/nuvoton.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 80ba12ecdd8..7cec8f58610 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -180,8 +180,8 @@ static const struct superio_registers reg_table[] = { NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, 0x01,EOT}}, {0x08, "PORT80 UART", - {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, - {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, + {0x80,0x00,0x00,0x10,0x00,0x00,EOT}}, {0x09, "GPIO8-9, GPIO1-8 Alternate Function", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, 0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,EOT}, @@ -984,6 +984,7 @@ void probe_idregs_nuvoton(uint16_t port) uint16_t chip_id = 0; uint8_t chip_rev = 0; uint16_t iobase = 0; + uint8_t val; int i; /* Probe for the 16bit IDs first to avoid collisions */ @@ -1055,6 +1056,12 @@ void probe_idregs_nuvoton(uint16_t port) dump_data(iobase + 5, i); break; case 0xd590: /* NCT6687D-W */ + val = regval(port, 0x1d); + regwrite(port, 0x1d, val | 8); + printf("IRQ Type: 0x%02x%02x\n", regval(port, 0x10), regval(port, 0x11)); + printf("IRQ polarity: 0x%02x%02x\n", regval(port, 0x13), regval(port, 0x14)); + regwrite(port, 0x1d, val); + dump_nct6687d_gpios(port); /* One can use the APCI/BIOS register set, although the * resulting data is still the same when using software From 5719271e8e38fea1b02000ff9f5508b30ecd724a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:28:25 +0200 Subject: [PATCH 45/62] acpi/acpigen_pci_root_resource_producer.c: Include VGA memory in VGA resource MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The root bridge resources should also include the RAM for VGA if VGA is available on given root bridge. Upstream-Status: Pending Change-Id: I9a1da3651d09ec5634de398617dbc2aeda33e734 Signed-off-by: Michał Żygowski --- src/acpi/acpigen_pci_root_resource_producer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c index b49c653109d..75a206e5441 100644 --- a/src/acpi/acpigen_pci_root_resource_producer.c +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -122,7 +122,8 @@ void pci_domain_fill_ssdt(const struct device *domain) if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); acpigen_resource_producer_io(VGA_IO_BASE, VGA_IO_LIMIT); - acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, + /* Report VGA MMIO + extra 128K for VGA OptionROM in legacy C segment */ + acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT + 0x20000, MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); } From ac59f8bfc68a5737b641b086d33b184511e6bdc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:30:16 +0200 Subject: [PATCH 46/62] soc/amd/phoenix/chipset_opensil.cb: use PCIe bridge scan for internal GPP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use PCI Express bridge scan function for internal GPP bridges, because openSIL does not program the PCIe capabilities yet. Let coreboot set ASPM, Max Payload, Clock PM and others so that the devices work properly. Upstream-Status: Pending Change-Id: I35ab7a31cbb40879a35a491e43742f816216973e Signed-off-by: Michał Żygowski --- src/soc/amd/common/block/pci/pcie_gpp.c | 10 ++++++++++ src/soc/amd/phoenix/chipset_opensil.cb | 6 +++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 0f983d04bea..9dac1c9d7e3 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -71,6 +71,16 @@ struct device_operations amd_internal_pcie_gpp_ops = { .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; +struct device_operations amd_internal_pcie_gpp_ops_exp = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, +}; + struct device_operations amd_external_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index 0a88128c480..3328cc9c9b7 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -64,7 +64,7 @@ chip soc/amd/phoenix device pci 08.0 on end # Dummy device function, do not disable device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - ops amd_internal_pcie_gpp_ops + ops amd_internal_pcie_gpp_ops_exp device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -116,13 +116,13 @@ chip soc/amd/phoenix device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B - ops amd_internal_pcie_gpp_ops + ops amd_internal_pcie_gpp_ops_exp device pci 0.0 on end # dummy, do not disable device pci 0.1 alias ipu off end end device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - ops amd_internal_pcie_gpp_ops + ops amd_internal_pcie_gpp_ops_exp device pci 0.0 on end # dummy, do not disable device pci 0.3 alias usb4_xhci_0 off ops xhci_pci_ops From c1d611a18194967f3724b1c6000cbe21221f8a4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:32:21 +0200 Subject: [PATCH 47/62] soc/amd/phoenix/acpi: Add IOAPIC interrupt routing function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch to IOAPIC interrupt routing when _PIC function is evaluated by the OS and interrupt routing is enabled. The change reflects what turin_poc does. Additionally there is a function added to disable all PIC IRQ routing once the IOAPIC routing is enabled. Upstream-Status: Pending Change-Id: I444a1380d6d84d5bb2d5e93bd0a2cb7b93cfc21e Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/acpi/ioapic_routing.asl | 31 ++++++++++++++ src/soc/amd/phoenix/acpi/pci_int_defs.asl | 45 +++++++++++++++++++++ src/soc/amd/phoenix/acpi/soc.asl | 2 + 3 files changed, 78 insertions(+) create mode 100644 src/soc/amd/phoenix/acpi/ioapic_routing.asl diff --git a/src/soc/amd/phoenix/acpi/ioapic_routing.asl b/src/soc/amd/phoenix/acpi/ioapic_routing.asl new file mode 100644 index 00000000000..aec8b39b2ed --- /dev/null +++ b/src/soc/amd/phoenix/acpi/ioapic_routing.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (PCI0) { + OperationRegion (NAPC, PCI_Config, 0xB8, 0x08) + Field (NAPC, DWordAcc, NoLock, Preserve) + { + NAPX, 32, + NAPD, 32 + } +} + +/* + * Clears IoapicSbFeatureEn on GNB IOAPIC to switch routing to IOAPIC. + */ +Mutex (NAPM, 0x00) +Method (NAPE, 0, NotSerialized) +{ + If (PICM == 0) + { + Return + } + + \_SB.DSPI() + + Acquire (NAPM, 0xFFFF) + \_SB.PCI0.NAPX = 0x14300000 + Local0 = \_SB.PCI0.NAPD + Local0 &= 0xFFFFFFEF + \_SB.PCI0.NAPD = Local0 + Release (NAPM) +} diff --git a/src/soc/amd/phoenix/acpi/pci_int_defs.asl b/src/soc/amd/phoenix/acpi/pci_int_defs.asl index 5d6aadc3219..1cb325822d0 100644 --- a/src/soc/amd/phoenix/acpi/pci_int_defs.asl +++ b/src/soc/amd/phoenix/acpi/pci_int_defs.asl @@ -22,6 +22,27 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ + Offset (0x0C), + SIRA, 0x00000008, /* Index 0x0C: Serial IRQA */ + SIRB, 0x00000008, /* Index 0x0D: Serial IRQB */ + SIRC, 0x00000008, /* Index 0x0E: Serial IRQC */ + SIRD, 0x00000008, /* Index 0x0F: Serial IRQD */ + PIRS, 0x00000008, /* Index 0x10: SCI */ + Offset (0x13), + HDAD, 0x00000008, /* Index 0x13: HDA */ + Offset (0x17), + SDCL, 0x00000008, /* Index 0x17: SD */ + Offset (0x1A), + SDIO, 0x00000008, /* Index 0x1A: SDIO */ + Offset (0x30), + USB1, 0x00000008, /* Index 0x30: XHCI1 */ + Offset (0x34), + USB3, 0x00000008, /* Index 0x34: XHCI3 */ + Offset (0x41), + SATA, 0x00000008, /* Index 0x41: SATA */ + Offset (0x43), + EMMC, 0x00000008, /* Index 0x43: EMMC */ + Offset (0x60), PGSC, 0x00000008, /* Index 0x60: GEventSci */ PGSM, 0x00000008, /* Index 0x61: GEventSmi */ @@ -69,3 +90,27 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { IUA2, 0x00000008, /* Index 0xF8: UART2 */ IUA3, 0x00000008, /* Index 0xF9: UART3 */ } + +Method (DSPI, 0, NotSerialized) +{ + PIRA = 0x1F + HDAD = 0x1F + PIRB = 0x1F + PIRC = 0x1F + USB1 = 0x1F + USB3 = 0x1F + PIRD = 0x1F + SATA = 0x1F + PIRE = 0x1F + PIRF = 0x1F + PIRG = 0x1F + PIRH = 0x1F + IORA = 0x10 + IORB = 0x11 + IORC = 0x12 + IORD = 0x13 + IORE = 0x14 + IORF = 0x15 + IORG = 0x16 + IORH = 0x17 +} diff --git a/src/soc/amd/phoenix/acpi/soc.asl b/src/soc/amd/phoenix/acpi/soc.asl index ee2e9c886b0..41bdbdc1c01 100644 --- a/src/soc/amd/phoenix/acpi/soc.asl +++ b/src/soc/amd/phoenix/acpi/soc.asl @@ -24,6 +24,8 @@ Scope(\_SB) { Scope(PCI0) { #include } /* End PCI0 scope */ + + #include "ioapic_routing.asl" } /* End \_SB scope */ #include From eb8b3cff258cc9bc921f34e6676120d9431783e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:38:42 +0200 Subject: [PATCH 48/62] mainboard/msi/ms7e56: Add eSPI initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize eSPI interrupts and watchdog. Upstream-Status: Pending Change-Id: I1e1de121ecca3457f32ea607d6bc70d318cace59 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/bootblock.c | 58 ++++++++++++++++++++++--- src/mainboard/msi/ms7e56/early_gpio.c | 6 +-- src/soc/amd/common/block/lpc/espi_def.h | 3 ++ 3 files changed, 59 insertions(+), 8 deletions(-) diff --git a/src/mainboard/msi/ms7e56/bootblock.c b/src/mainboard/msi/ms7e56/bootblock.c index a32df252723..b00ab6bc2e6 100644 --- a/src/mainboard/msi/ms7e56/bootblock.c +++ b/src/mainboard/msi/ms7e56/bootblock.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +#include #include #include +#include #include #include #include @@ -16,20 +20,64 @@ #define EC_IO_BASE 0xa20 -void bootblock_mainboard_early_init(void) +void mb_set_up_early_espi(void) { + espi_switch_to_spi1_pads(); mainboard_program_early_gpios(); +} - espi_switch_to_spi1_pads(); +static void post_espi_init(void) +{ + volatile void *espi_base = (void *)lpc_get_spibase() + ESPI_OFFSET_FROM_BAR; + uint32_t value; + + /* Initialzie eSPI watchdog timer */ + value = read32(espi_base + ESPI_GLOBAL_CONTROL_0); + value &= ~(ESPI_WDG_CNT_MASK | ESPI_AL_IDLE_TIMER_MASK); + value |= (ESPI_AL_IDLE_TIMER_MASK | (0x1400 << ESPI_WDG_CNT_SHIFT)); + write32(espi_base + ESPI_GLOBAL_CONTROL_0, value); + + write32(espi_base + ESPI_GLOBAL_CONTROL_0, + read32(espi_base + ESPI_GLOBAL_CONTROL_0) | ESPI_WDG_EN); + write32(espi_base + ESPI_GLOBAL_CONTROL_0, + read32(espi_base + ESPI_GLOBAL_CONTROL_0) | ESPI_WAIT_CHKEN); + + value = read32(espi_base + ESPI_GLOBAL_CONTROL_0); + value &= ~ESPI_WAIT_CNT_MASK; + value |= ESPI_WAIT_CNT_MASK; + value |= (1 << 31); // set reserved bit as vendor BIOS does + write32(espi_base + ESPI_GLOBAL_CONTROL_0, value); + + /* Program RX Virtual Wires */ + write32(espi_base + ESPI_RXVW_INDEX, 0x00040506); + write32(espi_base + ESPI_RXVW_MISC_CNTL, 0x00000007); + + value = read32(espi_base + ESPI_GLOBAL_CONTROL_1); + value |= ESPI_REQ_NOTWITH_VW_REQ; + write32(espi_base + ESPI_GLOBAL_CONTROL_1, value); + + /* Clear and enable interrupts */ + value = read32(espi_base + ESPI_SLAVE0_INT_STS); + if (value) + write32(espi_base + ESPI_SLAVE0_INT_STS, value); + + write32(espi_base + ESPI_SLAVE0_INT_EN, UINT32_MAX); +} + +void bootblock_mainboard_early_init(void) +{ + post_espi_init(); /* Replicate vendor settings for multi-function pins in global config LDN */ nuvoton_pnp_enter_conf_state(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x10, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(GPIO_DEV, 0x11, 0xff); // IRQ0-7 level triggered, low pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low /* Below are multi-pin function */ pnp_write_config(GPIO_DEV, 0x15, 0x0a); - pnp_write_config(GPIO_DEV, 0x1a, 0x80); + pnp_write_config(GPIO_DEV, 0x1a, 0x82); pnp_write_config(GPIO_DEV, 0x1b, 0x02); pnp_write_config(GPIO_DEV, 0x1d, 0x00); pnp_write_config(GPIO_DEV, 0x1e, 0xa2); @@ -57,8 +105,8 @@ void bootblock_mainboard_early_init(void) /* Configure yellow and green LED */ pnp_write_config(POWER_DEV, 0xe7, 0xa0); pnp_write_config(POWER_DEV, 0xe8, 0x07); -// pnp_set_logical_device(P80_UART_DEV); -// pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); + pnp_set_logical_device(P80_UART_DEV); + pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); /* Configure EC */ pnp_set_logical_device(EC_DEV); diff --git a/src/mainboard/msi/ms7e56/early_gpio.c b/src/mainboard/msi/ms7e56/early_gpio.c index f3dc89764ad..50df3b9d669 100644 --- a/src/mainboard/msi/ms7e56/early_gpio.c +++ b/src/mainboard/msi/ms7e56/early_gpio.c @@ -14,15 +14,15 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* ESPI_SOC_CLK */ PAD_NF(GPIO_77, SPI1_CLK, PULL_DOWN), /* ESPI_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_DOWN), + PAD_NF(GPIO_81, SPI1_DAT0, PULL_UP), /* ESPI_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_DOWN), + PAD_NF(GPIO_80, SPI1_DAT1, PULL_UP), /* ESPI_DATA2 */ PAD_NF(GPIO_68, SPI1_DAT2, PULL_UP), /* ESPI_DATA3 */ PAD_NF(GPIO_69, SPI1_DAT3, PULL_UP), /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_UP), /* ESPI_RESET_L */ PAD_NF(GPIO_21, ESPI_RESET_L, PULL_UP), /* SPI_ROM_REQ */ diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h index 7f371c1a1a5..1b4fcb36f5d 100644 --- a/src/soc/amd/common/block/lpc/espi_def.h +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -25,6 +25,7 @@ #define ESPI_WDG_EN (1 << 0) #define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_REQ_NOTWITH_VW_REQ (1 << 21) #define ESPI_ALERT_ENABLE (1 << 20) /* Mendocino and later SoCs */ #define ESPI_RGCMD_INT_MAP_SHIFT 13 #define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) @@ -80,6 +81,8 @@ #define ESPI_MMIO_BASE_REG4 0xbc #define ESPI_MMIO_SIZE_REG2 0xc0 +#define ESPI_RXVW_INDEX 0xa4 +#define ESPI_RXVW_MISC_CNTL 0xa8 #define ESPI_RXVW_POLARITY 0xac #define ESPI_DECODE_RANGES_PER_REG_GROUP 4 From 20302224e4c6ff3a913076127106b9d5d53d79dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:40:09 +0200 Subject: [PATCH 49/62] mainboard/msi/ms7e56: Remove obsolete remove_devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I60fb42f835fbe0cfdec25a8b8bf044a1390ab8a7 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/Makefile.mk | 1 - src/mainboard/msi/ms7e56/mainboard.c | 5 +---- src/mainboard/msi/ms7e56/update_devicetree.c | 21 -------------------- src/mainboard/msi/ms7e56/update_devicetree.h | 8 -------- 4 files changed, 1 insertion(+), 34 deletions(-) delete mode 100644 src/mainboard/msi/ms7e56/update_devicetree.c delete mode 100644 src/mainboard/msi/ms7e56/update_devicetree.h diff --git a/src/mainboard/msi/ms7e56/Makefile.mk b/src/mainboard/msi/ms7e56/Makefile.mk index f4352025962..249ada920cd 100644 --- a/src/mainboard/msi/ms7e56/Makefile.mk +++ b/src/mainboard/msi/ms7e56/Makefile.mk @@ -5,7 +5,6 @@ bootblock-y += early_gpio.c ramstage-y += gpio.c ramstage-y += smbios.c -ramstage-y += update_devicetree.c ifneq ($(wildcard $(src)/mainboard/$(MAINBOARDDIR)/data*.apcb),) APCB_SOURCES = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb diff --git a/src/mainboard/msi/ms7e56/mainboard.c b/src/mainboard/msi/ms7e56/mainboard.c index b9c06cf6bd7..40431daaf3b 100644 --- a/src/mainboard/msi/ms7e56/mainboard.c +++ b/src/mainboard/msi/ms7e56/mainboard.c @@ -6,7 +6,6 @@ #include #include #include "gpio.h" -#include "update_devicetree.h" /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is accessed via I/O ports 0xc00/0xc01. */ @@ -59,10 +58,8 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) static void mainboard_init(void *chip_info) { mainboard_program_gpios(); - - mainboard_update_devicetree_opensil(); } struct chip_operations mainboard_ops = { - .init = mainboard_init, + .init = mainboard_init }; diff --git a/src/mainboard/msi/ms7e56/update_devicetree.c b/src/mainboard/msi/ms7e56/update_devicetree.c deleted file mode 100644 index 5938f2a735f..00000000000 --- a/src/mainboard/msi/ms7e56/update_devicetree.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include "update_devicetree.h" - -static void mainboard_update_mpio(void) -{ -} - -static void mainboard_update_ddi(void) -{ -} - -void mainboard_update_devicetree_opensil(void) -{ - mainboard_update_mpio(); - mainboard_update_ddi(); -} diff --git a/src/mainboard/msi/ms7e56/update_devicetree.h b/src/mainboard/msi/ms7e56/update_devicetree.h deleted file mode 100644 index 6f98dbd0ef4..00000000000 --- a/src/mainboard/msi/ms7e56/update_devicetree.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_UPDATE_DEVICETREE_H -#define MAINBOARD_UPDATE_DEVICETREE_H - -void mainboard_update_devicetree_opensil(void); - -#endif /* MAINBOARD_UPDATE_DEVICETREE_H */ From 5979fdb07a90df71fb8d5bf169f7f0b2e1d64ac0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:40:58 +0200 Subject: [PATCH 50/62] vc/amd/opensil/phoenix_poc/mpio: Fill NBIO params for IOMMU and APIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fill missing parameters for NBIO IOMMU and APIC, because some of them were no set per devicetree or were duplicated in CCX class input block. They have to be in sync. Upstream-Status: Pending Change-Id: I695bcccf0d549748862efd4017d50aabf658d37b Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index 59ba565b32c..4d4c77b24c4 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -143,12 +144,21 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) input->EsmTargetSpeed = 16; input->CfgRxMarginPersistenceMode = 1; input->SevSnpSupport = false; + input->IommuAvicSupport = true; + input->IommuSupport = is_dev_enabled(DEV_PTR(iommu)); input->Usb4Rt0En = is_dev_enabled(DEV_PTR(usb4_router_0)); input->Usb4Rt0PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_0)); input->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1)); input->Usb4Rt1PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_1)); gfx_data->Usb4Rt0En = input->Usb4Rt0En; gfx_data->Usb4Rt1En = input->Usb4Rt1En; + + if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND)) + input->AmdApicMode = xApicMode; + else if (CONFIG(X2APIC_ONLY)) + input->AmdApicMode = x2ApicMode; + else + input->AmdApicMode = ApicAutoMode; } #ifndef MPIO_ENGINE_DATA_INITIALIZER From fd8ffc1efbf5ad1d23401b74da14e1a2de5a9efd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 10:42:10 +0200 Subject: [PATCH 51/62] vc/amd/opensil/phoenix_poc/ramstage.c: Limit MMIO to 1TB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the MMIO limit to 1TB minus the reserved space for IOMMU and ROM3 to reflect vendor BIOS settings. Upstream-Status: Pending Change-Id: Id43cb3aeff491facfb48546ff89cbc2eb50b7a5c Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/ramstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 7b1178ef274..5e6038c6575 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -72,8 +73,7 @@ static void setup_rc_manager_default(SIL_CONTEXT *SilContext) rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS; rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB; rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB; - /* MmioAbove4GLimit will be adjusted down in openSIL */ - rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size()); + rc_mgr_input_block->MmioAbove4GLimit = IOMMU_RESERVED_MMIO_BASE; rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0; /* Enforce remapping and address space reduction, as this is what AGESA does */ rc_mgr_input_block->AmdFabric1TbRemap = 1; From 209dc780f1b5e99ae59086d1c4e6c79a000de2c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 11:24:15 +0200 Subject: [PATCH 52/62] soc/amd/phoenix: Add CPPC support with openSIL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Report min and max frequency in CPPC structures so that AMD P-state driver probes correctly on Linux. Upstream-Status: Pending Change-Id: I5f28db05bad9a2016dd203818e199a9dd5c8511a Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/Kconfig | 2 +- src/soc/amd/phoenix/acpi.c | 39 +++++++++++++++++++ .../amd/opensil/phoenix_poc/opensil | 2 +- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index e3132fc1147..1d1e215106b 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -27,7 +27,7 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 85eac9bd906..08b3a4bd96a 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,10 @@ #include #include "chip.h" +#if CONFIG(SOC_AMD_PHOENIX_OPENSIL) +#include +#endif + unsigned long soc_acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd40_t *ivhd, struct device *nb_dev, struct device *iommu_dev) { @@ -165,3 +170,37 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size) *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } + +#if CONFIG(SOC_AMD_PHOENIX_OPENSIL) +enum cb_err get_ccx_cppc_min_frequency(uint32_t *freq) +{ + SIL_CONTEXT SilContext = { + .ApobBaseAddress = CONFIG_PSP_APOB_DRAM_ADDRESS, + .SilMemBaseAddress = (uintptr_t)cbmem_find(CBMEM_ID_AMD_OPENSIL) + }; + + if (SilContext.SilMemBaseAddress == 0) + return CB_ERR; + + if (xPrfGetCppcMinFrequency(&SilContext, freq) != SilPass) + return CB_ERR; + + return CB_SUCCESS; +} + +enum cb_err get_ccx_cppc_nom_frequency(uint32_t *freq) +{ + SIL_CONTEXT SilContext = { + .ApobBaseAddress = CONFIG_PSP_APOB_DRAM_ADDRESS, + .SilMemBaseAddress = (uintptr_t)cbmem_find(CBMEM_ID_AMD_OPENSIL) + }; + + if (SilContext.SilMemBaseAddress == 0) + return CB_ERR; + + if (xPrfGetCppcNomFrequency(&SilContext, freq) != SilPass) + return CB_ERR; + + return CB_SUCCESS; +} +#endif diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index aa8d9b6b50b..2b4a72bfa32 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit aa8d9b6b50b80c2fae95802ae6094b37a6bf5ad9 +Subproject commit 2b4a72bfa32417b82ffb31e3bd46c15a45e31a24 From a76d7878ab6b1859254b18abb4f98d0c4d5f2325 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 11:51:06 +0200 Subject: [PATCH 53/62] mainbaord/msi/ms7e56: Add Promontory21 GPIO ACPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: I7cd1fca2060c1da09df01c069d57d0365eafd5b1 Signed-off-by: Michał Żygowski --- .../amd/promontory21/acpi/prom21_gpio.asl | 198 ++++++++++++++++++ src/mainboard/msi/ms7e56/dsdt.asl | 1 + 2 files changed, 199 insertions(+) create mode 100644 src/drivers/amd/promontory21/acpi/prom21_gpio.asl diff --git a/src/drivers/amd/promontory21/acpi/prom21_gpio.asl b/src/drivers/amd/promontory21/acpi/prom21_gpio.asl new file mode 100644 index 00000000000..4f126ff2947 --- /dev/null +++ b/src/drivers/amd/promontory21/acpi/prom21_gpio.asl @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (\_SB) +{ + Name (TGPI, 0x0F) + Device (PTIO) + { + Name (_HID, "AMDIF031") + Name (_CID, "AMDIF031") + Name (_UID, 0) + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFEC40000, + 0x00001000, + ) + }) + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device (ASMT) + { + Name (_HID, "ASMT0001") + Name (_CID, "ASMT0001") + Name (_UID, 0) + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0000 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0001 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0002 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0003 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0004 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0005 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0006 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0007 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0008 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0009 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000A + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000B + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000C + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000D + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000E + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x000F + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0010 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0011 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0012 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0013 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0014 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0015 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0016 + } + GpioIo (Exclusive, PullUp, 0x0000, 0x0000, IoRestrictionNone, + "\\_SB.PTIO", 0x00, ResourceConsumer, , + RawDataBuffer (0x01) { 0x01 }) + { + 0x0017 + } + }) + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If ((TGPI == One)) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + } +} diff --git a/src/mainboard/msi/ms7e56/dsdt.asl b/src/mainboard/msi/ms7e56/dsdt.asl index 3388ca99f04..a1df208cc91 100644 --- a/src/mainboard/msi/ms7e56/dsdt.asl +++ b/src/mainboard/msi/ms7e56/dsdt.asl @@ -21,4 +21,5 @@ DefinitionBlock ( } #include "acpi/mainboard.asl" + #include } From a34f7e74867972b3a8b2430938432d9458cfafa6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 14:53:46 +0200 Subject: [PATCH 54/62] soc/amd/phoenix/include/soc/amd_pci_int_defs.h: Add missing IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add IRQs that are reference in reference code or ACPI on PHX AM5 devices. Upstream-Status: Pending Change-Id: Ice4de51b3aa702dd8ee0442a74660d6e3f39e1db Signed-off-by: Michał Żygowski --- src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h index 74bb4548c48..8adf01d2280 100644 --- a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h @@ -32,14 +32,17 @@ #define PIRQ_ASF 0x12 /* ASF */ /* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -/* 0x17-0x19 reserved */ +#define PIRQ_SD 0x17 /* Performance Monitor */ +/* 0x18-0x19 reserved */ #define PIRQ_SDIO 0x1a /* SDIO */ /* 0x1b-0x1f reserved */ #define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x5f reserved */ +/* 0x24-0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x5f reserved */ #define PIRQ_GSCI 0x60 /* GEventSci Interrupt */ #define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ From 6ebf3089b080aaa1a3e8764a237ac8f1fec440e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 14:48:18 +0200 Subject: [PATCH 55/62] mainboard/msi/ms7e56/mainboard.c: Update interrupt routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Program interrupts only for used devices. Upstream-Status: Pending Change-Id: I3c4560e9d5aaee2144182c11e1bdd9c4717528b2 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/mainboard.c | 36 +++++++++++++++------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/mainboard/msi/ms7e56/mainboard.c b/src/mainboard/msi/ms7e56/mainboard.c index 40431daaf3b..118b79e42c5 100644 --- a/src/mainboard/msi/ms7e56/mainboard.c +++ b/src/mainboard/msi/ms7e56/mainboard.c @@ -21,26 +21,28 @@ * 9: acpi <- soc/amd/common/acpi/lpc.asl */ static const struct fch_irq_routing fch_irq_map[] = { - { PIRQ_A, 10, 0x10 }, - { PIRQ_B, 11, 0x11 }, - { PIRQ_C, 11, 0x12 }, - { PIRQ_D, 10, 0x13 }, - { PIRQ_E, 10, 0x14 }, - { PIRQ_F, 11, 0x15 }, - { PIRQ_G, 11, 0x16 }, - { PIRQ_H, 10, 0x17 }, + { PIRQ_A, 0x03, 0x10 }, + { PIRQ_B, 0x04, 0x11 }, + { PIRQ_C, 0x05, 0x12 }, + { PIRQ_D, 0x06, 0x13 }, + { PIRQ_E, 0x0a, 0x14 }, + { PIRQ_F, 0x0b, 0x15 }, + { PIRQ_G, 0x0e, 0x16 }, + { PIRQ_H, 0x0f, 0x17 }, { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, 0x10 }, { PIRQ_SDIO, PIRQ_NC, 0x10 }, { PIRQ_GPIO, 0x07, 0x07 }, - { PIRQ_I2C0, 0x0a, 0x0a }, - { PIRQ_I2C1, 0x0b, 0x0b }, - { PIRQ_I2C2, 0x0e, 0x0e }, - { PIRQ_I2C3, 0x0f, 0x06 }, - { PIRQ_UART0, 4, 0x03 }, - { PIRQ_UART1, 3, 0x0e }, - { PIRQ_UART2, 4, 0x05 }, - { PIRQ_UART3, 3, 0x0f }, - { PIRQ_UART4, 4, 0x10 }, + { PIRQ_EMMC, PIRQ_NC, 0x05 }, + { PIRQ_I2C0, PIRQ_NC, 0x03 }, + { PIRQ_I2C1, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C2, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C3, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART0, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART1, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART2, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART3, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART4, PIRQ_NC, PIRQ_NC }, /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, { PIRQ_MISC0, 0x91, 0x00 }, From 7bfdff33dffc27328bcf570cc67ad11ddb9fe27e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 14:49:19 +0200 Subject: [PATCH 56/62] mb/msi/ms7e56: Describe ACPI devices and ACPI events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generate missing devices in SSDT. Add GPE and ACPI events as in vendor BIOS. Upstream-Status: Pending Change-Id: I11097dc269c7b44e241ae32d0947ebde712f8011 Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/acpi/mainboard.asl | 245 ++++++++++++++++++ src/mainboard/msi/ms7e56/mainboard.c | 44 ++++ .../amd/opensil/phoenix_poc/opensil | 2 +- 3 files changed, 290 insertions(+), 1 deletion(-) diff --git a/src/mainboard/msi/ms7e56/acpi/mainboard.asl b/src/mainboard/msi/ms7e56/acpi/mainboard.asl index da058a0e0e5..cb7d6f5a2d1 100644 --- a/src/mainboard/msi/ms7e56/acpi/mainboard.asl +++ b/src/mainboard/msi/ms7e56/acpi/mainboard.asl @@ -1,5 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +External (\_SB.PCI0.GP09, DeviceObj) +External (\_SB.PCI0.GP0A, DeviceObj) +External (\_SB.PCI0.GP0B, DeviceObj) +External (\_SB.PCI0.GP0C, DeviceObj) +External (\_SB.PCI0.GP11, DeviceObj) +External (\_SB.PCI0.GP12, DeviceObj) +External (\_SB.PCI0.GP11, DeviceObj) +External (\_SB.PCI0.GP41.XHC1, DeviceObj) +External (\_SB.PCI0.GP41.XHC2, DeviceObj) +External (\_SB.PCI0.GP41.AZAL, DeviceObj) +External (\_SB.PCI0.GP41.ACPD, DeviceObj) + Scope (\_SB.PCI0) { /* This device triggers automatic drivers and MSI utilities installation on Windows */ Device (MSIV) { @@ -10,3 +22,236 @@ Scope (\_SB.PCI0) { } } } + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + } + + Name (S0IX, 0) + + /* + * Read dword from memory + * Arg0 - Base Address + * Arg1 - Offset + */ + Method (M04B, 2, Serialized) { + Local0 = 0 + If (Arg0 != 0) { + Local0 = Arg0 + Arg1 + OperationRegion (VARM, SystemMemory, Local0, 0x4) + Field (VARM, DWordAcc, NoLock, Preserve) { + VARR, 32, + } + Local0 = VARR + } + Return (Local0) + } + + /* + * Write dword to memory + * Arg0 - Base Address + * Arg1 - Offset + * Arg2 - Dword of data + */ + Method (M04E, 3, Serialized) { + If (Arg0 != 0) { + Local0 = Arg0 + Arg1 + OperationRegion (VARM, SystemMemory, Local0, 0x4) + Field (VARM, DWordAcc, NoLock, Preserve) { + VARR, 32, + } + VARR = Arg2 + } + } + + /* + * Write Memory + * Arg0 - Base Address + * Arg1 - Offset + * Arg2 - Start Bit + * Arg3 - Bit Width + * Arg4 - Value + */ + Method (M014, 5, Serialized) + { + Local1 = M04B (Arg0, Arg1) + Local5 = 0x7FFFFFFF + Local5 |= 0x80000000 + Local2 = (Arg2 + Arg3) + Local2 = (32 - Local2) + Local2 = (((Local5 << Local2) & Local5) >> Local2) + Local2 = ((Local2 >> Arg2) << Arg2) + Local3 = (Arg4 << Arg2) + Local4 = ((Local1 & (Local5 ^ Local2)) | Local3) + M04E (Arg0, Arg1, Local4) + } +} + +Scope (\_GPE) +{ + Method (_L02, 0, Serialized) + { + Notify (\_SB.PCI0.GP11, 0x00) + Notify (\_SB.PCI0.GP11, 0x02) + } + + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0.GP09, 0x02) + Notify (\_SB.PCI0.GP0A, 0x02) + } + + Method (_L0E, 0, NotSerialized) + { + Notify (\_SB.PCI0.GP0C, 0x02) + Notify (\_SB.PWRB, 0x02) + } + + Method (_L0F, 0, NotSerialized) + { + Notify (\_SB.PCI0.GP0B, 0x02) + Notify (\_SB.PWRB, 0x02) + } + + Method (_L16, 0, NotSerialized) + { + Notify (\_SB.PCI0.GP12, Zero) + Notify (\_SB.PCI0.GP12, 0x02) + } +} + +Scope (\_SB.GPIO) +{ + + Method (_AEI, 0, Serialized) + { + Name (BUFF, ResourceTemplate () + { + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x01F4, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x000A + } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0003 + } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0020 + } + }) + Name (BUNP, ResourceTemplate () + { + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault, 0x1388, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0000 + } + GpioInt (Level, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x003D + } + GpioInt (Level, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x003E + } + GpioInt (Level, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x003A + } + GpioInt (Level, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x003B + } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0002 + } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0003 + } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x0009 + } + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x01F4, + "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { + 0x000A + } + }) + If (S0IX) { + Return (BUNP) + } Else { + Return (BUFF) + } + } + + Method (_EVT, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (Zero) { Notify (\_SB.PWRB, 0x80) } + Case (0x3A) { + If (CondRefOf (\_SB.PCI0.GP41.XHC1)) + { + Notify (\_SB.PCI0.GP41.XHC1, 0x02) + } + } + Case (0x3B) { + If (CondRefOf (\_SB.PCI0.GP41.XHC2)) + { + Notify (\_SB.PCI0.GP41.XHC2, 0x02) + } + } + Case (0x3D) { + If (CondRefOf (\_SB.PCI0.GP41.AZAL)) + { + Notify (\_SB.PCI0.GP41.AZAL, 0x02) + } + } + Case (0x3E) { + If (CondRefOf (\_SB.PCI0.GP41.ACPD)) + { + Notify (\_SB.PCI0.GP41.ACPD, 0x02) + } + } + Case (0x02) + { + \_SB.M014 (0xFED80200, 0, 0, 32, 0x0100) + If (CondRefOf (\_GPE._L08)) + { + \_GPE._L08 () + } + } + Case (0x03) + { + + \_SB.M014 (0xFED80200, 0, 0, 32, 0x04) + If (CondRefOf (\_GPE._L02)) + { + \_GPE._L02 () + } + } + Case (0x20) + { + \_SB.M014 (0xFED80200, 0, 0, 32, 0x00800000) + If (CondRefOf (\_GPE._L02)) + { + \_GPE._L02 () + } + } + Case (0x09) + { + If (CondRefOf (\_GPE._L16)) + { + \_GPE._L16 () + } + } + } + } +} diff --git a/src/mainboard/msi/ms7e56/mainboard.c b/src/mainboard/msi/ms7e56/mainboard.c index 118b79e42c5..a46ab023739 100644 --- a/src/mainboard/msi/ms7e56/mainboard.c +++ b/src/mainboard/msi/ms7e56/mainboard.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include +#include #include #include "gpio.h" @@ -57,9 +60,50 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) return fch_irq_map; } +static const char *hda_acpi_name(const struct device *dev) +{ + return "AZAL"; +} + +static const char *gfx_hda_acpi_name(const struct device *dev) +{ + return "HDAU"; +} + +static const char *crypto_acpi_name(const struct device *dev) +{ + return "APSP"; +} + +#define SET_AUDIO_DEV_OPS(dev) \ + struct device *dev = (struct device *)DEV_PTR(dev); \ + if (is_dev_enabled(dev)) { \ + (dev)->ops = &phx_ ## dev ## _audio_ops; \ + (dev)->ops->acpi_name = dev ## _acpi_name; \ + (dev)->ops->acpi_fill_ssdt = acpi_device_write_pci_dev; \ + } + +static struct device_operations phx_hda_audio_ops; +static struct device_operations phx_gfx_hda_audio_ops; + static void mainboard_init(void *chip_info) { + struct device *psp = (struct device *)DEV_PTR(crypto); + mainboard_program_gpios(); + + memcpy(&phx_hda_audio_ops, &default_azalia_audio_ops, + sizeof(default_azalia_audio_ops)); + memcpy(&phx_gfx_hda_audio_ops, &default_azalia_audio_ops, + sizeof(default_azalia_audio_ops)); + + SET_AUDIO_DEV_OPS(gfx_hda); + SET_AUDIO_DEV_OPS(hda); + + if (is_dev_enabled(psp)) { + psp->ops->acpi_name = crypto_acpi_name; + psp->ops->acpi_fill_ssdt = acpi_device_write_pci_dev; + } } struct chip_operations mainboard_ops = { diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 2b4a72bfa32..f0d5f2ef9a5 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 2b4a72bfa32417b82ffb31e3bd46c15a45e31a24 +Subproject commit f0d5f2ef9a5797b4c588974dfde3e3eec7d283b2 From 457dc9b62c076607cf30c50bf91a9696d5beeac5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 15:31:50 +0200 Subject: [PATCH 57/62] soc/amd/phoenix/chipset_opensil.cb: Assign HDA ops for iGFX audio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assign Azalia operations to let mainboards provide HDA verbs for integrated GPU audio. Upstream-Status: Pending Change-Id: I2e36056a9bfb92d392bfde5f21243411fa4c9cae Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 1 - src/soc/amd/phoenix/chipset_opensil.cb | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 2895b198f23..a59b8d948f7 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -656,7 +656,6 @@ chip soc/amd/phoenix end end # Internal GPU (GFX) device ref gfx_hda on - ops default_azalia_audio_ops smbios_dev_info 1 "IGD Audio" end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index 3328cc9c9b7..f3a3cc8f872 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -66,7 +66,7 @@ chip soc/amd/phoenix device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops_exp device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) - device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) + device pci 0.1 alias gfx_hda off ops default_azalia_audio_ops end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off ops xhci_pci_ops From 26621d19527af29e682f4f77813d73accd31006f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 2 Jun 2026 15:32:47 +0200 Subject: [PATCH 58/62] amdblocks/graphics: Do not create the _ROM method when using openSIL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The openSIL does not support GOP. GOP has to be launched by UEFIPayload. UEFIPaylaod will load the VBIOS from the FFS as passed to the build. Upstream-Status: Pending Change-Id: I248d890eaec0054e4e12c8442dab23a788de9a67 Signed-off-by: Michał Żygowski --- src/soc/amd/common/block/graphics/graphics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 369fd85192e..648286d68d9 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -131,7 +131,7 @@ static void graphics_fill_ssdt(const struct device *dev) acpi_device_write_pci_dev(dev); /* Use the VFCT copy when using GOP */ - if (!CONFIG(RUN_FSP_GOP)) + if (!CONFIG(RUN_FSP_GOP) && !CONFIG(SOC_AMD_OPENSIL)) pci_rom_ssdt(dev); if (CONFIG(SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF)) From d5c26487d86542586bc2858226955b74353911f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 2 May 2026 17:39:45 +0200 Subject: [PATCH 59/62] acpi/acpi.c: don't publish stub VFCT when VBIOS is not embedded MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit acpi_create_vfct returns without resetting header->length when no VBIOS is found. The in-source comment claims it returns with length == 0 (which the caller in pci_rom_write_acpi_tables checks before adding the table to XSDT), but the code leaves length at sizeof(acpi_vfct_t) from the prior acpi_fill_header call, so a 104-byte header-only VFCT gets added anyway. Match the comment: clear header->length before returning. Beyond fixing the comment/code mismatch, this also works around a bug in some AMD discrete-GPU UEFI option ROM drivers (observed on Radeon RX 9070 XT) that find the stub VFCT in XSDT, try to replace it with their own, and pass the XSDT index of VFCT to UninstallAcpiTable() instead of the TableKey returned by InstallAcpiTable(). The wrong table at that numeric handle gets removed - in our case the MADT, leaving the OS unable to bring up APs. With no stub VFCT in XSDT, the GOP driver's install path never enters the buggy uninstall code. TEST=Boot with Radeon 9070 XT and with disabled Option ROM execution, observe that coreboot does not create a VFCT table, and that the GOP driver never enters the buggy codepath in the UEFI payload. Change-Id: I8798093b735eabfe95b9028a2c0622c4b4f76da8 Upstream-Status: Submitted [CB:92495] Signed-off-by: Michał Kopeć --- src/acpi/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 11f82732395..2f98f659068 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -704,8 +704,10 @@ void acpi_create_vfct(const struct device *device, current = acpi_fill_vfct_func(device, vfct, current); /* If no BIOS image, return with header->length == 0. */ - if (!vfct->VBIOSImageOffset) + if (!vfct->VBIOSImageOffset) { + header->length = 0; return; + } /* (Re)calculate length and checksum. */ header->length = current - (unsigned long)vfct; From 4156c24881a148cbf6a4a5630b51ce552125a2e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 3 Jun 2026 09:49:23 +0200 Subject: [PATCH 60/62] vc/amd/opensil/phoenix_poc/mpio/chip.c: Enable GFX HDA based on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream-Status: Pending Change-Id: Ia595a9ececff382d800ba54b7eed54fc3d6073b6 Signed-off-by: Michał Żygowski --- src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index 4d4c77b24c4..4f0b391e12a 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -146,6 +146,7 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) input->SevSnpSupport = false; input->IommuAvicSupport = true; input->IommuSupport = is_dev_enabled(DEV_PTR(iommu)); + input->CfgAzaliaEnable = is_dev_enabled(DEV_PTR(gfx_hda)); input->Usb4Rt0En = is_dev_enabled(DEV_PTR(usb4_router_0)); input->Usb4Rt0PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_0)); input->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1)); From 1c1d1a3e9a7645f49753e59bad25ccad84368dd3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 3 Jun 2026 10:32:47 +0200 Subject: [PATCH 61/62] configs/config.msi_ms7e56: Update config and enable capsule updates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1b0b8f93f470d2e6c9e8fea77c55361a41d56855 Upstream-Status: Inappropriate [custom config] Signed-off-by: Michał Żygowski --- configs/config.msi_ms7e56 | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/configs/config.msi_ms7e56 b/configs/config.msi_ms7e56 index 9820a36378c..9467c526fd5 100644 --- a/configs/config.msi_ms7e56 +++ b/configs/config.msi_ms7e56 @@ -1,10 +1,10 @@ +CONFIG_LOCALVERSION="v0.9.0-rc1" CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y +CONFIG_MAINBOARD_VERSION="1.0" CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x2000000 CONFIG_EDK2_BOOT_TIMEOUT=3 CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=39 CONFIG_VGA_BIOS_FILE="Phoenix_generic_vbios.bin" @@ -20,11 +20,15 @@ CONFIG_NO_GFX_INIT=y CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y CONFIG_DRIVERS_EFI_VARIABLE_STORE=y CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="0d982a4d-3a6a-43e4-906c-8c70c0ad7ffe" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090001 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090001 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y CONFIG_TPM2=y # CONFIG_TPM_HASH_SHA1 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_TAG_OR_REV="origin/cbmem_pci_rb_info" +CONFIG_EDK2_TAG_OR_REV="origin/dasharo" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_LOAD_OPTION_ROMS=y # CONFIG_EDK2_PS2_SUPPORT is not set @@ -55,6 +59,8 @@ CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y # CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS is not set # CONFIG_EDK2_FUM_AUTO_IPXE_BOOT is not set +CONFIG_EDK2_CAPSULE_DOES_NOT_SURVIVE_RESET=y +CONFIG_EDK2_SHOW_CAPSULE_REPORT=y CONFIG_DISPLAY_MTRRS=y CONFIG_OPENSIL_DEBUG_PREFIX=y CONFIG_OPENSIL_DEBUG_APOB=y From 81c2237513df3d5d094058ed58252d70651b2e96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 3 Jun 2026 11:07:38 +0200 Subject: [PATCH 62/62] mb/msi/ms7e56/devicetree.cb: Set proper polarity for SIO UART IRQ4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SIO is configured for low level interrupts. Reflect that in eSPI controller configuratio nso that the interrupts in OS work correctly. TEST=Enable serial console in Linux and get login prompt. Upstream-Status: Pending Change-Id: I4de833f3a73157c03d35f1bcdf3b476f3da6721e Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index a59b8d948f7..bbb95610d7d 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -41,6 +41,7 @@ chip soc/amd/phoenix .oob_ch_en = 1, .flash_ch_en = 1, .irq_mask = 0xffe107, + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(4), }" register "s0ix_enable" = "false"